1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
4 * Author: Jon Ringle <jringle@gridpoint.com>
6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/i2c.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/spi/spi.h>
26 #include <linux/uaccess.h>
27 #include <uapi/linux/sched/types.h>
29 #define SC16IS7XX_NAME "sc16is7xx"
30 #define SC16IS7XX_MAX_DEVS 8
32 /* SC16IS7XX register definitions */
33 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
34 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
35 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
36 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
37 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
38 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
39 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
40 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
41 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
42 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
43 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
44 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
45 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
48 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
51 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
54 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
60 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
61 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
64 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
65 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
67 /* Enhanced Register set: Only if (LCR == 0xBF) */
68 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
69 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
70 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
71 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
72 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
74 /* IER register bits */
75 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
76 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
83 /* IER register bits - write only if (EFR[4] == 1) */
84 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
85 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
86 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
87 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
89 /* FCR register bits */
90 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
91 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
92 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
93 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
94 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96 /* FCR register bits - write only if (EFR[4] == 1) */
97 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
98 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
100 /* IIR register bits */
101 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
102 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
103 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
104 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
105 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
107 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
110 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
113 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
114 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
118 /* LCR register bits */
119 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
120 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
122 * Word length bits table:
128 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
130 * STOP length bit table:
132 * 1 -> 1-1.5 stop bits if
134 * 2 stop bits otherwise
136 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
137 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
138 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
139 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
140 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
141 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
142 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
143 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
144 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
145 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
147 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
150 /* MCR register bits */
151 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
154 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
155 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
156 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
157 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
161 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
165 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
170 /* LSR register bits */
171 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
172 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
173 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
174 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
175 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
176 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
177 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
178 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
179 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
181 /* MSR register bits */
182 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
183 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
187 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
191 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
195 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
196 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
199 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
202 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
205 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
209 * TCR trigger levels are available from 0 to 60 characters with a granularity
211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
212 * no built-in hardware check to make sure this condition is met. Also, the TCR
213 * must be programmed with this condition before auto RTS or software flow
214 * control is enabled to avoid spurious operation of the device.
216 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
217 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
223 * trigger levels. Trigger levels from 4 characters to 60 characters are
224 * available with a granularity of four.
226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
228 * the trigger level defined in FCR is discarded. This applies to both transmit
229 * FIFO and receive FIFO trigger level setting.
231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
232 * default state, that is, '00'.
234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
237 /* IOControl register bits (Only 750/760) */
238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
239 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
240 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
242 /* EFCR register bits */
243 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
246 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
247 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
248 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
249 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
250 * 0 = rate upto 115.2 kbit/s
252 * 1 = rate upto 1.152 Mbit/s
256 /* EFR register bits */
257 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
258 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
259 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
260 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
261 * and writing to IER[7:4],
264 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
265 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
267 * SWFLOW bits 3 & 2 table:
268 * 00 -> no transmitter flow
270 * 01 -> transmitter generates
272 * 10 -> transmitter generates
274 * 11 -> transmitter generates
275 * XON1, XON2, XOFF1 and
278 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
279 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
281 * SWFLOW bits 3 & 2 table:
282 * 00 -> no received flow
284 * 01 -> receiver compares
286 * 10 -> receiver compares
288 * 11 -> receiver compares
289 * XON1, XON2, XOFF1 and
292 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
293 SC16IS7XX_EFR_AUTOCTS_BIT | \
294 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
295 SC16IS7XX_EFR_SWFLOW3_BIT | \
296 SC16IS7XX_EFR_SWFLOW2_BIT | \
297 SC16IS7XX_EFR_SWFLOW1_BIT | \
298 SC16IS7XX_EFR_SWFLOW0_BIT)
301 /* Misc definitions */
302 #define SC16IS7XX_FIFO_SIZE (64)
303 #define SC16IS7XX_REG_SHIFT 2
305 struct sc16is7xx_devtype {
312 #define SC16IS7XX_RECONF_MD (1 << 0)
313 #define SC16IS7XX_RECONF_IER (1 << 1)
314 #define SC16IS7XX_RECONF_RS485 (1 << 2)
316 struct sc16is7xx_one_config {
322 struct sc16is7xx_one {
323 struct uart_port port;
325 struct kthread_work tx_work;
326 struct kthread_work reg_work;
327 struct kthread_delayed_work ms_work;
328 struct sc16is7xx_one_config config;
330 unsigned int old_mctrl;
333 struct sc16is7xx_port {
334 const struct sc16is7xx_devtype *devtype;
335 struct regmap *regmap;
337 #ifdef CONFIG_GPIOLIB
338 struct gpio_chip gpio;
340 unsigned char buf[SC16IS7XX_FIFO_SIZE];
341 struct kthread_worker kworker;
342 struct task_struct *kworker_task;
343 struct mutex efr_lock;
344 struct sc16is7xx_one p[];
347 static unsigned long sc16is7xx_lines;
349 static struct uart_driver sc16is7xx_uart = {
350 .owner = THIS_MODULE,
352 .nr = SC16IS7XX_MAX_DEVS,
355 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit);
356 static void sc16is7xx_stop_tx(struct uart_port *port);
358 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
359 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
361 static int sc16is7xx_line(struct uart_port *port)
363 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
368 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
370 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
371 unsigned int val = 0;
372 const u8 line = sc16is7xx_line(port);
374 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
379 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
381 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
382 const u8 line = sc16is7xx_line(port);
384 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
387 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
389 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
390 const u8 line = sc16is7xx_line(port);
391 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
393 regcache_cache_bypass(s->regmap, true);
394 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
395 regcache_cache_bypass(s->regmap, false);
398 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
400 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
401 const u8 line = sc16is7xx_line(port);
402 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
405 * Don't send zero-length data, at least on SPI it confuses the chip
406 * delivering wrong TXLVL data.
408 if (unlikely(!to_send))
411 regcache_cache_bypass(s->regmap, true);
412 regmap_raw_write(s->regmap, addr, s->buf, to_send);
413 regcache_cache_bypass(s->regmap, false);
416 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
419 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
420 const u8 line = sc16is7xx_line(port);
422 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
426 static int sc16is7xx_alloc_line(void)
430 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
432 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
433 if (!test_and_set_bit(i, &sc16is7xx_lines))
439 static void sc16is7xx_power(struct uart_port *port, int on)
441 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
442 SC16IS7XX_IER_SLEEP_BIT,
443 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
446 static const struct sc16is7xx_devtype sc16is74x_devtype = {
453 static const struct sc16is7xx_devtype sc16is750_devtype = {
460 static const struct sc16is7xx_devtype sc16is752_devtype = {
467 static const struct sc16is7xx_devtype sc16is760_devtype = {
474 static const struct sc16is7xx_devtype sc16is762_devtype = {
481 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
483 switch (reg >> SC16IS7XX_REG_SHIFT) {
484 case SC16IS7XX_RHR_REG:
485 case SC16IS7XX_IIR_REG:
486 case SC16IS7XX_LSR_REG:
487 case SC16IS7XX_MSR_REG:
488 case SC16IS7XX_TXLVL_REG:
489 case SC16IS7XX_RXLVL_REG:
490 case SC16IS7XX_IOSTATE_REG:
499 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
501 switch (reg >> SC16IS7XX_REG_SHIFT) {
502 case SC16IS7XX_RHR_REG:
511 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
513 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
516 unsigned long clk = port->uartclk, div = clk / 16 / baud;
519 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
523 /* In an amazing feat of design, the Enhanced Features Register shares
524 * the address of the Interrupt Identification Register, and is
525 * switched in by writing a magic value (0xbf) to the Line Control
526 * Register. Any interrupt firing during this time will see the EFR
527 * where it expects the IIR to be, leading to "Unexpected interrupt"
530 * Prevent this possibility by claiming a mutex while accessing the
531 * EFR, and claiming the same mutex from within the interrupt handler.
532 * This is similar to disabling the interrupt, but that doesn't work
533 * because the bulk of the interrupt processing is run as a workqueue
534 * job in thread context.
536 mutex_lock(&s->efr_lock);
538 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
540 /* Open the LCR divisors for configuration */
541 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
542 SC16IS7XX_LCR_CONF_MODE_B);
544 /* Enable enhanced features */
545 regcache_cache_bypass(s->regmap, true);
546 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
547 SC16IS7XX_EFR_ENABLE_BIT,
548 SC16IS7XX_EFR_ENABLE_BIT);
550 regcache_cache_bypass(s->regmap, false);
552 /* Put LCR back to the normal mode */
553 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
555 mutex_unlock(&s->efr_lock);
557 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
558 SC16IS7XX_MCR_CLKSEL_BIT,
561 /* Open the LCR divisors for configuration */
562 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
563 SC16IS7XX_LCR_CONF_MODE_A);
565 /* Write the new divisor */
566 regcache_cache_bypass(s->regmap, true);
567 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
568 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
569 regcache_cache_bypass(s->regmap, false);
571 /* Put LCR back to the normal mode */
572 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
574 return DIV_ROUND_CLOSEST(clk / 16, div);
577 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
580 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
581 unsigned int lsr = 0, ch, flag, bytes_read, i;
582 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
584 if (unlikely(rxlen >= sizeof(s->buf))) {
585 dev_warn_ratelimited(port->dev,
586 "ttySC%i: Possible RX FIFO overrun: %d\n",
588 port->icount.buf_overrun++;
589 /* Ensure sanity of RX level */
590 rxlen = sizeof(s->buf);
594 /* Only read lsr if there are possible errors in FIFO */
596 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
597 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
598 read_lsr = false; /* No errors left in FIFO */
603 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
606 sc16is7xx_fifo_read(port, rxlen);
610 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
616 if (lsr & SC16IS7XX_LSR_BI_BIT) {
618 if (uart_handle_break(port))
620 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
621 port->icount.parity++;
622 else if (lsr & SC16IS7XX_LSR_FE_BIT)
623 port->icount.frame++;
624 else if (lsr & SC16IS7XX_LSR_OE_BIT)
625 port->icount.overrun++;
627 lsr &= port->read_status_mask;
628 if (lsr & SC16IS7XX_LSR_BI_BIT)
630 else if (lsr & SC16IS7XX_LSR_PE_BIT)
632 else if (lsr & SC16IS7XX_LSR_FE_BIT)
634 else if (lsr & SC16IS7XX_LSR_OE_BIT)
638 for (i = 0; i < bytes_read; ++i) {
640 if (uart_handle_sysrq_char(port, ch))
643 if (lsr & port->ignore_status_mask)
646 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
652 tty_flip_buffer_push(&port->state->port);
655 static void sc16is7xx_handle_tx(struct uart_port *port)
657 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
658 struct circ_buf *xmit = &port->state->xmit;
659 unsigned int txlen, to_send, i;
662 if (unlikely(port->x_char)) {
663 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
669 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
670 spin_lock_irqsave(&port->lock, flags);
671 sc16is7xx_stop_tx(port);
672 spin_unlock_irqrestore(&port->lock, flags);
676 /* Get length of data pending in circular buffer */
677 to_send = uart_circ_chars_pending(xmit);
678 if (likely(to_send)) {
679 /* Limit to size of TX FIFO */
680 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
681 if (txlen > SC16IS7XX_FIFO_SIZE) {
682 dev_err_ratelimited(port->dev,
683 "chip reports %d free bytes in TX fifo, but it only has %d",
684 txlen, SC16IS7XX_FIFO_SIZE);
687 to_send = (to_send > txlen) ? txlen : to_send;
689 /* Add data to send */
690 port->icount.tx += to_send;
692 /* Convert to linear buffer */
693 for (i = 0; i < to_send; ++i) {
694 s->buf[i] = xmit->buf[xmit->tail];
695 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
698 sc16is7xx_fifo_write(port, to_send);
701 spin_lock_irqsave(&port->lock, flags);
702 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
703 uart_write_wakeup(port);
705 if (uart_circ_empty(xmit))
706 sc16is7xx_stop_tx(port);
707 spin_unlock_irqrestore(&port->lock, flags);
710 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
712 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
713 unsigned int mctrl = 0;
715 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
716 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
717 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0;
718 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0;
722 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
724 struct uart_port *port = &one->port;
725 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
727 unsigned int status, changed;
729 lockdep_assert_held_once(&s->efr_lock);
731 status = sc16is7xx_get_hwmctrl(port);
732 changed = status ^ one->old_mctrl;
737 one->old_mctrl = status;
739 spin_lock_irqsave(&port->lock, flags);
740 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
742 if (changed & TIOCM_DSR)
744 if (changed & TIOCM_CAR)
745 uart_handle_dcd_change(port, status & TIOCM_CAR);
746 if (changed & TIOCM_CTS)
747 uart_handle_cts_change(port, status & TIOCM_CTS);
749 wake_up_interruptible(&port->state->port.delta_msr_wait);
750 spin_unlock_irqrestore(&port->lock, flags);
753 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
755 struct uart_port *port = &s->p[portno].port;
758 unsigned int iir, rxlen;
759 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
761 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
762 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
765 iir &= SC16IS7XX_IIR_ID_MASK;
768 case SC16IS7XX_IIR_RDI_SRC:
769 case SC16IS7XX_IIR_RLSE_SRC:
770 case SC16IS7XX_IIR_RTOI_SRC:
771 case SC16IS7XX_IIR_XOFFI_SRC:
772 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
774 sc16is7xx_handle_rx(port, rxlen, iir);
776 /* CTSRTS interrupt comes only when CTS goes inactive */
777 case SC16IS7XX_IIR_CTSRTS_SRC:
778 case SC16IS7XX_IIR_MSI_SRC:
779 sc16is7xx_update_mlines(one);
781 case SC16IS7XX_IIR_THRI_SRC:
782 sc16is7xx_handle_tx(port);
785 dev_err_ratelimited(port->dev,
786 "ttySC%i: Unexpected interrupt: %x",
794 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
796 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
798 mutex_lock(&s->efr_lock);
801 bool keep_polling = false;
804 for (i = 0; i < s->devtype->nr_uart; ++i)
805 keep_polling |= sc16is7xx_port_irq(s, i);
810 mutex_unlock(&s->efr_lock);
815 static void sc16is7xx_tx_proc(struct kthread_work *ws)
817 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
818 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
821 if ((port->rs485.flags & SER_RS485_ENABLED) &&
822 (port->rs485.delay_rts_before_send > 0))
823 msleep(port->rs485.delay_rts_before_send);
825 mutex_lock(&s->efr_lock);
826 sc16is7xx_handle_tx(port);
827 mutex_unlock(&s->efr_lock);
829 spin_lock_irqsave(&port->lock, flags);
830 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
831 spin_unlock_irqrestore(&port->lock, flags);
834 static void sc16is7xx_reconf_rs485(struct uart_port *port)
836 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
837 SC16IS7XX_EFCR_RTS_INVERT_BIT;
839 struct serial_rs485 *rs485 = &port->rs485;
840 unsigned long irqflags;
842 spin_lock_irqsave(&port->lock, irqflags);
843 if (rs485->flags & SER_RS485_ENABLED) {
844 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
846 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
847 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
849 spin_unlock_irqrestore(&port->lock, irqflags);
851 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
854 static void sc16is7xx_reg_proc(struct kthread_work *ws)
856 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
857 struct sc16is7xx_one_config config;
858 unsigned long irqflags;
860 spin_lock_irqsave(&one->port.lock, irqflags);
861 config = one->config;
862 memset(&one->config, 0, sizeof(one->config));
863 spin_unlock_irqrestore(&one->port.lock, irqflags);
865 if (config.flags & SC16IS7XX_RECONF_MD) {
868 /* Device ignores RTS setting when hardware flow is enabled */
869 if (one->port.mctrl & TIOCM_RTS)
870 mcr |= SC16IS7XX_MCR_RTS_BIT;
872 if (one->port.mctrl & TIOCM_DTR)
873 mcr |= SC16IS7XX_MCR_DTR_BIT;
875 if (one->port.mctrl & TIOCM_LOOP)
876 mcr |= SC16IS7XX_MCR_LOOP_BIT;
877 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
878 SC16IS7XX_MCR_RTS_BIT |
879 SC16IS7XX_MCR_DTR_BIT |
880 SC16IS7XX_MCR_LOOP_BIT,
884 if (config.flags & SC16IS7XX_RECONF_IER)
885 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
886 config.ier_mask, config.ier_val);
888 if (config.flags & SC16IS7XX_RECONF_RS485)
889 sc16is7xx_reconf_rs485(&one->port);
892 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
894 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
895 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
897 lockdep_assert_held_once(&port->lock);
899 one->config.flags |= SC16IS7XX_RECONF_IER;
900 one->config.ier_mask |= bit;
901 one->config.ier_val &= ~bit;
902 kthread_queue_work(&s->kworker, &one->reg_work);
905 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
907 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
908 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
910 lockdep_assert_held_once(&port->lock);
912 one->config.flags |= SC16IS7XX_RECONF_IER;
913 one->config.ier_mask |= bit;
914 one->config.ier_val |= bit;
915 kthread_queue_work(&s->kworker, &one->reg_work);
918 static void sc16is7xx_stop_tx(struct uart_port *port)
920 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
923 static void sc16is7xx_stop_rx(struct uart_port *port)
925 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
928 static void sc16is7xx_ms_proc(struct kthread_work *ws)
930 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);
931 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
933 if (one->port.state) {
934 mutex_lock(&s->efr_lock);
935 sc16is7xx_update_mlines(one);
936 mutex_unlock(&s->efr_lock);
938 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
942 static void sc16is7xx_enable_ms(struct uart_port *port)
944 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
945 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
947 lockdep_assert_held_once(&port->lock);
949 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
952 static void sc16is7xx_start_tx(struct uart_port *port)
954 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
955 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
957 kthread_queue_work(&s->kworker, &one->tx_work);
960 static void sc16is7xx_throttle(struct uart_port *port)
965 * Hardware flow control is enabled and thus the device ignores RTS
966 * value set in MCR register. Stop reading data from RX FIFO so the
967 * AutoRTS feature will de-activate RTS output.
969 spin_lock_irqsave(&port->lock, flags);
970 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
971 spin_unlock_irqrestore(&port->lock, flags);
974 static void sc16is7xx_unthrottle(struct uart_port *port)
978 spin_lock_irqsave(&port->lock, flags);
979 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
980 spin_unlock_irqrestore(&port->lock, flags);
983 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
987 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
989 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
992 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
994 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
996 /* Called with port lock taken so we can only return cached value */
997 return one->old_mctrl;
1000 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
1002 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1003 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1005 one->config.flags |= SC16IS7XX_RECONF_MD;
1006 kthread_queue_work(&s->kworker, &one->reg_work);
1009 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
1011 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
1012 SC16IS7XX_LCR_TXBREAK_BIT,
1013 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
1016 static void sc16is7xx_set_termios(struct uart_port *port,
1017 struct ktermios *termios,
1018 struct ktermios *old)
1020 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1021 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1022 unsigned int lcr, flow = 0;
1024 unsigned long flags;
1026 kthread_cancel_delayed_work_sync(&one->ms_work);
1028 /* Mask termios capabilities we don't support */
1029 termios->c_cflag &= ~CMSPAR;
1032 switch (termios->c_cflag & CSIZE) {
1034 lcr = SC16IS7XX_LCR_WORD_LEN_5;
1037 lcr = SC16IS7XX_LCR_WORD_LEN_6;
1040 lcr = SC16IS7XX_LCR_WORD_LEN_7;
1043 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1046 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1047 termios->c_cflag &= ~CSIZE;
1048 termios->c_cflag |= CS8;
1053 if (termios->c_cflag & PARENB) {
1054 lcr |= SC16IS7XX_LCR_PARITY_BIT;
1055 if (!(termios->c_cflag & PARODD))
1056 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1060 if (termios->c_cflag & CSTOPB)
1061 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1063 /* Set read status mask */
1064 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1065 if (termios->c_iflag & INPCK)
1066 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1067 SC16IS7XX_LSR_FE_BIT;
1068 if (termios->c_iflag & (BRKINT | PARMRK))
1069 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1071 /* Set status ignore mask */
1072 port->ignore_status_mask = 0;
1073 if (termios->c_iflag & IGNBRK)
1074 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1075 if (!(termios->c_cflag & CREAD))
1076 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1078 /* As above, claim the mutex while accessing the EFR. */
1079 mutex_lock(&s->efr_lock);
1081 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1082 SC16IS7XX_LCR_CONF_MODE_B);
1084 /* Configure flow control */
1085 regcache_cache_bypass(s->regmap, true);
1086 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1087 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1089 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1090 if (termios->c_cflag & CRTSCTS) {
1091 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1092 SC16IS7XX_EFR_AUTORTS_BIT;
1093 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1095 if (termios->c_iflag & IXON)
1096 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1097 if (termios->c_iflag & IXOFF)
1098 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1100 sc16is7xx_port_update(port,
1102 SC16IS7XX_EFR_FLOWCTRL_BITS,
1104 regcache_cache_bypass(s->regmap, false);
1106 /* Update LCR register */
1107 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1109 mutex_unlock(&s->efr_lock);
1111 /* Get baud rate generator configuration */
1112 baud = uart_get_baud_rate(port, termios, old,
1113 port->uartclk / 16 / 4 / 0xffff,
1114 port->uartclk / 16);
1116 /* Setup baudrate generator */
1117 baud = sc16is7xx_set_baud(port, baud);
1119 spin_lock_irqsave(&port->lock, flags);
1121 /* Update timeout according to new baud rate */
1122 uart_update_timeout(port, termios->c_cflag, baud);
1124 if (UART_ENABLE_MS(port, termios->c_cflag))
1125 sc16is7xx_enable_ms(port);
1127 spin_unlock_irqrestore(&port->lock, flags);
1130 static int sc16is7xx_config_rs485(struct uart_port *port,
1131 struct serial_rs485 *rs485)
1133 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1134 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1136 if (rs485->flags & SER_RS485_ENABLED) {
1137 bool rts_during_rx, rts_during_tx;
1139 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
1140 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
1142 if (rts_during_rx == rts_during_tx)
1144 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
1145 rts_during_tx, rts_during_rx);
1148 * RTS signal is handled by HW, it's timing can't be influenced.
1149 * However, it's sometimes useful to delay TX even without RTS
1150 * control therefore we try to handle .delay_rts_before_send.
1152 if (rs485->delay_rts_after_send)
1156 port->rs485 = *rs485;
1157 one->config.flags |= SC16IS7XX_RECONF_RS485;
1158 kthread_queue_work(&s->kworker, &one->reg_work);
1163 static int sc16is7xx_startup(struct uart_port *port)
1165 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1166 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1168 unsigned long flags;
1170 sc16is7xx_power(port, 1);
1173 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1174 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1176 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1177 SC16IS7XX_FCR_FIFO_BIT);
1180 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1181 SC16IS7XX_LCR_CONF_MODE_B);
1183 regcache_cache_bypass(s->regmap, true);
1185 /* Enable write access to enhanced features and internal clock div */
1186 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1187 SC16IS7XX_EFR_ENABLE_BIT,
1188 SC16IS7XX_EFR_ENABLE_BIT);
1190 /* Enable TCR/TLR */
1191 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1192 SC16IS7XX_MCR_TCRTLR_BIT,
1193 SC16IS7XX_MCR_TCRTLR_BIT);
1195 /* Configure flow control levels */
1196 /* Flow control halt level 48, resume level 24 */
1197 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1198 SC16IS7XX_TCR_RX_RESUME(24) |
1199 SC16IS7XX_TCR_RX_HALT(48));
1201 regcache_cache_bypass(s->regmap, false);
1203 /* Now, initialize the UART */
1204 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1206 /* Enable IrDA mode if requested in DT */
1207 /* This bit must be written with LCR[7] = 0 */
1208 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1209 SC16IS7XX_MCR_IRDA_BIT,
1211 SC16IS7XX_MCR_IRDA_BIT : 0);
1213 /* Enable the Rx and Tx FIFO */
1214 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1215 SC16IS7XX_EFCR_RXDISABLE_BIT |
1216 SC16IS7XX_EFCR_TXDISABLE_BIT,
1219 /* Enable RX, CTS change and modem lines interrupts */
1220 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1221 SC16IS7XX_IER_MSI_BIT;
1222 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1224 /* Enable modem status polling */
1225 spin_lock_irqsave(&port->lock, flags);
1226 sc16is7xx_enable_ms(port);
1227 spin_unlock_irqrestore(&port->lock, flags);
1232 static void sc16is7xx_shutdown(struct uart_port *port)
1234 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1235 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1237 kthread_cancel_delayed_work_sync(&one->ms_work);
1239 /* Disable all interrupts */
1240 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1241 /* Disable TX/RX, clear auto RS485 and RTS invert */
1242 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1243 SC16IS7XX_EFCR_RXDISABLE_BIT |
1244 SC16IS7XX_EFCR_TXDISABLE_BIT |
1245 SC16IS7XX_EFCR_AUTO_RS485_BIT |
1246 SC16IS7XX_EFCR_RTS_INVERT_BIT,
1247 SC16IS7XX_EFCR_RXDISABLE_BIT |
1248 SC16IS7XX_EFCR_TXDISABLE_BIT);
1250 sc16is7xx_power(port, 0);
1252 kthread_flush_worker(&s->kworker);
1255 static const char *sc16is7xx_type(struct uart_port *port)
1257 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1259 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1262 static int sc16is7xx_request_port(struct uart_port *port)
1268 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1270 if (flags & UART_CONFIG_TYPE)
1271 port->type = PORT_SC16IS7XX;
1274 static int sc16is7xx_verify_port(struct uart_port *port,
1275 struct serial_struct *s)
1277 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1279 if (s->irq != port->irq)
1285 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1286 unsigned int oldstate)
1288 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1291 static void sc16is7xx_null_void(struct uart_port *port)
1296 static const struct uart_ops sc16is7xx_ops = {
1297 .tx_empty = sc16is7xx_tx_empty,
1298 .set_mctrl = sc16is7xx_set_mctrl,
1299 .get_mctrl = sc16is7xx_get_mctrl,
1300 .stop_tx = sc16is7xx_stop_tx,
1301 .start_tx = sc16is7xx_start_tx,
1302 .throttle = sc16is7xx_throttle,
1303 .unthrottle = sc16is7xx_unthrottle,
1304 .stop_rx = sc16is7xx_stop_rx,
1305 .enable_ms = sc16is7xx_enable_ms,
1306 .break_ctl = sc16is7xx_break_ctl,
1307 .startup = sc16is7xx_startup,
1308 .shutdown = sc16is7xx_shutdown,
1309 .set_termios = sc16is7xx_set_termios,
1310 .type = sc16is7xx_type,
1311 .request_port = sc16is7xx_request_port,
1312 .release_port = sc16is7xx_null_void,
1313 .config_port = sc16is7xx_config_port,
1314 .verify_port = sc16is7xx_verify_port,
1318 #ifdef CONFIG_GPIOLIB
1319 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1322 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1323 struct uart_port *port = &s->p[0].port;
1325 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1327 return !!(val & BIT(offset));
1330 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1332 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1333 struct uart_port *port = &s->p[0].port;
1335 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1336 val ? BIT(offset) : 0);
1339 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1342 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1343 struct uart_port *port = &s->p[0].port;
1345 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1350 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1351 unsigned offset, int val)
1353 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1354 struct uart_port *port = &s->p[0].port;
1355 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1358 state |= BIT(offset);
1360 state &= ~BIT(offset);
1361 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1362 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1369 static int sc16is7xx_probe(struct device *dev,
1370 const struct sc16is7xx_devtype *devtype,
1371 struct regmap *regmap, int irq)
1373 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1377 struct sc16is7xx_port *s;
1380 return PTR_ERR(regmap);
1383 * This device does not have an identification register that would
1384 * tell us if we are really connected to the correct device.
1385 * The best we can do is to check if communication is at all possible.
1387 ret = regmap_read(regmap,
1388 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val);
1390 return -EPROBE_DEFER;
1392 /* Alloc port structure */
1393 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1395 dev_err(dev, "Error allocating port structure\n");
1399 /* Always ask for fixed clock rate from a property. */
1400 device_property_read_u32(dev, "clock-frequency", &uartclk);
1402 s->clk = devm_clk_get_optional(dev, NULL);
1404 return PTR_ERR(s->clk);
1406 ret = clk_prepare_enable(s->clk);
1410 freq = clk_get_rate(s->clk);
1417 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1423 s->devtype = devtype;
1424 dev_set_drvdata(dev, s);
1425 mutex_init(&s->efr_lock);
1427 kthread_init_worker(&s->kworker);
1428 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1430 if (IS_ERR(s->kworker_task)) {
1431 ret = PTR_ERR(s->kworker_task);
1434 sched_set_fifo(s->kworker_task);
1436 #ifdef CONFIG_GPIOLIB
1437 if (devtype->nr_gpio) {
1438 /* Setup GPIO cotroller */
1439 s->gpio.owner = THIS_MODULE;
1440 s->gpio.parent = dev;
1441 s->gpio.label = dev_name(dev);
1442 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1443 s->gpio.get = sc16is7xx_gpio_get;
1444 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1445 s->gpio.set = sc16is7xx_gpio_set;
1447 s->gpio.ngpio = devtype->nr_gpio;
1448 s->gpio.can_sleep = 1;
1449 ret = gpiochip_add_data(&s->gpio, s);
1455 /* reset device, purging any pending irq / data */
1456 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1457 SC16IS7XX_IOCONTROL_SRESET_BIT);
1459 for (i = 0; i < devtype->nr_uart; ++i) {
1461 /* Initialize port data */
1462 s->p[i].port.dev = dev;
1463 s->p[i].port.irq = irq;
1464 s->p[i].port.type = PORT_SC16IS7XX;
1465 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1466 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1467 s->p[i].port.iobase = i;
1468 s->p[i].port.iotype = UPIO_PORT;
1469 s->p[i].port.uartclk = freq;
1470 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1471 s->p[i].port.ops = &sc16is7xx_ops;
1472 s->p[i].old_mctrl = 0;
1473 s->p[i].port.line = sc16is7xx_alloc_line();
1475 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1480 /* Disable all interrupts */
1481 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1483 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1484 SC16IS7XX_EFCR_RXDISABLE_BIT |
1485 SC16IS7XX_EFCR_TXDISABLE_BIT);
1487 /* Use GPIO lines as modem status registers */
1488 if (devtype->has_mctrl)
1489 sc16is7xx_port_write(&s->p[i].port,
1490 SC16IS7XX_IOCONTROL_REG,
1491 SC16IS7XX_IOCONTROL_MODEM_BIT);
1493 /* Initialize kthread work structs */
1494 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1495 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1496 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);
1498 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1501 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1502 SC16IS7XX_LCR_CONF_MODE_B);
1504 regcache_cache_bypass(s->regmap, true);
1506 /* Enable write access to enhanced features */
1507 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1508 SC16IS7XX_EFR_ENABLE_BIT);
1510 regcache_cache_bypass(s->regmap, false);
1512 /* Restore access to general registers */
1513 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1515 /* Go to suspend mode */
1516 sc16is7xx_power(&s->p[i].port, 0);
1520 struct property *prop;
1524 of_property_for_each_u32(dev->of_node, "irda-mode-ports",
1526 if (u < devtype->nr_uart)
1527 s->p[u].irda_mode = true;
1531 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1532 * If that succeeds, we can allow sharing the interrupt as well.
1533 * In case the interrupt controller doesn't support that, we fall
1534 * back to a non-shared falling-edge trigger.
1536 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1537 IRQF_TRIGGER_LOW | IRQF_SHARED |
1543 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1544 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1550 for (i--; i >= 0; i--) {
1551 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1552 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1555 #ifdef CONFIG_GPIOLIB
1556 if (devtype->nr_gpio)
1557 gpiochip_remove(&s->gpio);
1561 kthread_stop(s->kworker_task);
1564 clk_disable_unprepare(s->clk);
1569 static void sc16is7xx_remove(struct device *dev)
1571 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1574 #ifdef CONFIG_GPIOLIB
1575 if (s->devtype->nr_gpio)
1576 gpiochip_remove(&s->gpio);
1579 for (i = 0; i < s->devtype->nr_uart; i++) {
1580 kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1581 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1582 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1583 sc16is7xx_power(&s->p[i].port, 0);
1586 kthread_flush_worker(&s->kworker);
1587 kthread_stop(s->kworker_task);
1589 clk_disable_unprepare(s->clk);
1592 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1593 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1594 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1595 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1596 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1597 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1598 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1601 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1603 static struct regmap_config regcfg = {
1607 .cache_type = REGCACHE_RBTREE,
1608 .volatile_reg = sc16is7xx_regmap_volatile,
1609 .precious_reg = sc16is7xx_regmap_precious,
1612 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1613 static int sc16is7xx_spi_probe(struct spi_device *spi)
1615 const struct sc16is7xx_devtype *devtype;
1616 struct regmap *regmap;
1620 spi->bits_per_word = 8;
1621 /* only supports mode 0 on SC16IS762 */
1622 spi->mode = spi->mode ? : SPI_MODE_0;
1623 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1624 ret = spi_setup(spi);
1628 if (spi->dev.of_node) {
1629 devtype = device_get_match_data(&spi->dev);
1633 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1635 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1638 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1639 (devtype->nr_uart - 1);
1640 regmap = devm_regmap_init_spi(spi, ®cfg);
1642 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq);
1645 static void sc16is7xx_spi_remove(struct spi_device *spi)
1647 sc16is7xx_remove(&spi->dev);
1650 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1651 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1652 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1653 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1654 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1655 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1656 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1657 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1661 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1663 static struct spi_driver sc16is7xx_spi_uart_driver = {
1665 .name = SC16IS7XX_NAME,
1666 .of_match_table = sc16is7xx_dt_ids,
1668 .probe = sc16is7xx_spi_probe,
1669 .remove = sc16is7xx_spi_remove,
1670 .id_table = sc16is7xx_spi_id_table,
1673 MODULE_ALIAS("spi:sc16is7xx");
1676 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1677 static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1678 const struct i2c_device_id *id)
1680 const struct sc16is7xx_devtype *devtype;
1681 struct regmap *regmap;
1683 if (i2c->dev.of_node) {
1684 devtype = device_get_match_data(&i2c->dev);
1688 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1691 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1692 (devtype->nr_uart - 1);
1693 regmap = devm_regmap_init_i2c(i2c, ®cfg);
1695 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq);
1698 static int sc16is7xx_i2c_remove(struct i2c_client *client)
1700 sc16is7xx_remove(&client->dev);
1705 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1706 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1707 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1708 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1709 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1710 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1711 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1712 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1715 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1717 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1719 .name = SC16IS7XX_NAME,
1720 .of_match_table = sc16is7xx_dt_ids,
1722 .probe = sc16is7xx_i2c_probe,
1723 .remove = sc16is7xx_i2c_remove,
1724 .id_table = sc16is7xx_i2c_id_table,
1729 static int __init sc16is7xx_init(void)
1733 ret = uart_register_driver(&sc16is7xx_uart);
1735 pr_err("Registering UART driver failed\n");
1739 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1740 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1742 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1747 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1748 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1750 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1756 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1759 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1760 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1763 uart_unregister_driver(&sc16is7xx_uart);
1766 module_init(sc16is7xx_init);
1768 static void __exit sc16is7xx_exit(void)
1770 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1771 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1774 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1775 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1777 uart_unregister_driver(&sc16is7xx_uart);
1779 module_exit(sc16is7xx_exit);
1781 MODULE_LICENSE("GPL");
1782 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1783 MODULE_DESCRIPTION("SC16IS7XX serial driver");