drivers/tty/serial/samsung_tty.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7  */
   8
   9 /* Note on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22  */
  23
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/ioport.h>
  29 #include <linux/io.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/init.h>
  32 #include <linux/sysrq.h>
  33 #include <linux/console.h>
  34 #include <linux/tty.h>
  35 #include <linux/tty_flip.h>
  36 #include <linux/serial_core.h>
  37 #include <linux/serial.h>
  38 #include <linux/serial_s3c.h>
  39 #include <linux/delay.h>
  40 #include <linux/clk.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/of.h>
  43 #include <asm/irq.h>
  44
  45 /* UART name and device definitions */
  46
  47 #define S3C24XX_SERIAL_NAME     "ttySAC"
  48 #define S3C24XX_SERIAL_MAJOR    204
  49 #define S3C24XX_SERIAL_MINOR    64
  50
  51 #define S3C24XX_TX_PIO                  1
  52 #define S3C24XX_TX_DMA                  2
  53 #define S3C24XX_RX_PIO                  1
  54 #define S3C24XX_RX_DMA                  2
  55
  56 /* flag to ignore all characters coming in */
  57 #define RXSTAT_DUMMY_READ (0x10000000)
  58
  59 enum s3c24xx_port_type {
  60         TYPE_S3C24XX,
  61         TYPE_S3C6400,
  62         TYPE_APPLE_S5L,
  63 };
  64
  65 struct s3c24xx_uart_info {
  66         char                    *name;
  67         enum s3c24xx_port_type  type;
  68         unsigned int            port_type;
  69         unsigned int            fifosize;
  70         unsigned long           rx_fifomask;
  71         unsigned long           rx_fifoshift;
  72         unsigned long           rx_fifofull;
  73         unsigned long           tx_fifomask;
  74         unsigned long           tx_fifoshift;
  75         unsigned long           tx_fifofull;
  76         unsigned int            def_clk_sel;
  77         unsigned long           num_clks;
  78         unsigned long           clksel_mask;
  79         unsigned long           clksel_shift;
  80         unsigned long           ucon_mask;
  81
  82         /* uart port features */
  83
  84         unsigned int            has_divslot:1;
  85 };
  86
  87 struct s3c24xx_serial_drv_data {
  88         struct s3c24xx_uart_info        *info;
  89         struct s3c2410_uartcfg          *def_cfg;
  90         unsigned int                    fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
  91 };
  92
  93 struct s3c24xx_uart_dma {
  94         unsigned int                    rx_chan_id;
  95         unsigned int                    tx_chan_id;
  96
  97         struct dma_slave_config         rx_conf;
  98         struct dma_slave_config         tx_conf;
  99
 100         struct dma_chan                 *rx_chan;
 101         struct dma_chan                 *tx_chan;
 102
 103         dma_addr_t                      rx_addr;
 104         dma_addr_t                      tx_addr;
 105
 106         dma_cookie_t                    rx_cookie;
 107         dma_cookie_t                    tx_cookie;
 108
 109         char                            *rx_buf;
 110
 111         dma_addr_t                      tx_transfer_addr;
 112
 113         size_t                          rx_size;
 114         size_t                          tx_size;
 115
 116         struct dma_async_tx_descriptor  *tx_desc;
 117         struct dma_async_tx_descriptor  *rx_desc;
 118
 119         int                             tx_bytes_requested;
 120         int                             rx_bytes_requested;
 121 };
 122
 123 struct s3c24xx_uart_port {
 124         unsigned char                   rx_claimed;
 125         unsigned char                   tx_claimed;
 126         unsigned char                   rx_enabled;
 127         unsigned char                   tx_enabled;
 128         unsigned int                    pm_level;
 129         unsigned long                   baudclk_rate;
 130         unsigned int                    min_dma_size;
 131
 132         unsigned int                    rx_irq;
 133         unsigned int                    tx_irq;
 134
 135         unsigned int                    tx_in_progress;
 136         unsigned int                    tx_mode;
 137         unsigned int                    rx_mode;
 138
 139         struct s3c24xx_uart_info        *info;
 140         struct clk                      *clk;
 141         struct clk                      *baudclk;
 142         struct uart_port                port;
 143         struct s3c24xx_serial_drv_data  *drv_data;
 144
 145         /* reference to platform data */
 146         struct s3c2410_uartcfg          *cfg;
 147
 148         struct s3c24xx_uart_dma         *dma;
 149
 150 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 151         struct notifier_block           freq_transition;
 152 #endif
 153 };
 154
 155 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
 156
 157 /* conversion functions */
 158
 159 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 160
 161 /* register access controls */
 162
 163 #define portaddr(port, reg) ((port)->membase + (reg))
 164 #define portaddrl(port, reg) \
 165         ((unsigned long *)(unsigned long)((port)->membase + (reg)))
 166
 167 static u32 rd_reg(struct uart_port *port, u32 reg)
 168 {
 169         switch (port->iotype) {
 170         case UPIO_MEM:
 171                 return readb_relaxed(portaddr(port, reg));
 172         case UPIO_MEM32:
 173                 return readl_relaxed(portaddr(port, reg));
 174         default:
 175                 return 0;
 176         }
 177         return 0;
 178 }
 179
 180 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 181
 182 static void wr_reg(struct uart_port *port, u32 reg, u32 val)
 183 {
 184         switch (port->iotype) {
 185         case UPIO_MEM:
 186                 writeb_relaxed(val, portaddr(port, reg));
 187                 break;
 188         case UPIO_MEM32:
 189                 writel_relaxed(val, portaddr(port, reg));
 190                 break;
 191         }
 192 }
 193
 194 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 195
 196 /* Byte-order aware bit setting/clearing functions. */
 197
 198 static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
 199                                    unsigned int reg)
 200 {
 201         unsigned long flags;
 202         u32 val;
 203
 204         local_irq_save(flags);
 205         val = rd_regl(port, reg);
 206         val |= (1 << idx);
 207         wr_regl(port, reg, val);
 208         local_irq_restore(flags);
 209 }
 210
 211 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
 212                                      unsigned int reg)
 213 {
 214         unsigned long flags;
 215         u32 val;
 216
 217         local_irq_save(flags);
 218         val = rd_regl(port, reg);
 219         val &= ~(1 << idx);
 220         wr_regl(port, reg, val);
 221         local_irq_restore(flags);
 222 }
 223
 224 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 225 {
 226         return container_of(port, struct s3c24xx_uart_port, port);
 227 }
 228
 229 /* translate a port to the device name */
 230
 231 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 232 {
 233         return to_platform_device(port->dev)->name;
 234 }
 235
 236 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 237 {
 238         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 239 }
 240
 241 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 242 {
 243         struct s3c24xx_uart_port *ourport = to_ourport(port);
 244         unsigned long flags;
 245         unsigned int ucon, ufcon;
 246         int count = 10000;
 247
 248         spin_lock_irqsave(&port->lock, flags);
 249
 250         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 251                 udelay(100);
 252
 253         ufcon = rd_regl(port, S3C2410_UFCON);
 254         ufcon |= S3C2410_UFCON_RESETRX;
 255         wr_regl(port, S3C2410_UFCON, ufcon);
 256
 257         ucon = rd_regl(port, S3C2410_UCON);
 258         ucon |= S3C2410_UCON_RXIRQMODE;
 259         wr_regl(port, S3C2410_UCON, ucon);
 260
 261         ourport->rx_enabled = 1;
 262         spin_unlock_irqrestore(&port->lock, flags);
 263 }
 264
 265 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 266 {
 267         struct s3c24xx_uart_port *ourport = to_ourport(port);
 268         unsigned long flags;
 269         unsigned int ucon;
 270
 271         spin_lock_irqsave(&port->lock, flags);
 272
 273         ucon = rd_regl(port, S3C2410_UCON);
 274         ucon &= ~S3C2410_UCON_RXIRQMODE;
 275         wr_regl(port, S3C2410_UCON, ucon);
 276
 277         ourport->rx_enabled = 0;
 278         spin_unlock_irqrestore(&port->lock, flags);
 279 }
 280
 281 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 282 {
 283         struct s3c24xx_uart_port *ourport = to_ourport(port);
 284         struct s3c24xx_uart_dma *dma = ourport->dma;
 285         struct circ_buf *xmit = &port->state->xmit;
 286         struct dma_tx_state state;
 287         int count;
 288
 289         if (!ourport->tx_enabled)
 290                 return;
 291
 292         switch (ourport->info->type) {
 293         case TYPE_S3C6400:
 294                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 295                 break;
 296         case TYPE_APPLE_S5L:
 297                 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
 298                 break;
 299         default:
 300                 disable_irq_nosync(ourport->tx_irq);
 301                 break;
 302         }
 303
 304         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 305                 dmaengine_pause(dma->tx_chan);
 306                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 307                 dmaengine_terminate_all(dma->tx_chan);
 308                 dma_sync_single_for_cpu(ourport->port.dev,
 309                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 310                 async_tx_ack(dma->tx_desc);
 311                 count = dma->tx_bytes_requested - state.residue;
 312                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 313                 port->icount.tx += count;
 314         }
 315
 316         ourport->tx_enabled = 0;
 317         ourport->tx_in_progress = 0;
 318
 319         if (port->flags & UPF_CONS_FLOW)
 320                 s3c24xx_serial_rx_enable(port);
 321
 322         ourport->tx_mode = 0;
 323 }
 324
 325 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 326
 327 static void s3c24xx_serial_tx_dma_complete(void *args)
 328 {
 329         struct s3c24xx_uart_port *ourport = args;
 330         struct uart_port *port = &ourport->port;
 331         struct circ_buf *xmit = &port->state->xmit;
 332         struct s3c24xx_uart_dma *dma = ourport->dma;
 333         struct dma_tx_state state;
 334         unsigned long flags;
 335         int count;
 336
 337         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 338         count = dma->tx_bytes_requested - state.residue;
 339         async_tx_ack(dma->tx_desc);
 340
 341         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 342                                 dma->tx_size, DMA_TO_DEVICE);
 343
 344         spin_lock_irqsave(&port->lock, flags);
 345
 346         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 347         port->icount.tx += count;
 348         ourport->tx_in_progress = 0;
 349
 350         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 351                 uart_write_wakeup(port);
 352
 353         s3c24xx_serial_start_next_tx(ourport);
 354         spin_unlock_irqrestore(&port->lock, flags);
 355 }
 356
 357 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 358 {
 359         struct uart_port *port = &ourport->port;
 360         u32 ucon;
 361
 362         /* Mask Tx interrupt */
 363         switch (ourport->info->type) {
 364         case TYPE_S3C6400:
 365                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 366                 break;
 367         case TYPE_APPLE_S5L:
 368                 WARN_ON(1); // No DMA
 369                 break;
 370         default:
 371                 disable_irq_nosync(ourport->tx_irq);
 372                 break;
 373         }
 374
 375         /* Enable tx dma mode */
 376         ucon = rd_regl(port, S3C2410_UCON);
 377         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 378         ucon |= (dma_get_cache_alignment() >= 16) ?
 379                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 380         ucon |= S3C64XX_UCON_TXMODE_DMA;
 381         wr_regl(port,  S3C2410_UCON, ucon);
 382
 383         ourport->tx_mode = S3C24XX_TX_DMA;
 384 }
 385
 386 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 387 {
 388         struct uart_port *port = &ourport->port;
 389         u32 ucon, ufcon;
 390
 391         /* Set ufcon txtrig */
 392         ourport->tx_in_progress = S3C24XX_TX_PIO;
 393         ufcon = rd_regl(port, S3C2410_UFCON);
 394         wr_regl(port,  S3C2410_UFCON, ufcon);
 395
 396         /* Enable tx pio mode */
 397         ucon = rd_regl(port, S3C2410_UCON);
 398         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 399         ucon |= S3C64XX_UCON_TXMODE_CPU;
 400         wr_regl(port,  S3C2410_UCON, ucon);
 401
 402         /* Unmask Tx interrupt */
 403         switch (ourport->info->type) {
 404         case TYPE_S3C6400:
 405                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 406                                   S3C64XX_UINTM);
 407                 break;
 408         case TYPE_APPLE_S5L:
 409                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
 410                 wr_regl(port, S3C2410_UCON, ucon);
 411                 break;
 412         default:
 413                 enable_irq(ourport->tx_irq);
 414                 break;
 415         }
 416
 417         ourport->tx_mode = S3C24XX_TX_PIO;
 418
 419         /*
 420          * The Apple version only has edge triggered TX IRQs, so we need
 421          * to kick off the process by sending some characters here.
 422          */
 423         if (ourport->info->type == TYPE_APPLE_S5L)
 424                 s3c24xx_serial_tx_chars(ourport);
 425 }
 426
 427 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 428 {
 429         if (ourport->tx_mode != S3C24XX_TX_PIO)
 430                 enable_tx_pio(ourport);
 431 }
 432
 433 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 434                                       unsigned int count)
 435 {
 436         struct uart_port *port = &ourport->port;
 437         struct circ_buf *xmit = &port->state->xmit;
 438         struct s3c24xx_uart_dma *dma = ourport->dma;
 439
 440         if (ourport->tx_mode != S3C24XX_TX_DMA)
 441                 enable_tx_dma(ourport);
 442
 443         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 444         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 445
 446         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 447                                 dma->tx_size, DMA_TO_DEVICE);
 448
 449         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 450                                 dma->tx_transfer_addr, dma->tx_size,
 451                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 452         if (!dma->tx_desc) {
 453                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 454                 return -EIO;
 455         }
 456
 457         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 458         dma->tx_desc->callback_param = ourport;
 459         dma->tx_bytes_requested = dma->tx_size;
 460
 461         ourport->tx_in_progress = S3C24XX_TX_DMA;
 462         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 463         dma_async_issue_pending(dma->tx_chan);
 464         return 0;
 465 }
 466
 467 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 468 {
 469         struct uart_port *port = &ourport->port;
 470         struct circ_buf *xmit = &port->state->xmit;
 471         unsigned long count;
 472
 473         /* Get data size up to the end of buffer */
 474         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 475
 476         if (!count) {
 477                 s3c24xx_serial_stop_tx(port);
 478                 return;
 479         }
 480
 481         if (!ourport->dma || !ourport->dma->tx_chan ||
 482             count < ourport->min_dma_size ||
 483             xmit->tail & (dma_get_cache_alignment() - 1))
 484                 s3c24xx_serial_start_tx_pio(ourport);
 485         else
 486                 s3c24xx_serial_start_tx_dma(ourport, count);
 487 }
 488
 489 static void s3c24xx_serial_start_tx(struct uart_port *port)
 490 {
 491         struct s3c24xx_uart_port *ourport = to_ourport(port);
 492         struct circ_buf *xmit = &port->state->xmit;
 493
 494         if (!ourport->tx_enabled) {
 495                 if (port->flags & UPF_CONS_FLOW)
 496                         s3c24xx_serial_rx_disable(port);
 497
 498                 ourport->tx_enabled = 1;
 499                 if (!ourport->dma || !ourport->dma->tx_chan)
 500                         s3c24xx_serial_start_tx_pio(ourport);
 501         }
 502
 503         if (ourport->dma && ourport->dma->tx_chan) {
 504                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 505                         s3c24xx_serial_start_next_tx(ourport);
 506         }
 507 }
 508
 509 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 510                 struct tty_port *tty, int count)
 511 {
 512         struct s3c24xx_uart_dma *dma = ourport->dma;
 513         int copied;
 514
 515         if (!count)
 516                 return;
 517
 518         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 519                                 dma->rx_size, DMA_FROM_DEVICE);
 520
 521         ourport->port.icount.rx += count;
 522         if (!tty) {
 523                 dev_err(ourport->port.dev, "No tty port\n");
 524                 return;
 525         }
 526         copied = tty_insert_flip_string(tty,
 527                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 528         if (copied != count) {
 529                 WARN_ON(1);
 530                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 531         }
 532 }
 533
 534 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 535 {
 536         struct s3c24xx_uart_port *ourport = to_ourport(port);
 537         struct s3c24xx_uart_dma *dma = ourport->dma;
 538         struct tty_port *t = &port->state->port;
 539         struct dma_tx_state state;
 540         enum dma_status dma_status;
 541         unsigned int received;
 542
 543         if (ourport->rx_enabled) {
 544                 dev_dbg(port->dev, "stopping rx\n");
 545                 switch (ourport->info->type) {
 546                 case TYPE_S3C6400:
 547                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 548                                         S3C64XX_UINTM);
 549                         break;
 550                 case TYPE_APPLE_S5L:
 551                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
 552                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
 553                         break;
 554                 default:
 555                         disable_irq_nosync(ourport->rx_irq);
 556                         break;
 557                 }
 558                 ourport->rx_enabled = 0;
 559         }
 560         if (dma && dma->rx_chan) {
 561                 dmaengine_pause(dma->tx_chan);
 562                 dma_status = dmaengine_tx_status(dma->rx_chan,
 563                                 dma->rx_cookie, &state);
 564                 if (dma_status == DMA_IN_PROGRESS ||
 565                         dma_status == DMA_PAUSED) {
 566                         received = dma->rx_bytes_requested - state.residue;
 567                         dmaengine_terminate_all(dma->rx_chan);
 568                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 569                 }
 570         }
 571 }
 572
 573 static inline struct s3c24xx_uart_info
 574         *s3c24xx_port_to_info(struct uart_port *port)
 575 {
 576         return to_ourport(port)->info;
 577 }
 578
 579 static inline struct s3c2410_uartcfg
 580         *s3c24xx_port_to_cfg(struct uart_port *port)
 581 {
 582         struct s3c24xx_uart_port *ourport;
 583
 584         if (port->dev == NULL)
 585                 return NULL;
 586
 587         ourport = container_of(port, struct s3c24xx_uart_port, port);
 588         return ourport->cfg;
 589 }
 590
 591 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 592                                      unsigned long ufstat)
 593 {
 594         struct s3c24xx_uart_info *info = ourport->info;
 595
 596         if (ufstat & info->rx_fifofull)
 597                 return ourport->port.fifosize;
 598
 599         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 600 }
 601
 602 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 603 static void s3c24xx_serial_rx_dma_complete(void *args)
 604 {
 605         struct s3c24xx_uart_port *ourport = args;
 606         struct uart_port *port = &ourport->port;
 607
 608         struct s3c24xx_uart_dma *dma = ourport->dma;
 609         struct tty_port *t = &port->state->port;
 610         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 611
 612         struct dma_tx_state state;
 613         unsigned long flags;
 614         int received;
 615
 616         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 617         received  = dma->rx_bytes_requested - state.residue;
 618         async_tx_ack(dma->rx_desc);
 619
 620         spin_lock_irqsave(&port->lock, flags);
 621
 622         if (received)
 623                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 624
 625         if (tty) {
 626                 tty_flip_buffer_push(t);
 627                 tty_kref_put(tty);
 628         }
 629
 630         s3c64xx_start_rx_dma(ourport);
 631
 632         spin_unlock_irqrestore(&port->lock, flags);
 633 }
 634
 635 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 636 {
 637         struct s3c24xx_uart_dma *dma = ourport->dma;
 638
 639         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 640                                 dma->rx_size, DMA_FROM_DEVICE);
 641
 642         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 643                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 644                                 DMA_PREP_INTERRUPT);
 645         if (!dma->rx_desc) {
 646                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 647                 return;
 648         }
 649
 650         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 651         dma->rx_desc->callback_param = ourport;
 652         dma->rx_bytes_requested = dma->rx_size;
 653
 654         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 655         dma_async_issue_pending(dma->rx_chan);
 656 }
 657
 658 /* ? - where has parity gone?? */
 659 #define S3C2410_UERSTAT_PARITY (0x1000)
 660
 661 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 662 {
 663         struct uart_port *port = &ourport->port;
 664         unsigned int ucon;
 665
 666         /* set Rx mode to DMA mode */
 667         ucon = rd_regl(port, S3C2410_UCON);
 668         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 669                         S3C64XX_UCON_TIMEOUT_MASK |
 670                         S3C64XX_UCON_EMPTYINT_EN |
 671                         S3C64XX_UCON_DMASUS_EN |
 672                         S3C64XX_UCON_TIMEOUT_EN |
 673                         S3C64XX_UCON_RXMODE_MASK);
 674         ucon |= S3C64XX_UCON_RXBURST_16 |
 675                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 676                         S3C64XX_UCON_EMPTYINT_EN |
 677                         S3C64XX_UCON_TIMEOUT_EN |
 678                         S3C64XX_UCON_RXMODE_DMA;
 679         wr_regl(port, S3C2410_UCON, ucon);
 680
 681         ourport->rx_mode = S3C24XX_RX_DMA;
 682 }
 683
 684 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 685 {
 686         struct uart_port *port = &ourport->port;
 687         unsigned int ucon;
 688
 689         /* set Rx mode to DMA mode */
 690         ucon = rd_regl(port, S3C2410_UCON);
 691         ucon &= ~S3C64XX_UCON_RXMODE_MASK;
 692         ucon |= S3C64XX_UCON_RXMODE_CPU;
 693
 694         /* Apple types use these bits for IRQ masks */
 695         if (ourport->info->type != TYPE_APPLE_S5L) {
 696                 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 697                                 S3C64XX_UCON_EMPTYINT_EN |
 698                                 S3C64XX_UCON_DMASUS_EN |
 699                                 S3C64XX_UCON_TIMEOUT_EN);
 700                 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 701                                 S3C64XX_UCON_TIMEOUT_EN;
 702         }
 703         wr_regl(port, S3C2410_UCON, ucon);
 704
 705         ourport->rx_mode = S3C24XX_RX_PIO;
 706 }
 707
 708 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 709
 710 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 711 {
 712         unsigned int utrstat, received;
 713         struct s3c24xx_uart_port *ourport = dev_id;
 714         struct uart_port *port = &ourport->port;
 715         struct s3c24xx_uart_dma *dma = ourport->dma;
 716         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 717         struct tty_port *t = &port->state->port;
 718         struct dma_tx_state state;
 719
 720         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 721         rd_regl(port, S3C2410_UFSTAT);
 722
 723         spin_lock(&port->lock);
 724
 725         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 726                 s3c64xx_start_rx_dma(ourport);
 727                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 728                         enable_rx_dma(ourport);
 729                 goto finish;
 730         }
 731
 732         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 733                 dmaengine_pause(dma->rx_chan);
 734                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 735                 dmaengine_terminate_all(dma->rx_chan);
 736                 received = dma->rx_bytes_requested - state.residue;
 737                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 738
 739                 enable_rx_pio(ourport);
 740         }
 741
 742         s3c24xx_serial_rx_drain_fifo(ourport);
 743
 744         if (tty) {
 745                 tty_flip_buffer_push(t);
 746                 tty_kref_put(tty);
 747         }
 748
 749         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 750
 751 finish:
 752         spin_unlock(&port->lock);
 753
 754         return IRQ_HANDLED;
 755 }
 756
 757 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 758 {
 759         struct uart_port *port = &ourport->port;
 760         unsigned int ufcon, ch, flag, ufstat, uerstat;
 761         unsigned int fifocnt = 0;
 762         int max_count = port->fifosize;
 763
 764         while (max_count-- > 0) {
 765                 /*
 766                  * Receive all characters known to be in FIFO
 767                  * before reading FIFO level again
 768                  */
 769                 if (fifocnt == 0) {
 770                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 771                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 772                         if (fifocnt == 0)
 773                                 break;
 774                 }
 775                 fifocnt--;
 776
 777                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 778                 ch = rd_reg(port, S3C2410_URXH);
 779
 780                 if (port->flags & UPF_CONS_FLOW) {
 781                         int txe = s3c24xx_serial_txempty_nofifo(port);
 782
 783                         if (ourport->rx_enabled) {
 784                                 if (!txe) {
 785                                         ourport->rx_enabled = 0;
 786                                         continue;
 787                                 }
 788                         } else {
 789                                 if (txe) {
 790                                         ufcon = rd_regl(port, S3C2410_UFCON);
 791                                         ufcon |= S3C2410_UFCON_RESETRX;
 792                                         wr_regl(port, S3C2410_UFCON, ufcon);
 793                                         ourport->rx_enabled = 1;
 794                                         return;
 795                                 }
 796                                 continue;
 797                         }
 798                 }
 799
 800                 /* insert the character into the buffer */
 801
 802                 flag = TTY_NORMAL;
 803                 port->icount.rx++;
 804
 805                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 806                         dev_dbg(port->dev,
 807                                 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
 808                                 ch, uerstat);
 809
 810                         /* check for break */
 811                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 812                                 dev_dbg(port->dev, "break!\n");
 813                                 port->icount.brk++;
 814                                 if (uart_handle_break(port))
 815                                         continue; /* Ignore character */
 816                         }
 817
 818                         if (uerstat & S3C2410_UERSTAT_FRAME)
 819                                 port->icount.frame++;
 820                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 821                                 port->icount.overrun++;
 822
 823                         uerstat &= port->read_status_mask;
 824
 825                         if (uerstat & S3C2410_UERSTAT_BREAK)
 826                                 flag = TTY_BREAK;
 827                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 828                                 flag = TTY_PARITY;
 829                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 830                                             S3C2410_UERSTAT_OVERRUN))
 831                                 flag = TTY_FRAME;
 832                 }
 833
 834                 if (uart_handle_sysrq_char(port, ch))
 835                         continue; /* Ignore character */
 836
 837                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 838                                  ch, flag);
 839         }
 840
 841         tty_flip_buffer_push(&port->state->port);
 842 }
 843
 844 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 845 {
 846         struct s3c24xx_uart_port *ourport = dev_id;
 847         struct uart_port *port = &ourport->port;
 848
 849         spin_lock(&port->lock);
 850         s3c24xx_serial_rx_drain_fifo(ourport);
 851         spin_unlock(&port->lock);
 852
 853         return IRQ_HANDLED;
 854 }
 855
 856 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
 857 {
 858         struct s3c24xx_uart_port *ourport = dev_id;
 859
 860         if (ourport->dma && ourport->dma->rx_chan)
 861                 return s3c24xx_serial_rx_chars_dma(dev_id);
 862         return s3c24xx_serial_rx_chars_pio(dev_id);
 863 }
 864
 865 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
 866 {
 867         struct uart_port *port = &ourport->port;
 868         struct circ_buf *xmit = &port->state->xmit;
 869         int count, dma_count = 0;
 870
 871         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 872
 873         if (ourport->dma && ourport->dma->tx_chan &&
 874             count >= ourport->min_dma_size) {
 875                 int align = dma_get_cache_alignment() -
 876                         (xmit->tail & (dma_get_cache_alignment() - 1));
 877                 if (count - align >= ourport->min_dma_size) {
 878                         dma_count = count - align;
 879                         count = align;
 880                 }
 881         }
 882
 883         if (port->x_char) {
 884                 wr_reg(port, S3C2410_UTXH, port->x_char);
 885                 port->icount.tx++;
 886                 port->x_char = 0;
 887                 return;
 888         }
 889
 890         /* if there isn't anything more to transmit, or the uart is now
 891          * stopped, disable the uart and exit
 892          */
 893
 894         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 895                 s3c24xx_serial_stop_tx(port);
 896                 return;
 897         }
 898
 899         /* try and drain the buffer... */
 900
 901         if (count > port->fifosize) {
 902                 count = port->fifosize;
 903                 dma_count = 0;
 904         }
 905
 906         while (!uart_circ_empty(xmit) && count > 0) {
 907                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 908                         break;
 909
 910                 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 911                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 912                 port->icount.tx++;
 913                 count--;
 914         }
 915
 916         if (!count && dma_count) {
 917                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 918                 return;
 919         }
 920
 921         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 922                 spin_unlock(&port->lock);
 923                 uart_write_wakeup(port);
 924                 spin_lock(&port->lock);
 925         }
 926
 927         if (uart_circ_empty(xmit))
 928                 s3c24xx_serial_stop_tx(port);
 929 }
 930
 931 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
 932 {
 933         struct s3c24xx_uart_port *ourport = id;
 934         struct uart_port *port = &ourport->port;
 935
 936         spin_lock(&port->lock);
 937
 938         s3c24xx_serial_tx_chars(ourport);
 939
 940         spin_unlock(&port->lock);
 941         return IRQ_HANDLED;
 942 }
 943
 944 /* interrupt handler for s3c64xx and later SoC's.*/
 945 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 946 {
 947         struct s3c24xx_uart_port *ourport = id;
 948         struct uart_port *port = &ourport->port;
 949         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 950         irqreturn_t ret = IRQ_HANDLED;
 951
 952         if (pend & S3C64XX_UINTM_RXD_MSK) {
 953                 ret = s3c24xx_serial_rx_irq(irq, id);
 954                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 955         }
 956         if (pend & S3C64XX_UINTM_TXD_MSK) {
 957                 ret = s3c24xx_serial_tx_irq(irq, id);
 958                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 959         }
 960         return ret;
 961 }
 962
 963 /* interrupt handler for Apple SoC's.*/
 964 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
 965 {
 966         struct s3c24xx_uart_port *ourport = id;
 967         struct uart_port *port = &ourport->port;
 968         unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
 969         irqreturn_t ret = IRQ_NONE;
 970
 971         if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
 972                 wr_regl(port, S3C2410_UTRSTAT,
 973                         APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
 974                 ret = s3c24xx_serial_rx_irq(irq, id);
 975         }
 976         if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
 977                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
 978                 ret = s3c24xx_serial_tx_irq(irq, id);
 979         }
 980
 981         return ret;
 982 }
 983
 984 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 985 {
 986         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 987         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 988         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 989
 990         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 991                 if ((ufstat & info->tx_fifomask) != 0 ||
 992                     (ufstat & info->tx_fifofull))
 993                         return 0;
 994
 995                 return 1;
 996         }
 997
 998         return s3c24xx_serial_txempty_nofifo(port);
 999 }
1000
1001 /* no modem control lines */
1002 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1003 {
1004         unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1005
1006         if (umstat & S3C2410_UMSTAT_CTS)
1007                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1008         else
1009                 return TIOCM_CAR | TIOCM_DSR;
1010 }
1011
1012 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1013 {
1014         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1015
1016         if (mctrl & TIOCM_RTS)
1017                 umcon |= S3C2410_UMCOM_RTS_LOW;
1018         else
1019                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1020
1021         wr_regl(port, S3C2410_UMCON, umcon);
1022 }
1023
1024 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1025 {
1026         unsigned long flags;
1027         unsigned int ucon;
1028
1029         spin_lock_irqsave(&port->lock, flags);
1030
1031         ucon = rd_regl(port, S3C2410_UCON);
1032
1033         if (break_state)
1034                 ucon |= S3C2410_UCON_SBREAK;
1035         else
1036                 ucon &= ~S3C2410_UCON_SBREAK;
1037
1038         wr_regl(port, S3C2410_UCON, ucon);
1039
1040         spin_unlock_irqrestore(&port->lock, flags);
1041 }
1042
1043 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1044 {
1045         struct s3c24xx_uart_dma *dma = p->dma;
1046         struct dma_slave_caps dma_caps;
1047         const char *reason = NULL;
1048         int ret;
1049
1050         /* Default slave configuration parameters */
1051         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
1052         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1053         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
1054         dma->rx_conf.src_maxburst       = 1;
1055
1056         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
1057         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1058         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
1059         dma->tx_conf.dst_maxburst       = 1;
1060
1061         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1062
1063         if (IS_ERR(dma->rx_chan)) {
1064                 reason = "DMA RX channel request failed";
1065                 ret = PTR_ERR(dma->rx_chan);
1066                 goto err_warn;
1067         }
1068
1069         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1070         if (ret < 0 ||
1071             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1072                 reason = "insufficient DMA RX engine capabilities";
1073                 ret = -EOPNOTSUPP;
1074                 goto err_release_rx;
1075         }
1076
1077         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1078
1079         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1080         if (IS_ERR(dma->tx_chan)) {
1081                 reason = "DMA TX channel request failed";
1082                 ret = PTR_ERR(dma->tx_chan);
1083                 goto err_release_rx;
1084         }
1085
1086         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1087         if (ret < 0 ||
1088             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1089                 reason = "insufficient DMA TX engine capabilities";
1090                 ret = -EOPNOTSUPP;
1091                 goto err_release_tx;
1092         }
1093
1094         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1095
1096         /* RX buffer */
1097         dma->rx_size = PAGE_SIZE;
1098
1099         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1100         if (!dma->rx_buf) {
1101                 ret = -ENOMEM;
1102                 goto err_release_tx;
1103         }
1104
1105         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
1106                                 dma->rx_size, DMA_FROM_DEVICE);
1107         if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
1108                 reason = "DMA mapping error for RX buffer";
1109                 ret = -EIO;
1110                 goto err_free_rx;
1111         }
1112
1113         /* TX buffer */
1114         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
1115                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
1116         if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
1117                 reason = "DMA mapping error for TX buffer";
1118                 ret = -EIO;
1119                 goto err_unmap_rx;
1120         }
1121
1122         return 0;
1123
1124 err_unmap_rx:
1125         dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
1126                          DMA_FROM_DEVICE);
1127 err_free_rx:
1128         kfree(dma->rx_buf);
1129 err_release_tx:
1130         dma_release_channel(dma->tx_chan);
1131 err_release_rx:
1132         dma_release_channel(dma->rx_chan);
1133 err_warn:
1134         if (reason)
1135                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1136         return ret;
1137 }
1138
1139 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1140 {
1141         struct s3c24xx_uart_dma *dma = p->dma;
1142
1143         if (dma->rx_chan) {
1144                 dmaengine_terminate_all(dma->rx_chan);
1145                 dma_unmap_single(p->port.dev, dma->rx_addr,
1146                                 dma->rx_size, DMA_FROM_DEVICE);
1147                 kfree(dma->rx_buf);
1148                 dma_release_channel(dma->rx_chan);
1149                 dma->rx_chan = NULL;
1150         }
1151
1152         if (dma->tx_chan) {
1153                 dmaengine_terminate_all(dma->tx_chan);
1154                 dma_unmap_single(p->port.dev, dma->tx_addr,
1155                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
1156                 dma_release_channel(dma->tx_chan);
1157                 dma->tx_chan = NULL;
1158         }
1159 }
1160
1161 static void s3c24xx_serial_shutdown(struct uart_port *port)
1162 {
1163         struct s3c24xx_uart_port *ourport = to_ourport(port);
1164
1165         if (ourport->tx_claimed) {
1166                 free_irq(ourport->tx_irq, ourport);
1167                 ourport->tx_enabled = 0;
1168                 ourport->tx_claimed = 0;
1169                 ourport->tx_mode = 0;
1170         }
1171
1172         if (ourport->rx_claimed) {
1173                 free_irq(ourport->rx_irq, ourport);
1174                 ourport->rx_claimed = 0;
1175                 ourport->rx_enabled = 0;
1176         }
1177
1178         if (ourport->dma)
1179                 s3c24xx_serial_release_dma(ourport);
1180
1181         ourport->tx_in_progress = 0;
1182 }
1183
1184 static void s3c64xx_serial_shutdown(struct uart_port *port)
1185 {
1186         struct s3c24xx_uart_port *ourport = to_ourport(port);
1187
1188         ourport->tx_enabled = 0;
1189         ourport->tx_mode = 0;
1190         ourport->rx_enabled = 0;
1191
1192         free_irq(port->irq, ourport);
1193
1194         wr_regl(port, S3C64XX_UINTP, 0xf);
1195         wr_regl(port, S3C64XX_UINTM, 0xf);
1196
1197         if (ourport->dma)
1198                 s3c24xx_serial_release_dma(ourport);
1199
1200         ourport->tx_in_progress = 0;
1201 }
1202
1203 static void apple_s5l_serial_shutdown(struct uart_port *port)
1204 {
1205         struct s3c24xx_uart_port *ourport = to_ourport(port);
1206
1207         unsigned int ucon;
1208
1209         ucon = rd_regl(port, S3C2410_UCON);
1210         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1211                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1212                   APPLE_S5L_UCON_RXTO_ENA_MSK);
1213         wr_regl(port, S3C2410_UCON, ucon);
1214
1215         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1216
1217         free_irq(port->irq, ourport);
1218
1219         ourport->tx_enabled = 0;
1220         ourport->tx_mode = 0;
1221         ourport->rx_enabled = 0;
1222
1223         if (ourport->dma)
1224                 s3c24xx_serial_release_dma(ourport);
1225
1226         ourport->tx_in_progress = 0;
1227 }
1228
1229 static int s3c24xx_serial_startup(struct uart_port *port)
1230 {
1231         struct s3c24xx_uart_port *ourport = to_ourport(port);
1232         int ret;
1233
1234         ourport->rx_enabled = 1;
1235
1236         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0,
1237                           s3c24xx_serial_portname(port), ourport);
1238
1239         if (ret != 0) {
1240                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1241                 return ret;
1242         }
1243
1244         ourport->rx_claimed = 1;
1245
1246         dev_dbg(port->dev, "requesting tx irq...\n");
1247
1248         ourport->tx_enabled = 1;
1249
1250         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0,
1251                           s3c24xx_serial_portname(port), ourport);
1252
1253         if (ret) {
1254                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1255                 goto err;
1256         }
1257
1258         ourport->tx_claimed = 1;
1259
1260         /* the port reset code should have done the correct
1261          * register setup for the port controls
1262          */
1263
1264         return ret;
1265
1266 err:
1267         s3c24xx_serial_shutdown(port);
1268         return ret;
1269 }
1270
1271 static int s3c64xx_serial_startup(struct uart_port *port)
1272 {
1273         struct s3c24xx_uart_port *ourport = to_ourport(port);
1274         unsigned long flags;
1275         unsigned int ufcon;
1276         int ret;
1277
1278         wr_regl(port, S3C64XX_UINTM, 0xf);
1279         if (ourport->dma) {
1280                 ret = s3c24xx_serial_request_dma(ourport);
1281                 if (ret < 0) {
1282                         devm_kfree(port->dev, ourport->dma);
1283                         ourport->dma = NULL;
1284                 }
1285         }
1286
1287         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1288                           s3c24xx_serial_portname(port), ourport);
1289         if (ret) {
1290                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1291                 return ret;
1292         }
1293
1294         /* For compatibility with s3c24xx Soc's */
1295         ourport->rx_enabled = 1;
1296         ourport->tx_enabled = 0;
1297
1298         spin_lock_irqsave(&port->lock, flags);
1299
1300         ufcon = rd_regl(port, S3C2410_UFCON);
1301         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1302         if (!uart_console(port))
1303                 ufcon |= S3C2410_UFCON_RESETTX;
1304         wr_regl(port, S3C2410_UFCON, ufcon);
1305
1306         enable_rx_pio(ourport);
1307
1308         spin_unlock_irqrestore(&port->lock, flags);
1309
1310         /* Enable Rx Interrupt */
1311         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1312
1313         return ret;
1314 }
1315
1316 static int apple_s5l_serial_startup(struct uart_port *port)
1317 {
1318         struct s3c24xx_uart_port *ourport = to_ourport(port);
1319         unsigned long flags;
1320         unsigned int ufcon;
1321         int ret;
1322
1323         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1324
1325         ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1326                           s3c24xx_serial_portname(port), ourport);
1327         if (ret) {
1328                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1329                 return ret;
1330         }
1331
1332         /* For compatibility with s3c24xx Soc's */
1333         ourport->rx_enabled = 1;
1334         ourport->tx_enabled = 0;
1335
1336         spin_lock_irqsave(&port->lock, flags);
1337
1338         ufcon = rd_regl(port, S3C2410_UFCON);
1339         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1340         if (!uart_console(port))
1341                 ufcon |= S3C2410_UFCON_RESETTX;
1342         wr_regl(port, S3C2410_UFCON, ufcon);
1343
1344         enable_rx_pio(ourport);
1345
1346         spin_unlock_irqrestore(&port->lock, flags);
1347
1348         /* Enable Rx Interrupt */
1349         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1350         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1351
1352         return ret;
1353 }
1354
1355 /* power power management control */
1356
1357 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1358                               unsigned int old)
1359 {
1360         struct s3c24xx_uart_port *ourport = to_ourport(port);
1361         int timeout = 10000;
1362
1363         ourport->pm_level = level;
1364
1365         switch (level) {
1366         case 3:
1367                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1368                         udelay(100);
1369
1370                 if (!IS_ERR(ourport->baudclk))
1371                         clk_disable_unprepare(ourport->baudclk);
1372
1373                 clk_disable_unprepare(ourport->clk);
1374                 break;
1375
1376         case 0:
1377                 clk_prepare_enable(ourport->clk);
1378
1379                 if (!IS_ERR(ourport->baudclk))
1380                         clk_prepare_enable(ourport->baudclk);
1381
1382                 break;
1383         default:
1384                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1385         }
1386 }
1387
1388 /* baud rate calculation
1389  *
1390  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1391  * of different sources, including the peripheral clock ("pclk") and an
1392  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1393  * with a programmable extra divisor.
1394  *
1395  * The following code goes through the clock sources, and calculates the
1396  * baud clocks (and the resultant actual baud rates) and then tries to
1397  * pick the closest one and select that.
1398  *
1399  */
1400
1401 #define MAX_CLK_NAME_LENGTH 15
1402
1403 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1404 {
1405         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1406         unsigned int ucon;
1407
1408         if (info->num_clks == 1)
1409                 return 0;
1410
1411         ucon = rd_regl(port, S3C2410_UCON);
1412         ucon &= info->clksel_mask;
1413         return ucon >> info->clksel_shift;
1414 }
1415
1416 static void s3c24xx_serial_setsource(struct uart_port *port,
1417                         unsigned int clk_sel)
1418 {
1419         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1420         unsigned int ucon;
1421
1422         if (info->num_clks == 1)
1423                 return;
1424
1425         ucon = rd_regl(port, S3C2410_UCON);
1426         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1427                 return;
1428
1429         ucon &= ~info->clksel_mask;
1430         ucon |= clk_sel << info->clksel_shift;
1431         wr_regl(port, S3C2410_UCON, ucon);
1432 }
1433
1434 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1435                         unsigned int req_baud, struct clk **best_clk,
1436                         unsigned int *clk_num)
1437 {
1438         struct s3c24xx_uart_info *info = ourport->info;
1439         struct clk *clk;
1440         unsigned long rate;
1441         unsigned int cnt, baud, quot, best_quot = 0;
1442         char clkname[MAX_CLK_NAME_LENGTH];
1443         int calc_deviation, deviation = (1 << 30) - 1;
1444
1445         for (cnt = 0; cnt < info->num_clks; cnt++) {
1446                 /* Keep selected clock if provided */
1447                 if (ourport->cfg->clk_sel &&
1448                         !(ourport->cfg->clk_sel & (1 << cnt)))
1449                         continue;
1450
1451                 sprintf(clkname, "clk_uart_baud%d", cnt);
1452                 clk = clk_get(ourport->port.dev, clkname);
1453                 if (IS_ERR(clk))
1454                         continue;
1455
1456                 rate = clk_get_rate(clk);
1457                 if (!rate)
1458                         continue;
1459
1460                 if (ourport->info->has_divslot) {
1461                         unsigned long div = rate / req_baud;
1462
1463                         /* The UDIVSLOT register on the newer UARTs allows us to
1464                          * get a divisor adjustment of 1/16th on the baud clock.
1465                          *
1466                          * We don't keep the UDIVSLOT value (the 16ths we
1467                          * calculated by not multiplying the baud by 16) as it
1468                          * is easy enough to recalculate.
1469                          */
1470
1471                         quot = div / 16;
1472                         baud = rate / div;
1473                 } else {
1474                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1475                         baud = rate / (quot * 16);
1476                 }
1477                 quot--;
1478
1479                 calc_deviation = req_baud - baud;
1480                 if (calc_deviation < 0)
1481                         calc_deviation = -calc_deviation;
1482
1483                 if (calc_deviation < deviation) {
1484                         *best_clk = clk;
1485                         best_quot = quot;
1486                         *clk_num = cnt;
1487                         deviation = calc_deviation;
1488                 }
1489         }
1490
1491         return best_quot;
1492 }
1493
1494 /* udivslot_table[]
1495  *
1496  * This table takes the fractional value of the baud divisor and gives
1497  * the recommended setting for the UDIVSLOT register.
1498  */
1499 static u16 udivslot_table[16] = {
1500         [0] = 0x0000,
1501         [1] = 0x0080,
1502         [2] = 0x0808,
1503         [3] = 0x0888,
1504         [4] = 0x2222,
1505         [5] = 0x4924,
1506         [6] = 0x4A52,
1507         [7] = 0x54AA,
1508         [8] = 0x5555,
1509         [9] = 0xD555,
1510         [10] = 0xD5D5,
1511         [11] = 0xDDD5,
1512         [12] = 0xDDDD,
1513         [13] = 0xDFDD,
1514         [14] = 0xDFDF,
1515         [15] = 0xFFDF,
1516 };
1517
1518 static void s3c24xx_serial_set_termios(struct uart_port *port,
1519                                        struct ktermios *termios,
1520                                        struct ktermios *old)
1521 {
1522         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1523         struct s3c24xx_uart_port *ourport = to_ourport(port);
1524         struct clk *clk = ERR_PTR(-EINVAL);
1525         unsigned long flags;
1526         unsigned int baud, quot, clk_sel = 0;
1527         unsigned int ulcon;
1528         unsigned int umcon;
1529         unsigned int udivslot = 0;
1530
1531         /*
1532          * We don't support modem control lines.
1533          */
1534         termios->c_cflag &= ~(HUPCL | CMSPAR);
1535         termios->c_cflag |= CLOCAL;
1536
1537         /*
1538          * Ask the core to calculate the divisor for us.
1539          */
1540
1541         baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1542         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1543         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1544                 quot = port->custom_divisor;
1545         if (IS_ERR(clk))
1546                 return;
1547
1548         /* check to see if we need  to change clock source */
1549
1550         if (ourport->baudclk != clk) {
1551                 clk_prepare_enable(clk);
1552
1553                 s3c24xx_serial_setsource(port, clk_sel);
1554
1555                 if (!IS_ERR(ourport->baudclk)) {
1556                         clk_disable_unprepare(ourport->baudclk);
1557                         ourport->baudclk = ERR_PTR(-EINVAL);
1558                 }
1559
1560                 ourport->baudclk = clk;
1561                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1562         }
1563
1564         if (ourport->info->has_divslot) {
1565                 unsigned int div = ourport->baudclk_rate / baud;
1566
1567                 if (cfg->has_fracval) {
1568                         udivslot = (div & 15);
1569                         dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1570                 } else {
1571                         udivslot = udivslot_table[div & 15];
1572                         dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1573                                 udivslot, div & 15);
1574                 }
1575         }
1576
1577         switch (termios->c_cflag & CSIZE) {
1578         case CS5:
1579                 dev_dbg(port->dev, "config: 5bits/char\n");
1580                 ulcon = S3C2410_LCON_CS5;
1581                 break;
1582         case CS6:
1583                 dev_dbg(port->dev, "config: 6bits/char\n");
1584                 ulcon = S3C2410_LCON_CS6;
1585                 break;
1586         case CS7:
1587                 dev_dbg(port->dev, "config: 7bits/char\n");
1588                 ulcon = S3C2410_LCON_CS7;
1589                 break;
1590         case CS8:
1591         default:
1592                 dev_dbg(port->dev, "config: 8bits/char\n");
1593                 ulcon = S3C2410_LCON_CS8;
1594                 break;
1595         }
1596
1597         /* preserve original lcon IR settings */
1598         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1599
1600         if (termios->c_cflag & CSTOPB)
1601                 ulcon |= S3C2410_LCON_STOPB;
1602
1603         if (termios->c_cflag & PARENB) {
1604                 if (termios->c_cflag & PARODD)
1605                         ulcon |= S3C2410_LCON_PODD;
1606                 else
1607                         ulcon |= S3C2410_LCON_PEVEN;
1608         } else {
1609                 ulcon |= S3C2410_LCON_PNONE;
1610         }
1611
1612         spin_lock_irqsave(&port->lock, flags);
1613
1614         dev_dbg(port->dev,
1615                 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1616                 ulcon, quot, udivslot);
1617
1618         wr_regl(port, S3C2410_ULCON, ulcon);
1619         wr_regl(port, S3C2410_UBRDIV, quot);
1620
1621         port->status &= ~UPSTAT_AUTOCTS;
1622
1623         umcon = rd_regl(port, S3C2410_UMCON);
1624         if (termios->c_cflag & CRTSCTS) {
1625                 umcon |= S3C2410_UMCOM_AFC;
1626                 /* Disable RTS when RX FIFO contains 63 bytes */
1627                 umcon &= ~S3C2412_UMCON_AFC_8;
1628                 port->status = UPSTAT_AUTOCTS;
1629         } else {
1630                 umcon &= ~S3C2410_UMCOM_AFC;
1631         }
1632         wr_regl(port, S3C2410_UMCON, umcon);
1633
1634         if (ourport->info->has_divslot)
1635                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1636
1637         dev_dbg(port->dev,
1638                 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1639                 rd_regl(port, S3C2410_ULCON),
1640                 rd_regl(port, S3C2410_UCON),
1641                 rd_regl(port, S3C2410_UFCON));
1642
1643         /*
1644          * Update the per-port timeout.
1645          */
1646         uart_update_timeout(port, termios->c_cflag, baud);
1647
1648         /*
1649          * Which character status flags are we interested in?
1650          */
1651         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1652         if (termios->c_iflag & INPCK)
1653                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1654                         S3C2410_UERSTAT_PARITY;
1655         /*
1656          * Which character status flags should we ignore?
1657          */
1658         port->ignore_status_mask = 0;
1659         if (termios->c_iflag & IGNPAR)
1660                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1661         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1662                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1663
1664         /*
1665          * Ignore all characters if CREAD is not set.
1666          */
1667         if ((termios->c_cflag & CREAD) == 0)
1668                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1669
1670         spin_unlock_irqrestore(&port->lock, flags);
1671 }
1672
1673 static const char *s3c24xx_serial_type(struct uart_port *port)
1674 {
1675         struct s3c24xx_uart_port *ourport = to_ourport(port);
1676
1677         switch (ourport->info->type) {
1678         case TYPE_S3C24XX:
1679                 return "S3C24XX";
1680         case TYPE_S3C6400:
1681                 return "S3C6400/10";
1682         case TYPE_APPLE_S5L:
1683                 return "APPLE S5L";
1684         default:
1685                 return NULL;
1686         }
1687 }
1688
1689 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1690 {
1691         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1692
1693         if (flags & UART_CONFIG_TYPE)
1694                 port->type = info->port_type;
1695 }
1696
1697 /*
1698  * verify the new serial_struct (for TIOCSSERIAL).
1699  */
1700 static int
1701 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1702 {
1703         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1704
1705         if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1706                 return -EINVAL;
1707
1708         return 0;
1709 }
1710
1711 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1712
1713 static struct console s3c24xx_serial_console;
1714
1715 static int __init s3c24xx_serial_console_init(void)
1716 {
1717         register_console(&s3c24xx_serial_console);
1718         return 0;
1719 }
1720 console_initcall(s3c24xx_serial_console_init);
1721
1722 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1723 #else
1724 #define S3C24XX_SERIAL_CONSOLE NULL
1725 #endif
1726
1727 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1728 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1729 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1730                          unsigned char c);
1731 #endif
1732
1733 static const struct uart_ops s3c24xx_serial_ops = {
1734         .pm             = s3c24xx_serial_pm,
1735         .tx_empty       = s3c24xx_serial_tx_empty,
1736         .get_mctrl      = s3c24xx_serial_get_mctrl,
1737         .set_mctrl      = s3c24xx_serial_set_mctrl,
1738         .stop_tx        = s3c24xx_serial_stop_tx,
1739         .start_tx       = s3c24xx_serial_start_tx,
1740         .stop_rx        = s3c24xx_serial_stop_rx,
1741         .break_ctl      = s3c24xx_serial_break_ctl,
1742         .startup        = s3c24xx_serial_startup,
1743         .shutdown       = s3c24xx_serial_shutdown,
1744         .set_termios    = s3c24xx_serial_set_termios,
1745         .type           = s3c24xx_serial_type,
1746         .config_port    = s3c24xx_serial_config_port,
1747         .verify_port    = s3c24xx_serial_verify_port,
1748 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1749         .poll_get_char = s3c24xx_serial_get_poll_char,
1750         .poll_put_char = s3c24xx_serial_put_poll_char,
1751 #endif
1752 };
1753
1754 static const struct uart_ops s3c64xx_serial_ops = {
1755         .pm             = s3c24xx_serial_pm,
1756         .tx_empty       = s3c24xx_serial_tx_empty,
1757         .get_mctrl      = s3c24xx_serial_get_mctrl,
1758         .set_mctrl      = s3c24xx_serial_set_mctrl,
1759         .stop_tx        = s3c24xx_serial_stop_tx,
1760         .start_tx       = s3c24xx_serial_start_tx,
1761         .stop_rx        = s3c24xx_serial_stop_rx,
1762         .break_ctl      = s3c24xx_serial_break_ctl,
1763         .startup        = s3c64xx_serial_startup,
1764         .shutdown       = s3c64xx_serial_shutdown,
1765         .set_termios    = s3c24xx_serial_set_termios,
1766         .type           = s3c24xx_serial_type,
1767         .config_port    = s3c24xx_serial_config_port,
1768         .verify_port    = s3c24xx_serial_verify_port,
1769 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1770         .poll_get_char = s3c24xx_serial_get_poll_char,
1771         .poll_put_char = s3c24xx_serial_put_poll_char,
1772 #endif
1773 };
1774
1775 static const struct uart_ops apple_s5l_serial_ops = {
1776         .pm             = s3c24xx_serial_pm,
1777         .tx_empty       = s3c24xx_serial_tx_empty,
1778         .get_mctrl      = s3c24xx_serial_get_mctrl,
1779         .set_mctrl      = s3c24xx_serial_set_mctrl,
1780         .stop_tx        = s3c24xx_serial_stop_tx,
1781         .start_tx       = s3c24xx_serial_start_tx,
1782         .stop_rx        = s3c24xx_serial_stop_rx,
1783         .break_ctl      = s3c24xx_serial_break_ctl,
1784         .startup        = apple_s5l_serial_startup,
1785         .shutdown       = apple_s5l_serial_shutdown,
1786         .set_termios    = s3c24xx_serial_set_termios,
1787         .type           = s3c24xx_serial_type,
1788         .config_port    = s3c24xx_serial_config_port,
1789         .verify_port    = s3c24xx_serial_verify_port,
1790 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1791         .poll_get_char = s3c24xx_serial_get_poll_char,
1792         .poll_put_char = s3c24xx_serial_put_poll_char,
1793 #endif
1794 };
1795
1796 static struct uart_driver s3c24xx_uart_drv = {
1797         .owner          = THIS_MODULE,
1798         .driver_name    = "s3c2410_serial",
1799         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1800         .cons           = S3C24XX_SERIAL_CONSOLE,
1801         .dev_name       = S3C24XX_SERIAL_NAME,
1802         .major          = S3C24XX_SERIAL_MAJOR,
1803         .minor          = S3C24XX_SERIAL_MINOR,
1804 };
1805
1806 #define __PORT_LOCK_UNLOCKED(i) \
1807         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1808 static struct s3c24xx_uart_port
1809 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1810         [0] = {
1811                 .port = {
1812                         .lock           = __PORT_LOCK_UNLOCKED(0),
1813                         .iotype         = UPIO_MEM,
1814                         .uartclk        = 0,
1815                         .fifosize       = 16,
1816                         .ops            = &s3c24xx_serial_ops,
1817                         .flags          = UPF_BOOT_AUTOCONF,
1818                         .line           = 0,
1819                 }
1820         },
1821         [1] = {
1822                 .port = {
1823                         .lock           = __PORT_LOCK_UNLOCKED(1),
1824                         .iotype         = UPIO_MEM,
1825                         .uartclk        = 0,
1826                         .fifosize       = 16,
1827                         .ops            = &s3c24xx_serial_ops,
1828                         .flags          = UPF_BOOT_AUTOCONF,
1829                         .line           = 1,
1830                 }
1831         },
1832 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1833         [2] = {
1834                 .port = {
1835                         .lock           = __PORT_LOCK_UNLOCKED(2),
1836                         .iotype         = UPIO_MEM,
1837                         .uartclk        = 0,
1838                         .fifosize       = 16,
1839                         .ops            = &s3c24xx_serial_ops,
1840                         .flags          = UPF_BOOT_AUTOCONF,
1841                         .line           = 2,
1842                 }
1843         },
1844 #endif
1845 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1846         [3] = {
1847                 .port = {
1848                         .lock           = __PORT_LOCK_UNLOCKED(3),
1849                         .iotype         = UPIO_MEM,
1850                         .uartclk        = 0,
1851                         .fifosize       = 16,
1852                         .ops            = &s3c24xx_serial_ops,
1853                         .flags          = UPF_BOOT_AUTOCONF,
1854                         .line           = 3,
1855                 }
1856         }
1857 #endif
1858 };
1859 #undef __PORT_LOCK_UNLOCKED
1860
1861 /* s3c24xx_serial_resetport
1862  *
1863  * reset the fifos and other the settings.
1864  */
1865
1866 static void s3c24xx_serial_resetport(struct uart_port *port,
1867                                    struct s3c2410_uartcfg *cfg)
1868 {
1869         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1870         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1871
1872         ucon &= (info->clksel_mask | info->ucon_mask);
1873         wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1874
1875         /* reset both fifos */
1876         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1877         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1878
1879         /* some delay is required after fifo reset */
1880         udelay(1);
1881 }
1882
1883 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1884
1885 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1886                                              unsigned long val, void *data)
1887 {
1888         struct s3c24xx_uart_port *port;
1889         struct uart_port *uport;
1890
1891         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1892         uport = &port->port;
1893
1894         /* check to see if port is enabled */
1895
1896         if (port->pm_level != 0)
1897                 return 0;
1898
1899         /* try and work out if the baudrate is changing, we can detect
1900          * a change in rate, but we do not have support for detecting
1901          * a disturbance in the clock-rate over the change.
1902          */
1903
1904         if (IS_ERR(port->baudclk))
1905                 goto exit;
1906
1907         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1908                 goto exit;
1909
1910         if (val == CPUFREQ_PRECHANGE) {
1911                 /* we should really shut the port down whilst the
1912                  * frequency change is in progress.
1913                  */
1914
1915         } else if (val == CPUFREQ_POSTCHANGE) {
1916                 struct ktermios *termios;
1917                 struct tty_struct *tty;
1918
1919                 if (uport->state == NULL)
1920                         goto exit;
1921
1922                 tty = uport->state->port.tty;
1923
1924                 if (tty == NULL)
1925                         goto exit;
1926
1927                 termios = &tty->termios;
1928
1929                 if (termios == NULL) {
1930                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1931                         goto exit;
1932                 }
1933
1934                 s3c24xx_serial_set_termios(uport, termios, NULL);
1935         }
1936
1937 exit:
1938         return 0;
1939 }
1940
1941 static inline int
1942 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1943 {
1944         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1945
1946         return cpufreq_register_notifier(&port->freq_transition,
1947                                          CPUFREQ_TRANSITION_NOTIFIER);
1948 }
1949
1950 static inline void
1951 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1952 {
1953         cpufreq_unregister_notifier(&port->freq_transition,
1954                                     CPUFREQ_TRANSITION_NOTIFIER);
1955 }
1956
1957 #else
1958 static inline int
1959 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1960 {
1961         return 0;
1962 }
1963
1964 static inline void
1965 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1966 {
1967 }
1968 #endif
1969
1970 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1971 {
1972         struct device *dev = ourport->port.dev;
1973         struct s3c24xx_uart_info *info = ourport->info;
1974         char clk_name[MAX_CLK_NAME_LENGTH];
1975         unsigned int clk_sel;
1976         struct clk *clk;
1977         int clk_num;
1978         int ret;
1979
1980         clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1981         for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1982                 if (!(clk_sel & (1 << clk_num)))
1983                         continue;
1984
1985                 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1986                 clk = clk_get(dev, clk_name);
1987                 if (IS_ERR(clk))
1988                         continue;
1989
1990                 ret = clk_prepare_enable(clk);
1991                 if (ret) {
1992                         clk_put(clk);
1993                         continue;
1994                 }
1995
1996                 ourport->baudclk = clk;
1997                 ourport->baudclk_rate = clk_get_rate(clk);
1998                 s3c24xx_serial_setsource(&ourport->port, clk_num);
1999
2000                 return 0;
2001         }
2002
2003         return -EINVAL;
2004 }
2005
2006 /* s3c24xx_serial_init_port
2007  *
2008  * initialise a single serial port from the platform device given
2009  */
2010
2011 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
2012                                     struct platform_device *platdev)
2013 {
2014         struct uart_port *port = &ourport->port;
2015         struct s3c2410_uartcfg *cfg = ourport->cfg;
2016         struct resource *res;
2017         int ret;
2018
2019         if (platdev == NULL)
2020                 return -ENODEV;
2021
2022         if (port->mapbase != 0)
2023                 return -EINVAL;
2024
2025         /* setup info for port */
2026         port->dev       = &platdev->dev;
2027
2028         port->uartclk = 1;
2029
2030         if (cfg->uart_flags & UPF_CONS_FLOW) {
2031                 dev_dbg(port->dev, "enabling flow control\n");
2032                 port->flags |= UPF_CONS_FLOW;
2033         }
2034
2035         /* sort our the physical and virtual addresses for each UART */
2036
2037         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
2038         if (res == NULL) {
2039                 dev_err(port->dev, "failed to find memory resource for uart\n");
2040                 return -EINVAL;
2041         }
2042
2043         dev_dbg(port->dev, "resource %pR)\n", res);
2044
2045         port->membase = devm_ioremap_resource(port->dev, res);
2046         if (IS_ERR(port->membase)) {
2047                 dev_err(port->dev, "failed to remap controller address\n");
2048                 return -EBUSY;
2049         }
2050
2051         port->mapbase = res->start;
2052         ret = platform_get_irq(platdev, 0);
2053         if (ret < 0) {
2054                 port->irq = 0;
2055         } else {
2056                 port->irq = ret;
2057                 ourport->rx_irq = ret;
2058                 ourport->tx_irq = ret + 1;
2059         }
2060
2061         switch (ourport->info->type) {
2062         case TYPE_S3C24XX:
2063                 ret = platform_get_irq(platdev, 1);
2064                 if (ret > 0)
2065                         ourport->tx_irq = ret;
2066                 break;
2067         default:
2068                 break;
2069         }
2070
2071         /*
2072          * DMA is currently supported only on DT platforms, if DMA properties
2073          * are specified.
2074          */
2075         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
2076                                                      "dmas", NULL)) {
2077                 ourport->dma = devm_kzalloc(port->dev,
2078                                             sizeof(*ourport->dma),
2079                                             GFP_KERNEL);
2080                 if (!ourport->dma) {
2081                         ret = -ENOMEM;
2082                         goto err;
2083                 }
2084         }
2085
2086         ourport->clk    = clk_get(&platdev->dev, "uart");
2087         if (IS_ERR(ourport->clk)) {
2088                 pr_err("%s: Controller clock not found\n",
2089                                 dev_name(&platdev->dev));
2090                 ret = PTR_ERR(ourport->clk);
2091                 goto err;
2092         }
2093
2094         ret = clk_prepare_enable(ourport->clk);
2095         if (ret) {
2096                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
2097                 clk_put(ourport->clk);
2098                 goto err;
2099         }
2100
2101         ret = s3c24xx_serial_enable_baudclk(ourport);
2102         if (ret)
2103                 pr_warn("uart: failed to enable baudclk\n");
2104
2105         /* Keep all interrupts masked and cleared */
2106         switch (ourport->info->type) {
2107         case TYPE_S3C6400:
2108                 wr_regl(port, S3C64XX_UINTM, 0xf);
2109                 wr_regl(port, S3C64XX_UINTP, 0xf);
2110                 wr_regl(port, S3C64XX_UINTSP, 0xf);
2111                 break;
2112         case TYPE_APPLE_S5L: {
2113                 unsigned int ucon;
2114
2115                 ucon = rd_regl(port, S3C2410_UCON);
2116                 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2117                         APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2118                         APPLE_S5L_UCON_RXTO_ENA_MSK);
2119                 wr_regl(port, S3C2410_UCON, ucon);
2120
2121                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
2122                 break;
2123         }
2124         default:
2125                 break;
2126         }
2127
2128         dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
2129                 &port->mapbase, port->membase, port->irq,
2130                 ourport->rx_irq, ourport->tx_irq, port->uartclk);
2131
2132         /* reset the fifos (and setup the uart) */
2133         s3c24xx_serial_resetport(port, cfg);
2134
2135         return 0;
2136
2137 err:
2138         port->mapbase = 0;
2139         return ret;
2140 }
2141
2142 /* Device driver serial port probe */
2143
2144 #ifdef CONFIG_OF
2145 static const struct of_device_id s3c24xx_uart_dt_match[];
2146 #endif
2147
2148 static int probe_index;
2149
2150 static inline struct s3c24xx_serial_drv_data *
2151 s3c24xx_get_driver_data(struct platform_device *pdev)
2152 {
2153 #ifdef CONFIG_OF
2154         if (pdev->dev.of_node) {
2155                 const struct of_device_id *match;
2156
2157                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
2158                 return (struct s3c24xx_serial_drv_data *)match->data;
2159         }
2160 #endif
2161         return (struct s3c24xx_serial_drv_data *)
2162                         platform_get_device_id(pdev)->driver_data;
2163 }
2164
2165 static int s3c24xx_serial_probe(struct platform_device *pdev)
2166 {
2167         struct device_node *np = pdev->dev.of_node;
2168         struct s3c24xx_uart_port *ourport;
2169         int index = probe_index;
2170         int ret, prop = 0;
2171
2172         if (np) {
2173                 ret = of_alias_get_id(np, "serial");
2174                 if (ret >= 0)
2175                         index = ret;
2176         }
2177
2178         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2179                 dev_err(&pdev->dev, "serial%d out of range\n", index);
2180                 return -EINVAL;
2181         }
2182         ourport = &s3c24xx_serial_ports[index];
2183
2184         ourport->drv_data = s3c24xx_get_driver_data(pdev);
2185         if (!ourport->drv_data) {
2186                 dev_err(&pdev->dev, "could not find driver data\n");
2187                 return -ENODEV;
2188         }
2189
2190         ourport->baudclk = ERR_PTR(-EINVAL);
2191         ourport->info = ourport->drv_data->info;
2192         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2193                         dev_get_platdata(&pdev->dev) :
2194                         ourport->drv_data->def_cfg;
2195
2196         switch (ourport->info->type) {
2197         case TYPE_S3C24XX:
2198                 ourport->port.ops = &s3c24xx_serial_ops;
2199                 break;
2200         case TYPE_S3C6400:
2201                 ourport->port.ops = &s3c64xx_serial_ops;
2202                 break;
2203         case TYPE_APPLE_S5L:
2204                 ourport->port.ops = &apple_s5l_serial_ops;
2205                 break;
2206         }
2207
2208         if (np) {
2209                 of_property_read_u32(np,
2210                         "samsung,uart-fifosize", &ourport->port.fifosize);
2211
2212                 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2213                         switch (prop) {
2214                         case 1:
2215                                 ourport->port.iotype = UPIO_MEM;
2216                                 break;
2217                         case 4:
2218                                 ourport->port.iotype = UPIO_MEM32;
2219                                 break;
2220                         default:
2221                                 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2222                                                 prop);
2223                                 return -EINVAL;
2224                         }
2225                 }
2226         }
2227
2228         if (ourport->drv_data->fifosize[index])
2229                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2230         else if (ourport->info->fifosize)
2231                 ourport->port.fifosize = ourport->info->fifosize;
2232         ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2233
2234         /*
2235          * DMA transfers must be aligned at least to cache line size,
2236          * so find minimal transfer size suitable for DMA mode
2237          */
2238         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2239                                     dma_get_cache_alignment());
2240
2241         dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2242
2243         ret = s3c24xx_serial_init_port(ourport, pdev);
2244         if (ret < 0)
2245                 return ret;
2246
2247         if (!s3c24xx_uart_drv.state) {
2248                 ret = uart_register_driver(&s3c24xx_uart_drv);
2249                 if (ret < 0) {
2250                         pr_err("Failed to register Samsung UART driver\n");
2251                         return ret;
2252                 }
2253         }
2254
2255         dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2256         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2257         platform_set_drvdata(pdev, &ourport->port);
2258
2259         /*
2260          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2261          * so that a potential re-enablement through the pm-callback overlaps
2262          * and keeps the clock enabled in this case.
2263          */
2264         clk_disable_unprepare(ourport->clk);
2265         if (!IS_ERR(ourport->baudclk))
2266                 clk_disable_unprepare(ourport->baudclk);
2267
2268         ret = s3c24xx_serial_cpufreq_register(ourport);
2269         if (ret < 0)
2270                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2271
2272         probe_index++;
2273
2274         return 0;
2275 }
2276
2277 static int s3c24xx_serial_remove(struct platform_device *dev)
2278 {
2279         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2280
2281         if (port) {
2282                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2283                 uart_remove_one_port(&s3c24xx_uart_drv, port);
2284         }
2285
2286         uart_unregister_driver(&s3c24xx_uart_drv);
2287
2288         return 0;
2289 }
2290
2291 /* UART power management code */
2292 #ifdef CONFIG_PM_SLEEP
2293 static int s3c24xx_serial_suspend(struct device *dev)
2294 {
2295         struct uart_port *port = s3c24xx_dev_to_port(dev);
2296
2297         if (port)
2298                 uart_suspend_port(&s3c24xx_uart_drv, port);
2299
2300         return 0;
2301 }
2302
2303 static int s3c24xx_serial_resume(struct device *dev)
2304 {
2305         struct uart_port *port = s3c24xx_dev_to_port(dev);
2306         struct s3c24xx_uart_port *ourport = to_ourport(port);
2307
2308         if (port) {
2309                 clk_prepare_enable(ourport->clk);
2310                 if (!IS_ERR(ourport->baudclk))
2311                         clk_prepare_enable(ourport->baudclk);
2312                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2313                 if (!IS_ERR(ourport->baudclk))
2314                         clk_disable_unprepare(ourport->baudclk);
2315                 clk_disable_unprepare(ourport->clk);
2316
2317                 uart_resume_port(&s3c24xx_uart_drv, port);
2318         }
2319
2320         return 0;
2321 }
2322
2323 static int s3c24xx_serial_resume_noirq(struct device *dev)
2324 {
2325         struct uart_port *port = s3c24xx_dev_to_port(dev);
2326         struct s3c24xx_uart_port *ourport = to_ourport(port);
2327
2328         if (port) {
2329                 /* restore IRQ mask */
2330                 switch (ourport->info->type) {
2331                 case TYPE_S3C6400: {
2332                         unsigned int uintm = 0xf;
2333
2334                         if (ourport->tx_enabled)
2335                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2336                         if (ourport->rx_enabled)
2337                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2338                         clk_prepare_enable(ourport->clk);
2339                         if (!IS_ERR(ourport->baudclk))
2340                                 clk_prepare_enable(ourport->baudclk);
2341                         wr_regl(port, S3C64XX_UINTM, uintm);
2342                         if (!IS_ERR(ourport->baudclk))
2343                                 clk_disable_unprepare(ourport->baudclk);
2344                         clk_disable_unprepare(ourport->clk);
2345                         break;
2346                 }
2347                 case TYPE_APPLE_S5L: {
2348                         unsigned int ucon;
2349                         int ret;
2350
2351                         ret = clk_prepare_enable(ourport->clk);
2352                         if (ret) {
2353                                 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2354                                 return ret;
2355                         }
2356                         if (!IS_ERR(ourport->baudclk)) {
2357                                 ret = clk_prepare_enable(ourport->baudclk);
2358                                 if (ret) {
2359                                         dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2360                                         clk_disable_unprepare(ourport->clk);
2361                                         return ret;
2362                                 }
2363                         }
2364
2365                         ucon = rd_regl(port, S3C2410_UCON);
2366
2367                         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2368                                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2369                                   APPLE_S5L_UCON_RXTO_ENA_MSK);
2370
2371                         if (ourport->tx_enabled)
2372                                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2373                         if (ourport->rx_enabled)
2374                                 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2375                                         APPLE_S5L_UCON_RXTO_ENA_MSK;
2376
2377                         wr_regl(port, S3C2410_UCON, ucon);
2378
2379                         if (!IS_ERR(ourport->baudclk))
2380                                 clk_disable_unprepare(ourport->baudclk);
2381                         clk_disable_unprepare(ourport->clk);
2382                         break;
2383                 }
2384                 default:
2385                         break;
2386                 }
2387         }
2388
2389         return 0;
2390 }
2391
2392 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2393         .suspend = s3c24xx_serial_suspend,
2394         .resume = s3c24xx_serial_resume,
2395         .resume_noirq = s3c24xx_serial_resume_noirq,
2396 };
2397 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
2398
2399 #else /* !CONFIG_PM_SLEEP */
2400
2401 #define SERIAL_SAMSUNG_PM_OPS   NULL
2402 #endif /* CONFIG_PM_SLEEP */
2403
2404 /* Console code */
2405
2406 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2407
2408 static struct uart_port *cons_uart;
2409
2410 static int
2411 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2412 {
2413         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2414         unsigned long ufstat, utrstat;
2415
2416         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2417                 /* fifo mode - check amount of data in fifo registers... */
2418
2419                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2420                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2421         }
2422
2423         /* in non-fifo mode, we go and use the tx buffer empty */
2424
2425         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2426         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2427 }
2428
2429 static bool
2430 s3c24xx_port_configured(unsigned int ucon)
2431 {
2432         /* consider the serial port configured if the tx/rx mode set */
2433         return (ucon & 0xf) != 0;
2434 }
2435
2436 #ifdef CONFIG_CONSOLE_POLL
2437 /*
2438  * Console polling routines for writing and reading from the uart while
2439  * in an interrupt or debug context.
2440  */
2441
2442 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2443 {
2444         struct s3c24xx_uart_port *ourport = to_ourport(port);
2445         unsigned int ufstat;
2446
2447         ufstat = rd_regl(port, S3C2410_UFSTAT);
2448         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2449                 return NO_POLL_CHAR;
2450
2451         return rd_reg(port, S3C2410_URXH);
2452 }
2453
2454 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2455                 unsigned char c)
2456 {
2457         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2458         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2459
2460         /* not possible to xmit on unconfigured port */
2461         if (!s3c24xx_port_configured(ucon))
2462                 return;
2463
2464         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2465                 cpu_relax();
2466         wr_reg(port, S3C2410_UTXH, c);
2467 }
2468
2469 #endif /* CONFIG_CONSOLE_POLL */
2470
2471 static void
2472 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2473 {
2474         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2475
2476         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2477                 cpu_relax();
2478         wr_reg(port, S3C2410_UTXH, ch);
2479 }
2480
2481 static void
2482 s3c24xx_serial_console_write(struct console *co, const char *s,
2483                              unsigned int count)
2484 {
2485         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2486
2487         /* not possible to xmit on unconfigured port */
2488         if (!s3c24xx_port_configured(ucon))
2489                 return;
2490
2491         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2492 }
2493
2494 static void __init
2495 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2496                            int *parity, int *bits)
2497 {
2498         struct clk *clk;
2499         unsigned int ulcon;
2500         unsigned int ucon;
2501         unsigned int ubrdiv;
2502         unsigned long rate;
2503         unsigned int clk_sel;
2504         char clk_name[MAX_CLK_NAME_LENGTH];
2505
2506         ulcon  = rd_regl(port, S3C2410_ULCON);
2507         ucon   = rd_regl(port, S3C2410_UCON);
2508         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2509
2510         if (s3c24xx_port_configured(ucon)) {
2511                 switch (ulcon & S3C2410_LCON_CSMASK) {
2512                 case S3C2410_LCON_CS5:
2513                         *bits = 5;
2514                         break;
2515                 case S3C2410_LCON_CS6:
2516                         *bits = 6;
2517                         break;
2518                 case S3C2410_LCON_CS7:
2519                         *bits = 7;
2520                         break;
2521                 case S3C2410_LCON_CS8:
2522                 default:
2523                         *bits = 8;
2524                         break;
2525                 }
2526
2527                 switch (ulcon & S3C2410_LCON_PMASK) {
2528                 case S3C2410_LCON_PEVEN:
2529                         *parity = 'e';
2530                         break;
2531
2532                 case S3C2410_LCON_PODD:
2533                         *parity = 'o';
2534                         break;
2535
2536                 case S3C2410_LCON_PNONE:
2537                 default:
2538                         *parity = 'n';
2539                 }
2540
2541                 /* now calculate the baud rate */
2542
2543                 clk_sel = s3c24xx_serial_getsource(port);
2544                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2545
2546                 clk = clk_get(port->dev, clk_name);
2547                 if (!IS_ERR(clk))
2548                         rate = clk_get_rate(clk);
2549                 else
2550                         rate = 1;
2551
2552                 *baud = rate / (16 * (ubrdiv + 1));
2553                 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2554         }
2555 }
2556
2557 static int __init
2558 s3c24xx_serial_console_setup(struct console *co, char *options)
2559 {
2560         struct uart_port *port;
2561         int baud = 9600;
2562         int bits = 8;
2563         int parity = 'n';
2564         int flow = 'n';
2565
2566         /* is this a valid port */
2567
2568         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2569                 co->index = 0;
2570
2571         port = &s3c24xx_serial_ports[co->index].port;
2572
2573         /* is the port configured? */
2574
2575         if (port->mapbase == 0x0)
2576                 return -ENODEV;
2577
2578         cons_uart = port;
2579
2580         /*
2581          * Check whether an invalid uart number has been specified, and
2582          * if so, search for the first available port that does have
2583          * console support.
2584          */
2585         if (options)
2586                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2587         else
2588                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2589
2590         dev_dbg(port->dev, "baud %d\n", baud);
2591
2592         return uart_set_options(port, co, baud, parity, bits, flow);
2593 }
2594
2595 static struct console s3c24xx_serial_console = {
2596         .name           = S3C24XX_SERIAL_NAME,
2597         .device         = uart_console_device,
2598         .flags          = CON_PRINTBUFFER,
2599         .index          = -1,
2600         .write          = s3c24xx_serial_console_write,
2601         .setup          = s3c24xx_serial_console_setup,
2602         .data           = &s3c24xx_uart_drv,
2603 };
2604 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2605
2606 #ifdef CONFIG_CPU_S3C2410
2607 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2608         .info = &(struct s3c24xx_uart_info) {
2609                 .name           = "Samsung S3C2410 UART",
2610                 .type           = TYPE_S3C24XX,
2611                 .port_type      = PORT_S3C2410,
2612                 .fifosize       = 16,
2613                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2614                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2615                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2616                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2617                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2618                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2619                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2620                 .num_clks       = 2,
2621                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2622                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2623         },
2624         .def_cfg = &(struct s3c2410_uartcfg) {
2625                 .ucon           = S3C2410_UCON_DEFAULT,
2626                 .ufcon          = S3C2410_UFCON_DEFAULT,
2627         },
2628 };
2629 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2630 #else
2631 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2632 #endif
2633
2634 #ifdef CONFIG_CPU_S3C2412
2635 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2636         .info = &(struct s3c24xx_uart_info) {
2637                 .name           = "Samsung S3C2412 UART",
2638                 .type           = TYPE_S3C24XX,
2639                 .port_type      = PORT_S3C2412,
2640                 .fifosize       = 64,
2641                 .has_divslot    = 1,
2642                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2643                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2644                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2645                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2646                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2647                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2648                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2649                 .num_clks       = 4,
2650                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2651                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2652         },
2653         .def_cfg = &(struct s3c2410_uartcfg) {
2654                 .ucon           = S3C2410_UCON_DEFAULT,
2655                 .ufcon          = S3C2410_UFCON_DEFAULT,
2656         },
2657 };
2658 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2659 #else
2660 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2661 #endif
2662
2663 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2664         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2665 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2666         .info = &(struct s3c24xx_uart_info) {
2667                 .name           = "Samsung S3C2440 UART",
2668                 .type           = TYPE_S3C24XX,
2669                 .port_type      = PORT_S3C2440,
2670                 .fifosize       = 64,
2671                 .has_divslot    = 1,
2672                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2673                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2674                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2675                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2676                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2677                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2678                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2679                 .num_clks       = 4,
2680                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2681                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2682                 .ucon_mask      = S3C2440_UCON0_DIVMASK,
2683         },
2684         .def_cfg = &(struct s3c2410_uartcfg) {
2685                 .ucon           = S3C2410_UCON_DEFAULT,
2686                 .ufcon          = S3C2410_UFCON_DEFAULT,
2687         },
2688 };
2689 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2690 #else
2691 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2692 #endif
2693
2694 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2695 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2696         .info = &(struct s3c24xx_uart_info) {
2697                 .name           = "Samsung S3C6400 UART",
2698                 .type           = TYPE_S3C6400,
2699                 .port_type      = PORT_S3C6400,
2700                 .fifosize       = 64,
2701                 .has_divslot    = 1,
2702                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2703                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2704                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2705                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2706                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2707                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2708                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2709                 .num_clks       = 4,
2710                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2711                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2712         },
2713         .def_cfg = &(struct s3c2410_uartcfg) {
2714                 .ucon           = S3C2410_UCON_DEFAULT,
2715                 .ufcon          = S3C2410_UFCON_DEFAULT,
2716         },
2717 };
2718 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2719 #else
2720 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2721 #endif
2722
2723 #ifdef CONFIG_CPU_S5PV210
2724 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2725         .info = &(struct s3c24xx_uart_info) {
2726                 .name           = "Samsung S5PV210 UART",
2727                 .type           = TYPE_S3C6400,
2728                 .port_type      = PORT_S3C6400,
2729                 .has_divslot    = 1,
2730                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2731                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2732                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2733                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2734                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2735                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2736                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2737                 .num_clks       = 2,
2738                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2739                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2740         },
2741         .def_cfg = &(struct s3c2410_uartcfg) {
2742                 .ucon           = S5PV210_UCON_DEFAULT,
2743                 .ufcon          = S5PV210_UFCON_DEFAULT,
2744         },
2745         .fifosize = { 256, 64, 16, 16 },
2746 };
2747 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2748 #else
2749 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2750 #endif
2751
2752 #if defined(CONFIG_ARCH_EXYNOS)
2753 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2754         .info = &(struct s3c24xx_uart_info) {                   \
2755                 .name           = "Samsung Exynos UART",        \
2756                 .type           = TYPE_S3C6400,                 \
2757                 .port_type      = PORT_S3C6400,                 \
2758                 .has_divslot    = 1,                            \
2759                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2760                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2761                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2762                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2763                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2764                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2765                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2766                 .num_clks       = 1,                            \
2767                 .clksel_mask    = 0,                            \
2768                 .clksel_shift   = 0,                            \
2769         },                                                      \
2770         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2771                 .ucon           = S5PV210_UCON_DEFAULT,         \
2772                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2773                 .has_fracval    = 1,                            \
2774         }                                                       \
2775
2776 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2777         EXYNOS_COMMON_SERIAL_DRV_DATA,
2778         .fifosize = { 256, 64, 16, 16 },
2779 };
2780
2781 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2782         EXYNOS_COMMON_SERIAL_DRV_DATA,
2783         .fifosize = { 64, 256, 16, 256 },
2784 };
2785
2786 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2787 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2788 #else
2789 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2790 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2791 #endif
2792
2793 #ifdef CONFIG_ARCH_APPLE
2794 static struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2795         .info = &(struct s3c24xx_uart_info) {
2796                 .name           = "Apple S5L UART",
2797                 .type           = TYPE_APPLE_S5L,
2798                 .port_type      = PORT_8250,
2799                 .fifosize       = 16,
2800                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2801                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2802                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2803                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2804                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2805                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2806                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2807                 .num_clks       = 1,
2808                 .clksel_mask    = 0,
2809                 .clksel_shift   = 0,
2810         },
2811         .def_cfg = &(struct s3c2410_uartcfg) {
2812                 .ucon           = APPLE_S5L_UCON_DEFAULT,
2813                 .ufcon          = S3C2410_UFCON_DEFAULT,
2814         },
2815 };
2816 #define S5L_SERIAL_DRV_DATA ((kernel_ulong_t)&s5l_serial_drv_data)
2817 #else
2818 #define S5L_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
2819 #endif
2820
2821 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2822         {
2823                 .name           = "s3c2410-uart",
2824                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2825         }, {
2826                 .name           = "s3c2412-uart",
2827                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2828         }, {
2829                 .name           = "s3c2440-uart",
2830                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2831         }, {
2832                 .name           = "s3c6400-uart",
2833                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2834         }, {
2835                 .name           = "s5pv210-uart",
2836                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2837         }, {
2838                 .name           = "exynos4210-uart",
2839                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2840         }, {
2841                 .name           = "exynos5433-uart",
2842                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2843         }, {
2844                 .name           = "s5l-uart",
2845                 .driver_data    = S5L_SERIAL_DRV_DATA,
2846         },
2847         { },
2848 };
2849 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2850
2851 #ifdef CONFIG_OF
2852 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2853         { .compatible = "samsung,s3c2410-uart",
2854                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2855         { .compatible = "samsung,s3c2412-uart",
2856                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2857         { .compatible = "samsung,s3c2440-uart",
2858                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2859         { .compatible = "samsung,s3c6400-uart",
2860                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2861         { .compatible = "samsung,s5pv210-uart",
2862                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2863         { .compatible = "samsung,exynos4210-uart",
2864                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2865         { .compatible = "samsung,exynos5433-uart",
2866                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2867         { .compatible = "apple,s5l-uart",
2868                 .data = (void *)S5L_SERIAL_DRV_DATA },
2869         {},
2870 };
2871 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2872 #endif
2873
2874 static struct platform_driver samsung_serial_driver = {
2875         .probe          = s3c24xx_serial_probe,
2876         .remove         = s3c24xx_serial_remove,
2877         .id_table       = s3c24xx_serial_driver_ids,
2878         .driver         = {
2879                 .name   = "samsung-uart",
2880                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2881                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2882         },
2883 };
2884
2885 module_platform_driver(samsung_serial_driver);
2886
2887 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2888 /*
2889  * Early console.
2890  */
2891
2892 static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
2893 {
2894         switch (port->iotype) {
2895         case UPIO_MEM:
2896                 writeb(val, portaddr(port, reg));
2897                 break;
2898         case UPIO_MEM32:
2899                 writel(val, portaddr(port, reg));
2900                 break;
2901         }
2902 }
2903
2904 struct samsung_early_console_data {
2905         u32 txfull_mask;
2906 };
2907
2908 static void samsung_early_busyuart(struct uart_port *port)
2909 {
2910         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2911                 ;
2912 }
2913
2914 static void samsung_early_busyuart_fifo(struct uart_port *port)
2915 {
2916         struct samsung_early_console_data *data = port->private_data;
2917
2918         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2919                 ;
2920 }
2921
2922 static void samsung_early_putc(struct uart_port *port, int c)
2923 {
2924         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2925                 samsung_early_busyuart_fifo(port);
2926         else
2927                 samsung_early_busyuart(port);
2928
2929         wr_reg_barrier(port, S3C2410_UTXH, c);
2930 }
2931
2932 static void samsung_early_write(struct console *con, const char *s,
2933                                 unsigned int n)
2934 {
2935         struct earlycon_device *dev = con->data;
2936
2937         uart_console_write(&dev->port, s, n, samsung_early_putc);
2938 }
2939
2940 static int __init samsung_early_console_setup(struct earlycon_device *device,
2941                                               const char *opt)
2942 {
2943         if (!device->port.membase)
2944                 return -ENODEV;
2945
2946         device->con->write = samsung_early_write;
2947         return 0;
2948 }
2949
2950 /* S3C2410 */
2951 static struct samsung_early_console_data s3c2410_early_console_data = {
2952         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2953 };
2954
2955 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2956                                               const char *opt)
2957 {
2958         device->port.private_data = &s3c2410_early_console_data;
2959         return samsung_early_console_setup(device, opt);
2960 }
2961
2962 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2963                         s3c2410_early_console_setup);
2964
2965 /* S3C2412, S3C2440, S3C64xx */
2966 static struct samsung_early_console_data s3c2440_early_console_data = {
2967         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2968 };
2969
2970 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2971                                               const char *opt)
2972 {
2973         device->port.private_data = &s3c2440_early_console_data;
2974         return samsung_early_console_setup(device, opt);
2975 }
2976
2977 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2978                         s3c2440_early_console_setup);
2979 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2980                         s3c2440_early_console_setup);
2981 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2982                         s3c2440_early_console_setup);
2983
2984 /* S5PV210, Exynos */
2985 static struct samsung_early_console_data s5pv210_early_console_data = {
2986         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2987 };
2988
2989 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2990                                               const char *opt)
2991 {
2992         device->port.private_data = &s5pv210_early_console_data;
2993         return samsung_early_console_setup(device, opt);
2994 }
2995
2996 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2997                         s5pv210_early_console_setup);
2998 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2999                         s5pv210_early_console_setup);
3000
3001 /* Apple S5L */
3002 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
3003                                                 const char *opt)
3004 {
3005         /* Close enough to S3C2410 for earlycon... */
3006         device->port.private_data = &s3c2410_early_console_data;
3007
3008 #ifdef CONFIG_ARM64
3009         /* ... but we need to override the existing fixmap entry as nGnRnE */
3010         __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
3011                      __pgprot(PROT_DEVICE_nGnRnE));
3012 #endif
3013         return samsung_early_console_setup(device, opt);
3014 }
3015
3016 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
3017 #endif
3018
3019 MODULE_ALIAS("platform:samsung-uart");
3020 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
3021 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3022 MODULE_LICENSE("GPL v2");