1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR 7
42 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
48 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
50 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
53 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
56 * Here we define the default xmit fifo size used for each type of UART.
58 static const struct serial8250_config uart_config[] = {
83 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
84 .rxtrig_bytes = {1, 4, 8, 14},
85 .flags = UART_CAP_FIFO,
96 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
102 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
104 .rxtrig_bytes = {8, 16, 24, 28},
105 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
111 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
113 .rxtrig_bytes = {1, 16, 32, 56},
114 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
122 .name = "16C950/954",
125 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
126 .rxtrig_bytes = {16, 32, 112, 120},
127 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
128 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
134 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
136 .rxtrig_bytes = {8, 16, 56, 60},
137 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
143 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
144 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
150 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
151 .flags = UART_CAP_FIFO,
157 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
158 .flags = UART_CAP_FIFO | UART_NATSEMI,
164 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
165 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO,
178 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
179 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
185 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 .flags = UART_CAP_FIFO | UART_CAP_AFE,
192 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
194 .rxtrig_bytes = {1, 4, 8, 14},
195 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
202 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
209 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
211 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
218 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
219 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
220 .flags = UART_CAP_FIFO,
222 [PORT_BRCM_TRUMANAGE] = {
226 .flags = UART_CAP_HFIFO,
231 [PORT_ALTR_16550_F32] = {
232 .name = "Altera 16550 FIFO32",
235 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
236 .rxtrig_bytes = {1, 8, 16, 30},
237 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 [PORT_ALTR_16550_F64] = {
240 .name = "Altera 16550 FIFO64",
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .rxtrig_bytes = {1, 16, 32, 62},
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .rxtrig_bytes = {1, 32, 64, 126},
253 .flags = UART_CAP_FIFO | UART_CAP_AFE,
256 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
257 * workaround of errata A-008006 which states that tx_loadsz should
258 * be configured less than Maximum supported fifo bytes.
260 [PORT_16550A_FSL64] = {
261 .name = "16550A_FSL64",
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
266 .flags = UART_CAP_FIFO,
269 .name = "Palmchip BK-3103",
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .rxtrig_bytes = {1, 4, 8, 14},
274 .flags = UART_CAP_FIFO,
277 .name = "TI DA8xx/66AK2x",
280 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
282 .rxtrig_bytes = {1, 4, 8, 14},
283 .flags = UART_CAP_FIFO | UART_CAP_AFE,
286 .name = "MediaTek BTIF",
289 .fcr = UART_FCR_ENABLE_FIFO |
290 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
291 .flags = UART_CAP_FIFO,
294 .name = "Nuvoton 16550",
297 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
298 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
299 .rxtrig_bytes = {1, 4, 8, 14},
300 .flags = UART_CAP_FIFO,
306 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
307 .rxtrig_bytes = {1, 32, 64, 112},
308 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
312 /* Uart divisor latch read */
313 static int default_serial_dl_read(struct uart_8250_port *up)
315 /* Assign these in pieces to truncate any bits above 7. */
316 unsigned char dll = serial_in(up, UART_DLL);
317 unsigned char dlm = serial_in(up, UART_DLM);
319 return dll | dlm << 8;
322 /* Uart divisor latch write */
323 static void default_serial_dl_write(struct uart_8250_port *up, int value)
325 serial_out(up, UART_DLL, value & 0xff);
326 serial_out(up, UART_DLM, value >> 8 & 0xff);
329 #ifdef CONFIG_SERIAL_8250_RT288X
331 /* Au1x00/RT288x UART hardware has a weird register layout */
332 static const s8 au_io_in_map[8] = {
340 -1, /* UART_SCR (unmapped) */
343 static const s8 au_io_out_map[8] = {
349 -1, /* UART_LSR (unmapped) */
350 -1, /* UART_MSR (unmapped) */
351 -1, /* UART_SCR (unmapped) */
354 unsigned int au_serial_in(struct uart_port *p, int offset)
356 if (offset >= ARRAY_SIZE(au_io_in_map))
358 offset = au_io_in_map[offset];
361 return __raw_readl(p->membase + (offset << p->regshift));
364 void au_serial_out(struct uart_port *p, int offset, int value)
366 if (offset >= ARRAY_SIZE(au_io_out_map))
368 offset = au_io_out_map[offset];
371 __raw_writel(value, p->membase + (offset << p->regshift));
374 /* Au1x00 haven't got a standard divisor latch */
375 static int au_serial_dl_read(struct uart_8250_port *up)
377 return __raw_readl(up->port.membase + 0x28);
380 static void au_serial_dl_write(struct uart_8250_port *up, int value)
382 __raw_writel(value, up->port.membase + 0x28);
387 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
389 offset = offset << p->regshift;
390 outb(p->hub6 - 1 + offset, p->iobase);
391 return inb(p->iobase + 1);
394 static void hub6_serial_out(struct uart_port *p, int offset, int value)
396 offset = offset << p->regshift;
397 outb(p->hub6 - 1 + offset, p->iobase);
398 outb(value, p->iobase + 1);
401 static unsigned int mem_serial_in(struct uart_port *p, int offset)
403 offset = offset << p->regshift;
404 return readb(p->membase + offset);
407 static void mem_serial_out(struct uart_port *p, int offset, int value)
409 offset = offset << p->regshift;
410 writeb(value, p->membase + offset);
413 static void mem16_serial_out(struct uart_port *p, int offset, int value)
415 offset = offset << p->regshift;
416 writew(value, p->membase + offset);
419 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
421 offset = offset << p->regshift;
422 return readw(p->membase + offset);
425 static void mem32_serial_out(struct uart_port *p, int offset, int value)
427 offset = offset << p->regshift;
428 writel(value, p->membase + offset);
431 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
433 offset = offset << p->regshift;
434 return readl(p->membase + offset);
437 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
439 offset = offset << p->regshift;
440 iowrite32be(value, p->membase + offset);
443 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
445 offset = offset << p->regshift;
446 return ioread32be(p->membase + offset);
449 static unsigned int io_serial_in(struct uart_port *p, int offset)
451 offset = offset << p->regshift;
452 return inb(p->iobase + offset);
455 static void io_serial_out(struct uart_port *p, int offset, int value)
457 offset = offset << p->regshift;
458 outb(value, p->iobase + offset);
461 static int serial8250_default_handle_irq(struct uart_port *port);
463 static void set_io_from_upio(struct uart_port *p)
465 struct uart_8250_port *up = up_to_u8250p(p);
467 up->dl_read = default_serial_dl_read;
468 up->dl_write = default_serial_dl_write;
472 p->serial_in = hub6_serial_in;
473 p->serial_out = hub6_serial_out;
477 p->serial_in = mem_serial_in;
478 p->serial_out = mem_serial_out;
482 p->serial_in = mem16_serial_in;
483 p->serial_out = mem16_serial_out;
487 p->serial_in = mem32_serial_in;
488 p->serial_out = mem32_serial_out;
492 p->serial_in = mem32be_serial_in;
493 p->serial_out = mem32be_serial_out;
496 #ifdef CONFIG_SERIAL_8250_RT288X
498 p->serial_in = au_serial_in;
499 p->serial_out = au_serial_out;
500 up->dl_read = au_serial_dl_read;
501 up->dl_write = au_serial_dl_write;
506 p->serial_in = io_serial_in;
507 p->serial_out = io_serial_out;
510 /* Remember loaded iotype */
511 up->cur_iotype = p->iotype;
512 p->handle_irq = serial8250_default_handle_irq;
516 serial_port_out_sync(struct uart_port *p, int offset, int value)
524 p->serial_out(p, offset, value);
525 p->serial_in(p, UART_LCR); /* safe, no side-effects */
528 p->serial_out(p, offset, value);
535 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
537 serial_out(up, UART_SCR, offset);
538 serial_out(up, UART_ICR, value);
541 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
545 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
546 serial_out(up, UART_SCR, offset);
547 value = serial_in(up, UART_ICR);
548 serial_icr_write(up, UART_ACR, up->acr);
556 static void serial8250_clear_fifos(struct uart_8250_port *p)
558 if (p->capabilities & UART_CAP_FIFO) {
559 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
560 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
561 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
562 serial_out(p, UART_FCR, 0);
566 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
567 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
569 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
571 serial8250_clear_fifos(p);
572 serial_out(p, UART_FCR, p->fcr);
574 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
576 void serial8250_rpm_get(struct uart_8250_port *p)
578 if (!(p->capabilities & UART_CAP_RPM))
580 pm_runtime_get_sync(p->port.dev);
582 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
584 void serial8250_rpm_put(struct uart_8250_port *p)
586 if (!(p->capabilities & UART_CAP_RPM))
588 pm_runtime_mark_last_busy(p->port.dev);
589 pm_runtime_put_autosuspend(p->port.dev);
591 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
594 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
595 * @p: uart_8250_port port instance
597 * The function is used to start rs485 software emulating on the
598 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
599 * transmission. The function is idempotent, so it is safe to call it
602 * The caller MUST enable interrupt on empty shift register before
603 * calling serial8250_em485_init(). This interrupt is not a part of
604 * 8250 standard, but implementation defined.
606 * The function is supposed to be called from .rs485_config callback
607 * or from any other callback protected with p->port.lock spinlock.
609 * See also serial8250_em485_destroy()
611 * Return 0 - success, -errno - otherwise
613 static int serial8250_em485_init(struct uart_8250_port *p)
618 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
622 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
624 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
626 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
627 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
629 p->em485->active_timer = NULL;
630 p->em485->tx_stopped = true;
638 * serial8250_em485_destroy() - put uart_8250_port into normal state
639 * @p: uart_8250_port port instance
641 * The function is used to stop rs485 software emulating on the
642 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
643 * call it multiple times.
645 * The function is supposed to be called from .rs485_config callback
646 * or from any other callback protected with p->port.lock spinlock.
648 * See also serial8250_em485_init()
650 void serial8250_em485_destroy(struct uart_8250_port *p)
655 hrtimer_cancel(&p->em485->start_tx_timer);
656 hrtimer_cancel(&p->em485->stop_tx_timer);
661 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
664 * serial8250_em485_config() - generic ->rs485_config() callback
666 * @rs485: rs485 settings
668 * Generic callback usable by 8250 uart drivers to activate rs485 settings
669 * if the uart is incapable of driving RTS as a Transmit Enable signal in
670 * hardware, relying on software emulation instead.
672 int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
674 struct uart_8250_port *up = up_to_u8250p(port);
676 /* pick sane settings if the user hasn't */
677 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
678 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
679 rs485->flags |= SER_RS485_RTS_ON_SEND;
680 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
683 /* clamp the delays to [0, 100ms] */
684 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
685 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
687 memset(rs485->padding, 0, sizeof(rs485->padding));
688 port->rs485 = *rs485;
690 gpiod_set_value(port->rs485_term_gpio,
691 rs485->flags & SER_RS485_TERMINATE_BUS);
694 * Both serial8250_em485_init() and serial8250_em485_destroy()
697 if (rs485->flags & SER_RS485_ENABLED) {
698 int ret = serial8250_em485_init(up);
701 rs485->flags &= ~SER_RS485_ENABLED;
702 port->rs485.flags &= ~SER_RS485_ENABLED;
707 serial8250_em485_destroy(up);
710 EXPORT_SYMBOL_GPL(serial8250_em485_config);
713 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
714 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
715 * empty and the HW can idle again.
717 void serial8250_rpm_get_tx(struct uart_8250_port *p)
719 unsigned char rpm_active;
721 if (!(p->capabilities & UART_CAP_RPM))
724 rpm_active = xchg(&p->rpm_tx_active, 1);
727 pm_runtime_get_sync(p->port.dev);
729 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
731 void serial8250_rpm_put_tx(struct uart_8250_port *p)
733 unsigned char rpm_active;
735 if (!(p->capabilities & UART_CAP_RPM))
738 rpm_active = xchg(&p->rpm_tx_active, 0);
741 pm_runtime_mark_last_busy(p->port.dev);
742 pm_runtime_put_autosuspend(p->port.dev);
744 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
747 * IER sleep support. UARTs which have EFRs need the "extended
748 * capability" bit enabled. Note that on XR16C850s, we need to
749 * reset LCR to write to IER.
751 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
753 unsigned char lcr = 0, efr = 0;
755 serial8250_rpm_get(p);
757 if (p->capabilities & UART_CAP_SLEEP) {
758 if (p->capabilities & UART_CAP_EFR) {
759 lcr = serial_in(p, UART_LCR);
760 efr = serial_in(p, UART_EFR);
761 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
762 serial_out(p, UART_EFR, UART_EFR_ECB);
763 serial_out(p, UART_LCR, 0);
765 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
766 if (p->capabilities & UART_CAP_EFR) {
767 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
768 serial_out(p, UART_EFR, efr);
769 serial_out(p, UART_LCR, lcr);
773 serial8250_rpm_put(p);
776 #ifdef CONFIG_SERIAL_8250_RSA
778 * Attempts to turn on the RSA FIFO. Returns zero on failure.
779 * We set the port uart clock rate if we succeed.
781 static int __enable_rsa(struct uart_8250_port *up)
786 mode = serial_in(up, UART_RSA_MSR);
787 result = mode & UART_RSA_MSR_FIFO;
790 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
791 mode = serial_in(up, UART_RSA_MSR);
792 result = mode & UART_RSA_MSR_FIFO;
796 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
801 static void enable_rsa(struct uart_8250_port *up)
803 if (up->port.type == PORT_RSA) {
804 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
805 spin_lock_irq(&up->port.lock);
807 spin_unlock_irq(&up->port.lock);
809 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
810 serial_out(up, UART_RSA_FRR, 0);
815 * Attempts to turn off the RSA FIFO. Returns zero on failure.
816 * It is unknown why interrupts were disabled in here. However,
817 * the caller is expected to preserve this behaviour by grabbing
818 * the spinlock before calling this function.
820 static void disable_rsa(struct uart_8250_port *up)
825 if (up->port.type == PORT_RSA &&
826 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
827 spin_lock_irq(&up->port.lock);
829 mode = serial_in(up, UART_RSA_MSR);
830 result = !(mode & UART_RSA_MSR_FIFO);
833 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
834 mode = serial_in(up, UART_RSA_MSR);
835 result = !(mode & UART_RSA_MSR_FIFO);
839 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
840 spin_unlock_irq(&up->port.lock);
843 #endif /* CONFIG_SERIAL_8250_RSA */
846 * This is a quickie test to see how big the FIFO is.
847 * It doesn't work at all the time, more's the pity.
849 static int size_fifo(struct uart_8250_port *up)
851 unsigned char old_fcr, old_mcr, old_lcr;
852 unsigned short old_dl;
855 old_lcr = serial_in(up, UART_LCR);
856 serial_out(up, UART_LCR, 0);
857 old_fcr = serial_in(up, UART_FCR);
858 old_mcr = serial8250_in_MCR(up);
859 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
860 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
861 serial8250_out_MCR(up, UART_MCR_LOOP);
862 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
863 old_dl = serial_dl_read(up);
864 serial_dl_write(up, 0x0001);
865 serial_out(up, UART_LCR, 0x03);
866 for (count = 0; count < 256; count++)
867 serial_out(up, UART_TX, count);
868 mdelay(20);/* FIXME - schedule_timeout */
869 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
870 (count < 256); count++)
871 serial_in(up, UART_RX);
872 serial_out(up, UART_FCR, old_fcr);
873 serial8250_out_MCR(up, old_mcr);
874 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
875 serial_dl_write(up, old_dl);
876 serial_out(up, UART_LCR, old_lcr);
882 * Read UART ID using the divisor method - set DLL and DLM to zero
883 * and the revision will be in DLL and device type in DLM. We
884 * preserve the device state across this.
886 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
888 unsigned char old_lcr;
889 unsigned int id, old_dl;
891 old_lcr = serial_in(p, UART_LCR);
892 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
893 old_dl = serial_dl_read(p);
894 serial_dl_write(p, 0);
895 id = serial_dl_read(p);
896 serial_dl_write(p, old_dl);
898 serial_out(p, UART_LCR, old_lcr);
904 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
905 * When this function is called we know it is at least a StarTech
906 * 16650 V2, but it might be one of several StarTech UARTs, or one of
907 * its clones. (We treat the broken original StarTech 16650 V1 as a
908 * 16550, and why not? Startech doesn't seem to even acknowledge its
911 * What evil have men's minds wrought...
913 static void autoconfig_has_efr(struct uart_8250_port *up)
915 unsigned int id1, id2, id3, rev;
918 * Everything with an EFR has SLEEP
920 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
923 * First we check to see if it's an Oxford Semiconductor UART.
925 * If we have to do this here because some non-National
926 * Semiconductor clone chips lock up if you try writing to the
927 * LSR register (which serial_icr_read does)
931 * Check for Oxford Semiconductor 16C950.
933 * EFR [4] must be set else this test fails.
935 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
936 * claims that it's needed for 952 dual UART's (which are not
937 * recommended for new designs).
940 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
941 serial_out(up, UART_EFR, UART_EFR_ECB);
942 serial_out(up, UART_LCR, 0x00);
943 id1 = serial_icr_read(up, UART_ID1);
944 id2 = serial_icr_read(up, UART_ID2);
945 id3 = serial_icr_read(up, UART_ID3);
946 rev = serial_icr_read(up, UART_REV);
948 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
950 if (id1 == 0x16 && id2 == 0xC9 &&
951 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
952 up->port.type = PORT_16C950;
955 * Enable work around for the Oxford Semiconductor 952 rev B
956 * chip which causes it to seriously miscalculate baud rates
959 if (id3 == 0x52 && rev == 0x01)
960 up->bugs |= UART_BUG_QUOT;
965 * We check for a XR16C850 by setting DLL and DLM to 0, and then
966 * reading back DLL and DLM. The chip type depends on the DLM
968 * 0x10 - XR16C850 and the DLL contains the chip revision.
972 id1 = autoconfig_read_divisor_id(up);
973 DEBUG_AUTOCONF("850id=%04x ", id1);
976 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
977 up->port.type = PORT_16850;
982 * It wasn't an XR16C850.
984 * We distinguish between the '654 and the '650 by counting
985 * how many bytes are in the FIFO. I'm using this for now,
986 * since that's the technique that was sent to me in the
987 * serial driver update, but I'm not convinced this works.
988 * I've had problems doing this in the past. -TYT
990 if (size_fifo(up) == 64)
991 up->port.type = PORT_16654;
993 up->port.type = PORT_16650V2;
997 * We detected a chip without a FIFO. Only two fall into
998 * this category - the original 8250 and the 16450. The
999 * 16450 has a scratch register (accessible with LCR=0)
1001 static void autoconfig_8250(struct uart_8250_port *up)
1003 unsigned char scratch, status1, status2;
1005 up->port.type = PORT_8250;
1007 scratch = serial_in(up, UART_SCR);
1008 serial_out(up, UART_SCR, 0xa5);
1009 status1 = serial_in(up, UART_SCR);
1010 serial_out(up, UART_SCR, 0x5a);
1011 status2 = serial_in(up, UART_SCR);
1012 serial_out(up, UART_SCR, scratch);
1014 if (status1 == 0xa5 && status2 == 0x5a)
1015 up->port.type = PORT_16450;
1018 static int broken_efr(struct uart_8250_port *up)
1021 * Exar ST16C2550 "A2" devices incorrectly detect as
1022 * having an EFR, and report an ID of 0x0201. See
1023 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1025 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1032 * We know that the chip has FIFOs. Does it have an EFR? The
1033 * EFR is located in the same register position as the IIR and
1034 * we know the top two bits of the IIR are currently set. The
1035 * EFR should contain zero. Try to read the EFR.
1037 static void autoconfig_16550a(struct uart_8250_port *up)
1039 unsigned char status1, status2;
1040 unsigned int iersave;
1042 up->port.type = PORT_16550A;
1043 up->capabilities |= UART_CAP_FIFO;
1045 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1049 * Check for presence of the EFR when DLAB is set.
1050 * Only ST16C650V1 UARTs pass this test.
1052 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1053 if (serial_in(up, UART_EFR) == 0) {
1054 serial_out(up, UART_EFR, 0xA8);
1055 if (serial_in(up, UART_EFR) != 0) {
1056 DEBUG_AUTOCONF("EFRv1 ");
1057 up->port.type = PORT_16650;
1058 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1060 serial_out(up, UART_LCR, 0);
1061 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1063 status1 = serial_in(up, UART_IIR) >> 5;
1064 serial_out(up, UART_FCR, 0);
1065 serial_out(up, UART_LCR, 0);
1068 up->port.type = PORT_16550A_FSL64;
1070 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1072 serial_out(up, UART_EFR, 0);
1077 * Maybe it requires 0xbf to be written to the LCR.
1078 * (other ST16C650V2 UARTs, TI16C752A, etc)
1080 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1081 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1082 DEBUG_AUTOCONF("EFRv2 ");
1083 autoconfig_has_efr(up);
1088 * Check for a National Semiconductor SuperIO chip.
1089 * Attempt to switch to bank 2, read the value of the LOOP bit
1090 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1091 * switch back to bank 2, read it from EXCR1 again and check
1092 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1094 serial_out(up, UART_LCR, 0);
1095 status1 = serial8250_in_MCR(up);
1096 serial_out(up, UART_LCR, 0xE0);
1097 status2 = serial_in(up, 0x02); /* EXCR1 */
1099 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1100 serial_out(up, UART_LCR, 0);
1101 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1102 serial_out(up, UART_LCR, 0xE0);
1103 status2 = serial_in(up, 0x02); /* EXCR1 */
1104 serial_out(up, UART_LCR, 0);
1105 serial8250_out_MCR(up, status1);
1107 if ((status2 ^ status1) & UART_MCR_LOOP) {
1108 unsigned short quot;
1110 serial_out(up, UART_LCR, 0xE0);
1112 quot = serial_dl_read(up);
1115 if (ns16550a_goto_highspeed(up))
1116 serial_dl_write(up, quot);
1118 serial_out(up, UART_LCR, 0);
1120 up->port.uartclk = 921600*16;
1121 up->port.type = PORT_NS16550A;
1122 up->capabilities |= UART_NATSEMI;
1128 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1129 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1130 * Try setting it with and without DLAB set. Cheap clones
1131 * set bit 5 without DLAB set.
1133 serial_out(up, UART_LCR, 0);
1134 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1135 status1 = serial_in(up, UART_IIR) >> 5;
1136 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1137 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1138 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1139 status2 = serial_in(up, UART_IIR) >> 5;
1140 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1141 serial_out(up, UART_LCR, 0);
1143 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1145 if (status1 == 6 && status2 == 7) {
1146 up->port.type = PORT_16750;
1147 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1152 * Try writing and reading the UART_IER_UUE bit (b6).
1153 * If it works, this is probably one of the Xscale platform's
1155 * We're going to explicitly set the UUE bit to 0 before
1156 * trying to write and read a 1 just to make sure it's not
1157 * already a 1 and maybe locked there before we even start start.
1159 iersave = serial_in(up, UART_IER);
1160 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1161 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1163 * OK it's in a known zero state, try writing and reading
1164 * without disturbing the current state of the other bits.
1166 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1167 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1170 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1172 DEBUG_AUTOCONF("Xscale ");
1173 up->port.type = PORT_XSCALE;
1174 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1179 * If we got here we couldn't force the IER_UUE bit to 0.
1180 * Log it and continue.
1182 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1184 serial_out(up, UART_IER, iersave);
1187 * We distinguish between 16550A and U6 16550A by counting
1188 * how many bytes are in the FIFO.
1190 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1191 up->port.type = PORT_U6_16550A;
1192 up->capabilities |= UART_CAP_AFE;
1197 * This routine is called by rs_init() to initialize a specific serial
1198 * port. It determines what type of UART chip this serial port is
1199 * using: 8250, 16450, 16550, 16550A. The important question is
1200 * whether or not this UART is a 16550A or not, since this will
1201 * determine whether or not we can use its FIFO features or not.
1203 static void autoconfig(struct uart_8250_port *up)
1205 unsigned char status1, scratch, scratch2, scratch3;
1206 unsigned char save_lcr, save_mcr;
1207 struct uart_port *port = &up->port;
1208 unsigned long flags;
1209 unsigned int old_capabilities;
1211 if (!port->iobase && !port->mapbase && !port->membase)
1214 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1215 port->name, port->iobase, port->membase);
1218 * We really do need global IRQs disabled here - we're going to
1219 * be frobbing the chips IRQ enable register to see if it exists.
1221 spin_lock_irqsave(&port->lock, flags);
1223 up->capabilities = 0;
1226 if (!(port->flags & UPF_BUGGY_UART)) {
1228 * Do a simple existence test first; if we fail this,
1229 * there's no point trying anything else.
1231 * 0x80 is used as a nonsense port to prevent against
1232 * false positives due to ISA bus float. The
1233 * assumption is that 0x80 is a non-existent port;
1234 * which should be safe since include/asm/io.h also
1235 * makes this assumption.
1237 * Note: this is safe as long as MCR bit 4 is clear
1238 * and the device is in "PC" mode.
1240 scratch = serial_in(up, UART_IER);
1241 serial_out(up, UART_IER, 0);
1246 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1247 * 16C754B) allow only to modify them if an EFR bit is set.
1249 scratch2 = serial_in(up, UART_IER) & 0x0f;
1250 serial_out(up, UART_IER, 0x0F);
1254 scratch3 = serial_in(up, UART_IER) & 0x0f;
1255 serial_out(up, UART_IER, scratch);
1256 if (scratch2 != 0 || scratch3 != 0x0F) {
1258 * We failed; there's nothing here
1260 spin_unlock_irqrestore(&port->lock, flags);
1261 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1262 scratch2, scratch3);
1267 save_mcr = serial8250_in_MCR(up);
1268 save_lcr = serial_in(up, UART_LCR);
1271 * Check to see if a UART is really there. Certain broken
1272 * internal modems based on the Rockwell chipset fail this
1273 * test, because they apparently don't implement the loopback
1274 * test mode. So this test is skipped on the COM 1 through
1275 * COM 4 ports. This *should* be safe, since no board
1276 * manufacturer would be stupid enough to design a board
1277 * that conflicts with COM 1-4 --- we hope!
1279 if (!(port->flags & UPF_SKIP_TEST)) {
1280 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1281 status1 = serial_in(up, UART_MSR) & 0xF0;
1282 serial8250_out_MCR(up, save_mcr);
1283 if (status1 != 0x90) {
1284 spin_unlock_irqrestore(&port->lock, flags);
1285 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1292 * We're pretty sure there's a port here. Lets find out what
1293 * type of port it is. The IIR top two bits allows us to find
1294 * out if it's 8250 or 16450, 16550, 16550A or later. This
1295 * determines what we test for next.
1297 * We also initialise the EFR (if any) to zero for later. The
1298 * EFR occupies the same register location as the FCR and IIR.
1300 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1301 serial_out(up, UART_EFR, 0);
1302 serial_out(up, UART_LCR, 0);
1304 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1306 /* Assign this as it is to truncate any bits above 7. */
1307 scratch = serial_in(up, UART_IIR);
1309 switch (scratch >> 6) {
1311 autoconfig_8250(up);
1314 port->type = PORT_UNKNOWN;
1317 port->type = PORT_16550;
1320 autoconfig_16550a(up);
1324 #ifdef CONFIG_SERIAL_8250_RSA
1326 * Only probe for RSA ports if we got the region.
1328 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1330 port->type = PORT_RSA;
1333 serial_out(up, UART_LCR, save_lcr);
1335 port->fifosize = uart_config[up->port.type].fifo_size;
1336 old_capabilities = up->capabilities;
1337 up->capabilities = uart_config[port->type].flags;
1338 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1340 if (port->type == PORT_UNKNOWN)
1346 #ifdef CONFIG_SERIAL_8250_RSA
1347 if (port->type == PORT_RSA)
1348 serial_out(up, UART_RSA_FRR, 0);
1350 serial8250_out_MCR(up, save_mcr);
1351 serial8250_clear_fifos(up);
1352 serial_in(up, UART_RX);
1353 if (up->capabilities & UART_CAP_UUE)
1354 serial_out(up, UART_IER, UART_IER_UUE);
1356 serial_out(up, UART_IER, 0);
1359 spin_unlock_irqrestore(&port->lock, flags);
1362 * Check if the device is a Fintek F81216A
1364 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1365 fintek_8250_probe(up);
1367 if (up->capabilities != old_capabilities) {
1368 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1369 old_capabilities, up->capabilities);
1372 DEBUG_AUTOCONF("iir=%d ", scratch);
1373 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1376 static void autoconfig_irq(struct uart_8250_port *up)
1378 struct uart_port *port = &up->port;
1379 unsigned char save_mcr, save_ier;
1380 unsigned char save_ICP = 0;
1381 unsigned int ICP = 0;
1385 if (port->flags & UPF_FOURPORT) {
1386 ICP = (port->iobase & 0xfe0) | 0x1f;
1387 save_ICP = inb_p(ICP);
1392 if (uart_console(port))
1395 /* forget possible initially masked and pending IRQ */
1396 probe_irq_off(probe_irq_on());
1397 save_mcr = serial8250_in_MCR(up);
1398 save_ier = serial_in(up, UART_IER);
1399 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1401 irqs = probe_irq_on();
1402 serial8250_out_MCR(up, 0);
1404 if (port->flags & UPF_FOURPORT) {
1405 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1407 serial8250_out_MCR(up,
1408 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1410 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1411 serial_in(up, UART_LSR);
1412 serial_in(up, UART_RX);
1413 serial_in(up, UART_IIR);
1414 serial_in(up, UART_MSR);
1415 serial_out(up, UART_TX, 0xFF);
1417 irq = probe_irq_off(irqs);
1419 serial8250_out_MCR(up, save_mcr);
1420 serial_out(up, UART_IER, save_ier);
1422 if (port->flags & UPF_FOURPORT)
1423 outb_p(save_ICP, ICP);
1425 if (uart_console(port))
1428 port->irq = (irq > 0) ? irq : 0;
1431 static void serial8250_stop_rx(struct uart_port *port)
1433 struct uart_8250_port *up = up_to_u8250p(port);
1435 serial8250_rpm_get(up);
1437 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1438 up->port.read_status_mask &= ~UART_LSR_DR;
1439 serial_port_out(port, UART_IER, up->ier);
1441 serial8250_rpm_put(up);
1445 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1446 * @p: uart 8250 port
1448 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1450 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1452 unsigned char mcr = serial8250_in_MCR(p);
1454 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1455 mcr |= UART_MCR_RTS;
1457 mcr &= ~UART_MCR_RTS;
1458 serial8250_out_MCR(p, mcr);
1461 * Empty the RX FIFO, we are not interested in anything
1462 * received during the half-duplex transmission.
1463 * Enable previously disabled RX interrupts.
1465 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1466 serial8250_clear_and_reinit_fifos(p);
1468 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1469 serial_port_out(&p->port, UART_IER, p->ier);
1472 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1474 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1476 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1478 struct uart_8250_port *p = em485->port;
1479 unsigned long flags;
1481 serial8250_rpm_get(p);
1482 spin_lock_irqsave(&p->port.lock, flags);
1483 if (em485->active_timer == &em485->stop_tx_timer) {
1484 p->rs485_stop_tx(p);
1485 em485->active_timer = NULL;
1486 em485->tx_stopped = true;
1488 spin_unlock_irqrestore(&p->port.lock, flags);
1489 serial8250_rpm_put(p);
1491 return HRTIMER_NORESTART;
1494 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1496 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1499 static void __stop_tx_rs485(struct uart_8250_port *p)
1501 struct uart_8250_em485 *em485 = p->em485;
1504 * rs485_stop_tx() is going to set RTS according to config
1505 * AND flush RX FIFO if required.
1507 if (p->port.rs485.delay_rts_after_send > 0) {
1508 em485->active_timer = &em485->stop_tx_timer;
1509 start_hrtimer_ms(&em485->stop_tx_timer,
1510 p->port.rs485.delay_rts_after_send);
1512 p->rs485_stop_tx(p);
1513 em485->active_timer = NULL;
1514 em485->tx_stopped = true;
1518 static inline void __do_stop_tx(struct uart_8250_port *p)
1520 if (serial8250_clear_THRI(p))
1521 serial8250_rpm_put_tx(p);
1524 static inline void __stop_tx(struct uart_8250_port *p)
1526 struct uart_8250_em485 *em485 = p->em485;
1529 unsigned char lsr = serial_in(p, UART_LSR);
1531 * To provide required timeing and allow FIFO transfer,
1532 * __stop_tx_rs485() must be called only when both FIFO and
1533 * shift register are empty. It is for device driver to enable
1534 * interrupt on TEMT.
1536 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1544 static void serial8250_stop_tx(struct uart_port *port)
1546 struct uart_8250_port *up = up_to_u8250p(port);
1548 serial8250_rpm_get(up);
1552 * We really want to stop the transmitter from sending.
1554 if (port->type == PORT_16C950) {
1555 up->acr |= UART_ACR_TXDIS;
1556 serial_icr_write(up, UART_ACR, up->acr);
1558 serial8250_rpm_put(up);
1561 static inline void __start_tx(struct uart_port *port)
1563 struct uart_8250_port *up = up_to_u8250p(port);
1565 if (up->dma && !up->dma->tx_dma(up))
1568 if (serial8250_set_THRI(up)) {
1569 if (up->bugs & UART_BUG_TXEN) {
1572 lsr = serial_in(up, UART_LSR);
1573 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1574 if (lsr & UART_LSR_THRE)
1575 serial8250_tx_chars(up);
1580 * Re-enable the transmitter if we disabled it.
1582 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1583 up->acr &= ~UART_ACR_TXDIS;
1584 serial_icr_write(up, UART_ACR, up->acr);
1589 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1590 * @up: uart 8250 port
1592 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1593 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1594 * (Some chips use inverse semantics.) Further assumes that reception is
1595 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1596 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1598 void serial8250_em485_start_tx(struct uart_8250_port *up)
1600 unsigned char mcr = serial8250_in_MCR(up);
1602 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1603 serial8250_stop_rx(&up->port);
1605 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1606 mcr |= UART_MCR_RTS;
1608 mcr &= ~UART_MCR_RTS;
1609 serial8250_out_MCR(up, mcr);
1611 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1613 static inline void start_tx_rs485(struct uart_port *port)
1615 struct uart_8250_port *up = up_to_u8250p(port);
1616 struct uart_8250_em485 *em485 = up->em485;
1618 em485->active_timer = NULL;
1620 if (em485->tx_stopped) {
1621 em485->tx_stopped = false;
1623 up->rs485_start_tx(up);
1625 if (up->port.rs485.delay_rts_before_send > 0) {
1626 em485->active_timer = &em485->start_tx_timer;
1627 start_hrtimer_ms(&em485->start_tx_timer,
1628 up->port.rs485.delay_rts_before_send);
1636 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1638 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1640 struct uart_8250_port *p = em485->port;
1641 unsigned long flags;
1643 spin_lock_irqsave(&p->port.lock, flags);
1644 if (em485->active_timer == &em485->start_tx_timer) {
1645 __start_tx(&p->port);
1646 em485->active_timer = NULL;
1648 spin_unlock_irqrestore(&p->port.lock, flags);
1650 return HRTIMER_NORESTART;
1653 static void serial8250_start_tx(struct uart_port *port)
1655 struct uart_8250_port *up = up_to_u8250p(port);
1656 struct uart_8250_em485 *em485 = up->em485;
1658 serial8250_rpm_get_tx(up);
1661 em485->active_timer == &em485->start_tx_timer)
1665 start_tx_rs485(port);
1670 static void serial8250_throttle(struct uart_port *port)
1672 port->throttle(port);
1675 static void serial8250_unthrottle(struct uart_port *port)
1677 port->unthrottle(port);
1680 static void serial8250_disable_ms(struct uart_port *port)
1682 struct uart_8250_port *up = up_to_u8250p(port);
1684 /* no MSR capabilities */
1685 if (up->bugs & UART_BUG_NOMSR)
1688 mctrl_gpio_disable_ms(up->gpios);
1690 up->ier &= ~UART_IER_MSI;
1691 serial_port_out(port, UART_IER, up->ier);
1694 static void serial8250_enable_ms(struct uart_port *port)
1696 struct uart_8250_port *up = up_to_u8250p(port);
1698 /* no MSR capabilities */
1699 if (up->bugs & UART_BUG_NOMSR)
1702 mctrl_gpio_enable_ms(up->gpios);
1704 up->ier |= UART_IER_MSI;
1706 serial8250_rpm_get(up);
1707 serial_port_out(port, UART_IER, up->ier);
1708 serial8250_rpm_put(up);
1711 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1713 struct uart_port *port = &up->port;
1715 char flag = TTY_NORMAL;
1717 if (likely(lsr & UART_LSR_DR))
1718 ch = serial_in(up, UART_RX);
1721 * Intel 82571 has a Serial Over Lan device that will
1722 * set UART_LSR_BI without setting UART_LSR_DR when
1723 * it receives a break. To avoid reading from the
1724 * receive buffer without UART_LSR_DR bit set, we
1725 * just force the read character to be 0
1731 lsr |= up->lsr_saved_flags;
1732 up->lsr_saved_flags = 0;
1734 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1735 if (lsr & UART_LSR_BI) {
1736 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1739 * We do the SysRQ and SAK checking
1740 * here because otherwise the break
1741 * may get masked by ignore_status_mask
1742 * or read_status_mask.
1744 if (uart_handle_break(port))
1746 } else if (lsr & UART_LSR_PE)
1747 port->icount.parity++;
1748 else if (lsr & UART_LSR_FE)
1749 port->icount.frame++;
1750 if (lsr & UART_LSR_OE)
1751 port->icount.overrun++;
1754 * Mask off conditions which should be ignored.
1756 lsr &= port->read_status_mask;
1758 if (lsr & UART_LSR_BI) {
1759 dev_dbg(port->dev, "handling break\n");
1761 } else if (lsr & UART_LSR_PE)
1763 else if (lsr & UART_LSR_FE)
1766 if (uart_prepare_sysrq_char(port, ch))
1769 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1771 EXPORT_SYMBOL_GPL(serial8250_read_char);
1774 * serial8250_rx_chars: processes according to the passed in LSR
1775 * value, and returns the remaining LSR bits not handled
1776 * by this Rx routine.
1778 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1780 struct uart_port *port = &up->port;
1781 int max_count = 256;
1784 serial8250_read_char(up, lsr);
1785 if (--max_count == 0)
1787 lsr = serial_in(up, UART_LSR);
1788 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1790 tty_flip_buffer_push(&port->state->port);
1793 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1795 void serial8250_tx_chars(struct uart_8250_port *up)
1797 struct uart_port *port = &up->port;
1798 struct circ_buf *xmit = &port->state->xmit;
1802 serial_out(up, UART_TX, port->x_char);
1807 if (uart_tx_stopped(port)) {
1808 serial8250_stop_tx(port);
1811 if (uart_circ_empty(xmit)) {
1816 count = up->tx_loadsz;
1818 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1819 if (up->bugs & UART_BUG_TXRACE) {
1821 * The Aspeed BMC virtual UARTs have a bug where data
1822 * may get stuck in the BMC's Tx FIFO from bursts of
1823 * writes on the APB interface.
1825 * Delay back-to-back writes by a read cycle to avoid
1826 * stalling the VUART. Read a register that won't have
1827 * side-effects and discard the result.
1829 serial_in(up, UART_SCR);
1831 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1833 if (uart_circ_empty(xmit))
1835 if ((up->capabilities & UART_CAP_HFIFO) &&
1836 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1838 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1839 if ((up->capabilities & UART_CAP_MINI) &&
1840 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1842 } while (--count > 0);
1844 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1845 uart_write_wakeup(port);
1848 * With RPM enabled, we have to wait until the FIFO is empty before the
1849 * HW can go idle. So we get here once again with empty FIFO and disable
1850 * the interrupt and RPM in __stop_tx()
1852 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1855 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1857 /* Caller holds uart port lock */
1858 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1860 struct uart_port *port = &up->port;
1861 unsigned int status = serial_in(up, UART_MSR);
1863 status |= up->msr_saved_flags;
1864 up->msr_saved_flags = 0;
1865 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1866 port->state != NULL) {
1867 if (status & UART_MSR_TERI)
1869 if (status & UART_MSR_DDSR)
1871 if (status & UART_MSR_DDCD)
1872 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1873 if (status & UART_MSR_DCTS)
1874 uart_handle_cts_change(port, status & UART_MSR_CTS);
1876 wake_up_interruptible(&port->state->port.delta_msr_wait);
1881 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1883 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1885 switch (iir & 0x3f) {
1886 case UART_IIR_RX_TIMEOUT:
1887 serial8250_rx_dma_flush(up);
1892 return up->dma->rx_dma(up);
1896 * This handles the interrupt from one port.
1898 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1900 unsigned char status;
1901 struct uart_8250_port *up = up_to_u8250p(port);
1902 bool skip_rx = false;
1903 unsigned long flags;
1905 if (iir & UART_IIR_NO_INT)
1908 spin_lock_irqsave(&port->lock, flags);
1910 status = serial_port_in(port, UART_LSR);
1913 * If port is stopped and there are no error conditions in the
1914 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1915 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1916 * control when FIFO occupancy reaches preset threshold, thus
1917 * halting RX. This only works when auto HW flow control is
1920 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1921 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1922 !(port->read_status_mask & UART_LSR_DR))
1925 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1926 if (!up->dma || handle_rx_dma(up, iir))
1927 status = serial8250_rx_chars(up, status);
1929 serial8250_modem_status(up);
1930 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1931 (up->ier & UART_IER_THRI))
1932 serial8250_tx_chars(up);
1934 uart_unlock_and_check_sysrq_irqrestore(port, flags);
1938 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1940 static int serial8250_default_handle_irq(struct uart_port *port)
1942 struct uart_8250_port *up = up_to_u8250p(port);
1946 serial8250_rpm_get(up);
1948 iir = serial_port_in(port, UART_IIR);
1949 ret = serial8250_handle_irq(port, iir);
1951 serial8250_rpm_put(up);
1956 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1957 * have a programmable TX threshold that triggers the THRE interrupt in
1958 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1959 * has space available. Load it up with tx_loadsz bytes.
1961 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1963 unsigned long flags;
1964 unsigned int iir = serial_port_in(port, UART_IIR);
1966 /* TX Threshold IRQ triggered so load up FIFO */
1967 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1968 struct uart_8250_port *up = up_to_u8250p(port);
1970 spin_lock_irqsave(&port->lock, flags);
1971 serial8250_tx_chars(up);
1972 spin_unlock_irqrestore(&port->lock, flags);
1975 iir = serial_port_in(port, UART_IIR);
1976 return serial8250_handle_irq(port, iir);
1979 static unsigned int serial8250_tx_empty(struct uart_port *port)
1981 struct uart_8250_port *up = up_to_u8250p(port);
1982 unsigned long flags;
1985 serial8250_rpm_get(up);
1987 spin_lock_irqsave(&port->lock, flags);
1988 lsr = serial_port_in(port, UART_LSR);
1989 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1990 spin_unlock_irqrestore(&port->lock, flags);
1992 serial8250_rpm_put(up);
1994 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1997 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1999 struct uart_8250_port *up = up_to_u8250p(port);
2000 unsigned int status;
2003 serial8250_rpm_get(up);
2004 status = serial8250_modem_status(up);
2005 serial8250_rpm_put(up);
2007 val = serial8250_MSR_to_TIOCM(status);
2009 return mctrl_gpio_get(up->gpios, &val);
2013 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2015 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2017 if (port->get_mctrl)
2018 return port->get_mctrl(port);
2019 return serial8250_do_get_mctrl(port);
2022 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2024 struct uart_8250_port *up = up_to_u8250p(port);
2027 if (port->rs485.flags & SER_RS485_ENABLED) {
2028 if (serial8250_in_MCR(up) & UART_MCR_RTS)
2031 mctrl &= ~TIOCM_RTS;
2034 mcr = serial8250_TIOCM_to_MCR(mctrl);
2036 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2038 serial8250_out_MCR(up, mcr);
2040 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2042 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2044 if (port->set_mctrl)
2045 port->set_mctrl(port, mctrl);
2047 serial8250_do_set_mctrl(port, mctrl);
2050 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2052 struct uart_8250_port *up = up_to_u8250p(port);
2053 unsigned long flags;
2055 serial8250_rpm_get(up);
2056 spin_lock_irqsave(&port->lock, flags);
2057 if (break_state == -1)
2058 up->lcr |= UART_LCR_SBC;
2060 up->lcr &= ~UART_LCR_SBC;
2061 serial_port_out(port, UART_LCR, up->lcr);
2062 spin_unlock_irqrestore(&port->lock, flags);
2063 serial8250_rpm_put(up);
2067 * Wait for transmitter & holding register to empty
2069 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2071 unsigned int status, tmout = 10000;
2073 /* Wait up to 10ms for the character(s) to be sent. */
2075 status = serial_in(up, UART_LSR);
2077 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2079 if ((status & bits) == bits)
2084 touch_nmi_watchdog();
2087 /* Wait up to 1s for flow control if necessary */
2088 if (up->port.flags & UPF_CONS_FLOW) {
2089 for (tmout = 1000000; tmout; tmout--) {
2090 unsigned int msr = serial_in(up, UART_MSR);
2091 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2092 if (msr & UART_MSR_CTS)
2095 touch_nmi_watchdog();
2100 #ifdef CONFIG_CONSOLE_POLL
2102 * Console polling routines for writing and reading from the uart while
2103 * in an interrupt or debug context.
2106 static int serial8250_get_poll_char(struct uart_port *port)
2108 struct uart_8250_port *up = up_to_u8250p(port);
2112 serial8250_rpm_get(up);
2114 lsr = serial_port_in(port, UART_LSR);
2116 if (!(lsr & UART_LSR_DR)) {
2117 status = NO_POLL_CHAR;
2121 status = serial_port_in(port, UART_RX);
2123 serial8250_rpm_put(up);
2128 static void serial8250_put_poll_char(struct uart_port *port,
2132 struct uart_8250_port *up = up_to_u8250p(port);
2134 serial8250_rpm_get(up);
2136 * First save the IER then disable the interrupts
2138 ier = serial_port_in(port, UART_IER);
2139 if (up->capabilities & UART_CAP_UUE)
2140 serial_port_out(port, UART_IER, UART_IER_UUE);
2142 serial_port_out(port, UART_IER, 0);
2144 wait_for_xmitr(up, BOTH_EMPTY);
2146 * Send the character out.
2148 serial_port_out(port, UART_TX, c);
2151 * Finally, wait for transmitter to become empty
2152 * and restore the IER
2154 wait_for_xmitr(up, BOTH_EMPTY);
2155 serial_port_out(port, UART_IER, ier);
2156 serial8250_rpm_put(up);
2159 #endif /* CONFIG_CONSOLE_POLL */
2161 int serial8250_do_startup(struct uart_port *port)
2163 struct uart_8250_port *up = up_to_u8250p(port);
2164 unsigned long flags;
2165 unsigned char lsr, iir;
2168 if (!port->fifosize)
2169 port->fifosize = uart_config[port->type].fifo_size;
2171 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2172 if (!up->capabilities)
2173 up->capabilities = uart_config[port->type].flags;
2176 if (port->iotype != up->cur_iotype)
2177 set_io_from_upio(port);
2179 serial8250_rpm_get(up);
2180 if (port->type == PORT_16C950) {
2181 /* Wake up and initialize UART */
2183 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2184 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2185 serial_port_out(port, UART_IER, 0);
2186 serial_port_out(port, UART_LCR, 0);
2187 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2188 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2189 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2190 serial_port_out(port, UART_LCR, 0);
2193 if (port->type == PORT_DA830) {
2194 /* Reset the port */
2195 serial_port_out(port, UART_IER, 0);
2196 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2199 /* Enable Tx, Rx and free run mode */
2200 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2201 UART_DA830_PWREMU_MGMT_UTRST |
2202 UART_DA830_PWREMU_MGMT_URRST |
2203 UART_DA830_PWREMU_MGMT_FREE);
2206 if (port->type == PORT_NPCM) {
2208 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2209 * register). Enable it, and set TIOC (timeout interrupt
2210 * comparator) to be 0x20 for correct operation.
2212 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2215 #ifdef CONFIG_SERIAL_8250_RSA
2217 * If this is an RSA port, see if we can kick it up to the
2218 * higher speed clock.
2224 * Clear the FIFO buffers and disable them.
2225 * (they will be reenabled in set_termios())
2227 serial8250_clear_fifos(up);
2230 * Clear the interrupt registers.
2232 serial_port_in(port, UART_LSR);
2233 serial_port_in(port, UART_RX);
2234 serial_port_in(port, UART_IIR);
2235 serial_port_in(port, UART_MSR);
2238 * At this point, there's no way the LSR could still be 0xff;
2239 * if it is, then bail out, because there's likely no UART
2242 if (!(port->flags & UPF_BUGGY_UART) &&
2243 (serial_port_in(port, UART_LSR) == 0xff)) {
2244 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2250 * For a XR16C850, we need to set the trigger levels
2252 if (port->type == PORT_16850) {
2255 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2257 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2258 serial_port_out(port, UART_FCTR,
2259 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2260 serial_port_out(port, UART_TRG, UART_TRG_96);
2261 serial_port_out(port, UART_FCTR,
2262 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2263 serial_port_out(port, UART_TRG, UART_TRG_96);
2265 serial_port_out(port, UART_LCR, 0);
2269 * For the Altera 16550 variants, set TX threshold trigger level.
2271 if (((port->type == PORT_ALTR_16550_F32) ||
2272 (port->type == PORT_ALTR_16550_F64) ||
2273 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2274 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2275 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2276 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2278 serial_port_out(port, UART_ALTR_AFR,
2279 UART_ALTR_EN_TXFIFO_LW);
2280 serial_port_out(port, UART_ALTR_TX_LOW,
2281 port->fifosize - up->tx_loadsz);
2282 port->handle_irq = serial8250_tx_threshold_handle_irq;
2286 /* Check if we need to have shared IRQs */
2287 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2288 up->port.irqflags |= IRQF_SHARED;
2290 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2293 if (port->irqflags & IRQF_SHARED)
2294 disable_irq_nosync(port->irq);
2297 * Test for UARTs that do not reassert THRE when the
2298 * transmitter is idle and the interrupt has already
2299 * been cleared. Real 16550s should always reassert
2300 * this interrupt whenever the transmitter is idle and
2301 * the interrupt is enabled. Delays are necessary to
2302 * allow register changes to become visible.
2304 spin_lock_irqsave(&port->lock, flags);
2306 wait_for_xmitr(up, UART_LSR_THRE);
2307 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2308 udelay(1); /* allow THRE to set */
2309 iir1 = serial_port_in(port, UART_IIR);
2310 serial_port_out(port, UART_IER, 0);
2311 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2312 udelay(1); /* allow a working UART time to re-assert THRE */
2313 iir = serial_port_in(port, UART_IIR);
2314 serial_port_out(port, UART_IER, 0);
2316 spin_unlock_irqrestore(&port->lock, flags);
2318 if (port->irqflags & IRQF_SHARED)
2319 enable_irq(port->irq);
2322 * If the interrupt is not reasserted, or we otherwise
2323 * don't trust the iir, setup a timer to kick the UART
2324 * on a regular basis.
2326 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2327 up->port.flags & UPF_BUG_THRE) {
2328 up->bugs |= UART_BUG_THRE;
2332 retval = up->ops->setup_irq(up);
2337 * Now, initialize the UART
2339 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2341 spin_lock_irqsave(&port->lock, flags);
2342 if (up->port.flags & UPF_FOURPORT) {
2344 up->port.mctrl |= TIOCM_OUT1;
2347 * Most PC uarts need OUT2 raised to enable interrupts.
2350 up->port.mctrl |= TIOCM_OUT2;
2352 serial8250_set_mctrl(port, port->mctrl);
2355 * Serial over Lan (SoL) hack:
2356 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2357 * used for Serial Over Lan. Those chips take a longer time than a
2358 * normal serial device to signalize that a transmission data was
2359 * queued. Due to that, the above test generally fails. One solution
2360 * would be to delay the reading of iir. However, this is not
2361 * reliable, since the timeout is variable. So, let's just don't
2362 * test if we receive TX irq. This way, we'll never enable
2365 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2366 goto dont_test_tx_en;
2369 * Do a quick test to see if we receive an interrupt when we enable
2372 serial_port_out(port, UART_IER, UART_IER_THRI);
2373 lsr = serial_port_in(port, UART_LSR);
2374 iir = serial_port_in(port, UART_IIR);
2375 serial_port_out(port, UART_IER, 0);
2377 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2378 if (!(up->bugs & UART_BUG_TXEN)) {
2379 up->bugs |= UART_BUG_TXEN;
2380 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2383 up->bugs &= ~UART_BUG_TXEN;
2387 spin_unlock_irqrestore(&port->lock, flags);
2390 * Clear the interrupt registers again for luck, and clear the
2391 * saved flags to avoid getting false values from polling
2392 * routines or the previous session.
2394 serial_port_in(port, UART_LSR);
2395 serial_port_in(port, UART_RX);
2396 serial_port_in(port, UART_IIR);
2397 serial_port_in(port, UART_MSR);
2398 up->lsr_saved_flags = 0;
2399 up->msr_saved_flags = 0;
2402 * Request DMA channels for both RX and TX.
2405 const char *msg = NULL;
2407 if (uart_console(port))
2408 msg = "forbid DMA for kernel console";
2409 else if (serial8250_request_dma(up))
2410 msg = "failed to request DMA";
2412 dev_warn_ratelimited(port->dev, "%s\n", msg);
2418 * Set the IER shadow for rx interrupts but defer actual interrupt
2419 * enable until after the FIFOs are enabled; otherwise, an already-
2420 * active sender can swamp the interrupt handler with "too much work".
2422 up->ier = UART_IER_RLSI | UART_IER_RDI;
2424 if (port->flags & UPF_FOURPORT) {
2427 * Enable interrupts on the AST Fourport board
2429 icp = (port->iobase & 0xfe0) | 0x01f;
2435 serial8250_rpm_put(up);
2438 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2440 static int serial8250_startup(struct uart_port *port)
2443 return port->startup(port);
2444 return serial8250_do_startup(port);
2447 void serial8250_do_shutdown(struct uart_port *port)
2449 struct uart_8250_port *up = up_to_u8250p(port);
2450 unsigned long flags;
2452 serial8250_rpm_get(up);
2454 * Disable interrupts from this port
2456 spin_lock_irqsave(&port->lock, flags);
2458 serial_port_out(port, UART_IER, 0);
2459 spin_unlock_irqrestore(&port->lock, flags);
2461 synchronize_irq(port->irq);
2464 serial8250_release_dma(up);
2466 spin_lock_irqsave(&port->lock, flags);
2467 if (port->flags & UPF_FOURPORT) {
2468 /* reset interrupts on the AST Fourport board */
2469 inb((port->iobase & 0xfe0) | 0x1f);
2470 port->mctrl |= TIOCM_OUT1;
2472 port->mctrl &= ~TIOCM_OUT2;
2474 serial8250_set_mctrl(port, port->mctrl);
2475 spin_unlock_irqrestore(&port->lock, flags);
2478 * Disable break condition and FIFOs
2480 serial_port_out(port, UART_LCR,
2481 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2482 serial8250_clear_fifos(up);
2484 #ifdef CONFIG_SERIAL_8250_RSA
2486 * Reset the RSA board back to 115kbps compat mode.
2492 * Read data port to reset things, and then unlink from
2495 serial_port_in(port, UART_RX);
2496 serial8250_rpm_put(up);
2498 up->ops->release_irq(up);
2500 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2502 static void serial8250_shutdown(struct uart_port *port)
2505 port->shutdown(port);
2507 serial8250_do_shutdown(port);
2510 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2511 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2514 struct uart_port *port = &up->port;
2516 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2519 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2523 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2524 struct uart_8250_port *up = up_to_u8250p(port);
2528 * Handle magic divisors for baud rates above baud_base on SMSC
2529 * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2530 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2531 * magic divisors actually reprogram the baud rate generator's
2532 * reference clock derived from chips's 14.318MHz clock input.
2534 * Documentation claims that with these magic divisors the base
2535 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2536 * for the extra baud rates of 460800bps and 230400bps rather
2537 * than the usual base frequency of 1.8462MHz. However empirical
2538 * evidence contradicts that.
2540 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2541 * effectively used as a clock prescaler selection bit for the
2542 * base frequency of 7.3728MHz, always used. If set to 0, then
2543 * the base frequency is divided by 4 for use by the Baud Rate
2544 * Generator, for the usual arrangement where the value of 1 of
2545 * the divisor produces the baud rate of 115200bps. Conversely,
2546 * if set to 1 and high-speed operation has been enabled with the
2547 * Serial Port Mode Register in the Device Configuration Space,
2548 * then the base frequency is supplied directly to the Baud Rate
2549 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2550 * 0x8004, etc. the respective baud rates produced are 460800bps,
2551 * 230400bps, 153600bps, 115200bps, etc.
2553 * In all cases only low 15 bits of the divisor are used to divide
2554 * the baud base and therefore 32767 is the maximum divisor value
2555 * possible, even though documentation says that the programmable
2556 * Baud Rate Generator is capable of dividing the internal PLL
2557 * clock by any divisor from 1 to 65535.
2559 if (magic_multiplier && baud >= port->uartclk / 6)
2561 else if (magic_multiplier && baud >= port->uartclk / 12)
2563 else if (up->port.type == PORT_NPCM)
2564 quot = npcm_get_divisor(up, baud);
2566 quot = uart_get_divisor(port, baud);
2569 * Oxford Semi 952 rev B workaround
2571 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2577 static unsigned int serial8250_get_divisor(struct uart_port *port,
2581 if (port->get_divisor)
2582 return port->get_divisor(port, baud, frac);
2584 return serial8250_do_get_divisor(port, baud, frac);
2587 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2592 switch (c_cflag & CSIZE) {
2594 cval = UART_LCR_WLEN5;
2597 cval = UART_LCR_WLEN6;
2600 cval = UART_LCR_WLEN7;
2604 cval = UART_LCR_WLEN8;
2608 if (c_cflag & CSTOPB)
2609 cval |= UART_LCR_STOP;
2610 if (c_cflag & PARENB) {
2611 cval |= UART_LCR_PARITY;
2612 if (up->bugs & UART_BUG_PARITY)
2613 up->fifo_bug = true;
2615 if (!(c_cflag & PARODD))
2616 cval |= UART_LCR_EPAR;
2618 if (c_cflag & CMSPAR)
2619 cval |= UART_LCR_SPAR;
2625 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2626 unsigned int quot, unsigned int quot_frac)
2628 struct uart_8250_port *up = up_to_u8250p(port);
2630 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2631 if (is_omap1510_8250(up)) {
2632 if (baud == 115200) {
2634 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2636 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2640 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2641 * otherwise just set DLAB
2643 if (up->capabilities & UART_NATSEMI)
2644 serial_port_out(port, UART_LCR, 0xe0);
2646 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2648 serial_dl_write(up, quot);
2650 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2652 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2653 unsigned int quot, unsigned int quot_frac)
2655 if (port->set_divisor)
2656 port->set_divisor(port, baud, quot, quot_frac);
2658 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2661 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2662 struct ktermios *termios,
2663 struct ktermios *old)
2665 unsigned int tolerance = port->uartclk / 100;
2670 * Handle magic divisors for baud rates above baud_base on SMSC
2671 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2672 * disable divisor values beyond 32767, which are unavailable.
2674 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2675 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2676 max = (port->uartclk + tolerance) / 4;
2678 min = port->uartclk / 16 / UART_DIV_MAX;
2679 max = (port->uartclk + tolerance) / 16;
2683 * Ask the core to calculate the divisor for us.
2684 * Allow 1% tolerance at the upper limit so uart clks marginally
2685 * slower than nominal still match standard baud rates without
2686 * causing transmission errors.
2688 return uart_get_baud_rate(port, termios, old, min, max);
2692 * Note in order to avoid the tty port mutex deadlock don't use the next method
2693 * within the uart port callbacks. Primarily it's supposed to be utilized to
2694 * handle a sudden reference clock rate change.
2696 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2698 struct uart_8250_port *up = up_to_u8250p(port);
2699 unsigned int baud, quot, frac = 0;
2700 struct ktermios *termios;
2701 unsigned long flags;
2703 mutex_lock(&port->state->port.mutex);
2705 if (port->uartclk == uartclk)
2708 port->uartclk = uartclk;
2710 if (!tty_port_initialized(&port->state->port))
2713 termios = &port->state->port.tty->termios;
2715 baud = serial8250_get_baud_rate(port, termios, NULL);
2716 quot = serial8250_get_divisor(port, baud, &frac);
2718 serial8250_rpm_get(up);
2719 spin_lock_irqsave(&port->lock, flags);
2721 uart_update_timeout(port, termios->c_cflag, baud);
2723 serial8250_set_divisor(port, baud, quot, frac);
2724 serial_port_out(port, UART_LCR, up->lcr);
2726 spin_unlock_irqrestore(&port->lock, flags);
2727 serial8250_rpm_put(up);
2730 mutex_unlock(&port->state->port.mutex);
2732 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2735 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2736 struct ktermios *old)
2738 struct uart_8250_port *up = up_to_u8250p(port);
2740 unsigned long flags;
2741 unsigned int baud, quot, frac = 0;
2743 if (up->capabilities & UART_CAP_MINI) {
2744 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2745 if ((termios->c_cflag & CSIZE) == CS5 ||
2746 (termios->c_cflag & CSIZE) == CS6)
2747 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2749 cval = serial8250_compute_lcr(up, termios->c_cflag);
2751 baud = serial8250_get_baud_rate(port, termios, old);
2752 quot = serial8250_get_divisor(port, baud, &frac);
2755 * Ok, we're now changing the port state. Do it with
2756 * interrupts disabled.
2758 serial8250_rpm_get(up);
2759 spin_lock_irqsave(&port->lock, flags);
2761 up->lcr = cval; /* Save computed LCR */
2763 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2764 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2765 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2766 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2767 up->fcr |= UART_FCR_TRIGGER_1;
2772 * MCR-based auto flow control. When AFE is enabled, RTS will be
2773 * deasserted when the receive FIFO contains more characters than
2774 * the trigger, or the MCR RTS bit is cleared.
2776 if (up->capabilities & UART_CAP_AFE) {
2777 up->mcr &= ~UART_MCR_AFE;
2778 if (termios->c_cflag & CRTSCTS)
2779 up->mcr |= UART_MCR_AFE;
2783 * Update the per-port timeout.
2785 uart_update_timeout(port, termios->c_cflag, baud);
2787 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2788 if (termios->c_iflag & INPCK)
2789 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2790 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2791 port->read_status_mask |= UART_LSR_BI;
2794 * Characteres to ignore
2796 port->ignore_status_mask = 0;
2797 if (termios->c_iflag & IGNPAR)
2798 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2799 if (termios->c_iflag & IGNBRK) {
2800 port->ignore_status_mask |= UART_LSR_BI;
2802 * If we're ignoring parity and break indicators,
2803 * ignore overruns too (for real raw support).
2805 if (termios->c_iflag & IGNPAR)
2806 port->ignore_status_mask |= UART_LSR_OE;
2810 * ignore all characters if CREAD is not set
2812 if ((termios->c_cflag & CREAD) == 0)
2813 port->ignore_status_mask |= UART_LSR_DR;
2816 * CTS flow control flag and modem status interrupts
2818 up->ier &= ~UART_IER_MSI;
2819 if (!(up->bugs & UART_BUG_NOMSR) &&
2820 UART_ENABLE_MS(&up->port, termios->c_cflag))
2821 up->ier |= UART_IER_MSI;
2822 if (up->capabilities & UART_CAP_UUE)
2823 up->ier |= UART_IER_UUE;
2824 if (up->capabilities & UART_CAP_RTOIE)
2825 up->ier |= UART_IER_RTOIE;
2827 serial_port_out(port, UART_IER, up->ier);
2829 if (up->capabilities & UART_CAP_EFR) {
2830 unsigned char efr = 0;
2832 * TI16C752/Startech hardware flow control. FIXME:
2833 * - TI16C752 requires control thresholds to be set.
2834 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2836 if (termios->c_cflag & CRTSCTS)
2837 efr |= UART_EFR_CTS;
2839 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2840 if (port->flags & UPF_EXAR_EFR)
2841 serial_port_out(port, UART_XR_EFR, efr);
2843 serial_port_out(port, UART_EFR, efr);
2846 serial8250_set_divisor(port, baud, quot, frac);
2849 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2850 * is written without DLAB set, this mode will be disabled.
2852 if (port->type == PORT_16750)
2853 serial_port_out(port, UART_FCR, up->fcr);
2855 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2856 if (port->type != PORT_16750) {
2857 /* emulated UARTs (Lucent Venus 167x) need two steps */
2858 if (up->fcr & UART_FCR_ENABLE_FIFO)
2859 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2860 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2862 serial8250_set_mctrl(port, port->mctrl);
2863 spin_unlock_irqrestore(&port->lock, flags);
2864 serial8250_rpm_put(up);
2866 /* Don't rewrite B0 */
2867 if (tty_termios_baud_rate(termios))
2868 tty_termios_encode_baud_rate(termios, baud, baud);
2870 EXPORT_SYMBOL(serial8250_do_set_termios);
2873 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2874 struct ktermios *old)
2876 if (port->set_termios)
2877 port->set_termios(port, termios, old);
2879 serial8250_do_set_termios(port, termios, old);
2882 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2884 if (termios->c_line == N_PPS) {
2885 port->flags |= UPF_HARDPPS_CD;
2886 spin_lock_irq(&port->lock);
2887 serial8250_enable_ms(port);
2888 spin_unlock_irq(&port->lock);
2890 port->flags &= ~UPF_HARDPPS_CD;
2891 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2892 spin_lock_irq(&port->lock);
2893 serial8250_disable_ms(port);
2894 spin_unlock_irq(&port->lock);
2898 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2901 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2903 if (port->set_ldisc)
2904 port->set_ldisc(port, termios);
2906 serial8250_do_set_ldisc(port, termios);
2909 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2910 unsigned int oldstate)
2912 struct uart_8250_port *p = up_to_u8250p(port);
2914 serial8250_set_sleep(p, state != 0);
2916 EXPORT_SYMBOL(serial8250_do_pm);
2919 serial8250_pm(struct uart_port *port, unsigned int state,
2920 unsigned int oldstate)
2923 port->pm(port, state, oldstate);
2925 serial8250_do_pm(port, state, oldstate);
2928 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2930 if (pt->port.mapsize)
2931 return pt->port.mapsize;
2932 if (pt->port.iotype == UPIO_AU) {
2933 if (pt->port.type == PORT_RT2880)
2937 if (is_omap1_8250(pt))
2938 return 0x16 << pt->port.regshift;
2940 return 8 << pt->port.regshift;
2944 * Resource handling.
2946 static int serial8250_request_std_resource(struct uart_8250_port *up)
2948 unsigned int size = serial8250_port_size(up);
2949 struct uart_port *port = &up->port;
2952 switch (port->iotype) {
2962 if (!request_mem_region(port->mapbase, size, "serial")) {
2967 if (port->flags & UPF_IOREMAP) {
2968 port->membase = ioremap(port->mapbase, size);
2969 if (!port->membase) {
2970 release_mem_region(port->mapbase, size);
2978 if (!request_region(port->iobase, size, "serial"))
2985 static void serial8250_release_std_resource(struct uart_8250_port *up)
2987 unsigned int size = serial8250_port_size(up);
2988 struct uart_port *port = &up->port;
2990 switch (port->iotype) {
3000 if (port->flags & UPF_IOREMAP) {
3001 iounmap(port->membase);
3002 port->membase = NULL;
3005 release_mem_region(port->mapbase, size);
3010 release_region(port->iobase, size);
3015 static void serial8250_release_port(struct uart_port *port)
3017 struct uart_8250_port *up = up_to_u8250p(port);
3019 serial8250_release_std_resource(up);
3022 static int serial8250_request_port(struct uart_port *port)
3024 struct uart_8250_port *up = up_to_u8250p(port);
3026 return serial8250_request_std_resource(up);
3029 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3031 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3032 unsigned char bytes;
3034 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3036 return bytes ? bytes : -EOPNOTSUPP;
3039 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3041 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3044 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3047 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3048 if (bytes < conf_type->rxtrig_bytes[i])
3049 /* Use the nearest lower value */
3050 return (--i) << UART_FCR_R_TRIG_SHIFT;
3053 return UART_FCR_R_TRIG_11;
3056 static int do_get_rxtrig(struct tty_port *port)
3058 struct uart_state *state = container_of(port, struct uart_state, port);
3059 struct uart_port *uport = state->uart_port;
3060 struct uart_8250_port *up = up_to_u8250p(uport);
3062 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3065 return fcr_get_rxtrig_bytes(up);
3068 static int do_serial8250_get_rxtrig(struct tty_port *port)
3072 mutex_lock(&port->mutex);
3073 rxtrig_bytes = do_get_rxtrig(port);
3074 mutex_unlock(&port->mutex);
3076 return rxtrig_bytes;
3079 static ssize_t rx_trig_bytes_show(struct device *dev,
3080 struct device_attribute *attr, char *buf)
3082 struct tty_port *port = dev_get_drvdata(dev);
3085 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3086 if (rxtrig_bytes < 0)
3087 return rxtrig_bytes;
3089 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
3092 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3094 struct uart_state *state = container_of(port, struct uart_state, port);
3095 struct uart_port *uport = state->uart_port;
3096 struct uart_8250_port *up = up_to_u8250p(uport);
3099 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3103 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3107 serial8250_clear_fifos(up);
3108 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3109 up->fcr |= (unsigned char)rxtrig;
3110 serial_out(up, UART_FCR, up->fcr);
3114 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3118 mutex_lock(&port->mutex);
3119 ret = do_set_rxtrig(port, bytes);
3120 mutex_unlock(&port->mutex);
3125 static ssize_t rx_trig_bytes_store(struct device *dev,
3126 struct device_attribute *attr, const char *buf, size_t count)
3128 struct tty_port *port = dev_get_drvdata(dev);
3129 unsigned char bytes;
3135 ret = kstrtou8(buf, 10, &bytes);
3139 ret = do_serial8250_set_rxtrig(port, bytes);
3146 static DEVICE_ATTR_RW(rx_trig_bytes);
3148 static struct attribute *serial8250_dev_attrs[] = {
3149 &dev_attr_rx_trig_bytes.attr,
3153 static struct attribute_group serial8250_dev_attr_group = {
3154 .attrs = serial8250_dev_attrs,
3157 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3159 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3161 if (conf_type->rxtrig_bytes[0])
3162 up->port.attr_group = &serial8250_dev_attr_group;
3165 static void serial8250_config_port(struct uart_port *port, int flags)
3167 struct uart_8250_port *up = up_to_u8250p(port);
3171 * Find the region that we can probe for. This in turn
3172 * tells us whether we can probe for the type of port.
3174 ret = serial8250_request_std_resource(up);
3178 if (port->iotype != up->cur_iotype)
3179 set_io_from_upio(port);
3181 if (flags & UART_CONFIG_TYPE)
3184 if (port->rs485.flags & SER_RS485_ENABLED)
3185 port->rs485_config(port, &port->rs485);
3187 /* if access method is AU, it is a 16550 with a quirk */
3188 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3189 up->bugs |= UART_BUG_NOMSR;
3191 /* HW bugs may trigger IRQ while IIR == NO_INT */
3192 if (port->type == PORT_TEGRA)
3193 up->bugs |= UART_BUG_NOMSR;
3195 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3198 if (port->type == PORT_UNKNOWN)
3199 serial8250_release_std_resource(up);
3201 register_dev_spec_attr_grp(up);
3202 up->fcr = uart_config[up->port.type].fcr;
3206 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3208 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3209 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3210 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3211 ser->type == PORT_STARTECH)
3216 static const char *serial8250_type(struct uart_port *port)
3218 int type = port->type;
3220 if (type >= ARRAY_SIZE(uart_config))
3222 return uart_config[type].name;
3225 static const struct uart_ops serial8250_pops = {
3226 .tx_empty = serial8250_tx_empty,
3227 .set_mctrl = serial8250_set_mctrl,
3228 .get_mctrl = serial8250_get_mctrl,
3229 .stop_tx = serial8250_stop_tx,
3230 .start_tx = serial8250_start_tx,
3231 .throttle = serial8250_throttle,
3232 .unthrottle = serial8250_unthrottle,
3233 .stop_rx = serial8250_stop_rx,
3234 .enable_ms = serial8250_enable_ms,
3235 .break_ctl = serial8250_break_ctl,
3236 .startup = serial8250_startup,
3237 .shutdown = serial8250_shutdown,
3238 .set_termios = serial8250_set_termios,
3239 .set_ldisc = serial8250_set_ldisc,
3240 .pm = serial8250_pm,
3241 .type = serial8250_type,
3242 .release_port = serial8250_release_port,
3243 .request_port = serial8250_request_port,
3244 .config_port = serial8250_config_port,
3245 .verify_port = serial8250_verify_port,
3246 #ifdef CONFIG_CONSOLE_POLL
3247 .poll_get_char = serial8250_get_poll_char,
3248 .poll_put_char = serial8250_put_poll_char,
3252 void serial8250_init_port(struct uart_8250_port *up)
3254 struct uart_port *port = &up->port;
3256 spin_lock_init(&port->lock);
3257 port->ops = &serial8250_pops;
3258 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3260 up->cur_iotype = 0xFF;
3262 EXPORT_SYMBOL_GPL(serial8250_init_port);
3264 void serial8250_set_defaults(struct uart_8250_port *up)
3266 struct uart_port *port = &up->port;
3268 if (up->port.flags & UPF_FIXED_TYPE) {
3269 unsigned int type = up->port.type;
3271 if (!up->port.fifosize)
3272 up->port.fifosize = uart_config[type].fifo_size;
3274 up->tx_loadsz = uart_config[type].tx_loadsz;
3275 if (!up->capabilities)
3276 up->capabilities = uart_config[type].flags;
3279 set_io_from_upio(port);
3281 /* default dma handlers */
3283 if (!up->dma->tx_dma)
3284 up->dma->tx_dma = serial8250_tx_dma;
3285 if (!up->dma->rx_dma)
3286 up->dma->rx_dma = serial8250_rx_dma;
3289 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3291 #ifdef CONFIG_SERIAL_8250_CONSOLE
3293 static void serial8250_console_putchar(struct uart_port *port, int ch)
3295 struct uart_8250_port *up = up_to_u8250p(port);
3297 wait_for_xmitr(up, UART_LSR_THRE);
3298 serial_port_out(port, UART_TX, ch);
3302 * Restore serial console when h/w power-off detected
3304 static void serial8250_console_restore(struct uart_8250_port *up)
3306 struct uart_port *port = &up->port;
3307 struct ktermios termios;
3308 unsigned int baud, quot, frac = 0;
3310 termios.c_cflag = port->cons->cflag;
3311 if (port->state->port.tty && termios.c_cflag == 0)
3312 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3314 baud = serial8250_get_baud_rate(port, &termios, NULL);
3315 quot = serial8250_get_divisor(port, baud, &frac);
3317 serial8250_set_divisor(port, baud, quot, frac);
3318 serial_port_out(port, UART_LCR, up->lcr);
3319 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3323 * Print a string to the serial port trying not to disturb
3324 * any possible real use of the port...
3326 * The console_lock must be held when we get here.
3328 * Doing runtime PM is really a bad idea for the kernel console.
3329 * Thus, we assume the function is called when device is powered up.
3331 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3334 struct uart_8250_em485 *em485 = up->em485;
3335 struct uart_port *port = &up->port;
3336 unsigned long flags;
3340 touch_nmi_watchdog();
3342 if (oops_in_progress)
3343 locked = spin_trylock_irqsave(&port->lock, flags);
3345 spin_lock_irqsave(&port->lock, flags);
3348 * First save the IER then disable the interrupts
3350 ier = serial_port_in(port, UART_IER);
3352 if (up->capabilities & UART_CAP_UUE)
3353 serial_port_out(port, UART_IER, UART_IER_UUE);
3355 serial_port_out(port, UART_IER, 0);
3357 /* check scratch reg to see if port powered off during system sleep */
3358 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3359 serial8250_console_restore(up);
3364 if (em485->tx_stopped)
3365 up->rs485_start_tx(up);
3366 mdelay(port->rs485.delay_rts_before_send);
3369 uart_console_write(port, s, count, serial8250_console_putchar);
3372 * Finally, wait for transmitter to become empty
3373 * and restore the IER
3375 wait_for_xmitr(up, BOTH_EMPTY);
3378 mdelay(port->rs485.delay_rts_after_send);
3379 if (em485->tx_stopped)
3380 up->rs485_stop_tx(up);
3383 serial_port_out(port, UART_IER, ier);
3386 * The receive handling will happen properly because the
3387 * receive ready bit will still be set; it is not cleared
3388 * on read. However, modem control will not, we must
3389 * call it if we have saved something in the saved flags
3390 * while processing with interrupts off.
3392 if (up->msr_saved_flags)
3393 serial8250_modem_status(up);
3396 spin_unlock_irqrestore(&port->lock, flags);
3399 static unsigned int probe_baud(struct uart_port *port)
3401 unsigned char lcr, dll, dlm;
3404 lcr = serial_port_in(port, UART_LCR);
3405 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3406 dll = serial_port_in(port, UART_DLL);
3407 dlm = serial_port_in(port, UART_DLM);
3408 serial_port_out(port, UART_LCR, lcr);
3410 quot = (dlm << 8) | dll;
3411 return (port->uartclk / 16) / quot;
3414 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3422 if (!port->iobase && !port->membase)
3426 uart_parse_options(options, &baud, &parity, &bits, &flow);
3428 baud = probe_baud(port);
3430 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3435 pm_runtime_get_sync(port->dev);
3440 int serial8250_console_exit(struct uart_port *port)
3443 pm_runtime_put_sync(port->dev);
3448 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3450 MODULE_LICENSE("GPL");