drivers/thunderbolt/nhi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Thunderbolt driver - NHI driver
   4  *
   5  * The NHI (native host interface) is the pci device that allows us to send and
   6  * receive frames from the thunderbolt bus.
   7  *
   8  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
   9  * Copyright (C) 2018, Intel Corporation
  10  */
  11
  12 #include <linux/pm_runtime.h>
  13 #include <linux/slab.h>
  14 #include <linux/errno.h>
  15 #include <linux/pci.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/module.h>
  18 #include <linux/delay.h>
  19 #include <linux/property.h>
  20
  21 #include "nhi.h"
  22 #include "nhi_regs.h"
  23 #include "tb.h"
  24
  25 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
  26
  27 #define RING_FIRST_USABLE_HOPID 1
  28
  29 /*
  30  * Minimal number of vectors when we use MSI-X. Two for control channel
  31  * Rx/Tx and the rest four are for cross domain DMA paths.
  32  */
  33 #define MSIX_MIN_VECS           6
  34 #define MSIX_MAX_VECS           16
  35
  36 #define NHI_MAILBOX_TIMEOUT     500 /* ms */
  37
  38 static int ring_interrupt_index(struct tb_ring *ring)
  39 {
  40         int bit = ring->hop;
  41         if (!ring->is_tx)
  42                 bit += ring->nhi->hop_count;
  43         return bit;
  44 }
  45
  46 /*
  47  * ring_interrupt_active() - activate/deactivate interrupts for a single ring
  48  *
  49  * ring->nhi->lock must be held.
  50  */
  51 static void ring_interrupt_active(struct tb_ring *ring, bool active)
  52 {
  53         int reg = REG_RING_INTERRUPT_BASE +
  54                   ring_interrupt_index(ring) / 32 * 4;
  55         int bit = ring_interrupt_index(ring) & 31;
  56         int mask = 1 << bit;
  57         u32 old, new;
  58
  59         if (ring->irq > 0) {
  60                 u32 step, shift, ivr, misc;
  61                 void __iomem *ivr_base;
  62                 int index;
  63
  64                 if (ring->is_tx)
  65                         index = ring->hop;
  66                 else
  67                         index = ring->hop + ring->nhi->hop_count;
  68
  69                 /*
  70                  * Ask the hardware to clear interrupt status bits automatically
  71                  * since we already know which interrupt was triggered.
  72                  */
  73                 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
  74                 if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) {
  75                         misc |= REG_DMA_MISC_INT_AUTO_CLEAR;
  76                         iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC);
  77                 }
  78
  79                 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
  80                 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
  81                 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
  82                 ivr = ioread32(ivr_base + step);
  83                 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
  84                 if (active)
  85                         ivr |= ring->vector << shift;
  86                 iowrite32(ivr, ivr_base + step);
  87         }
  88
  89         old = ioread32(ring->nhi->iobase + reg);
  90         if (active)
  91                 new = old | mask;
  92         else
  93                 new = old & ~mask;
  94
  95         dev_dbg(&ring->nhi->pdev->dev,
  96                 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
  97                 active ? "enabling" : "disabling", reg, bit, old, new);
  98
  99         if (new == old)
 100                 dev_WARN(&ring->nhi->pdev->dev,
 101                                          "interrupt for %s %d is already %s\n",
 102                                          RING_TYPE(ring), ring->hop,
 103                                          active ? "enabled" : "disabled");
 104         iowrite32(new, ring->nhi->iobase + reg);
 105 }
 106
 107 /*
 108  * nhi_disable_interrupts() - disable interrupts for all rings
 109  *
 110  * Use only during init and shutdown.
 111  */
 112 static void nhi_disable_interrupts(struct tb_nhi *nhi)
 113 {
 114         int i = 0;
 115         /* disable interrupts */
 116         for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
 117                 iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i);
 118
 119         /* clear interrupt status bits */
 120         for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
 121                 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i);
 122 }
 123
 124 /* ring helper methods */
 125
 126 static void __iomem *ring_desc_base(struct tb_ring *ring)
 127 {
 128         void __iomem *io = ring->nhi->iobase;
 129         io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
 130         io += ring->hop * 16;
 131         return io;
 132 }
 133
 134 static void __iomem *ring_options_base(struct tb_ring *ring)
 135 {
 136         void __iomem *io = ring->nhi->iobase;
 137         io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
 138         io += ring->hop * 32;
 139         return io;
 140 }
 141
 142 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
 143 {
 144         /*
 145          * The other 16-bits in the register is read-only and writes to it
 146          * are ignored by the hardware so we can save one ioread32() by
 147          * filling the read-only bits with zeroes.
 148          */
 149         iowrite32(cons, ring_desc_base(ring) + 8);
 150 }
 151
 152 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
 153 {
 154         /* See ring_iowrite_cons() above for explanation */
 155         iowrite32(prod << 16, ring_desc_base(ring) + 8);
 156 }
 157
 158 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
 159 {
 160         iowrite32(value, ring_desc_base(ring) + offset);
 161 }
 162
 163 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
 164 {
 165         iowrite32(value, ring_desc_base(ring) + offset);
 166         iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
 167 }
 168
 169 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
 170 {
 171         iowrite32(value, ring_options_base(ring) + offset);
 172 }
 173
 174 static bool ring_full(struct tb_ring *ring)
 175 {
 176         return ((ring->head + 1) % ring->size) == ring->tail;
 177 }
 178
 179 static bool ring_empty(struct tb_ring *ring)
 180 {
 181         return ring->head == ring->tail;
 182 }
 183
 184 /*
 185  * ring_write_descriptors() - post frames from ring->queue to the controller
 186  *
 187  * ring->lock is held.
 188  */
 189 static void ring_write_descriptors(struct tb_ring *ring)
 190 {
 191         struct ring_frame *frame, *n;
 192         struct ring_desc *descriptor;
 193         list_for_each_entry_safe(frame, n, &ring->queue, list) {
 194                 if (ring_full(ring))
 195                         break;
 196                 list_move_tail(&frame->list, &ring->in_flight);
 197                 descriptor = &ring->descriptors[ring->head];
 198                 descriptor->phys = frame->buffer_phy;
 199                 descriptor->time = 0;
 200                 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
 201                 if (ring->is_tx) {
 202                         descriptor->length = frame->size;
 203                         descriptor->eof = frame->eof;
 204                         descriptor->sof = frame->sof;
 205                 }
 206                 ring->head = (ring->head + 1) % ring->size;
 207                 if (ring->is_tx)
 208                         ring_iowrite_prod(ring, ring->head);
 209                 else
 210                         ring_iowrite_cons(ring, ring->head);
 211         }
 212 }
 213
 214 /*
 215  * ring_work() - progress completed frames
 216  *
 217  * If the ring is shutting down then all frames are marked as canceled and
 218  * their callbacks are invoked.
 219  *
 220  * Otherwise we collect all completed frame from the ring buffer, write new
 221  * frame to the ring buffer and invoke the callbacks for the completed frames.
 222  */
 223 static void ring_work(struct work_struct *work)
 224 {
 225         struct tb_ring *ring = container_of(work, typeof(*ring), work);
 226         struct ring_frame *frame;
 227         bool canceled = false;
 228         unsigned long flags;
 229         LIST_HEAD(done);
 230
 231         spin_lock_irqsave(&ring->lock, flags);
 232
 233         if (!ring->running) {
 234                 /*  Move all frames to done and mark them as canceled. */
 235                 list_splice_tail_init(&ring->in_flight, &done);
 236                 list_splice_tail_init(&ring->queue, &done);
 237                 canceled = true;
 238                 goto invoke_callback;
 239         }
 240
 241         while (!ring_empty(ring)) {
 242                 if (!(ring->descriptors[ring->tail].flags
 243                                 & RING_DESC_COMPLETED))
 244                         break;
 245                 frame = list_first_entry(&ring->in_flight, typeof(*frame),
 246                                          list);
 247                 list_move_tail(&frame->list, &done);
 248                 if (!ring->is_tx) {
 249                         frame->size = ring->descriptors[ring->tail].length;
 250                         frame->eof = ring->descriptors[ring->tail].eof;
 251                         frame->sof = ring->descriptors[ring->tail].sof;
 252                         frame->flags = ring->descriptors[ring->tail].flags;
 253                 }
 254                 ring->tail = (ring->tail + 1) % ring->size;
 255         }
 256         ring_write_descriptors(ring);
 257
 258 invoke_callback:
 259         /* allow callbacks to schedule new work */
 260         spin_unlock_irqrestore(&ring->lock, flags);
 261         while (!list_empty(&done)) {
 262                 frame = list_first_entry(&done, typeof(*frame), list);
 263                 /*
 264                  * The callback may reenqueue or delete frame.
 265                  * Do not hold on to it.
 266                  */
 267                 list_del_init(&frame->list);
 268                 if (frame->callback)
 269                         frame->callback(ring, frame, canceled);
 270         }
 271 }
 272
 273 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
 274 {
 275         unsigned long flags;
 276         int ret = 0;
 277
 278         spin_lock_irqsave(&ring->lock, flags);
 279         if (ring->running) {
 280                 list_add_tail(&frame->list, &ring->queue);
 281                 ring_write_descriptors(ring);
 282         } else {
 283                 ret = -ESHUTDOWN;
 284         }
 285         spin_unlock_irqrestore(&ring->lock, flags);
 286         return ret;
 287 }
 288 EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
 289
 290 /**
 291  * tb_ring_poll() - Poll one completed frame from the ring
 292  * @ring: Ring to poll
 293  *
 294  * This function can be called when @start_poll callback of the @ring
 295  * has been called. It will read one completed frame from the ring and
 296  * return it to the caller. Returns %NULL if there is no more completed
 297  * frames.
 298  */
 299 struct ring_frame *tb_ring_poll(struct tb_ring *ring)
 300 {
 301         struct ring_frame *frame = NULL;
 302         unsigned long flags;
 303
 304         spin_lock_irqsave(&ring->lock, flags);
 305         if (!ring->running)
 306                 goto unlock;
 307         if (ring_empty(ring))
 308                 goto unlock;
 309
 310         if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
 311                 frame = list_first_entry(&ring->in_flight, typeof(*frame),
 312                                          list);
 313                 list_del_init(&frame->list);
 314
 315                 if (!ring->is_tx) {
 316                         frame->size = ring->descriptors[ring->tail].length;
 317                         frame->eof = ring->descriptors[ring->tail].eof;
 318                         frame->sof = ring->descriptors[ring->tail].sof;
 319                         frame->flags = ring->descriptors[ring->tail].flags;
 320                 }
 321
 322                 ring->tail = (ring->tail + 1) % ring->size;
 323         }
 324
 325 unlock:
 326         spin_unlock_irqrestore(&ring->lock, flags);
 327         return frame;
 328 }
 329 EXPORT_SYMBOL_GPL(tb_ring_poll);
 330
 331 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
 332 {
 333         int idx = ring_interrupt_index(ring);
 334         int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
 335         int bit = idx % 32;
 336         u32 val;
 337
 338         val = ioread32(ring->nhi->iobase + reg);
 339         if (mask)
 340                 val &= ~BIT(bit);
 341         else
 342                 val |= BIT(bit);
 343         iowrite32(val, ring->nhi->iobase + reg);
 344 }
 345
 346 /* Both @nhi->lock and @ring->lock should be held */
 347 static void __ring_interrupt(struct tb_ring *ring)
 348 {
 349         if (!ring->running)
 350                 return;
 351
 352         if (ring->start_poll) {
 353                 __ring_interrupt_mask(ring, true);
 354                 ring->start_poll(ring->poll_data);
 355         } else {
 356                 schedule_work(&ring->work);
 357         }
 358 }
 359
 360 /**
 361  * tb_ring_poll_complete() - Re-start interrupt for the ring
 362  * @ring: Ring to re-start the interrupt
 363  *
 364  * This will re-start (unmask) the ring interrupt once the user is done
 365  * with polling.
 366  */
 367 void tb_ring_poll_complete(struct tb_ring *ring)
 368 {
 369         unsigned long flags;
 370
 371         spin_lock_irqsave(&ring->nhi->lock, flags);
 372         spin_lock(&ring->lock);
 373         if (ring->start_poll)
 374                 __ring_interrupt_mask(ring, false);
 375         spin_unlock(&ring->lock);
 376         spin_unlock_irqrestore(&ring->nhi->lock, flags);
 377 }
 378 EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
 379
 380 static irqreturn_t ring_msix(int irq, void *data)
 381 {
 382         struct tb_ring *ring = data;
 383
 384         spin_lock(&ring->nhi->lock);
 385         spin_lock(&ring->lock);
 386         __ring_interrupt(ring);
 387         spin_unlock(&ring->lock);
 388         spin_unlock(&ring->nhi->lock);
 389
 390         return IRQ_HANDLED;
 391 }
 392
 393 static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
 394 {
 395         struct tb_nhi *nhi = ring->nhi;
 396         unsigned long irqflags;
 397         int ret;
 398
 399         if (!nhi->pdev->msix_enabled)
 400                 return 0;
 401
 402         ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
 403         if (ret < 0)
 404                 return ret;
 405
 406         ring->vector = ret;
 407
 408         ret = pci_irq_vector(ring->nhi->pdev, ring->vector);
 409         if (ret < 0)
 410                 goto err_ida_remove;
 411
 412         ring->irq = ret;
 413
 414         irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
 415         ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
 416         if (ret)
 417                 goto err_ida_remove;
 418
 419         return 0;
 420
 421 err_ida_remove:
 422         ida_simple_remove(&nhi->msix_ida, ring->vector);
 423
 424         return ret;
 425 }
 426
 427 static void ring_release_msix(struct tb_ring *ring)
 428 {
 429         if (ring->irq <= 0)
 430                 return;
 431
 432         free_irq(ring->irq, ring);
 433         ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
 434         ring->vector = 0;
 435         ring->irq = 0;
 436 }
 437
 438 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
 439 {
 440         int ret = 0;
 441
 442         spin_lock_irq(&nhi->lock);
 443
 444         if (ring->hop < 0) {
 445                 unsigned int i;
 446
 447                 /*
 448                  * Automatically allocate HopID from the non-reserved
 449                  * range 1 .. hop_count - 1.
 450                  */
 451                 for (i = RING_FIRST_USABLE_HOPID; i < nhi->hop_count; i++) {
 452                         if (ring->is_tx) {
 453                                 if (!nhi->tx_rings[i]) {
 454                                         ring->hop = i;
 455                                         break;
 456                                 }
 457                         } else {
 458                                 if (!nhi->rx_rings[i]) {
 459                                         ring->hop = i;
 460                                         break;
 461                                 }
 462                         }
 463                 }
 464         }
 465
 466         if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
 467                 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
 468                 ret = -EINVAL;
 469                 goto err_unlock;
 470         }
 471         if (ring->is_tx && nhi->tx_rings[ring->hop]) {
 472                 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
 473                          ring->hop);
 474                 ret = -EBUSY;
 475                 goto err_unlock;
 476         } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
 477                 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
 478                          ring->hop);
 479                 ret = -EBUSY;
 480                 goto err_unlock;
 481         }
 482
 483         if (ring->is_tx)
 484                 nhi->tx_rings[ring->hop] = ring;
 485         else
 486                 nhi->rx_rings[ring->hop] = ring;
 487
 488 err_unlock:
 489         spin_unlock_irq(&nhi->lock);
 490
 491         return ret;
 492 }
 493
 494 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
 495                                      bool transmit, unsigned int flags,
 496                                      int e2e_tx_hop, u16 sof_mask, u16 eof_mask,
 497                                      void (*start_poll)(void *),
 498                                      void *poll_data)
 499 {
 500         struct tb_ring *ring = NULL;
 501
 502         dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
 503                 transmit ? "TX" : "RX", hop, size);
 504
 505         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 506         if (!ring)
 507                 return NULL;
 508
 509         spin_lock_init(&ring->lock);
 510         INIT_LIST_HEAD(&ring->queue);
 511         INIT_LIST_HEAD(&ring->in_flight);
 512         INIT_WORK(&ring->work, ring_work);
 513
 514         ring->nhi = nhi;
 515         ring->hop = hop;
 516         ring->is_tx = transmit;
 517         ring->size = size;
 518         ring->flags = flags;
 519         ring->e2e_tx_hop = e2e_tx_hop;
 520         ring->sof_mask = sof_mask;
 521         ring->eof_mask = eof_mask;
 522         ring->head = 0;
 523         ring->tail = 0;
 524         ring->running = false;
 525         ring->start_poll = start_poll;
 526         ring->poll_data = poll_data;
 527
 528         ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
 529                         size * sizeof(*ring->descriptors),
 530                         &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
 531         if (!ring->descriptors)
 532                 goto err_free_ring;
 533
 534         if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
 535                 goto err_free_descs;
 536
 537         if (nhi_alloc_hop(nhi, ring))
 538                 goto err_release_msix;
 539
 540         return ring;
 541
 542 err_release_msix:
 543         ring_release_msix(ring);
 544 err_free_descs:
 545         dma_free_coherent(&ring->nhi->pdev->dev,
 546                           ring->size * sizeof(*ring->descriptors),
 547                           ring->descriptors, ring->descriptors_dma);
 548 err_free_ring:
 549         kfree(ring);
 550
 551         return NULL;
 552 }
 553
 554 /**
 555  * tb_ring_alloc_tx() - Allocate DMA ring for transmit
 556  * @nhi: Pointer to the NHI the ring is to be allocated
 557  * @hop: HopID (ring) to allocate
 558  * @size: Number of entries in the ring
 559  * @flags: Flags for the ring
 560  */
 561 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
 562                                  unsigned int flags)
 563 {
 564         return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL);
 565 }
 566 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
 567
 568 /**
 569  * tb_ring_alloc_rx() - Allocate DMA ring for receive
 570  * @nhi: Pointer to the NHI the ring is to be allocated
 571  * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
 572  * @size: Number of entries in the ring
 573  * @flags: Flags for the ring
 574  * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags
 575  * @sof_mask: Mask of PDF values that start a frame
 576  * @eof_mask: Mask of PDF values that end a frame
 577  * @start_poll: If not %NULL the ring will call this function when an
 578  *              interrupt is triggered and masked, instead of callback
 579  *              in each Rx frame.
 580  * @poll_data: Optional data passed to @start_poll
 581  */
 582 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
 583                                  unsigned int flags, int e2e_tx_hop,
 584                                  u16 sof_mask, u16 eof_mask,
 585                                  void (*start_poll)(void *), void *poll_data)
 586 {
 587         return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask,
 588                              start_poll, poll_data);
 589 }
 590 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
 591
 592 /**
 593  * tb_ring_start() - enable a ring
 594  * @ring: Ring to start
 595  *
 596  * Must not be invoked in parallel with tb_ring_stop().
 597  */
 598 void tb_ring_start(struct tb_ring *ring)
 599 {
 600         u16 frame_size;
 601         u32 flags;
 602
 603         spin_lock_irq(&ring->nhi->lock);
 604         spin_lock(&ring->lock);
 605         if (ring->nhi->going_away)
 606                 goto err;
 607         if (ring->running) {
 608                 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
 609                 goto err;
 610         }
 611         dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n",
 612                 RING_TYPE(ring), ring->hop);
 613
 614         if (ring->flags & RING_FLAG_FRAME) {
 615                 /* Means 4096 */
 616                 frame_size = 0;
 617                 flags = RING_FLAG_ENABLE;
 618         } else {
 619                 frame_size = TB_FRAME_SIZE;
 620                 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
 621         }
 622
 623         ring_iowrite64desc(ring, ring->descriptors_dma, 0);
 624         if (ring->is_tx) {
 625                 ring_iowrite32desc(ring, ring->size, 12);
 626                 ring_iowrite32options(ring, 0, 4); /* time releated ? */
 627                 ring_iowrite32options(ring, flags, 0);
 628         } else {
 629                 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
 630
 631                 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
 632                 ring_iowrite32options(ring, sof_eof_mask, 4);
 633                 ring_iowrite32options(ring, flags, 0);
 634         }
 635
 636         /*
 637          * Now that the ring valid bit is set we can configure E2E if
 638          * enabled for the ring.
 639          */
 640         if (ring->flags & RING_FLAG_E2E) {
 641                 if (!ring->is_tx) {
 642                         u32 hop;
 643
 644                         hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT;
 645                         hop &= REG_RX_OPTIONS_E2E_HOP_MASK;
 646                         flags |= hop;
 647
 648                         dev_dbg(&ring->nhi->pdev->dev,
 649                                 "enabling E2E for %s %d with TX HopID %d\n",
 650                                 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop);
 651                 } else {
 652                         dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n",
 653                                 RING_TYPE(ring), ring->hop);
 654                 }
 655
 656                 flags |= RING_FLAG_E2E_FLOW_CONTROL;
 657                 ring_iowrite32options(ring, flags, 0);
 658         }
 659
 660         ring_interrupt_active(ring, true);
 661         ring->running = true;
 662 err:
 663         spin_unlock(&ring->lock);
 664         spin_unlock_irq(&ring->nhi->lock);
 665 }
 666 EXPORT_SYMBOL_GPL(tb_ring_start);
 667
 668 /**
 669  * tb_ring_stop() - shutdown a ring
 670  * @ring: Ring to stop
 671  *
 672  * Must not be invoked from a callback.
 673  *
 674  * This method will disable the ring. Further calls to
 675  * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
 676  * called.
 677  *
 678  * All enqueued frames will be canceled and their callbacks will be executed
 679  * with frame->canceled set to true (on the callback thread). This method
 680  * returns only after all callback invocations have finished.
 681  */
 682 void tb_ring_stop(struct tb_ring *ring)
 683 {
 684         spin_lock_irq(&ring->nhi->lock);
 685         spin_lock(&ring->lock);
 686         dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n",
 687                 RING_TYPE(ring), ring->hop);
 688         if (ring->nhi->going_away)
 689                 goto err;
 690         if (!ring->running) {
 691                 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
 692                          RING_TYPE(ring), ring->hop);
 693                 goto err;
 694         }
 695         ring_interrupt_active(ring, false);
 696
 697         ring_iowrite32options(ring, 0, 0);
 698         ring_iowrite64desc(ring, 0, 0);
 699         ring_iowrite32desc(ring, 0, 8);
 700         ring_iowrite32desc(ring, 0, 12);
 701         ring->head = 0;
 702         ring->tail = 0;
 703         ring->running = false;
 704
 705 err:
 706         spin_unlock(&ring->lock);
 707         spin_unlock_irq(&ring->nhi->lock);
 708
 709         /*
 710          * schedule ring->work to invoke callbacks on all remaining frames.
 711          */
 712         schedule_work(&ring->work);
 713         flush_work(&ring->work);
 714 }
 715 EXPORT_SYMBOL_GPL(tb_ring_stop);
 716
 717 /*
 718  * tb_ring_free() - free ring
 719  *
 720  * When this method returns all invocations of ring->callback will have
 721  * finished.
 722  *
 723  * Ring must be stopped.
 724  *
 725  * Must NOT be called from ring_frame->callback!
 726  */
 727 void tb_ring_free(struct tb_ring *ring)
 728 {
 729         spin_lock_irq(&ring->nhi->lock);
 730         /*
 731          * Dissociate the ring from the NHI. This also ensures that
 732          * nhi_interrupt_work cannot reschedule ring->work.
 733          */
 734         if (ring->is_tx)
 735                 ring->nhi->tx_rings[ring->hop] = NULL;
 736         else
 737                 ring->nhi->rx_rings[ring->hop] = NULL;
 738
 739         if (ring->running) {
 740                 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
 741                          RING_TYPE(ring), ring->hop);
 742         }
 743         spin_unlock_irq(&ring->nhi->lock);
 744
 745         ring_release_msix(ring);
 746
 747         dma_free_coherent(&ring->nhi->pdev->dev,
 748                           ring->size * sizeof(*ring->descriptors),
 749                           ring->descriptors, ring->descriptors_dma);
 750
 751         ring->descriptors = NULL;
 752         ring->descriptors_dma = 0;
 753
 754
 755         dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring),
 756                 ring->hop);
 757
 758         /*
 759          * ring->work can no longer be scheduled (it is scheduled only
 760          * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
 761          * to finish before freeing the ring.
 762          */
 763         flush_work(&ring->work);
 764         kfree(ring);
 765 }
 766 EXPORT_SYMBOL_GPL(tb_ring_free);
 767
 768 /**
 769  * nhi_mailbox_cmd() - Send a command through NHI mailbox
 770  * @nhi: Pointer to the NHI structure
 771  * @cmd: Command to send
 772  * @data: Data to be send with the command
 773  *
 774  * Sends mailbox command to the firmware running on NHI. Returns %0 in
 775  * case of success and negative errno in case of failure.
 776  */
 777 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
 778 {
 779         ktime_t timeout;
 780         u32 val;
 781
 782         iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
 783
 784         val = ioread32(nhi->iobase + REG_INMAIL_CMD);
 785         val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
 786         val |= REG_INMAIL_OP_REQUEST | cmd;
 787         iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
 788
 789         timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
 790         do {
 791                 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
 792                 if (!(val & REG_INMAIL_OP_REQUEST))
 793                         break;
 794                 usleep_range(10, 20);
 795         } while (ktime_before(ktime_get(), timeout));
 796
 797         if (val & REG_INMAIL_OP_REQUEST)
 798                 return -ETIMEDOUT;
 799         if (val & REG_INMAIL_ERROR)
 800                 return -EIO;
 801
 802         return 0;
 803 }
 804
 805 /**
 806  * nhi_mailbox_mode() - Return current firmware operation mode
 807  * @nhi: Pointer to the NHI structure
 808  *
 809  * The function reads current firmware operation mode using NHI mailbox
 810  * registers and returns it to the caller.
 811  */
 812 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
 813 {
 814         u32 val;
 815
 816         val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
 817         val &= REG_OUTMAIL_CMD_OPMODE_MASK;
 818         val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
 819
 820         return (enum nhi_fw_mode)val;
 821 }
 822
 823 static void nhi_interrupt_work(struct work_struct *work)
 824 {
 825         struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
 826         int value = 0; /* Suppress uninitialized usage warning. */
 827         int bit;
 828         int hop = -1;
 829         int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
 830         struct tb_ring *ring;
 831
 832         spin_lock_irq(&nhi->lock);
 833
 834         /*
 835          * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
 836          * (TX, RX, RX overflow). We iterate over the bits and read a new
 837          * dwords as required. The registers are cleared on read.
 838          */
 839         for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
 840                 if (bit % 32 == 0)
 841                         value = ioread32(nhi->iobase
 842                                          + REG_RING_NOTIFY_BASE
 843                                          + 4 * (bit / 32));
 844                 if (++hop == nhi->hop_count) {
 845                         hop = 0;
 846                         type++;
 847                 }
 848                 if ((value & (1 << (bit % 32))) == 0)
 849                         continue;
 850                 if (type == 2) {
 851                         dev_warn(&nhi->pdev->dev,
 852                                  "RX overflow for ring %d\n",
 853                                  hop);
 854                         continue;
 855                 }
 856                 if (type == 0)
 857                         ring = nhi->tx_rings[hop];
 858                 else
 859                         ring = nhi->rx_rings[hop];
 860                 if (ring == NULL) {
 861                         dev_warn(&nhi->pdev->dev,
 862                                  "got interrupt for inactive %s ring %d\n",
 863                                  type ? "RX" : "TX",
 864                                  hop);
 865                         continue;
 866                 }
 867
 868                 spin_lock(&ring->lock);
 869                 __ring_interrupt(ring);
 870                 spin_unlock(&ring->lock);
 871         }
 872         spin_unlock_irq(&nhi->lock);
 873 }
 874
 875 static irqreturn_t nhi_msi(int irq, void *data)
 876 {
 877         struct tb_nhi *nhi = data;
 878         schedule_work(&nhi->interrupt_work);
 879         return IRQ_HANDLED;
 880 }
 881
 882 static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
 883 {
 884         struct pci_dev *pdev = to_pci_dev(dev);
 885         struct tb *tb = pci_get_drvdata(pdev);
 886         struct tb_nhi *nhi = tb->nhi;
 887         int ret;
 888
 889         ret = tb_domain_suspend_noirq(tb);
 890         if (ret)
 891                 return ret;
 892
 893         if (nhi->ops && nhi->ops->suspend_noirq) {
 894                 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
 895                 if (ret)
 896                         return ret;
 897         }
 898
 899         return 0;
 900 }
 901
 902 static int nhi_suspend_noirq(struct device *dev)
 903 {
 904         return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
 905 }
 906
 907 static int nhi_freeze_noirq(struct device *dev)
 908 {
 909         struct pci_dev *pdev = to_pci_dev(dev);
 910         struct tb *tb = pci_get_drvdata(pdev);
 911
 912         return tb_domain_freeze_noirq(tb);
 913 }
 914
 915 static int nhi_thaw_noirq(struct device *dev)
 916 {
 917         struct pci_dev *pdev = to_pci_dev(dev);
 918         struct tb *tb = pci_get_drvdata(pdev);
 919
 920         return tb_domain_thaw_noirq(tb);
 921 }
 922
 923 static bool nhi_wake_supported(struct pci_dev *pdev)
 924 {
 925         u8 val;
 926
 927         /*
 928          * If power rails are sustainable for wakeup from S4 this
 929          * property is set by the BIOS.
 930          */
 931         if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
 932                 return !!val;
 933
 934         return true;
 935 }
 936
 937 static int nhi_poweroff_noirq(struct device *dev)
 938 {
 939         struct pci_dev *pdev = to_pci_dev(dev);
 940         bool wakeup;
 941
 942         wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
 943         return __nhi_suspend_noirq(dev, wakeup);
 944 }
 945
 946 static void nhi_enable_int_throttling(struct tb_nhi *nhi)
 947 {
 948         /* Throttling is specified in 256ns increments */
 949         u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
 950         unsigned int i;
 951
 952         /*
 953          * Configure interrupt throttling for all vectors even if we
 954          * only use few.
 955          */
 956         for (i = 0; i < MSIX_MAX_VECS; i++) {
 957                 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
 958                 iowrite32(throttle, nhi->iobase + reg);
 959         }
 960 }
 961
 962 static int nhi_resume_noirq(struct device *dev)
 963 {
 964         struct pci_dev *pdev = to_pci_dev(dev);
 965         struct tb *tb = pci_get_drvdata(pdev);
 966         struct tb_nhi *nhi = tb->nhi;
 967         int ret;
 968
 969         /*
 970          * Check that the device is still there. It may be that the user
 971          * unplugged last device which causes the host controller to go
 972          * away on PCs.
 973          */
 974         if (!pci_device_is_present(pdev)) {
 975                 nhi->going_away = true;
 976         } else {
 977                 if (nhi->ops && nhi->ops->resume_noirq) {
 978                         ret = nhi->ops->resume_noirq(nhi);
 979                         if (ret)
 980                                 return ret;
 981                 }
 982                 nhi_enable_int_throttling(tb->nhi);
 983         }
 984
 985         return tb_domain_resume_noirq(tb);
 986 }
 987
 988 static int nhi_suspend(struct device *dev)
 989 {
 990         struct pci_dev *pdev = to_pci_dev(dev);
 991         struct tb *tb = pci_get_drvdata(pdev);
 992
 993         return tb_domain_suspend(tb);
 994 }
 995
 996 static void nhi_complete(struct device *dev)
 997 {
 998         struct pci_dev *pdev = to_pci_dev(dev);
 999         struct tb *tb = pci_get_drvdata(pdev);
1000
1001         /*
1002          * If we were runtime suspended when system suspend started,
1003          * schedule runtime resume now. It should bring the domain back
1004          * to functional state.
1005          */
1006         if (pm_runtime_suspended(&pdev->dev))
1007                 pm_runtime_resume(&pdev->dev);
1008         else
1009                 tb_domain_complete(tb);
1010 }
1011
1012 static int nhi_runtime_suspend(struct device *dev)
1013 {
1014         struct pci_dev *pdev = to_pci_dev(dev);
1015         struct tb *tb = pci_get_drvdata(pdev);
1016         struct tb_nhi *nhi = tb->nhi;
1017         int ret;
1018
1019         ret = tb_domain_runtime_suspend(tb);
1020         if (ret)
1021                 return ret;
1022
1023         if (nhi->ops && nhi->ops->runtime_suspend) {
1024                 ret = nhi->ops->runtime_suspend(tb->nhi);
1025                 if (ret)
1026                         return ret;
1027         }
1028         return 0;
1029 }
1030
1031 static int nhi_runtime_resume(struct device *dev)
1032 {
1033         struct pci_dev *pdev = to_pci_dev(dev);
1034         struct tb *tb = pci_get_drvdata(pdev);
1035         struct tb_nhi *nhi = tb->nhi;
1036         int ret;
1037
1038         if (nhi->ops && nhi->ops->runtime_resume) {
1039                 ret = nhi->ops->runtime_resume(nhi);
1040                 if (ret)
1041                         return ret;
1042         }
1043
1044         nhi_enable_int_throttling(nhi);
1045         return tb_domain_runtime_resume(tb);
1046 }
1047
1048 static void nhi_shutdown(struct tb_nhi *nhi)
1049 {
1050         int i;
1051
1052         dev_dbg(&nhi->pdev->dev, "shutdown\n");
1053
1054         for (i = 0; i < nhi->hop_count; i++) {
1055                 if (nhi->tx_rings[i])
1056                         dev_WARN(&nhi->pdev->dev,
1057                                  "TX ring %d is still active\n", i);
1058                 if (nhi->rx_rings[i])
1059                         dev_WARN(&nhi->pdev->dev,
1060                                  "RX ring %d is still active\n", i);
1061         }
1062         nhi_disable_interrupts(nhi);
1063         /*
1064          * We have to release the irq before calling flush_work. Otherwise an
1065          * already executing IRQ handler could call schedule_work again.
1066          */
1067         if (!nhi->pdev->msix_enabled) {
1068                 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1069                 flush_work(&nhi->interrupt_work);
1070         }
1071         ida_destroy(&nhi->msix_ida);
1072
1073         if (nhi->ops && nhi->ops->shutdown)
1074                 nhi->ops->shutdown(nhi);
1075 }
1076
1077 static int nhi_init_msi(struct tb_nhi *nhi)
1078 {
1079         struct pci_dev *pdev = nhi->pdev;
1080         int res, irq, nvec;
1081
1082         /* In case someone left them on. */
1083         nhi_disable_interrupts(nhi);
1084
1085         nhi_enable_int_throttling(nhi);
1086
1087         ida_init(&nhi->msix_ida);
1088
1089         /*
1090          * The NHI has 16 MSI-X vectors or a single MSI. We first try to
1091          * get all MSI-X vectors and if we succeed, each ring will have
1092          * one MSI-X. If for some reason that does not work out, we
1093          * fallback to a single MSI.
1094          */
1095         nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
1096                                      PCI_IRQ_MSIX);
1097         if (nvec < 0) {
1098                 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1099                 if (nvec < 0)
1100                         return nvec;
1101
1102                 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
1103
1104                 irq = pci_irq_vector(nhi->pdev, 0);
1105                 if (irq < 0)
1106                         return irq;
1107
1108                 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1109                                        IRQF_NO_SUSPEND, "thunderbolt", nhi);
1110                 if (res) {
1111                         dev_err(&pdev->dev, "request_irq failed, aborting\n");
1112                         return res;
1113                 }
1114         }
1115
1116         return 0;
1117 }
1118
1119 static bool nhi_imr_valid(struct pci_dev *pdev)
1120 {
1121         u8 val;
1122
1123         if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1124                 return !!val;
1125
1126         return true;
1127 }
1128
1129 static struct tb *nhi_select_cm(struct tb_nhi *nhi)
1130 {
1131         struct tb *tb;
1132
1133         /*
1134          * USB4 case is simple. If we got control of any of the
1135          * capabilities, we use software CM.
1136          */
1137         if (tb_acpi_is_native())
1138                 return tb_probe(nhi);
1139
1140         /*
1141          * Either firmware based CM is running (we did not get control
1142          * from the firmware) or this is pre-USB4 PC so try first
1143          * firmware CM and then fallback to software CM.
1144          */
1145         tb = icm_probe(nhi);
1146         if (!tb)
1147                 tb = tb_probe(nhi);
1148
1149         return tb;
1150 }
1151
1152 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1153 {
1154         struct tb_nhi *nhi;
1155         struct tb *tb;
1156         int res;
1157
1158         if (!nhi_imr_valid(pdev)) {
1159                 dev_warn(&pdev->dev, "firmware image not valid, aborting\n");
1160                 return -ENODEV;
1161         }
1162
1163         res = pcim_enable_device(pdev);
1164         if (res) {
1165                 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
1166                 return res;
1167         }
1168
1169         res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1170         if (res) {
1171                 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
1172                 return res;
1173         }
1174
1175         nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1176         if (!nhi)
1177                 return -ENOMEM;
1178
1179         nhi->pdev = pdev;
1180         nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1181         /* cannot fail - table is allocated bin pcim_iomap_regions */
1182         nhi->iobase = pcim_iomap_table(pdev)[0];
1183         nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1184         dev_dbg(&pdev->dev, "total paths: %d\n", nhi->hop_count);
1185
1186         nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1187                                      sizeof(*nhi->tx_rings), GFP_KERNEL);
1188         nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1189                                      sizeof(*nhi->rx_rings), GFP_KERNEL);
1190         if (!nhi->tx_rings || !nhi->rx_rings)
1191                 return -ENOMEM;
1192
1193         res = nhi_init_msi(nhi);
1194         if (res) {
1195                 dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
1196                 return res;
1197         }
1198
1199         spin_lock_init(&nhi->lock);
1200
1201         res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1202         if (res)
1203                 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1204         if (res) {
1205                 dev_err(&pdev->dev, "failed to set DMA mask\n");
1206                 return res;
1207         }
1208
1209         pci_set_master(pdev);
1210
1211         if (nhi->ops && nhi->ops->init) {
1212                 res = nhi->ops->init(nhi);
1213                 if (res)
1214                         return res;
1215         }
1216
1217         tb = nhi_select_cm(nhi);
1218         if (!tb) {
1219                 dev_err(&nhi->pdev->dev,
1220                         "failed to determine connection manager, aborting\n");
1221                 return -ENODEV;
1222         }
1223
1224         dev_dbg(&nhi->pdev->dev, "NHI initialized, starting thunderbolt\n");
1225
1226         res = tb_domain_add(tb);
1227         if (res) {
1228                 /*
1229                  * At this point the RX/TX rings might already have been
1230                  * activated. Do a proper shutdown.
1231                  */
1232                 tb_domain_put(tb);
1233                 nhi_shutdown(nhi);
1234                 return res;
1235         }
1236         pci_set_drvdata(pdev, tb);
1237
1238         device_wakeup_enable(&pdev->dev);
1239
1240         pm_runtime_allow(&pdev->dev);
1241         pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1242         pm_runtime_use_autosuspend(&pdev->dev);
1243         pm_runtime_put_autosuspend(&pdev->dev);
1244
1245         return 0;
1246 }
1247
1248 static void nhi_remove(struct pci_dev *pdev)
1249 {
1250         struct tb *tb = pci_get_drvdata(pdev);
1251         struct tb_nhi *nhi = tb->nhi;
1252
1253         pm_runtime_get_sync(&pdev->dev);
1254         pm_runtime_dont_use_autosuspend(&pdev->dev);
1255         pm_runtime_forbid(&pdev->dev);
1256
1257         tb_domain_remove(tb);
1258         nhi_shutdown(nhi);
1259 }
1260
1261 /*
1262  * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1263  * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1264  * resume_noirq until we are done.
1265  */
1266 static const struct dev_pm_ops nhi_pm_ops = {
1267         .suspend_noirq = nhi_suspend_noirq,
1268         .resume_noirq = nhi_resume_noirq,
1269         .freeze_noirq = nhi_freeze_noirq,  /*
1270                                             * we just disable hotplug, the
1271                                             * pci-tunnels stay alive.
1272                                             */
1273         .thaw_noirq = nhi_thaw_noirq,
1274         .restore_noirq = nhi_resume_noirq,
1275         .suspend = nhi_suspend,
1276         .poweroff_noirq = nhi_poweroff_noirq,
1277         .poweroff = nhi_suspend,
1278         .complete = nhi_complete,
1279         .runtime_suspend = nhi_runtime_suspend,
1280         .runtime_resume = nhi_runtime_resume,
1281 };
1282
1283 static struct pci_device_id nhi_ids[] = {
1284         /*
1285          * We have to specify class, the TB bridges use the same device and
1286          * vendor (sub)id on gen 1 and gen 2 controllers.
1287          */
1288         {
1289                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1290                 .vendor = PCI_VENDOR_ID_INTEL,
1291                 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1292                 .subvendor = 0x2222, .subdevice = 0x1111,
1293         },
1294         {
1295                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1296                 .vendor = PCI_VENDOR_ID_INTEL,
1297                 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1298                 .subvendor = 0x2222, .subdevice = 0x1111,
1299         },
1300         {
1301                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1302                 .vendor = PCI_VENDOR_ID_INTEL,
1303                 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1304                 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1305         },
1306         {
1307                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1308                 .vendor = PCI_VENDOR_ID_INTEL,
1309                 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1310                 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1311         },
1312
1313         /* Thunderbolt 3 */
1314         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1315         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1316         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1317         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1318         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1319         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1320         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1321         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1322         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1323         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1324         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1325           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1326         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1327           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1328         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0),
1329           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1330         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1),
1331           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1332         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0),
1333           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1334         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1),
1335           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1336         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0),
1337           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1338         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1),
1339           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1340
1341         /* Any USB4 compliant host */
1342         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) },
1343
1344         { 0,}
1345 };
1346
1347 MODULE_DEVICE_TABLE(pci, nhi_ids);
1348 MODULE_LICENSE("GPL");
1349
1350 static struct pci_driver nhi_driver = {
1351         .name = "thunderbolt",
1352         .id_table = nhi_ids,
1353         .probe = nhi_probe,
1354         .remove = nhi_remove,
1355         .shutdown = nhi_remove,
1356         .driver.pm = &nhi_pm_ops,
1357 };
1358
1359 static int __init nhi_init(void)
1360 {
1361         int ret;
1362
1363         ret = tb_domain_init();
1364         if (ret)
1365                 return ret;
1366         ret = pci_register_driver(&nhi_driver);
1367         if (ret)
1368                 tb_domain_exit();
1369         return ret;
1370 }
1371
1372 static void __exit nhi_unload(void)
1373 {
1374         pci_unregister_driver(&nhi_driver);
1375         tb_domain_exit();
1376 }
1377
1378 rootfs_initcall(nhi_init);
1379 module_exit(nhi_unload);