drivers/staging/r8188eu/hal/odm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
   3
   4 /*  include files */
   5
   6 #include "../include/odm_precomp.h"
   7
   8 static const u16 dB_Invert_Table[8][12] = {
   9         {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
  10         {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
  11         {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
  12         {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
  13         {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
  14         {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
  15         {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
  16         {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
  17 };
  18
  19 /* avoid to warn in FreeBSD ==> To DO modify */
  20 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {
  21         /*  UL                  DL */
  22         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
  23         {0xa44f, 0x5ea44f, 0x5e431c}, /*  1:realtek AP */
  24         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  2:unknown AP => realtek_92SE */
  25         {0x5ea32b, 0x5ea42b, 0x5e4322}, /*  3:broadcom AP */
  26         {0x5ea422, 0x00a44f, 0x00a44f}, /*  4:ralink AP */
  27         {0x5ea322, 0x00a630, 0x00a44f}, /*  5:atheros AP */
  28         {0x5e4322, 0x5e4322, 0x5e4322},/*  6:cisco AP */
  29         {0x5ea44f, 0x00a44f, 0x5ea42b}, /*  8:marvell AP */
  30         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  10:unknown AP=> 92U AP */
  31         {0x5ea42b, 0xa630, 0x5e431c}, /*  11:airgocap AP */
  32 };
  33
  34 /*  Global var */
  35 u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
  36         0x7f8001fe, /*  0, +6.0dB */
  37         0x788001e2, /*  1, +5.5dB */
  38         0x71c001c7, /*  2, +5.0dB */
  39         0x6b8001ae, /*  3, +4.5dB */
  40         0x65400195, /*  4, +4.0dB */
  41         0x5fc0017f, /*  5, +3.5dB */
  42         0x5a400169, /*  6, +3.0dB */
  43         0x55400155, /*  7, +2.5dB */
  44         0x50800142, /*  8, +2.0dB */
  45         0x4c000130, /*  9, +1.5dB */
  46         0x47c0011f, /*  10, +1.0dB */
  47         0x43c0010f, /*  11, +0.5dB */
  48         0x40000100, /*  12, +0dB */
  49         0x3c8000f2, /*  13, -0.5dB */
  50         0x390000e4, /*  14, -1.0dB */
  51         0x35c000d7, /*  15, -1.5dB */
  52         0x32c000cb, /*  16, -2.0dB */
  53         0x300000c0, /*  17, -2.5dB */
  54         0x2d4000b5, /*  18, -3.0dB */
  55         0x2ac000ab, /*  19, -3.5dB */
  56         0x288000a2, /*  20, -4.0dB */
  57         0x26000098, /*  21, -4.5dB */
  58         0x24000090, /*  22, -5.0dB */
  59         0x22000088, /*  23, -5.5dB */
  60         0x20000080, /*  24, -6.0dB */
  61         0x1e400079, /*  25, -6.5dB */
  62         0x1c800072, /*  26, -7.0dB */
  63         0x1b00006c, /*  27. -7.5dB */
  64         0x19800066, /*  28, -8.0dB */
  65         0x18000060, /*  29, -8.5dB */
  66         0x16c0005b, /*  30, -9.0dB */
  67         0x15800056, /*  31, -9.5dB */
  68         0x14400051, /*  32, -10.0dB */
  69         0x1300004c, /*  33, -10.5dB */
  70         0x12000048, /*  34, -11.0dB */
  71         0x11000044, /*  35, -11.5dB */
  72         0x10000040, /*  36, -12.0dB */
  73         0x0f00003c,/*  37, -12.5dB */
  74         0x0e400039,/*  38, -13.0dB */
  75         0x0d800036,/*  39, -13.5dB */
  76         0x0cc00033,/*  40, -14.0dB */
  77         0x0c000030,/*  41, -14.5dB */
  78         0x0b40002d,/*  42, -15.0dB */
  79 };
  80
  81 u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
  82         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /*  0, +0dB */
  83         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  1, -0.5dB */
  84         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  2, -1.0dB */
  85         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  3, -1.5dB */
  86         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  4, -2.0dB */
  87         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  5, -2.5dB */
  88         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  6, -3.0dB */
  89         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  7, -3.5dB */
  90         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  8, -4.0dB */
  91         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  9, -4.5dB */
  92         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  10, -5.0dB */
  93         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  11, -5.5dB */
  94         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  12, -6.0dB */
  95         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  13, -6.5dB */
  96         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  14, -7.0dB */
  97         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  15, -7.5dB */
  98         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */
  99         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  17, -8.5dB */
 100         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  18, -9.0dB */
 101         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  19, -9.5dB */
 102         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  20, -10.0dB */
 103         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  21, -10.5dB */
 104         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  22, -11.0dB */
 105         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*  23, -11.5dB */
 106         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*  24, -12.0dB */
 107         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*  25, -12.5dB */
 108         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*  26, -13.0dB */
 109         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  27, -13.5dB */
 110         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  28, -14.0dB */
 111         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  29, -14.5dB */
 112         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  30, -15.0dB */
 113         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*  31, -15.5dB */
 114         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        /*  32, -16.0dB */
 115 };
 116
 117 u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
 118         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /*  0, +0dB */
 119         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /*  1, -0.5dB */
 120         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /*  2, -1.0dB */
 121         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*  3, -1.5dB */
 122         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /*  4, -2.0dB */
 123         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*  5, -2.5dB */
 124         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /*  6, -3.0dB */
 125         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /*  7, -3.5dB */
 126         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /*  8, -4.0dB */
 127         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*  9, -4.5dB */
 128         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /*  10, -5.0dB */
 129         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  11, -5.5dB */
 130         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  12, -6.0dB */
 131         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /*  13, -6.5dB */
 132         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /*  14, -7.0dB */
 133         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  15, -7.5dB */
 134         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  16, -8.0dB */
 135         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  17, -8.5dB */
 136         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  18, -9.0dB */
 137         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  19, -9.5dB */
 138         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  20, -10.0dB */
 139         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  21, -10.5dB */
 140         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  22, -11.0dB */
 141         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  23, -11.5dB */
 142         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  24, -12.0dB */
 143         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  25, -12.5dB */
 144         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  26, -13.0dB */
 145         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  27, -13.5dB */
 146         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  28, -14.0dB */
 147         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  29, -14.5dB */
 148         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  30, -15.0dB */
 149         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  31, -15.5dB */
 150         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}  /*  32, -16.0dB */
 151 };
 152
 153 #define         RxDefaultAnt1           0x65a9
 154 #define RxDefaultAnt2           0x569a
 155
 156 /* 3 Export Interface */
 157
 158 /*  2011/09/21 MH Add to describe different team necessary resource allocate?? */
 159 void ODM_DMInit(struct odm_dm_struct *pDM_Odm)
 160 {
 161         /* 2012.05.03 Luke: For all IC series */
 162         odm_CommonInfoSelfInit(pDM_Odm);
 163         odm_DIGInit(pDM_Odm);
 164         odm_RateAdaptiveMaskInit(pDM_Odm);
 165
 166         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
 167                 ;
 168         } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
 169                 odm_PrimaryCCA_Init(pDM_Odm);    /*  Gary */
 170                 odm_DynamicBBPowerSavingInit(pDM_Odm);
 171                 odm_DynamicTxPowerInit(pDM_Odm);
 172                 odm_TXPowerTrackingInit(pDM_Odm);
 173                 ODM_EdcaTurboInit(pDM_Odm);
 174                 ODM_RAInfo_Init_all(pDM_Odm);
 175                 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)   ||
 176                     (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
 177                     (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
 178                         odm_InitHybridAntDiv(pDM_Odm);
 179                 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
 180                         odm_SwAntDivInit(pDM_Odm);
 181         }
 182 }
 183
 184 /*  2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
 185 /*  You can not add any dummy function here, be care, you can only use DM structure */
 186 /*  to perform any new ODM_DM. */
 187 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm)
 188 {
 189         /* 2012.05.03 Luke: For all IC series */
 190         odm_GlobalAdapterCheck();
 191         odm_CommonInfoSelfUpdate(pDM_Odm);
 192         odm_FalseAlarmCounterStatistics(pDM_Odm);
 193         odm_RSSIMonitorCheck(pDM_Odm);
 194
 195         /* For CE Platform(SPRD or Tablet) */
 196         /* 8723A or 8189ES platform */
 197         /* NeilChen--2012--08--24-- */
 198         /* Fix Leave LPS issue */
 199         if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/*  in LPS mode */
 200             ((pDM_Odm->SupportICType & (ODM_RTL8723A)) ||
 201             (pDM_Odm->SupportICType & (ODM_RTL8188E) &&
 202             ((pDM_Odm->SupportInterface  == ODM_ITRF_SDIO)))))
 203                 odm_DIGbyRSSI_LPS(pDM_Odm);
 204         else
 205                 odm_DIG(pDM_Odm);
 206         odm_CCKPacketDetectionThresh(pDM_Odm);
 207
 208         if (*(pDM_Odm->pbPowerSaving))
 209                 return;
 210
 211         odm_RefreshRateAdaptiveMask(pDM_Odm);
 212
 213         odm_DynamicBBPowerSaving(pDM_Odm);
 214         odm_DynamicPrimaryCCA(pDM_Odm);
 215         if ((pDM_Odm->AntDivType ==  CG_TRX_HW_ANTDIV)  ||
 216             (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)  ||
 217             (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
 218                 odm_HwAntDiv(pDM_Odm);
 219         else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
 220                 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
 221
 222         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
 223                 ;
 224         } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
 225                 ODM_TXPowerTrackingCheck(pDM_Odm);
 226               odm_EdcaTurboCheck(pDM_Odm);
 227                 odm_DynamicTxPower(pDM_Odm);
 228         }
 229         odm_dtc(pDM_Odm);
 230 }
 231
 232 /*  Init /.. Fixed HW value. Only init time. */
 233 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value)
 234 {
 235         /*  This section is used for init value */
 236         switch  (CmnInfo) {
 237         /*  Fixed ODM value. */
 238         case    ODM_CMNINFO_ABILITY:
 239                 pDM_Odm->SupportAbility = (u32)Value;
 240                 break;
 241         case    ODM_CMNINFO_PLATFORM:
 242                 pDM_Odm->SupportPlatform = (u8)Value;
 243                 break;
 244         case    ODM_CMNINFO_INTERFACE:
 245                 pDM_Odm->SupportInterface = (u8)Value;
 246                 break;
 247         case    ODM_CMNINFO_MP_TEST_CHIP:
 248                 pDM_Odm->bIsMPChip = (u8)Value;
 249                 break;
 250         case    ODM_CMNINFO_IC_TYPE:
 251                 pDM_Odm->SupportICType = Value;
 252                 break;
 253         case    ODM_CMNINFO_CUT_VER:
 254                 pDM_Odm->CutVersion = (u8)Value;
 255                 break;
 256         case    ODM_CMNINFO_FAB_VER:
 257                 pDM_Odm->FabVersion = (u8)Value;
 258                 break;
 259         case    ODM_CMNINFO_RF_TYPE:
 260                 pDM_Odm->RFType = (u8)Value;
 261                 break;
 262         case    ODM_CMNINFO_RF_ANTENNA_TYPE:
 263                 pDM_Odm->AntDivType = (u8)Value;
 264                 break;
 265         case    ODM_CMNINFO_BOARD_TYPE:
 266                 pDM_Odm->BoardType = (u8)Value;
 267                 break;
 268         case    ODM_CMNINFO_EXT_LNA:
 269                 pDM_Odm->ExtLNA = (u8)Value;
 270                 break;
 271         case    ODM_CMNINFO_EXT_PA:
 272                 pDM_Odm->ExtPA = (u8)Value;
 273                 break;
 274         case    ODM_CMNINFO_EXT_TRSW:
 275                 pDM_Odm->ExtTRSW = (u8)Value;
 276                 break;
 277         case    ODM_CMNINFO_PATCH_ID:
 278                 pDM_Odm->PatchID = (u8)Value;
 279                 break;
 280         case    ODM_CMNINFO_BINHCT_TEST:
 281                 pDM_Odm->bInHctTest = (bool)Value;
 282                 break;
 283         case    ODM_CMNINFO_BWIFI_TEST:
 284                 pDM_Odm->bWIFITest = (bool)Value;
 285                 break;
 286         case    ODM_CMNINFO_SMART_CONCURRENT:
 287                 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
 288                 break;
 289         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 290         default:
 291                 /* do nothing */
 292                 break;
 293         }
 294
 295         /*  Tx power tracking BB swing table. */
 296         /*  The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
 297         pDM_Odm->BbSwingIdxOfdm                 = 12; /*  Set defalut value as index 12. */
 298         pDM_Odm->BbSwingIdxOfdmCurrent  = 12;
 299         pDM_Odm->BbSwingFlagOfdm                = false;
 300 }
 301
 302 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue)
 303 {
 304         /*  */
 305         /*  Hook call by reference pointer. */
 306         /*  */
 307         switch  (CmnInfo) {
 308         /*  Dynamic call by reference pointer. */
 309         case    ODM_CMNINFO_MAC_PHY_MODE:
 310                 pDM_Odm->pMacPhyMode = (u8 *)pValue;
 311                 break;
 312         case    ODM_CMNINFO_TX_UNI:
 313                 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue;
 314                 break;
 315         case    ODM_CMNINFO_RX_UNI:
 316                 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue;
 317                 break;
 318         case    ODM_CMNINFO_WM_MODE:
 319                 pDM_Odm->pWirelessMode = (u8 *)pValue;
 320                 break;
 321         case    ODM_CMNINFO_BAND:
 322                 pDM_Odm->pBandType = (u8 *)pValue;
 323                 break;
 324         case    ODM_CMNINFO_SEC_CHNL_OFFSET:
 325                 pDM_Odm->pSecChOffset = (u8 *)pValue;
 326                 break;
 327         case    ODM_CMNINFO_SEC_MODE:
 328                 pDM_Odm->pSecurity = (u8 *)pValue;
 329                 break;
 330         case    ODM_CMNINFO_BW:
 331                 pDM_Odm->pBandWidth = (u8 *)pValue;
 332                 break;
 333         case    ODM_CMNINFO_CHNL:
 334                 pDM_Odm->pChannel = (u8 *)pValue;
 335                 break;
 336         case    ODM_CMNINFO_DMSP_GET_VALUE:
 337                 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue;
 338                 break;
 339         case    ODM_CMNINFO_BUDDY_ADAPTOR:
 340                 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue;
 341                 break;
 342         case    ODM_CMNINFO_DMSP_IS_MASTER:
 343                 pDM_Odm->pbMasterOfDMSP = (bool *)pValue;
 344                 break;
 345         case    ODM_CMNINFO_SCAN:
 346                 pDM_Odm->pbScanInProcess = (bool *)pValue;
 347                 break;
 348         case    ODM_CMNINFO_POWER_SAVING:
 349                 pDM_Odm->pbPowerSaving = (bool *)pValue;
 350                 break;
 351         case    ODM_CMNINFO_ONE_PATH_CCA:
 352                 pDM_Odm->pOnePathCCA = (u8 *)pValue;
 353                 break;
 354         case    ODM_CMNINFO_DRV_STOP:
 355                 pDM_Odm->pbDriverStopped =  (bool *)pValue;
 356                 break;
 357         case    ODM_CMNINFO_PNP_IN:
 358                 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep =  (bool *)pValue;
 359                 break;
 360         case    ODM_CMNINFO_INIT_ON:
 361                 pDM_Odm->pinit_adpt_in_progress =  (bool *)pValue;
 362                 break;
 363         case    ODM_CMNINFO_ANT_TEST:
 364                 pDM_Odm->pAntennaTest =  (u8 *)pValue;
 365                 break;
 366         case    ODM_CMNINFO_NET_CLOSED:
 367                 pDM_Odm->pbNet_closed = (bool *)pValue;
 368                 break;
 369         case    ODM_CMNINFO_MP_MODE:
 370                 pDM_Odm->mp_mode = (u8 *)pValue;
 371                 break;
 372         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 373         default:
 374                 /* do nothing */
 375                 break;
 376         }
 377 }
 378
 379 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue)
 380 {
 381         /*  Hook call by reference pointer. */
 382         switch  (CmnInfo) {
 383         /*  Dynamic call by reference pointer. */
 384         case    ODM_CMNINFO_STA_STATUS:
 385                 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
 386                 break;
 387         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 388         default:
 389                 /* do nothing */
 390                 break;
 391         }
 392 }
 393
 394 /*  Update Band/CHannel/.. The values are dynamic but non-per-packet. */
 395 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value)
 396 {
 397         /*  */
 398         /*  This init variable may be changed in run time. */
 399         /*  */
 400         switch  (CmnInfo) {
 401         case    ODM_CMNINFO_ABILITY:
 402                 pDM_Odm->SupportAbility = (u32)Value;
 403                 break;
 404         case    ODM_CMNINFO_RF_TYPE:
 405                 pDM_Odm->RFType = (u8)Value;
 406                 break;
 407         case    ODM_CMNINFO_WIFI_DIRECT:
 408                 pDM_Odm->bWIFI_Direct = (bool)Value;
 409                 break;
 410         case    ODM_CMNINFO_WIFI_DISPLAY:
 411                 pDM_Odm->bWIFI_Display = (bool)Value;
 412                 break;
 413         case    ODM_CMNINFO_LINK:
 414                 pDM_Odm->bLinked = (bool)Value;
 415                 break;
 416         case    ODM_CMNINFO_RSSI_MIN:
 417                 pDM_Odm->RSSI_Min = (u8)Value;
 418                 break;
 419         case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
 420                 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
 421                 break;
 422         case    ODM_CMNINFO_RA_THRESHOLD_LOW:
 423                 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
 424                 break;
 425         }
 426 }
 427
 428 void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm)
 429 {
 430         pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT9);
 431         pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
 432         if (pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
 433                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
 434         if (pDM_Odm->SupportICType & (ODM_RTL8723A))
 435                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
 436 }
 437
 438 void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm)
 439 {
 440         u8 EntryCnt = 0;
 441         u8 i;
 442         struct sta_info *pEntry;
 443
 444         if (*(pDM_Odm->pBandWidth) == ODM_BW40M) {
 445                 if (*(pDM_Odm->pSecChOffset) == 1)
 446                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2;
 447                 else if (*(pDM_Odm->pSecChOffset) == 2)
 448                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2;
 449         } else {
 450                 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
 451         }
 452
 453         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 454                 pEntry = pDM_Odm->pODM_StaInfo[i];
 455                 if (IS_STA_VALID(pEntry))
 456                         EntryCnt++;
 457         }
 458         if (EntryCnt == 1)
 459                 pDM_Odm->bOneEntryOnly = true;
 460         else
 461                 pDM_Odm->bOneEntryOnly = false;
 462 }
 463
 464 static int getIGIForDiff(int value_IGI)
 465 {
 466         #define ONERCCA_LOW_TH          0x30
 467         #define ONERCCA_LOW_DIFF        8
 468
 469         if (value_IGI < ONERCCA_LOW_TH) {
 470                 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF)
 471                         return ONERCCA_LOW_TH;
 472                 else
 473                         return value_IGI + ONERCCA_LOW_DIFF;
 474         } else {
 475                 return value_IGI;
 476         }
 477 }
 478
 479 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI)
 480 {
 481         struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
 482
 483         if (pDM_DigTable->CurIGValue != CurrentIGI) {
 484                 if (pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP)) {
 485                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 486                                 if (pDM_Odm->SupportICType != ODM_RTL8188E)
 487                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 488                 } else if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) {
 489                         switch (*(pDM_Odm->pOnePathCCA)) {
 490                         case ODM_CCA_2R:
 491                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 492                                         if (pDM_Odm->SupportICType != ODM_RTL8188E)
 493                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 494                                 break;
 495                         case ODM_CCA_1R_A:
 496                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 497                                         if (pDM_Odm->SupportICType != ODM_RTL8188E)
 498                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI));
 499                                 break;
 500                         case ODM_CCA_1R_B:
 501                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI));
 502                                         if (pDM_Odm->SupportICType != ODM_RTL8188E)
 503                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 504                                         break;
 505                                 }
 506                 }
 507                 /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */
 508                 pDM_DigTable->CurIGValue = CurrentIGI;
 509         }
 510 /*  Add by Neil Chen to enable edcca to MP Platform */
 511 }
 512
 513 /* Need LPS mode for CE platform --2012--08--24--- */
 514 /* 8723AS/8189ES */
 515 void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm)
 516 {
 517         struct adapter *pAdapter = pDM_Odm->Adapter;
 518         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 519
 520         u8 RSSI_Lower = DM_DIG_MIN_NIC;   /* 0x1E or 0x1C */
 521         u8 bFwCurrentInPSMode = false;
 522         u8 CurrentIGI = pDM_Odm->RSSI_Min;
 523
 524         if (!(pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8188E)))
 525                 return;
 526
 527         CurrentIGI = CurrentIGI + RSSI_OFFSET_DIG;
 528         bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
 529
 530         /*  Using FW PS mode to make IGI */
 531         if (bFwCurrentInPSMode) {
 532                 /* Adjust by  FA in LPS MODE */
 533                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
 534                         CurrentIGI = CurrentIGI+2;
 535                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
 536                         CurrentIGI = CurrentIGI+1;
 537                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
 538                         CurrentIGI = CurrentIGI-1;
 539         } else {
 540                 CurrentIGI = RSSI_Lower;
 541         }
 542
 543         /* Lower bound checking */
 544
 545         /* RSSI Lower bound check */
 546         if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
 547                 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
 548         else
 549                 RSSI_Lower = DM_DIG_MIN_NIC;
 550
 551         /* Upper and Lower Bound checking */
 552          if (CurrentIGI > DM_DIG_MAX_NIC)
 553                 CurrentIGI = DM_DIG_MAX_NIC;
 554          else if (CurrentIGI < RSSI_Lower)
 555                 CurrentIGI = RSSI_Lower;
 556
 557         ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
 558 }
 559
 560 void odm_DIGInit(struct odm_dm_struct *pDM_Odm)
 561 {
 562         struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
 563
 564         pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
 565         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
 566         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
 567         pDM_DigTable->FALowThresh       = DM_false_ALARM_THRESH_LOW;
 568         pDM_DigTable->FAHighThresh      = DM_false_ALARM_THRESH_HIGH;
 569         if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
 570                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 571                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 572         } else {
 573                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 574                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 575         }
 576         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
 577         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
 578         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
 579         pDM_DigTable->PreCCK_CCAThres = 0xFF;
 580         pDM_DigTable->CurCCK_CCAThres = 0x83;
 581         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
 582         pDM_DigTable->LargeFAHit = 0;
 583         pDM_DigTable->Recover_cnt = 0;
 584         pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
 585         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
 586         pDM_DigTable->bMediaConnect_0 = false;
 587         pDM_DigTable->bMediaConnect_1 = false;
 588
 589         /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */
 590         pDM_Odm->bDMInitialGainEnable = true;
 591 }
 592
 593 void odm_DIG(struct odm_dm_struct *pDM_Odm)
 594 {
 595         struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
 596         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 597         u8 DIG_Dynamic_MIN;
 598         u8 DIG_MaxOfMin;
 599         bool FirstConnect, FirstDisConnect;
 600         u8 dm_dig_max, dm_dig_min;
 601         u8 CurrentIGI = pDM_DigTable->CurIGValue;
 602
 603         if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT)))
 604                 return;
 605
 606         if (*(pDM_Odm->pbScanInProcess))
 607                 return;
 608
 609         /* add by Neil Chen to avoid PSD is processing */
 610         if (pDM_Odm->bDMInitialGainEnable == false)
 611                 return;
 612
 613         if (pDM_Odm->SupportICType == ODM_RTL8192D) {
 614                 if (*(pDM_Odm->pMacPhyMode) == ODM_DMSP) {
 615                         if (*(pDM_Odm->pbMasterOfDMSP)) {
 616                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 617                                 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 618                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 619                         } else {
 620                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
 621                                 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1);
 622                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1);
 623                         }
 624                 } else {
 625                         if (*(pDM_Odm->pBandType) == ODM_BAND_5G) {
 626                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 627                                 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 628                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 629                         } else {
 630                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
 631                                 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1);
 632                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1);
 633                         }
 634                 }
 635         } else {
 636                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 637                 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 638                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 639         }
 640
 641         /* 1 Boundary Decision */
 642         if ((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) &&
 643             ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
 644                 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) {
 645                         dm_dig_max = DM_DIG_MAX_AP_HP;
 646                         dm_dig_min = DM_DIG_MIN_AP_HP;
 647                 } else {
 648                         dm_dig_max = DM_DIG_MAX_NIC_HP;
 649                         dm_dig_min = DM_DIG_MIN_NIC_HP;
 650                 }
 651                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
 652         } else {
 653                 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) {
 654                         dm_dig_max = DM_DIG_MAX_AP;
 655                         dm_dig_min = DM_DIG_MIN_AP;
 656                         DIG_MaxOfMin = dm_dig_max;
 657                 } else {
 658                         dm_dig_max = DM_DIG_MAX_NIC;
 659                         dm_dig_min = DM_DIG_MIN_NIC;
 660                         DIG_MaxOfMin = DM_DIG_MAX_AP;
 661                 }
 662         }
 663         if (pDM_Odm->bLinked) {
 664               /* 2 8723A Series, offset need to be 10 */
 665                 if (pDM_Odm->SupportICType == (ODM_RTL8723A)) {
 666                         /* 2 Upper Bound */
 667                         if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
 668                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 669                         else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
 670                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
 671                         else
 672                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
 673                         /* 2 If BT is Concurrent, need to set Lower Bound */
 674                         DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
 675                 } else {
 676                         /* 2 Modify DIG upper bound */
 677                         if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
 678                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 679                         else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
 680                                 pDM_DigTable->rx_gain_range_max = dm_dig_min;
 681                         else
 682                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
 683                         /* 2 Modify DIG lower bound */
 684                         if (pDM_Odm->bOneEntryOnly) {
 685                                 if (pDM_Odm->RSSI_Min < dm_dig_min)
 686                                         DIG_Dynamic_MIN = dm_dig_min;
 687                                 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
 688                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
 689                                 else
 690                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
 691                         } else if ((pDM_Odm->SupportICType == ODM_RTL8188E) &&
 692                                    (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
 693                                 /* 1 Lower Bound for 88E AntDiv */
 694                                 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
 695                                         DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max;
 696                         } else {
 697                                 DIG_Dynamic_MIN = dm_dig_min;
 698                         }
 699                 }
 700         } else {
 701                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 702                 DIG_Dynamic_MIN = dm_dig_min;
 703         }
 704
 705         /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
 706         if (pFalseAlmCnt->Cnt_all > 10000) {
 707                 if (pDM_DigTable->LargeFAHit != 3)
 708                         pDM_DigTable->LargeFAHit++;
 709                 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
 710                         pDM_DigTable->ForbiddenIGI = CurrentIGI;
 711                         pDM_DigTable->LargeFAHit = 1;
 712                 }
 713
 714                 if (pDM_DigTable->LargeFAHit >= 3) {
 715                         if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
 716                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
 717                         else
 718                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 719                         pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */
 720                 }
 721
 722         } else {
 723                 /* Recovery mechanism for IGI lower bound */
 724                 if (pDM_DigTable->Recover_cnt != 0) {
 725                         pDM_DigTable->Recover_cnt--;
 726                 } else {
 727                         if (pDM_DigTable->LargeFAHit < 3) {
 728                                 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */
 729                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 730                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 731                                 } else {
 732                                         pDM_DigTable->ForbiddenIGI--;
 733                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 734                                 }
 735                         } else {
 736                                 pDM_DigTable->LargeFAHit = 0;
 737                         }
 738                 }
 739         }
 740
 741         /* 1 Adjust initial gain by false alarm */
 742         if (pDM_Odm->bLinked) {
 743                 if (FirstConnect) {
 744                         CurrentIGI = pDM_Odm->RSSI_Min;
 745                 } else {
 746                         if (pDM_Odm->SupportICType == ODM_RTL8192D) {
 747                                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D)
 748                                         CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 749                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D)
 750                                         CurrentIGI = CurrentIGI + 1; /* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 751                                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D)
 752                                         CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
 753                         } else {
 754                                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
 755                                                 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 756                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
 757                                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 758                                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
 759                                                 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
 760                         }
 761                 }
 762         } else {
 763                 if (FirstDisConnect) {
 764                         CurrentIGI = pDM_DigTable->rx_gain_range_min;
 765                 } else {
 766                         /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
 767                         if (pFalseAlmCnt->Cnt_all > 10000)
 768                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 769                         else if (pFalseAlmCnt->Cnt_all > 8000)
 770                                 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 771                         else if (pFalseAlmCnt->Cnt_all < 500)
 772                                 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
 773                 }
 774         }
 775         /* 1 Check initial gain by upper/lower bound */
 776         if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
 777                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
 778         if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
 779                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
 780
 781         /* 2 High power RSSI threshold */
 782
 783         ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
 784         pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
 785         pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
 786 }
 787
 788 /* 3============================================================ */
 789 /* 3 FASLE ALARM CHECK */
 790 /* 3============================================================ */
 791
 792 void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
 793 {
 794         u32 ret_value;
 795         struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
 796
 797         if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
 798                 return;
 799
 800         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
 801                 /* hold ofdm counter */
 802                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */
 803                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */
 804
 805                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
 806                 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
 807                 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
 808                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
 809                 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
 810                 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
 811                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
 812                 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
 813                 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
 814                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
 815                 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
 816
 817                 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
 818                                              FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
 819                                              FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
 820
 821                 if (pDM_Odm->SupportICType == ODM_RTL8188E) {
 822                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord);
 823                         FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
 824                         FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16);
 825                 }
 826
 827                 /* hold cck counter */
 828                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
 829                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
 830
 831                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
 832                 FalseAlmCnt->Cnt_Cck_fail = ret_value;
 833                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
 834                 FalseAlmCnt->Cnt_Cck_fail +=  (ret_value & 0xff)<<8;
 835
 836                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
 837                 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
 838
 839                 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
 840                                         FalseAlmCnt->Cnt_SB_Search_fail +
 841                                         FalseAlmCnt->Cnt_Parity_Fail +
 842                                         FalseAlmCnt->Cnt_Rate_Illegal +
 843                                         FalseAlmCnt->Cnt_Crc8_fail +
 844                                         FalseAlmCnt->Cnt_Mcs_fail +
 845                                         FalseAlmCnt->Cnt_Cck_fail);
 846
 847                 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
 848
 849                 if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
 850                         /* reset false alarm counter registers */
 851                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);
 852                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);
 853                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);
 854                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);
 855                         /* update ofdm counter */
 856                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /* update page C counter */
 857                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /* update page D counter */
 858
 859                         /* reset CCK CCA counter */
 860                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);
 861                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);
 862                         /* reset CCK FA counter */
 863                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);
 864                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);
 865                 }
 866         } else { /* FOR ODM_IC_11AC_SERIES */
 867                 /* read OFDM FA counter */
 868                 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord);
 869                 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord);
 870                 FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;
 871
 872                 /*  reset OFDM FA coutner */
 873                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1);
 874                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0);
 875                 /*  reset CCK FA counter */
 876                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);
 877                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);
 878         }
 879 }
 880
 881 /* 3============================================================ */
 882 /* 3 CCK Packet Detect Threshold */
 883 /* 3============================================================ */
 884
 885 void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm)
 886 {
 887         u8 CurCCK_CCAThres;
 888         struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
 889
 890         if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
 891                 return;
 892         if (pDM_Odm->ExtLNA)
 893                 return;
 894         if (pDM_Odm->bLinked) {
 895                 if (pDM_Odm->RSSI_Min > 25) {
 896                         CurCCK_CCAThres = 0xcd;
 897                 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
 898                         CurCCK_CCAThres = 0x83;
 899                 } else {
 900                         if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 901                                 CurCCK_CCAThres = 0x83;
 902                         else
 903                                 CurCCK_CCAThres = 0x40;
 904                 }
 905         } else {
 906                 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 907                         CurCCK_CCAThres = 0x83;
 908                 else
 909                         CurCCK_CCAThres = 0x40;
 910         }
 911         ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
 912 }
 913
 914 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres)
 915 {
 916         struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
 917
 918         if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)           /* modify by Guo.Mingzhi 2012-01-03 */
 919                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
 920         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
 921         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
 922 }
 923
 924 /* 3============================================================ */
 925 /* 3 BB Power Save */
 926 /* 3============================================================ */
 927 void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm)
 928 {
 929         struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
 930
 931         pDM_PSTable->PreCCAState = CCA_MAX;
 932         pDM_PSTable->CurCCAState = CCA_MAX;
 933         pDM_PSTable->PreRFState = RF_MAX;
 934         pDM_PSTable->CurRFState = RF_MAX;
 935         pDM_PSTable->Rssi_val_min = 0;
 936         pDM_PSTable->initialize = 0;
 937 }
 938
 939 void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm)
 940 {
 941         if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A))
 942                 return;
 943         if (!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE))
 944                 return;
 945         if (!(pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE)))
 946                 return;
 947
 948         /* 1 2.Power Saving for 92C */
 949         if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->RFType == ODM_2T2R)) {
 950                 odm_1R_CCA(pDM_Odm);
 951         } else {
 952         /*  20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. */
 953         /*  20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. */
 954         /* 1 3.Power Saving for 88C */
 955                 ODM_RF_Saving(pDM_Odm, false);
 956         }
 957 }
 958
 959 void odm_1R_CCA(struct odm_dm_struct *pDM_Odm)
 960 {
 961         struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
 962
 963         if (pDM_Odm->RSSI_Min != 0xFF) {
 964                 if (pDM_PSTable->PreCCAState == CCA_2R) {
 965                         if (pDM_Odm->RSSI_Min >= 35)
 966                                 pDM_PSTable->CurCCAState = CCA_1R;
 967                         else
 968                                 pDM_PSTable->CurCCAState = CCA_2R;
 969                 } else {
 970                         if (pDM_Odm->RSSI_Min <= 30)
 971                                 pDM_PSTable->CurCCAState = CCA_2R;
 972                         else
 973                                 pDM_PSTable->CurCCAState = CCA_1R;
 974                 }
 975         } else {
 976                 pDM_PSTable->CurCCAState = CCA_MAX;
 977         }
 978
 979         if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) {
 980                 if (pDM_PSTable->CurCCAState == CCA_1R) {
 981                         if (pDM_Odm->RFType == ODM_2T2R)
 982                                 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x13);
 983                         else
 984                                 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x23);
 985                 } else {
 986                         ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x33);
 987                 }
 988                 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
 989         }
 990 }
 991
 992 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
 993 {
 994         struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
 995         u8 Rssi_Up_bound = 30;
 996         u8 Rssi_Low_bound = 25;
 997
 998         if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
 999                 Rssi_Up_bound = 50;
1000                 Rssi_Low_bound = 45;
1001         }
1002         if (pDM_PSTable->initialize == 0) {
1003                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
1004                 pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
1005                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
1006                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
1007                 pDM_PSTable->initialize = 1;
1008         }
1009
1010         if (!bForceInNormal) {
1011                 if (pDM_Odm->RSSI_Min != 0xFF) {
1012                         if (pDM_PSTable->PreRFState == RF_Normal) {
1013                                 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
1014                                         pDM_PSTable->CurRFState = RF_Save;
1015                                 else
1016                                         pDM_PSTable->CurRFState = RF_Normal;
1017                         } else {
1018                                 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
1019                                         pDM_PSTable->CurRFState = RF_Normal;
1020                                 else
1021                                         pDM_PSTable->CurRFState = RF_Save;
1022                         }
1023                 } else {
1024                         pDM_PSTable->CurRFState = RF_MAX;
1025                 }
1026         } else {
1027                 pDM_PSTable->CurRFState = RF_Normal;
1028         }
1029
1030         if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
1031                 if (pDM_PSTable->CurRFState == RF_Save) {
1032                         /*  <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. */
1033                         /*  Suggested by SD3 Yu-Nan. 2011.01.20. */
1034                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
1035                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT5, 0x1); /* Reg874[5]=1b'1 */
1036                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
1037                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */
1038                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
1039                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
1040                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
1041                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */
1042                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */
1043                 } else {
1044                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);
1045                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
1046                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
1047                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
1048                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
1049
1050                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
1051                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT5, 0x0); /* Reg874[5]=1b'0 */
1052                 }
1053                 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
1054         }
1055 }
1056
1057 /* 3============================================================ */
1058 /* 3 RATR MASK */
1059 /* 3============================================================ */
1060 /* 3============================================================ */
1061 /* 3 Rate Adaptive */
1062 /* 3============================================================ */
1063
1064 void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm)
1065 {
1066         struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
1067
1068         pOdmRA->Type = DM_Type_ByDriver;
1069         if (pOdmRA->Type == DM_Type_ByDriver)
1070                 pDM_Odm->bUseRAMask = true;
1071         else
1072                 pDM_Odm->bUseRAMask = false;
1073
1074         pOdmRA->RATRState = DM_RATR_STA_INIT;
1075         pOdmRA->HighRSSIThresh = 50;
1076         pOdmRA->LowRSSIThresh = 20;
1077 }
1078
1079 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level)
1080 {
1081         struct sta_info *pEntry;
1082         u32 rate_bitmap = 0x0fffffff;
1083         u8 WirelessMode;
1084
1085         pEntry = pDM_Odm->pODM_StaInfo[macid];
1086         if (!IS_STA_VALID(pEntry))
1087                 return ra_mask;
1088
1089         WirelessMode = pEntry->wireless_mode;
1090
1091         switch (WirelessMode) {
1092         case ODM_WM_B:
1093                 if (ra_mask & 0x0000000c)               /* 11M or 5.5M enable */
1094                         rate_bitmap = 0x0000000d;
1095                 else
1096                         rate_bitmap = 0x0000000f;
1097                 break;
1098         case (ODM_WM_A|ODM_WM_G):
1099                 if (rssi_level == DM_RATR_STA_HIGH)
1100                         rate_bitmap = 0x00000f00;
1101                 else
1102                         rate_bitmap = 0x00000ff0;
1103                 break;
1104         case (ODM_WM_B|ODM_WM_G):
1105                 if (rssi_level == DM_RATR_STA_HIGH)
1106                         rate_bitmap = 0x00000f00;
1107                 else if (rssi_level == DM_RATR_STA_MIDDLE)
1108                         rate_bitmap = 0x00000ff0;
1109                 else
1110                         rate_bitmap = 0x00000ff5;
1111                 break;
1112         case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1113         case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1114                 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) {
1115                         if (rssi_level == DM_RATR_STA_HIGH) {
1116                                 rate_bitmap = 0x000f0000;
1117                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1118                                 rate_bitmap = 0x000ff000;
1119                         } else {
1120                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1121                                         rate_bitmap = 0x000ff015;
1122                                 else
1123                                         rate_bitmap = 0x000ff005;
1124                         }
1125                 } else {
1126                         if (rssi_level == DM_RATR_STA_HIGH) {
1127                                 rate_bitmap = 0x0f8f0000;
1128                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1129                                 rate_bitmap = 0x0f8ff000;
1130                         } else {
1131                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1132                                         rate_bitmap = 0x0f8ff015;
1133                                 else
1134                                         rate_bitmap = 0x0f8ff005;
1135                         }
1136                 }
1137                 break;
1138         default:
1139                 /* case WIRELESS_11_24N: */
1140                 /* case WIRELESS_11_5N: */
1141                 if (pDM_Odm->RFType == RF_1T2R)
1142                         rate_bitmap = 0x000fffff;
1143                 else
1144                         rate_bitmap = 0x0fffffff;
1145                 break;
1146         }
1147
1148         return rate_bitmap;
1149 }
1150
1151 /*-----------------------------------------------------------------------------
1152  * Function:    odm_RefreshRateAdaptiveMask()
1153  *
1154  * Overview:    Update rate table mask according to rssi
1155  *
1156  * Input:               NONE
1157  *
1158  * Output:              NONE
1159  *
1160  * Return:              NONE
1161  *
1162  * Revised History:
1163  *      When            Who             Remark
1164  *      05/27/2009      hpfan   Create Version 0.
1165  *
1166  *---------------------------------------------------------------------------*/
1167 void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm)
1168 {
1169         if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
1170                 return;
1171         /*  */
1172         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1173         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1174         /*  HW dynamic mechanism. */
1175         /*  */
1176         switch  (pDM_Odm->SupportPlatform) {
1177         case    ODM_MP:
1178                 odm_RefreshRateAdaptiveMaskMP(pDM_Odm);
1179                 break;
1180         case    ODM_CE:
1181                 odm_RefreshRateAdaptiveMaskCE(pDM_Odm);
1182                 break;
1183         case    ODM_AP:
1184         case    ODM_ADSL:
1185                 odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm);
1186                 break;
1187         }
1188 }
1189
1190 void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm)
1191 {
1192 }
1193
1194 void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm)
1195 {
1196         u8 i;
1197         struct adapter *pAdapter = pDM_Odm->Adapter;
1198
1199         if (pAdapter->bDriverStopped)
1200                 return;
1201
1202         if (!pDM_Odm->bUseRAMask)
1203                 return;
1204
1205         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1206                 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1207                 if (IS_STA_VALID(pstat)) {
1208                         if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level))
1209                                 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level);
1210                 }
1211         }
1212 }
1213
1214 void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm)
1215 {
1216 }
1217
1218 /*  Return Value: bool */
1219 /*  - true: RATRState is changed. */
1220 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState)
1221 {
1222         struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1223         const u8 GoUpGap = 5;
1224         u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1225         u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1226         u8 RATRState;
1227
1228         /*  Threshold Adjustment: */
1229         /*  when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1230         /*  Here GoUpGap is added to solve the boundary's level alternation issue. */
1231         switch (*pRATRState) {
1232         case DM_RATR_STA_INIT:
1233         case DM_RATR_STA_HIGH:
1234                 break;
1235         case DM_RATR_STA_MIDDLE:
1236                 HighRSSIThreshForRA += GoUpGap;
1237                 break;
1238         case DM_RATR_STA_LOW:
1239                 HighRSSIThreshForRA += GoUpGap;
1240                 LowRSSIThreshForRA += GoUpGap;
1241                 break;
1242         default:
1243                 break;
1244         }
1245
1246         /*  Decide RATRState by RSSI. */
1247         if (RSSI > HighRSSIThreshForRA)
1248                 RATRState = DM_RATR_STA_HIGH;
1249         else if (RSSI > LowRSSIThreshForRA)
1250                 RATRState = DM_RATR_STA_MIDDLE;
1251         else
1252                 RATRState = DM_RATR_STA_LOW;
1253
1254         if (*pRATRState != RATRState || bForceUpdate) {
1255                 *pRATRState = RATRState;
1256                 return true;
1257         }
1258         return false;
1259 }
1260
1261 /* 3============================================================ */
1262 /* 3 Dynamic Tx Power */
1263 /* 3============================================================ */
1264
1265 void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm)
1266 {
1267         struct adapter *Adapter = pDM_Odm->Adapter;
1268         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
1269         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1270         pdmpriv->bDynamicTxPowerEnable = false;
1271         pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
1272         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1273 }
1274
1275 void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm)
1276 {
1277         /*  For AP/ADSL use struct rtl8192cd_priv * */
1278         /*  For CE/NIC use struct adapter * */
1279
1280         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
1281                 return;
1282
1283         /*  2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */
1284         if (!pDM_Odm->ExtPA)
1285                 return;
1286
1287         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1288         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1289         /*  HW dynamic mechanism. */
1290         switch  (pDM_Odm->SupportPlatform) {
1291         case    ODM_MP:
1292         case    ODM_CE:
1293                 odm_DynamicTxPowerNIC(pDM_Odm);
1294                 break;
1295         case    ODM_AP:
1296                 odm_DynamicTxPowerAP(pDM_Odm);
1297                 break;
1298         case    ODM_ADSL:
1299                 break;
1300         }
1301 }
1302
1303 void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm)
1304 {
1305         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
1306                 return;
1307
1308         if (pDM_Odm->SupportICType == ODM_RTL8188E) {
1309                 /*  ??? */
1310                 /*  This part need to be redefined. */
1311         }
1312 }
1313
1314 void odm_DynamicTxPowerAP(struct odm_dm_struct *pDM_Odm)
1315 {
1316 }
1317
1318 /* 3============================================================ */
1319 /* 3 RSSI Monitor */
1320 /* 3============================================================ */
1321
1322 void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm)
1323 {
1324         if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1325                 return;
1326
1327         /*  */
1328         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1329         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1330         /*  HW dynamic mechanism. */
1331         /*  */
1332         switch  (pDM_Odm->SupportPlatform) {
1333         case    ODM_MP:
1334                 odm_RSSIMonitorCheckMP(pDM_Odm);
1335                 break;
1336         case    ODM_CE:
1337                 odm_RSSIMonitorCheckCE(pDM_Odm);
1338                 break;
1339         case    ODM_AP:
1340                 odm_RSSIMonitorCheckAP(pDM_Odm);
1341                 break;
1342         case    ODM_ADSL:
1343                 /* odm_DIGAP(pDM_Odm); */
1344                 break;
1345         }
1346
1347 }       /*  odm_RSSIMonitorCheck */
1348
1349 void odm_RSSIMonitorCheckMP(struct odm_dm_struct *pDM_Odm)
1350 {
1351 }
1352
1353 static void FindMinimumRSSI(struct adapter *pAdapter)
1354 {
1355         struct hal_data_8188e   *pHalData = GET_HAL_DATA(pAdapter);
1356         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1357         struct mlme_priv        *pmlmepriv = &pAdapter->mlmepriv;
1358
1359         /* 1 1.Determine the minimum RSSI */
1360         if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) &&
1361             (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1362                 pdmpriv->MinUndecoratedPWDBForDM = 0;
1363         if (check_fwstate(pmlmepriv, _FW_LINKED) == true)       /*  Default port */
1364                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1365         else /*  associated entry pwdb */
1366                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1367 }
1368
1369 void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm)
1370 {
1371         struct adapter *Adapter = pDM_Odm->Adapter;
1372         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
1373         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1374         int     i;
1375         int     tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1376         u8      sta_cnt = 0;
1377         u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1378         struct sta_info *psta;
1379         u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1380
1381         if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED))
1382                 return;
1383
1384         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1385                 psta = pDM_Odm->pODM_StaInfo[i];
1386                 if (IS_STA_VALID(psta) &&
1387                     (psta->state & WIFI_ASOC_STATE) &&
1388                     memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) &&
1389                     memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) {
1390                         if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1391                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1392
1393                         if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1394                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1395                         if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1396                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1397                 }
1398         }
1399
1400         for (i = 0; i < sta_cnt; i++) {
1401                 if (PWDB_rssi[i] != (0)) {
1402                         if (pHalData->fw_ractrl) {
1403                                 /*  Report every sta's RSSI to FW */
1404                         } else {
1405                                 ODM_RA_SetRSSI_8188E(
1406                                 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF));
1407                         }
1408                 }
1409         }
1410
1411         if (tmpEntryMaxPWDB != 0)       /*  If associated entry is found */
1412                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1413         else
1414                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1415
1416         if (tmpEntryMinPWDB != 0xff) /*  If associated entry is found */
1417                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1418         else
1419                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1420
1421         FindMinimumRSSI(Adapter);
1422         ODM_CmnInfoUpdate(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1423 }
1424
1425 void odm_RSSIMonitorCheckAP(struct odm_dm_struct *pDM_Odm)
1426 {
1427 }
1428
1429 void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm)
1430 {
1431         timer_setup(&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer, odm_SwAntDivChkAntSwitchCallback, 0);
1432 }
1433
1434 void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm)
1435 {
1436         ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
1437 }
1438
1439 void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm)
1440 {
1441         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
1442
1443         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->FastAntTrainingTimer);
1444 }
1445
1446 /* 3============================================================ */
1447 /* 3 Tx Power Tracking */
1448 /* 3============================================================ */
1449
1450 void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm)
1451 {
1452         odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
1453 }
1454
1455 void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm)
1456 {
1457         pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
1458         pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
1459         pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false;
1460         if (*(pDM_Odm->mp_mode) != 1)
1461                 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1462         MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl);
1463
1464         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1465 }
1466
1467 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm)
1468 {
1469         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1470         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1471         /*  HW dynamic mechanism. */
1472         switch  (pDM_Odm->SupportPlatform) {
1473         case    ODM_MP:
1474                 odm_TXPowerTrackingCheckMP(pDM_Odm);
1475                 break;
1476         case    ODM_CE:
1477                 odm_TXPowerTrackingCheckCE(pDM_Odm);
1478                 break;
1479         case    ODM_AP:
1480                 odm_TXPowerTrackingCheckAP(pDM_Odm);
1481                 break;
1482         case    ODM_ADSL:
1483                 break;
1484         }
1485 }
1486
1487 void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm)
1488 {
1489         struct adapter *Adapter = pDM_Odm->Adapter;
1490
1491         if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
1492                 return;
1493
1494         if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) {             /* at least delay 1 sec */
1495                 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
1496
1497                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
1498                 return;
1499         } else {
1500                 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter);
1501                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
1502         }
1503 }
1504
1505 void odm_TXPowerTrackingCheckMP(struct odm_dm_struct *pDM_Odm)
1506 {
1507 }
1508
1509 void odm_TXPowerTrackingCheckAP(struct odm_dm_struct *pDM_Odm)
1510 {
1511 }
1512
1513 /* antenna mapping info */
1514 /*  1: right-side antenna */
1515 /*  2/0: left-side antenna */
1516 /* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt:  for right-side antenna:   Ant:1    RxDefaultAnt1 */
1517 /* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt:  for left-side antenna:     Ant:0    RxDefaultAnt2 */
1518 /*  We select left antenna as default antenna in initial process, modify it as needed */
1519 /*  */
1520
1521 /* 3============================================================ */
1522 /* 3 SW Antenna Diversity */
1523 /* 3============================================================ */
1524 void odm_SwAntDivInit(struct odm_dm_struct *pDM_Odm)
1525 {
1526 }
1527
1528 void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID, struct odm_phy_status_info *pPhyInfo)
1529 {
1530 }
1531
1532 void odm_SwAntDivChkAntSwitch(struct odm_dm_struct *pDM_Odm, u8 Step)
1533 {
1534 }
1535
1536 void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm)
1537 {
1538 }
1539
1540 void odm_SwAntDivChkAntSwitchCallback(struct timer_list *t)
1541 {
1542 }
1543
1544 /* 3============================================================ */
1545 /* 3 SW Antenna Diversity */
1546 /* 3============================================================ */
1547
1548 void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm)
1549 {
1550         if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
1551                 return;
1552
1553         if (pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
1554                 ;
1555         else if (pDM_Odm->SupportICType == ODM_RTL8188E)
1556                 ODM_AntennaDiversityInit_88E(pDM_Odm);
1557 }
1558
1559 void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate)
1560 {
1561         struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1562
1563         if (pDM_SWAT_Table->antsel == 1) {
1564                 if (isCCKrate) {
1565                         pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++;
1566                 } else {
1567                         pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++;
1568                         pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll;
1569                 }
1570         } else {
1571                 if (isCCKrate) {
1572                         pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++;
1573                 } else {
1574                         pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++;
1575                         pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll;
1576                 }
1577         }
1578 }
1579
1580 void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm)
1581 {
1582         if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
1583                 return;
1584
1585         if (pDM_Odm->SupportICType == ODM_RTL8188E)
1586                 ODM_AntennaDiversity_88E(pDM_Odm);
1587 }
1588
1589 /* EDCA Turbo */
1590 void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm)
1591 {
1592         struct adapter *Adapter = pDM_Odm->Adapter;
1593         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1594         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1595         Adapter->recvpriv.bIsAnyNonBEPkts = false;
1596
1597 }       /*  ODM_InitEdcaTurbo */
1598
1599 void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm)
1600 {
1601         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1602         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1603         /*  HW dynamic mechanism. */
1604         if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1605                 return;
1606
1607         switch  (pDM_Odm->SupportPlatform) {
1608         case    ODM_MP:
1609                 break;
1610         case    ODM_CE:
1611                 odm_EdcaTurboCheckCE(pDM_Odm);
1612                 break;
1613         case    ODM_AP:
1614         case    ODM_ADSL:
1615                 break;
1616         }
1617 }       /*  odm_CheckEdcaTurbo */
1618
1619 void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm)
1620 {
1621         struct adapter *Adapter = pDM_Odm->Adapter;
1622         u32     trafficIndex;
1623         u32     edca_param;
1624         u64     cur_tx_bytes = 0;
1625         u64     cur_rx_bytes = 0;
1626         u8      bbtchange = false;
1627         struct hal_data_8188e           *pHalData = GET_HAL_DATA(Adapter);
1628         struct xmit_priv                *pxmitpriv = &(Adapter->xmitpriv);
1629         struct recv_priv                *precvpriv = &(Adapter->recvpriv);
1630         struct registry_priv    *pregpriv = &Adapter->registrypriv;
1631         struct mlme_ext_priv    *pmlmeext = &(Adapter->mlmeextpriv);
1632         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1633
1634         if ((pregpriv->wifi_spec == 1))/*  (pmlmeinfo->HT_enable == 0)) */
1635                 goto dm_CheckEdcaTurbo_EXIT;
1636
1637         if (pmlmeinfo->assoc_AP_vendor >=  HT_IOT_PEER_MAX)
1638                 goto dm_CheckEdcaTurbo_EXIT;
1639
1640         /*  Check if the status needs to be changed. */
1641         if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1642                 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1643                 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1644
1645                 /* traffic, TX or RX */
1646                 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1647                     (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1648                         if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1649                                 /*  Uplink TP is present. */
1650                                 trafficIndex = UP_LINK;
1651                         } else {
1652                                 /*  Balance TP is present. */
1653                                 trafficIndex = DOWN_LINK;
1654                         }
1655                 } else {
1656                         if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1657                                 /*  Downlink TP is present. */
1658                                 trafficIndex = DOWN_LINK;
1659                         } else {
1660                                 /*  Balance TP is present. */
1661                                 trafficIndex = UP_LINK;
1662                         }
1663                 }
1664
1665                 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1666                         if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1667                                 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1668                         else
1669                                 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1670
1671                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
1672
1673                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1674                 }
1675
1676                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1677         } else {
1678                 /*  Turn Off EDCA turbo here. */
1679                 /*  Restore original EDCA according to the declaration of AP. */
1680                  if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1681                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
1682                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1683                 }
1684         }
1685
1686 dm_CheckEdcaTurbo_EXIT:
1687         /*  Set variables for next time. */
1688         precvpriv->bIsAnyNonBEPkts = false;
1689         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1690         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1691 }
1692
1693 /*  need to ODM CE Platform */
1694 /* move to here for ANT detection mechanism using */
1695
1696 u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1697 {
1698         u32 psd_report;
1699
1700         /* Set DCO frequency index, offset=(40MHz/SamplePts)*point */
1701         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1702
1703         /* Start PSD calculation, Reg808[22]=0->1 */
1704         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1);
1705         /* Need to wait for HW PSD report */
1706         ODM_StallExecution(30);
1707         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);
1708         /* Read PSD report, Reg8B4[15:0] */
1709         psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1710
1711         psd_report = (u32) (ConvertTo_dB(psd_report))+(u32)(initial_gain_psd-0x1c);
1712
1713         return psd_report;
1714 }
1715
1716 u32 ConvertTo_dB(u32 Value)
1717 {
1718         u8 i;
1719         u8 j;
1720         u32 dB;
1721
1722         Value = Value & 0xFFFF;
1723         for (i = 0; i < 8; i++) {
1724                 if (Value <= dB_Invert_Table[i][11])
1725                         break;
1726         }
1727
1728         if (i >= 8)
1729                 return 96;      /*  maximum 96 dB */
1730
1731         for (j = 0; j < 12; j++) {
1732                 if (Value <= dB_Invert_Table[i][j])
1733                         break;
1734         }
1735
1736         dB = i*12 + j + 1;
1737
1738         return dB;
1739 }
1740
1741 /*  2011/09/22 MH Add for 92D global spin lock utilization. */
1742 void odm_GlobalAdapterCheck(void)
1743 {
1744 }       /*  odm_GlobalAdapterCheck */
1745
1746 /*  Description: */
1747 /*      Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1748 /*  Added by Joseph, 2012.03.22 */
1749 void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm)
1750 {
1751         struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1752
1753         pDM_SWAT_Table->ANTA_ON = true;
1754         pDM_SWAT_Table->ANTB_ON = true;
1755 }
1756
1757 /* 2 8723A ANT DETECT */
1758
1759 static void odm_PHY_SaveAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegisterNum)
1760 {
1761         u32 i;
1762
1763         /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1764         for (i = 0; i < RegisterNum; i++)
1765                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1766 }
1767
1768 static void odm_PHY_ReloadAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegiesterNum)
1769 {
1770         u32 i;
1771
1772         for (i = 0; i < RegiesterNum; i++)
1773                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1774 }
1775
1776 /* 2 8723A ANT DETECT */
1777 /*  Description: */
1778 /*      Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1779 /*      This function is cooperated with BB team Neil. */
1780 bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode)
1781 {
1782         struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1783         u32 CurrentChannel, RfLoopReg;
1784         u8 n;
1785         u32 Reg88c, Regc08, Reg874, Regc50;
1786         u8 initial_gain = 0x5a;
1787         u32 PSD_report_tmp;
1788         u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1789         bool bResult = true;
1790         u32 AFE_Backup[16];
1791         u32 AFE_REG_8723A[16] = {
1792                 rRx_Wait_CCA, rTx_CCK_RFON,
1793                 rTx_CCK_BBON, rTx_OFDM_RFON,
1794                 rTx_OFDM_BBON, rTx_To_Rx,
1795                 rTx_To_Tx, rRx_CCK,
1796                 rRx_OFDM, rRx_Wait_RIFS,
1797                 rRx_TO_Rx, rStandby,
1798                 rSleep, rPMPD_ANAEN,
1799                 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1800
1801         if (!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C)))
1802                 return bResult;
1803
1804         if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1805                 return bResult;
1806
1807         if (pDM_Odm->SupportICType == ODM_RTL8192C) {
1808                 /* Which path in ADC/DAC is turnned on for PSD: both I/Q */
1809                 ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3);
1810                 /* Ageraged number: 8 */
1811                 ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1);
1812                 /* pts = 128; */
1813                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
1814         }
1815
1816         /* 1 Backup Current RF/BB Settings */
1817
1818         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1819         RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1820         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  /*  change to Antenna A */
1821         /*  Step 1: USE IQK to transmitter single tone */
1822
1823         ODM_StallExecution(10);
1824
1825         /* Store A Path Register 88c, c08, 874, c50 */
1826         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1827         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1828         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1829         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1830
1831         /*  Store AFE Registers */
1832         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1833
1834         /* Set PSD 128 pts */
1835         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0);  /* 128 pts */
1836
1837         /*  To SET CH1 to do */
1838         ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     /* Channel 1 */
1839
1840         /*  AFE all on step */
1841         ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1842         ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1843         ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1844         ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1845         ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1846         ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1847         ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1848         ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1849         ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1850         ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1851         ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1852         ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1853         ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1854         ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1855         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1856         ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1857
1858         /*  3 wire Disable */
1859         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1860
1861         /* BB IQK Setting */
1862         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1863         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1864
1865         /* IQK setting tone@ 4.34Mhz */
1866         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1867         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1868
1869         /* Page B init */
1870         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1871         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1872         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1873         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1874         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1875         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1876         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1877
1878         /* RF loop Setting */
1879         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1880
1881         /* IQK Single tone start */
1882         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1883         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1884         ODM_StallExecution(1000);
1885         PSD_report_tmp = 0x0;
1886
1887         for (n = 0; n < 2; n++) {
1888                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1889                 if (PSD_report_tmp > AntA_report)
1890                         AntA_report = PSD_report_tmp;
1891         }
1892
1893         PSD_report_tmp = 0x0;
1894
1895         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);  /*  change to Antenna B */
1896         ODM_StallExecution(10);
1897
1898         for (n = 0; n < 2; n++) {
1899                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1900                 if (PSD_report_tmp > AntB_report)
1901                         AntB_report = PSD_report_tmp;
1902         }
1903
1904         /*  change to open case */
1905         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0);  /*  change to Ant A and B all open case */
1906         ODM_StallExecution(10);
1907
1908         for (n = 0; n < 2; n++) {
1909                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1910                 if (PSD_report_tmp > AntO_report)
1911                         AntO_report = PSD_report_tmp;
1912         }
1913
1914         /* Close IQK Single Tone function */
1915         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
1916         PSD_report_tmp = 0x0;
1917
1918         /* 1 Return to antanna A */
1919         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1920         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
1921         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
1922         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
1923         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
1924         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
1925         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1926         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
1927
1928         /* Reload AFE Registers */
1929         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1930
1931         if (pDM_Odm->SupportICType == ODM_RTL8723A) {
1932         /* 2 Test Ant B based on Ant A is ON */
1933                 if (mode == ANTTESTB) {
1934                         if (AntA_report >= 100) {
1935                                 if (AntB_report > (AntA_report+1))
1936                                         pDM_SWAT_Table->ANTB_ON = false;
1937                                 else
1938                                         pDM_SWAT_Table->ANTB_ON = true;
1939                         } else {
1940                                 pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1941                                 bResult = false;
1942                         }
1943                 } else if (mode == ANTTESTALL) {
1944                         /* 2 Test Ant A and B based on DPDT Open */
1945                         if ((AntO_report >= 100)&(AntO_report < 118)) {
1946                                 if (AntA_report > (AntO_report+1))
1947                                         pDM_SWAT_Table->ANTA_ON = false;
1948                                 else
1949                                         pDM_SWAT_Table->ANTA_ON = true;
1950
1951                                 if (AntB_report > (AntO_report+2))
1952                                         pDM_SWAT_Table->ANTB_ON = false;
1953                                 else
1954                                         pDM_SWAT_Table->ANTB_ON = true;
1955                         }
1956                 }
1957         } else if (pDM_Odm->SupportICType == ODM_RTL8192C) {
1958                 if (AntA_report >= 100) {
1959                         if (AntB_report > (AntA_report+2)) {
1960                                 pDM_SWAT_Table->ANTA_ON = false;
1961                                 pDM_SWAT_Table->ANTB_ON = true;
1962                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);
1963                         } else if (AntA_report > (AntB_report+2)) {
1964                                 pDM_SWAT_Table->ANTA_ON = true;
1965                                 pDM_SWAT_Table->ANTB_ON = false;
1966                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1967                         } else {
1968                                 pDM_SWAT_Table->ANTA_ON = true;
1969                                 pDM_SWAT_Table->ANTB_ON = true;
1970                         }
1971                 } else {
1972                         pDM_SWAT_Table->ANTA_ON = true; /*  Set Antenna A on as default */
1973                         pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1974                         bResult = false;
1975                 }
1976         }
1977         return bResult;
1978 }
1979
1980 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
1981 void odm_dtc(struct odm_dm_struct *pDM_Odm)
1982 {
1983 }