drivers/staging/hikey9xx/hi6421-spmi-pmic.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device driver for regulators in HISI PMIC IC
   4  *
   5  * Copyright (c) 2013 Linaro Ltd.
   6  * Copyright (c) 2011 Hisilicon.
   7  * Copyright (c) 2020-2021 Huawei Technologies Co., Ltd
   8  */
   9
  10 #include <linux/bitops.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/mfd/core.h>
  14 #include <linux/mfd/hi6421-spmi-pmic.h>
  15 #include <linux/module.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/spmi.h>
  20
  21 enum hi6421_spmi_pmic_irq_list {
  22         OTMP = 0,
  23         VBUS_CONNECT,
  24         VBUS_DISCONNECT,
  25         ALARMON_R,
  26         HOLD_6S,
  27         HOLD_1S,
  28         POWERKEY_UP,
  29         POWERKEY_DOWN,
  30         OCP_SCP_R,
  31         COUL_R,
  32         SIM0_HPD_R,
  33         SIM0_HPD_F,
  34         SIM1_HPD_R,
  35         SIM1_HPD_F,
  36
  37         PMIC_IRQ_LIST_MAX
  38 };
  39
  40 #define HISI_IRQ_BANK_SIZE              2
  41
  42 /*
  43  * IRQ number for the power key button and mask for both UP and DOWN IRQs
  44  */
  45 #define HISI_POWERKEY_IRQ_NUM           0
  46 #define HISI_IRQ_POWERKEY_UP_DOWN       (BIT(POWERKEY_DOWN) | BIT(POWERKEY_UP))
  47
  48 /*
  49  * Registers for IRQ address and IRQ mask bits
  50  *
  51  * Please notice that we need to regmap a larger region, as other
  52  * registers are used by the regulators.
  53  * See drivers/regulator/hi6421-regulator.c.
  54  */
  55 #define SOC_PMIC_IRQ_MASK_0_ADDR        0x0202
  56 #define SOC_PMIC_IRQ0_ADDR              0x0212
  57
  58 /*
  59  * The IRQs are mapped as:
  60  *
  61  *      ======================  =============   ============    =====
  62  *      IRQ                     MASK REGISTER   IRQ REGISTER    BIT
  63  *      ======================  =============   ============    =====
  64  *      OTMP                    0x0202          0x212           bit 0
  65  *      VBUS_CONNECT            0x0202          0x212           bit 1
  66  *      VBUS_DISCONNECT         0x0202          0x212           bit 2
  67  *      ALARMON_R               0x0202          0x212           bit 3
  68  *      HOLD_6S                 0x0202          0x212           bit 4
  69  *      HOLD_1S                 0x0202          0x212           bit 5
  70  *      POWERKEY_UP             0x0202          0x212           bit 6
  71  *      POWERKEY_DOWN           0x0202          0x212           bit 7
  72  *
  73  *      OCP_SCP_R               0x0203          0x213           bit 0
  74  *      COUL_R                  0x0203          0x213           bit 1
  75  *      SIM0_HPD_R              0x0203          0x213           bit 2
  76  *      SIM0_HPD_F              0x0203          0x213           bit 3
  77  *      SIM1_HPD_R              0x0203          0x213           bit 4
  78  *      SIM1_HPD_F              0x0203          0x213           bit 5
  79  *      ======================  =============   ============    =====
  80  *
  81  * Each mask register contains 8 bits. The ancillary macros below
  82  * convert a number from 0 to 14 into a register address and a bit mask
  83  */
  84 #define HISI_IRQ_MASK_REG(irq_data)     (SOC_PMIC_IRQ_MASK_0_ADDR + \
  85                                          (irqd_to_hwirq(irq_data) / BITS_PER_BYTE))
  86 #define HISI_IRQ_MASK_BIT(irq_data)     BIT(irqd_to_hwirq(irq_data) & (BITS_PER_BYTE - 1))
  87 #define HISI_8BITS_MASK                 0xff
  88
  89 static const struct mfd_cell hi6421v600_devs[] = {
  90         { .name = "hi6421v600-regulator", },
  91 };
  92
  93 static irqreturn_t hi6421_spmi_irq_handler(int irq, void *priv)
  94 {
  95         struct hi6421_spmi_pmic *ddata = (struct hi6421_spmi_pmic *)priv;
  96         unsigned long pending;
  97         unsigned int in;
  98         int i, offset;
  99
 100         for (i = 0; i < HISI_IRQ_BANK_SIZE; i++) {
 101                 regmap_read(ddata->regmap, SOC_PMIC_IRQ0_ADDR + i, &in);
 102
 103                 /* Mark pending IRQs as handled */
 104                 regmap_write(ddata->regmap, SOC_PMIC_IRQ0_ADDR + i, in);
 105
 106                 pending = in & HISI_8BITS_MASK;
 107
 108                 if (i == HISI_POWERKEY_IRQ_NUM &&
 109                     (pending & HISI_IRQ_POWERKEY_UP_DOWN) == HISI_IRQ_POWERKEY_UP_DOWN) {
 110                         /*
 111                          * If both powerkey down and up IRQs are received,
 112                          * handle them at the right order
 113                          */
 114                         generic_handle_irq(ddata->irqs[POWERKEY_DOWN]);
 115                         generic_handle_irq(ddata->irqs[POWERKEY_UP]);
 116                         pending &= ~HISI_IRQ_POWERKEY_UP_DOWN;
 117                 }
 118
 119                 if (!pending)
 120                         continue;
 121
 122                 for_each_set_bit(offset, &pending, BITS_PER_BYTE) {
 123                         generic_handle_irq(ddata->irqs[offset + i * BITS_PER_BYTE]);
 124                 }
 125         }
 126
 127         return IRQ_HANDLED;
 128 }
 129
 130 static void hi6421_spmi_irq_mask(struct irq_data *d)
 131 {
 132         struct hi6421_spmi_pmic *ddata = irq_data_get_irq_chip_data(d);
 133         unsigned long flags;
 134         unsigned int data;
 135         u32 offset;
 136
 137         offset = HISI_IRQ_MASK_REG(d);
 138
 139         spin_lock_irqsave(&ddata->lock, flags);
 140
 141         regmap_read(ddata->regmap, offset, &data);
 142         data |= HISI_IRQ_MASK_BIT(d);
 143         regmap_write(ddata->regmap, offset, data);
 144
 145         spin_unlock_irqrestore(&ddata->lock, flags);
 146 }
 147
 148 static void hi6421_spmi_irq_unmask(struct irq_data *d)
 149 {
 150         struct hi6421_spmi_pmic *ddata = irq_data_get_irq_chip_data(d);
 151         u32 data, offset;
 152         unsigned long flags;
 153
 154         offset = HISI_IRQ_MASK_REG(d);
 155
 156         spin_lock_irqsave(&ddata->lock, flags);
 157
 158         regmap_read(ddata->regmap, offset, &data);
 159         data &= ~HISI_IRQ_MASK_BIT(d);
 160         regmap_write(ddata->regmap, offset, data);
 161
 162         spin_unlock_irqrestore(&ddata->lock, flags);
 163 }
 164
 165 static struct irq_chip hi6421_spmi_pmu_irqchip = {
 166         .name           = "hi6421v600-irq",
 167         .irq_mask       = hi6421_spmi_irq_mask,
 168         .irq_unmask     = hi6421_spmi_irq_unmask,
 169         .irq_disable    = hi6421_spmi_irq_mask,
 170         .irq_enable     = hi6421_spmi_irq_unmask,
 171 };
 172
 173 static int hi6421_spmi_irq_map(struct irq_domain *d, unsigned int virq,
 174                                irq_hw_number_t hw)
 175 {
 176         struct hi6421_spmi_pmic *ddata = d->host_data;
 177
 178         irq_set_chip_and_handler_name(virq, &hi6421_spmi_pmu_irqchip,
 179                                       handle_simple_irq, "hi6421v600");
 180         irq_set_chip_data(virq, ddata);
 181         irq_set_irq_type(virq, IRQ_TYPE_NONE);
 182
 183         return 0;
 184 }
 185
 186 static const struct irq_domain_ops hi6421_spmi_domain_ops = {
 187         .map    = hi6421_spmi_irq_map,
 188         .xlate  = irq_domain_xlate_twocell,
 189 };
 190
 191 static void hi6421_spmi_pmic_irq_init(struct hi6421_spmi_pmic *ddata)
 192 {
 193         int i;
 194         unsigned int pending;
 195
 196         /* Mask all IRQs */
 197         for (i = 0; i < HISI_IRQ_BANK_SIZE; i++)
 198                 regmap_write(ddata->regmap, SOC_PMIC_IRQ_MASK_0_ADDR + i,
 199                              HISI_8BITS_MASK);
 200
 201         /* Mark all IRQs as handled */
 202         for (i = 0; i < HISI_IRQ_BANK_SIZE; i++) {
 203                 regmap_read(ddata->regmap, SOC_PMIC_IRQ0_ADDR + i, &pending);
 204                 regmap_write(ddata->regmap, SOC_PMIC_IRQ0_ADDR + i,
 205                              HISI_8BITS_MASK);
 206         }
 207 }
 208
 209 static const struct regmap_config regmap_config = {
 210         .reg_bits       = 16,
 211         .val_bits       = BITS_PER_BYTE,
 212         .max_register   = 0xffff,
 213         .fast_io        = true
 214 };
 215
 216 static int hi6421_spmi_pmic_probe(struct spmi_device *sdev)
 217 {
 218         struct device *dev = &sdev->dev;
 219         struct device_node *np = dev->of_node;
 220         struct hi6421_spmi_pmic *ddata;
 221         struct platform_device *pdev;
 222         unsigned int virq;
 223         int ret, i;
 224
 225         ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
 226         if (!ddata)
 227                 return -ENOMEM;
 228
 229         ddata->regmap = devm_regmap_init_spmi_ext(sdev, &regmap_config);
 230         if (IS_ERR(ddata->regmap))
 231                 return PTR_ERR(ddata->regmap);
 232
 233         spin_lock_init(&ddata->lock);
 234
 235         ddata->dev = dev;
 236
 237         pdev = container_of(dev, struct platform_device, dev);
 238
 239         ddata->irq = platform_get_irq(pdev, 0);
 240         if (ddata->irq < 0) {
 241                 dev_err(dev, "Error %d when getting IRQs\n", ddata->irq);
 242                 return ddata->irq;
 243         }
 244
 245         hi6421_spmi_pmic_irq_init(ddata);
 246
 247         ddata->irqs = devm_kzalloc(dev, PMIC_IRQ_LIST_MAX * sizeof(int), GFP_KERNEL);
 248         if (!ddata->irqs)
 249                 return -ENOMEM;
 250
 251         ddata->domain = irq_domain_add_simple(np, PMIC_IRQ_LIST_MAX, 0,
 252                                               &hi6421_spmi_domain_ops, ddata);
 253         if (!ddata->domain) {
 254                 dev_err(dev, "Failed to create IRQ domain\n");
 255                 return -ENODEV;
 256         }
 257
 258         for (i = 0; i < PMIC_IRQ_LIST_MAX; i++) {
 259                 virq = irq_create_mapping(ddata->domain, i);
 260                 if (!virq) {
 261                         dev_err(dev, "Failed to map H/W IRQ\n");
 262                         return -ENODEV;
 263                 }
 264                 ddata->irqs[i] = virq;
 265         }
 266
 267         ret = devm_request_threaded_irq(dev,
 268                                         ddata->irq, hi6421_spmi_irq_handler,
 269                                         NULL,
 270                                         IRQF_TRIGGER_LOW | IRQF_SHARED | IRQF_NO_SUSPEND,
 271                                         "pmic", ddata);
 272         if (ret < 0) {
 273                 dev_err(dev, "Failed to start IRQ handling thread: error %d\n",
 274                         ret);
 275                 return ret;
 276         }
 277
 278         dev_set_drvdata(&sdev->dev, ddata);
 279
 280         ret = devm_mfd_add_devices(&sdev->dev, PLATFORM_DEVID_NONE,
 281                                    hi6421v600_devs, ARRAY_SIZE(hi6421v600_devs),
 282                                    NULL, 0, NULL);
 283         if (ret < 0)
 284                 dev_err(dev, "Failed to add child devices: %d\n", ret);
 285
 286         return ret;
 287 }
 288
 289 static const struct of_device_id pmic_spmi_id_table[] = {
 290         { .compatible = "hisilicon,hi6421-spmi" },
 291         { }
 292 };
 293 MODULE_DEVICE_TABLE(of, pmic_spmi_id_table);
 294
 295 static struct spmi_driver hi6421_spmi_pmic_driver = {
 296         .driver = {
 297                 .name   = "hi6421-spmi-pmic",
 298                 .of_match_table = pmic_spmi_id_table,
 299         },
 300         .probe  = hi6421_spmi_pmic_probe,
 301 };
 302 module_spmi_driver(hi6421_spmi_pmic_driver);
 303
 304 MODULE_DESCRIPTION("HiSilicon Hi6421v600 SPMI PMIC driver");
 305 MODULE_LICENSE("GPL v2");