drivers/spi/spi-topcliff-pch.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * SPI bus driver for the Topcliff PCH used by Intel SoCs
   4  *
   5  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/pci.h>
  10 #include <linux/wait.h>
  11 #include <linux/spi/spi.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/sched.h>
  14 #include <linux/spi/spidev.h>
  15 #include <linux/module.h>
  16 #include <linux/device.h>
  17 #include <linux/platform_device.h>
  18
  19 #include <linux/dmaengine.h>
  20 #include <linux/pch_dma.h>
  21
  22 /* Register offsets */
  23 #define PCH_SPCR                0x00    /* SPI control register */
  24 #define PCH_SPBRR               0x04    /* SPI baud rate register */
  25 #define PCH_SPSR                0x08    /* SPI status register */
  26 #define PCH_SPDWR               0x0C    /* SPI write data register */
  27 #define PCH_SPDRR               0x10    /* SPI read data register */
  28 #define PCH_SSNXCR              0x18    /* SSN Expand Control Register */
  29 #define PCH_SRST                0x1C    /* SPI reset register */
  30 #define PCH_ADDRESS_SIZE        0x20
  31
  32 #define PCH_SPSR_TFD            0x000007C0
  33 #define PCH_SPSR_RFD            0x0000F800
  34
  35 #define PCH_READABLE(x)         (((x) & PCH_SPSR_RFD)>>11)
  36 #define PCH_WRITABLE(x)         (((x) & PCH_SPSR_TFD)>>6)
  37
  38 #define PCH_RX_THOLD            7
  39 #define PCH_RX_THOLD_MAX        15
  40
  41 #define PCH_TX_THOLD            2
  42
  43 #define PCH_MAX_BAUDRATE        5000000
  44 #define PCH_MAX_FIFO_DEPTH      16
  45
  46 #define STATUS_RUNNING          1
  47 #define STATUS_EXITING          2
  48 #define PCH_SLEEP_TIME          10
  49
  50 #define SSN_LOW                 0x02U
  51 #define SSN_HIGH                0x03U
  52 #define SSN_NO_CONTROL          0x00U
  53 #define PCH_MAX_CS              0xFF
  54 #define PCI_DEVICE_ID_GE_SPI    0x8816
  55
  56 #define SPCR_SPE_BIT            (1 << 0)
  57 #define SPCR_MSTR_BIT           (1 << 1)
  58 #define SPCR_LSBF_BIT           (1 << 4)
  59 #define SPCR_CPHA_BIT           (1 << 5)
  60 #define SPCR_CPOL_BIT           (1 << 6)
  61 #define SPCR_TFIE_BIT           (1 << 8)
  62 #define SPCR_RFIE_BIT           (1 << 9)
  63 #define SPCR_FIE_BIT            (1 << 10)
  64 #define SPCR_ORIE_BIT           (1 << 11)
  65 #define SPCR_MDFIE_BIT          (1 << 12)
  66 #define SPCR_FICLR_BIT          (1 << 24)
  67 #define SPSR_TFI_BIT            (1 << 0)
  68 #define SPSR_RFI_BIT            (1 << 1)
  69 #define SPSR_FI_BIT             (1 << 2)
  70 #define SPSR_ORF_BIT            (1 << 3)
  71 #define SPBRR_SIZE_BIT          (1 << 10)
  72
  73 #define PCH_ALL                 (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
  74                                 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
  75
  76 #define SPCR_RFIC_FIELD         20
  77 #define SPCR_TFIC_FIELD         16
  78
  79 #define MASK_SPBRR_SPBR_BITS    ((1 << 10) - 1)
  80 #define MASK_RFIC_SPCR_BITS     (0xf << SPCR_RFIC_FIELD)
  81 #define MASK_TFIC_SPCR_BITS     (0xf << SPCR_TFIC_FIELD)
  82
  83 #define PCH_CLOCK_HZ            50000000
  84 #define PCH_MAX_SPBR            1023
  85
  86 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
  87 #define PCI_DEVICE_ID_ML7213_SPI        0x802c
  88 #define PCI_DEVICE_ID_ML7223_SPI        0x800F
  89 #define PCI_DEVICE_ID_ML7831_SPI        0x8816
  90
  91 /*
  92  * Set the number of SPI instance max
  93  * Intel EG20T PCH :            1ch
  94  * LAPIS Semiconductor ML7213 IOH :     2ch
  95  * LAPIS Semiconductor ML7223 IOH :     1ch
  96  * LAPIS Semiconductor ML7831 IOH :     1ch
  97 */
  98 #define PCH_SPI_MAX_DEV                 2
  99
 100 #define PCH_BUF_SIZE            4096
 101 #define PCH_DMA_TRANS_SIZE      12
 102
 103 static int use_dma = 1;
 104
 105 struct pch_spi_dma_ctrl {
 106         struct dma_async_tx_descriptor  *desc_tx;
 107         struct dma_async_tx_descriptor  *desc_rx;
 108         struct pch_dma_slave            param_tx;
 109         struct pch_dma_slave            param_rx;
 110         struct dma_chan         *chan_tx;
 111         struct dma_chan         *chan_rx;
 112         struct scatterlist              *sg_tx_p;
 113         struct scatterlist              *sg_rx_p;
 114         struct scatterlist              sg_tx;
 115         struct scatterlist              sg_rx;
 116         int                             nent;
 117         void                            *tx_buf_virt;
 118         void                            *rx_buf_virt;
 119         dma_addr_t                      tx_buf_dma;
 120         dma_addr_t                      rx_buf_dma;
 121 };
 122 /**
 123  * struct pch_spi_data - Holds the SPI channel specific details
 124  * @io_remap_addr:              The remapped PCI base address
 125  * @io_base_addr:               Base address
 126  * @master:                     Pointer to the SPI master structure
 127  * @work:                       Reference to work queue handler
 128  * @wait:                       Wait queue for waking up upon receiving an
 129  *                              interrupt.
 130  * @transfer_complete:          Status of SPI Transfer
 131  * @bcurrent_msg_processing:    Status flag for message processing
 132  * @lock:                       Lock for protecting this structure
 133  * @queue:                      SPI Message queue
 134  * @status:                     Status of the SPI driver
 135  * @bpw_len:                    Length of data to be transferred in bits per
 136  *                              word
 137  * @transfer_active:            Flag showing active transfer
 138  * @tx_index:                   Transmit data count; for bookkeeping during
 139  *                              transfer
 140  * @rx_index:                   Receive data count; for bookkeeping during
 141  *                              transfer
 142  * @pkt_tx_buff:                Buffer for data to be transmitted
 143  * @pkt_rx_buff:                Buffer for received data
 144  * @n_curnt_chip:               The chip number that this SPI driver currently
 145  *                              operates on
 146  * @current_chip:               Reference to the current chip that this SPI
 147  *                              driver currently operates on
 148  * @current_msg:                The current message that this SPI driver is
 149  *                              handling
 150  * @cur_trans:                  The current transfer that this SPI driver is
 151  *                              handling
 152  * @board_dat:                  Reference to the SPI device data structure
 153  * @plat_dev:                   platform_device structure
 154  * @ch:                         SPI channel number
 155  * @dma:                        Local DMA information
 156  * @use_dma:                    True if DMA is to be used
 157  * @irq_reg_sts:                Status of IRQ registration
 158  * @save_total_len:             Save length while data is being transferred
 159  */
 160 struct pch_spi_data {
 161         void __iomem *io_remap_addr;
 162         unsigned long io_base_addr;
 163         struct spi_master *master;
 164         struct work_struct work;
 165         wait_queue_head_t wait;
 166         u8 transfer_complete;
 167         u8 bcurrent_msg_processing;
 168         spinlock_t lock;
 169         struct list_head queue;
 170         u8 status;
 171         u32 bpw_len;
 172         u8 transfer_active;
 173         u32 tx_index;
 174         u32 rx_index;
 175         u16 *pkt_tx_buff;
 176         u16 *pkt_rx_buff;
 177         u8 n_curnt_chip;
 178         struct spi_device *current_chip;
 179         struct spi_message *current_msg;
 180         struct spi_transfer *cur_trans;
 181         struct pch_spi_board_data *board_dat;
 182         struct platform_device  *plat_dev;
 183         int ch;
 184         struct pch_spi_dma_ctrl dma;
 185         int use_dma;
 186         u8 irq_reg_sts;
 187         int save_total_len;
 188 };
 189
 190 /**
 191  * struct pch_spi_board_data - Holds the SPI device specific details
 192  * @pdev:               Pointer to the PCI device
 193  * @suspend_sts:        Status of suspend
 194  * @num:                The number of SPI device instance
 195  */
 196 struct pch_spi_board_data {
 197         struct pci_dev *pdev;
 198         u8 suspend_sts;
 199         int num;
 200 };
 201
 202 struct pch_pd_dev_save {
 203         int num;
 204         struct platform_device *pd_save[PCH_SPI_MAX_DEV];
 205         struct pch_spi_board_data *board_dat;
 206 };
 207
 208 static const struct pci_device_id pch_spi_pcidev_id[] = {
 209         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),    1, },
 210         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
 211         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
 212         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
 213         { }
 214 };
 215
 216 /**
 217  * pch_spi_writereg() - Performs  register writes
 218  * @master:     Pointer to struct spi_master.
 219  * @idx:        Register offset.
 220  * @val:        Value to be written to register.
 221  */
 222 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
 223 {
 224         struct pch_spi_data *data = spi_master_get_devdata(master);
 225         iowrite32(val, (data->io_remap_addr + idx));
 226 }
 227
 228 /**
 229  * pch_spi_readreg() - Performs register reads
 230  * @master:     Pointer to struct spi_master.
 231  * @idx:        Register offset.
 232  */
 233 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
 234 {
 235         struct pch_spi_data *data = spi_master_get_devdata(master);
 236         return ioread32(data->io_remap_addr + idx);
 237 }
 238
 239 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
 240                                       u32 set, u32 clr)
 241 {
 242         u32 tmp = pch_spi_readreg(master, idx);
 243         tmp = (tmp & ~clr) | set;
 244         pch_spi_writereg(master, idx, tmp);
 245 }
 246
 247 static void pch_spi_set_master_mode(struct spi_master *master)
 248 {
 249         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
 250 }
 251
 252 /**
 253  * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
 254  * @master:     Pointer to struct spi_master.
 255  */
 256 static void pch_spi_clear_fifo(struct spi_master *master)
 257 {
 258         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
 259         pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
 260 }
 261
 262 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
 263                                 void __iomem *io_remap_addr)
 264 {
 265         u32 n_read, tx_index, rx_index, bpw_len;
 266         u16 *pkt_rx_buffer, *pkt_tx_buff;
 267         int read_cnt;
 268         u32 reg_spcr_val;
 269         void __iomem *spsr;
 270         void __iomem *spdrr;
 271         void __iomem *spdwr;
 272
 273         spsr = io_remap_addr + PCH_SPSR;
 274         iowrite32(reg_spsr_val, spsr);
 275
 276         if (data->transfer_active) {
 277                 rx_index = data->rx_index;
 278                 tx_index = data->tx_index;
 279                 bpw_len = data->bpw_len;
 280                 pkt_rx_buffer = data->pkt_rx_buff;
 281                 pkt_tx_buff = data->pkt_tx_buff;
 282
 283                 spdrr = io_remap_addr + PCH_SPDRR;
 284                 spdwr = io_remap_addr + PCH_SPDWR;
 285
 286                 n_read = PCH_READABLE(reg_spsr_val);
 287
 288                 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
 289                         pkt_rx_buffer[rx_index++] = ioread32(spdrr);
 290                         if (tx_index < bpw_len)
 291                                 iowrite32(pkt_tx_buff[tx_index++], spdwr);
 292                 }
 293
 294                 /* disable RFI if not needed */
 295                 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
 296                         reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
 297                         reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
 298
 299                         /* reset rx threshold */
 300                         reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
 301                         reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
 302
 303                         iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
 304                 }
 305
 306                 /* update counts */
 307                 data->tx_index = tx_index;
 308                 data->rx_index = rx_index;
 309
 310                 /* if transfer complete interrupt */
 311                 if (reg_spsr_val & SPSR_FI_BIT) {
 312                         if ((tx_index == bpw_len) && (rx_index == tx_index)) {
 313                                 /* disable interrupts */
 314                                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 315                                                    PCH_ALL);
 316
 317                                 /* transfer is completed;
 318                                    inform pch_spi_process_messages */
 319                                 data->transfer_complete = true;
 320                                 data->transfer_active = false;
 321                                 wake_up(&data->wait);
 322                         } else {
 323                                 dev_vdbg(&data->master->dev,
 324                                         "%s : Transfer is not completed",
 325                                         __func__);
 326                         }
 327                 }
 328         }
 329 }
 330
 331 /**
 332  * pch_spi_handler() - Interrupt handler
 333  * @irq:        The interrupt number.
 334  * @dev_id:     Pointer to struct pch_spi_board_data.
 335  */
 336 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
 337 {
 338         u32 reg_spsr_val;
 339         void __iomem *spsr;
 340         void __iomem *io_remap_addr;
 341         irqreturn_t ret = IRQ_NONE;
 342         struct pch_spi_data *data = dev_id;
 343         struct pch_spi_board_data *board_dat = data->board_dat;
 344
 345         if (board_dat->suspend_sts) {
 346                 dev_dbg(&board_dat->pdev->dev,
 347                         "%s returning due to suspend\n", __func__);
 348                 return IRQ_NONE;
 349         }
 350
 351         io_remap_addr = data->io_remap_addr;
 352         spsr = io_remap_addr + PCH_SPSR;
 353
 354         reg_spsr_val = ioread32(spsr);
 355
 356         if (reg_spsr_val & SPSR_ORF_BIT) {
 357                 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
 358                 if (data->current_msg->complete) {
 359                         data->transfer_complete = true;
 360                         data->current_msg->status = -EIO;
 361                         data->current_msg->complete(data->current_msg->context);
 362                         data->bcurrent_msg_processing = false;
 363                         data->current_msg = NULL;
 364                         data->cur_trans = NULL;
 365                 }
 366         }
 367
 368         if (data->use_dma)
 369                 return IRQ_NONE;
 370
 371         /* Check if the interrupt is for SPI device */
 372         if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
 373                 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
 374                 ret = IRQ_HANDLED;
 375         }
 376
 377         dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
 378                 __func__, ret);
 379
 380         return ret;
 381 }
 382
 383 /**
 384  * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
 385  * @master:     Pointer to struct spi_master.
 386  * @speed_hz:   Baud rate.
 387  */
 388 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
 389 {
 390         u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
 391
 392         /* if baud rate is less than we can support limit it */
 393         if (n_spbr > PCH_MAX_SPBR)
 394                 n_spbr = PCH_MAX_SPBR;
 395
 396         pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
 397 }
 398
 399 /**
 400  * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
 401  * @master:             Pointer to struct spi_master.
 402  * @bits_per_word:      Bits per word for SPI transfer.
 403  */
 404 static void pch_spi_set_bits_per_word(struct spi_master *master,
 405                                       u8 bits_per_word)
 406 {
 407         if (bits_per_word == 8)
 408                 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
 409         else
 410                 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
 411 }
 412
 413 /**
 414  * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
 415  * @spi:        Pointer to struct spi_device.
 416  */
 417 static void pch_spi_setup_transfer(struct spi_device *spi)
 418 {
 419         u32 flags = 0;
 420
 421         dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
 422                 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
 423                 spi->max_speed_hz);
 424         pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
 425
 426         /* set bits per word */
 427         pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
 428
 429         if (!(spi->mode & SPI_LSB_FIRST))
 430                 flags |= SPCR_LSBF_BIT;
 431         if (spi->mode & SPI_CPOL)
 432                 flags |= SPCR_CPOL_BIT;
 433         if (spi->mode & SPI_CPHA)
 434                 flags |= SPCR_CPHA_BIT;
 435         pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
 436                            (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
 437
 438         /* Clear the FIFO by toggling  FICLR to 1 and back to 0 */
 439         pch_spi_clear_fifo(spi->master);
 440 }
 441
 442 /**
 443  * pch_spi_reset() - Clears SPI registers
 444  * @master:     Pointer to struct spi_master.
 445  */
 446 static void pch_spi_reset(struct spi_master *master)
 447 {
 448         /* write 1 to reset SPI */
 449         pch_spi_writereg(master, PCH_SRST, 0x1);
 450
 451         /* clear reset */
 452         pch_spi_writereg(master, PCH_SRST, 0x0);
 453 }
 454
 455 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
 456 {
 457
 458         struct spi_transfer *transfer;
 459         struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
 460         int retval;
 461         unsigned long flags;
 462
 463         spin_lock_irqsave(&data->lock, flags);
 464         /* validate Tx/Rx buffers and Transfer length */
 465         list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
 466                 if (!transfer->tx_buf && !transfer->rx_buf) {
 467                         dev_err(&pspi->dev,
 468                                 "%s Tx and Rx buffer NULL\n", __func__);
 469                         retval = -EINVAL;
 470                         goto err_return_spinlock;
 471                 }
 472
 473                 if (!transfer->len) {
 474                         dev_err(&pspi->dev, "%s Transfer length invalid\n",
 475                                 __func__);
 476                         retval = -EINVAL;
 477                         goto err_return_spinlock;
 478                 }
 479
 480                 dev_dbg(&pspi->dev,
 481                         "%s Tx/Rx buffer valid. Transfer length valid\n",
 482                         __func__);
 483         }
 484         spin_unlock_irqrestore(&data->lock, flags);
 485
 486         /* We won't process any messages if we have been asked to terminate */
 487         if (data->status == STATUS_EXITING) {
 488                 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
 489                 retval = -ESHUTDOWN;
 490                 goto err_out;
 491         }
 492
 493         /* If suspended ,return -EINVAL */
 494         if (data->board_dat->suspend_sts) {
 495                 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
 496                 retval = -EINVAL;
 497                 goto err_out;
 498         }
 499
 500         /* set status of message */
 501         pmsg->actual_length = 0;
 502         dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
 503
 504         pmsg->status = -EINPROGRESS;
 505         spin_lock_irqsave(&data->lock, flags);
 506         /* add message to queue */
 507         list_add_tail(&pmsg->queue, &data->queue);
 508         spin_unlock_irqrestore(&data->lock, flags);
 509
 510         dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
 511
 512         schedule_work(&data->work);
 513         dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
 514
 515         retval = 0;
 516
 517 err_out:
 518         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 519         return retval;
 520 err_return_spinlock:
 521         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 522         spin_unlock_irqrestore(&data->lock, flags);
 523         return retval;
 524 }
 525
 526 static inline void pch_spi_select_chip(struct pch_spi_data *data,
 527                                        struct spi_device *pspi)
 528 {
 529         if (data->current_chip != NULL) {
 530                 if (pspi->chip_select != data->n_curnt_chip) {
 531                         dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
 532                         data->current_chip = NULL;
 533                 }
 534         }
 535
 536         data->current_chip = pspi;
 537
 538         data->n_curnt_chip = data->current_chip->chip_select;
 539
 540         dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
 541         pch_spi_setup_transfer(pspi);
 542 }
 543
 544 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
 545 {
 546         int size;
 547         u32 n_writes;
 548         int j;
 549         struct spi_message *pmsg, *tmp;
 550         const u8 *tx_buf;
 551         const u16 *tx_sbuf;
 552
 553         /* set baud rate if needed */
 554         if (data->cur_trans->speed_hz) {
 555                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 556                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 557         }
 558
 559         /* set bits per word if needed */
 560         if (data->cur_trans->bits_per_word &&
 561             (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
 562                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 563                 pch_spi_set_bits_per_word(data->master,
 564                                           data->cur_trans->bits_per_word);
 565                 *bpw = data->cur_trans->bits_per_word;
 566         } else {
 567                 *bpw = data->current_msg->spi->bits_per_word;
 568         }
 569
 570         /* reset Tx/Rx index */
 571         data->tx_index = 0;
 572         data->rx_index = 0;
 573
 574         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 575
 576         /* find alloc size */
 577         size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
 578
 579         /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
 580         data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
 581         if (data->pkt_tx_buff != NULL) {
 582                 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
 583                 if (!data->pkt_rx_buff)
 584                         kfree(data->pkt_tx_buff);
 585         }
 586
 587         if (!data->pkt_rx_buff) {
 588                 /* flush queue and set status of all transfers to -ENOMEM */
 589                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
 590                         pmsg->status = -ENOMEM;
 591
 592                         if (pmsg->complete)
 593                                 pmsg->complete(pmsg->context);
 594
 595                         /* delete from queue */
 596                         list_del_init(&pmsg->queue);
 597                 }
 598                 return;
 599         }
 600
 601         /* copy Tx Data */
 602         if (data->cur_trans->tx_buf != NULL) {
 603                 if (*bpw == 8) {
 604                         tx_buf = data->cur_trans->tx_buf;
 605                         for (j = 0; j < data->bpw_len; j++)
 606                                 data->pkt_tx_buff[j] = *tx_buf++;
 607                 } else {
 608                         tx_sbuf = data->cur_trans->tx_buf;
 609                         for (j = 0; j < data->bpw_len; j++)
 610                                 data->pkt_tx_buff[j] = *tx_sbuf++;
 611                 }
 612         }
 613
 614         /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
 615         n_writes = data->bpw_len;
 616         if (n_writes > PCH_MAX_FIFO_DEPTH)
 617                 n_writes = PCH_MAX_FIFO_DEPTH;
 618
 619         dev_dbg(&data->master->dev,
 620                 "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n",
 621                 __func__);
 622         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
 623
 624         for (j = 0; j < n_writes; j++)
 625                 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
 626
 627         /* update tx_index */
 628         data->tx_index = j;
 629
 630         /* reset transfer complete flag */
 631         data->transfer_complete = false;
 632         data->transfer_active = true;
 633 }
 634
 635 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
 636 {
 637         struct spi_message *pmsg, *tmp;
 638         dev_dbg(&data->master->dev, "%s called\n", __func__);
 639         /* Invoke complete callback
 640          * [To the spi core..indicating end of transfer] */
 641         data->current_msg->status = 0;
 642
 643         if (data->current_msg->complete) {
 644                 dev_dbg(&data->master->dev,
 645                         "%s:Invoking callback of SPI core\n", __func__);
 646                 data->current_msg->complete(data->current_msg->context);
 647         }
 648
 649         /* update status in global variable */
 650         data->bcurrent_msg_processing = false;
 651
 652         dev_dbg(&data->master->dev,
 653                 "%s:data->bcurrent_msg_processing = false\n", __func__);
 654
 655         data->current_msg = NULL;
 656         data->cur_trans = NULL;
 657
 658         /* check if we have items in list and not suspending
 659          * return 1 if list empty */
 660         if ((list_empty(&data->queue) == 0) &&
 661             (!data->board_dat->suspend_sts) &&
 662             (data->status != STATUS_EXITING)) {
 663                 /* We have some more work to do (either there is more tranint
 664                  * bpw;sfer requests in the current message or there are
 665                  *more messages)
 666                  */
 667                 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
 668                 schedule_work(&data->work);
 669         } else if (data->board_dat->suspend_sts ||
 670                    data->status == STATUS_EXITING) {
 671                 dev_dbg(&data->master->dev,
 672                         "%s suspend/remove initiated, flushing queue\n",
 673                         __func__);
 674                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
 675                         pmsg->status = -EIO;
 676
 677                         if (pmsg->complete)
 678                                 pmsg->complete(pmsg->context);
 679
 680                         /* delete from queue */
 681                         list_del_init(&pmsg->queue);
 682                 }
 683         }
 684 }
 685
 686 static void pch_spi_set_ir(struct pch_spi_data *data)
 687 {
 688         /* enable interrupts, set threshold, enable SPI */
 689         if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
 690                 /* set receive threshold to PCH_RX_THOLD */
 691                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 692                                    PCH_RX_THOLD << SPCR_RFIC_FIELD |
 693                                    SPCR_FIE_BIT | SPCR_RFIE_BIT |
 694                                    SPCR_ORIE_BIT | SPCR_SPE_BIT,
 695                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 696         else
 697                 /* set receive threshold to maximum */
 698                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 699                                    PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
 700                                    SPCR_FIE_BIT | SPCR_ORIE_BIT |
 701                                    SPCR_SPE_BIT,
 702                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 703
 704         /* Wait until the transfer completes; go to sleep after
 705                                  initiating the transfer. */
 706         dev_dbg(&data->master->dev,
 707                 "%s:waiting for transfer to get over\n", __func__);
 708
 709         wait_event_interruptible(data->wait, data->transfer_complete);
 710
 711         /* clear all interrupts */
 712         pch_spi_writereg(data->master, PCH_SPSR,
 713                          pch_spi_readreg(data->master, PCH_SPSR));
 714         /* Disable interrupts and SPI transfer */
 715         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
 716         /* clear FIFO */
 717         pch_spi_clear_fifo(data->master);
 718 }
 719
 720 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
 721 {
 722         int j;
 723         u8 *rx_buf;
 724         u16 *rx_sbuf;
 725
 726         /* copy Rx Data */
 727         if (!data->cur_trans->rx_buf)
 728                 return;
 729
 730         if (bpw == 8) {
 731                 rx_buf = data->cur_trans->rx_buf;
 732                 for (j = 0; j < data->bpw_len; j++)
 733                         *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
 734         } else {
 735                 rx_sbuf = data->cur_trans->rx_buf;
 736                 for (j = 0; j < data->bpw_len; j++)
 737                         *rx_sbuf++ = data->pkt_rx_buff[j];
 738         }
 739 }
 740
 741 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
 742 {
 743         int j;
 744         u8 *rx_buf;
 745         u16 *rx_sbuf;
 746         const u8 *rx_dma_buf;
 747         const u16 *rx_dma_sbuf;
 748
 749         /* copy Rx Data */
 750         if (!data->cur_trans->rx_buf)
 751                 return;
 752
 753         if (bpw == 8) {
 754                 rx_buf = data->cur_trans->rx_buf;
 755                 rx_dma_buf = data->dma.rx_buf_virt;
 756                 for (j = 0; j < data->bpw_len; j++)
 757                         *rx_buf++ = *rx_dma_buf++ & 0xFF;
 758                 data->cur_trans->rx_buf = rx_buf;
 759         } else {
 760                 rx_sbuf = data->cur_trans->rx_buf;
 761                 rx_dma_sbuf = data->dma.rx_buf_virt;
 762                 for (j = 0; j < data->bpw_len; j++)
 763                         *rx_sbuf++ = *rx_dma_sbuf++;
 764                 data->cur_trans->rx_buf = rx_sbuf;
 765         }
 766 }
 767
 768 static int pch_spi_start_transfer(struct pch_spi_data *data)
 769 {
 770         struct pch_spi_dma_ctrl *dma;
 771         unsigned long flags;
 772         int rtn;
 773
 774         dma = &data->dma;
 775
 776         spin_lock_irqsave(&data->lock, flags);
 777
 778         /* disable interrupts, SPI set enable */
 779         pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
 780
 781         spin_unlock_irqrestore(&data->lock, flags);
 782
 783         /* Wait until the transfer completes; go to sleep after
 784                                  initiating the transfer. */
 785         dev_dbg(&data->master->dev,
 786                 "%s:waiting for transfer to get over\n", __func__);
 787         rtn = wait_event_interruptible_timeout(data->wait,
 788                                                data->transfer_complete,
 789                                                msecs_to_jiffies(2 * HZ));
 790         if (!rtn)
 791                 dev_err(&data->master->dev,
 792                         "%s wait-event timeout\n", __func__);
 793
 794         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
 795                             DMA_FROM_DEVICE);
 796
 797         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
 798                             DMA_FROM_DEVICE);
 799         memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
 800
 801         async_tx_ack(dma->desc_rx);
 802         async_tx_ack(dma->desc_tx);
 803         kfree(dma->sg_tx_p);
 804         kfree(dma->sg_rx_p);
 805
 806         spin_lock_irqsave(&data->lock, flags);
 807
 808         /* clear fifo threshold, disable interrupts, disable SPI transfer */
 809         pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 810                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
 811                            SPCR_SPE_BIT);
 812         /* clear all interrupts */
 813         pch_spi_writereg(data->master, PCH_SPSR,
 814                          pch_spi_readreg(data->master, PCH_SPSR));
 815         /* clear FIFO */
 816         pch_spi_clear_fifo(data->master);
 817
 818         spin_unlock_irqrestore(&data->lock, flags);
 819
 820         return rtn;
 821 }
 822
 823 static void pch_dma_rx_complete(void *arg)
 824 {
 825         struct pch_spi_data *data = arg;
 826
 827         /* transfer is completed;inform pch_spi_process_messages_dma */
 828         data->transfer_complete = true;
 829         wake_up_interruptible(&data->wait);
 830 }
 831
 832 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
 833 {
 834         struct pch_dma_slave *param = slave;
 835
 836         if ((chan->chan_id == param->chan_id) &&
 837             (param->dma_dev == chan->device->dev)) {
 838                 chan->private = param;
 839                 return true;
 840         } else {
 841                 return false;
 842         }
 843 }
 844
 845 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
 846 {
 847         dma_cap_mask_t mask;
 848         struct dma_chan *chan;
 849         struct pci_dev *dma_dev;
 850         struct pch_dma_slave *param;
 851         struct pch_spi_dma_ctrl *dma;
 852         unsigned int width;
 853
 854         if (bpw == 8)
 855                 width = PCH_DMA_WIDTH_1_BYTE;
 856         else
 857                 width = PCH_DMA_WIDTH_2_BYTES;
 858
 859         dma = &data->dma;
 860         dma_cap_zero(mask);
 861         dma_cap_set(DMA_SLAVE, mask);
 862
 863         /* Get DMA's dev information */
 864         dma_dev = pci_get_slot(data->board_dat->pdev->bus,
 865                         PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
 866
 867         /* Set Tx DMA */
 868         param = &dma->param_tx;
 869         param->dma_dev = &dma_dev->dev;
 870         param->chan_id = data->ch * 2; /* Tx = 0, 2 */
 871         param->tx_reg = data->io_base_addr + PCH_SPDWR;
 872         param->width = width;
 873         chan = dma_request_channel(mask, pch_spi_filter, param);
 874         if (!chan) {
 875                 dev_err(&data->master->dev,
 876                         "ERROR: dma_request_channel FAILS(Tx)\n");
 877                 data->use_dma = 0;
 878                 return;
 879         }
 880         dma->chan_tx = chan;
 881
 882         /* Set Rx DMA */
 883         param = &dma->param_rx;
 884         param->dma_dev = &dma_dev->dev;
 885         param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */
 886         param->rx_reg = data->io_base_addr + PCH_SPDRR;
 887         param->width = width;
 888         chan = dma_request_channel(mask, pch_spi_filter, param);
 889         if (!chan) {
 890                 dev_err(&data->master->dev,
 891                         "ERROR: dma_request_channel FAILS(Rx)\n");
 892                 dma_release_channel(dma->chan_tx);
 893                 dma->chan_tx = NULL;
 894                 data->use_dma = 0;
 895                 return;
 896         }
 897         dma->chan_rx = chan;
 898 }
 899
 900 static void pch_spi_release_dma(struct pch_spi_data *data)
 901 {
 902         struct pch_spi_dma_ctrl *dma;
 903
 904         dma = &data->dma;
 905         if (dma->chan_tx) {
 906                 dma_release_channel(dma->chan_tx);
 907                 dma->chan_tx = NULL;
 908         }
 909         if (dma->chan_rx) {
 910                 dma_release_channel(dma->chan_rx);
 911                 dma->chan_rx = NULL;
 912         }
 913 }
 914
 915 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
 916 {
 917         const u8 *tx_buf;
 918         const u16 *tx_sbuf;
 919         u8 *tx_dma_buf;
 920         u16 *tx_dma_sbuf;
 921         struct scatterlist *sg;
 922         struct dma_async_tx_descriptor *desc_tx;
 923         struct dma_async_tx_descriptor *desc_rx;
 924         int num;
 925         int i;
 926         int size;
 927         int rem;
 928         int head;
 929         unsigned long flags;
 930         struct pch_spi_dma_ctrl *dma;
 931
 932         dma = &data->dma;
 933
 934         /* set baud rate if needed */
 935         if (data->cur_trans->speed_hz) {
 936                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 937                 spin_lock_irqsave(&data->lock, flags);
 938                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 939                 spin_unlock_irqrestore(&data->lock, flags);
 940         }
 941
 942         /* set bits per word if needed */
 943         if (data->cur_trans->bits_per_word &&
 944             (data->current_msg->spi->bits_per_word !=
 945              data->cur_trans->bits_per_word)) {
 946                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 947                 spin_lock_irqsave(&data->lock, flags);
 948                 pch_spi_set_bits_per_word(data->master,
 949                                           data->cur_trans->bits_per_word);
 950                 spin_unlock_irqrestore(&data->lock, flags);
 951                 *bpw = data->cur_trans->bits_per_word;
 952         } else {
 953                 *bpw = data->current_msg->spi->bits_per_word;
 954         }
 955         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 956
 957         if (data->bpw_len > PCH_BUF_SIZE) {
 958                 data->bpw_len = PCH_BUF_SIZE;
 959                 data->cur_trans->len -= PCH_BUF_SIZE;
 960         }
 961
 962         /* copy Tx Data */
 963         if (data->cur_trans->tx_buf != NULL) {
 964                 if (*bpw == 8) {
 965                         tx_buf = data->cur_trans->tx_buf;
 966                         tx_dma_buf = dma->tx_buf_virt;
 967                         for (i = 0; i < data->bpw_len; i++)
 968                                 *tx_dma_buf++ = *tx_buf++;
 969                 } else {
 970                         tx_sbuf = data->cur_trans->tx_buf;
 971                         tx_dma_sbuf = dma->tx_buf_virt;
 972                         for (i = 0; i < data->bpw_len; i++)
 973                                 *tx_dma_sbuf++ = *tx_sbuf++;
 974                 }
 975         }
 976
 977         /* Calculate Rx parameter for DMA transmitting */
 978         if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
 979                 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
 980                         num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
 981                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
 982                 } else {
 983                         num = data->bpw_len / PCH_DMA_TRANS_SIZE;
 984                         rem = PCH_DMA_TRANS_SIZE;
 985                 }
 986                 size = PCH_DMA_TRANS_SIZE;
 987         } else {
 988                 num = 1;
 989                 size = data->bpw_len;
 990                 rem = data->bpw_len;
 991         }
 992         dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
 993                 __func__, num, size, rem);
 994         spin_lock_irqsave(&data->lock, flags);
 995
 996         /* set receive fifo threshold and transmit fifo threshold */
 997         pch_spi_setclr_reg(data->master, PCH_SPCR,
 998                            ((size - 1) << SPCR_RFIC_FIELD) |
 999                            (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1000                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1001
1002         spin_unlock_irqrestore(&data->lock, flags);
1003
1004         /* RX */
1005         dma->sg_rx_p = kmalloc_array(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
1006         if (!dma->sg_rx_p)
1007                 return;
1008
1009         sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1010         /* offset, length setting */
1011         sg = dma->sg_rx_p;
1012         for (i = 0; i < num; i++, sg++) {
1013                 if (i == (num - 2)) {
1014                         sg->offset = size * i;
1015                         sg->offset = sg->offset * (*bpw / 8);
1016                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1017                                     sg->offset);
1018                         sg_dma_len(sg) = rem;
1019                 } else if (i == (num - 1)) {
1020                         sg->offset = size * (i - 1) + rem;
1021                         sg->offset = sg->offset * (*bpw / 8);
1022                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1023                                     sg->offset);
1024                         sg_dma_len(sg) = size;
1025                 } else {
1026                         sg->offset = size * i;
1027                         sg->offset = sg->offset * (*bpw / 8);
1028                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1029                                     sg->offset);
1030                         sg_dma_len(sg) = size;
1031                 }
1032                 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1033         }
1034         sg = dma->sg_rx_p;
1035         desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1036                                         num, DMA_DEV_TO_MEM,
1037                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1038         if (!desc_rx) {
1039                 dev_err(&data->master->dev,
1040                         "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1041                 return;
1042         }
1043         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1044         desc_rx->callback = pch_dma_rx_complete;
1045         desc_rx->callback_param = data;
1046         dma->nent = num;
1047         dma->desc_rx = desc_rx;
1048
1049         /* Calculate Tx parameter for DMA transmitting */
1050         if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1051                 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1052                 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1053                         num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1054                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1055                 } else {
1056                         num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1057                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1058                               PCH_DMA_TRANS_SIZE - head;
1059                 }
1060                 size = PCH_DMA_TRANS_SIZE;
1061         } else {
1062                 num = 1;
1063                 size = data->bpw_len;
1064                 rem = data->bpw_len;
1065                 head = 0;
1066         }
1067
1068         dma->sg_tx_p = kmalloc_array(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
1069         if (!dma->sg_tx_p)
1070                 return;
1071
1072         sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1073         /* offset, length setting */
1074         sg = dma->sg_tx_p;
1075         for (i = 0; i < num; i++, sg++) {
1076                 if (i == 0) {
1077                         sg->offset = 0;
1078                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1079                                     sg->offset);
1080                         sg_dma_len(sg) = size + head;
1081                 } else if (i == (num - 1)) {
1082                         sg->offset = head + size * i;
1083                         sg->offset = sg->offset * (*bpw / 8);
1084                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1085                                     sg->offset);
1086                         sg_dma_len(sg) = rem;
1087                 } else {
1088                         sg->offset = head + size * i;
1089                         sg->offset = sg->offset * (*bpw / 8);
1090                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1091                                     sg->offset);
1092                         sg_dma_len(sg) = size;
1093                 }
1094                 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1095         }
1096         sg = dma->sg_tx_p;
1097         desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1098                                         sg, num, DMA_MEM_TO_DEV,
1099                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1100         if (!desc_tx) {
1101                 dev_err(&data->master->dev,
1102                         "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1103                 return;
1104         }
1105         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1106         desc_tx->callback = NULL;
1107         desc_tx->callback_param = data;
1108         dma->nent = num;
1109         dma->desc_tx = desc_tx;
1110
1111         dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1112
1113         spin_lock_irqsave(&data->lock, flags);
1114         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1115         desc_rx->tx_submit(desc_rx);
1116         desc_tx->tx_submit(desc_tx);
1117         spin_unlock_irqrestore(&data->lock, flags);
1118
1119         /* reset transfer complete flag */
1120         data->transfer_complete = false;
1121 }
1122
1123 static void pch_spi_process_messages(struct work_struct *pwork)
1124 {
1125         struct spi_message *pmsg, *tmp;
1126         struct pch_spi_data *data;
1127         int bpw;
1128
1129         data = container_of(pwork, struct pch_spi_data, work);
1130         dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1131
1132         spin_lock(&data->lock);
1133         /* check if suspend has been initiated;if yes flush queue */
1134         if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1135                 dev_dbg(&data->master->dev,
1136                         "%s suspend/remove initiated, flushing queue\n", __func__);
1137                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1138                         pmsg->status = -EIO;
1139
1140                         if (pmsg->complete) {
1141                                 spin_unlock(&data->lock);
1142                                 pmsg->complete(pmsg->context);
1143                                 spin_lock(&data->lock);
1144                         }
1145
1146                         /* delete from queue */
1147                         list_del_init(&pmsg->queue);
1148                 }
1149
1150                 spin_unlock(&data->lock);
1151                 return;
1152         }
1153
1154         data->bcurrent_msg_processing = true;
1155         dev_dbg(&data->master->dev,
1156                 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1157
1158         /* Get the message from the queue and delete it from there. */
1159         data->current_msg = list_entry(data->queue.next, struct spi_message,
1160                                         queue);
1161
1162         list_del_init(&data->current_msg->queue);
1163
1164         data->current_msg->status = 0;
1165
1166         pch_spi_select_chip(data, data->current_msg->spi);
1167
1168         spin_unlock(&data->lock);
1169
1170         if (data->use_dma)
1171                 pch_spi_request_dma(data,
1172                                     data->current_msg->spi->bits_per_word);
1173         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1174         do {
1175                 int cnt;
1176                 /* If we are already processing a message get the next
1177                 transfer structure from the message otherwise retrieve
1178                 the 1st transfer request from the message. */
1179                 spin_lock(&data->lock);
1180                 if (data->cur_trans == NULL) {
1181                         data->cur_trans =
1182                                 list_entry(data->current_msg->transfers.next,
1183                                            struct spi_transfer, transfer_list);
1184                         dev_dbg(&data->master->dev,
1185                                 "%s :Getting 1st transfer message\n",
1186                                 __func__);
1187                 } else {
1188                         data->cur_trans =
1189                                 list_entry(data->cur_trans->transfer_list.next,
1190                                            struct spi_transfer, transfer_list);
1191                         dev_dbg(&data->master->dev,
1192                                 "%s :Getting next transfer message\n",
1193                                 __func__);
1194                 }
1195                 spin_unlock(&data->lock);
1196
1197                 if (!data->cur_trans->len)
1198                         goto out;
1199                 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1200                 data->save_total_len = data->cur_trans->len;
1201                 if (data->use_dma) {
1202                         int i;
1203                         char *save_rx_buf = data->cur_trans->rx_buf;
1204
1205                         for (i = 0; i < cnt; i++) {
1206                                 pch_spi_handle_dma(data, &bpw);
1207                                 if (!pch_spi_start_transfer(data)) {
1208                                         data->transfer_complete = true;
1209                                         data->current_msg->status = -EIO;
1210                                         data->current_msg->complete
1211                                                    (data->current_msg->context);
1212                                         data->bcurrent_msg_processing = false;
1213                                         data->current_msg = NULL;
1214                                         data->cur_trans = NULL;
1215                                         goto out;
1216                                 }
1217                                 pch_spi_copy_rx_data_for_dma(data, bpw);
1218                         }
1219                         data->cur_trans->rx_buf = save_rx_buf;
1220                 } else {
1221                         pch_spi_set_tx(data, &bpw);
1222                         pch_spi_set_ir(data);
1223                         pch_spi_copy_rx_data(data, bpw);
1224                         kfree(data->pkt_rx_buff);
1225                         data->pkt_rx_buff = NULL;
1226                         kfree(data->pkt_tx_buff);
1227                         data->pkt_tx_buff = NULL;
1228                 }
1229                 /* increment message count */
1230                 data->cur_trans->len = data->save_total_len;
1231                 data->current_msg->actual_length += data->cur_trans->len;
1232
1233                 dev_dbg(&data->master->dev,
1234                         "%s:data->current_msg->actual_length=%d\n",
1235                         __func__, data->current_msg->actual_length);
1236
1237                 spi_transfer_delay_exec(data->cur_trans);
1238
1239                 spin_lock(&data->lock);
1240
1241                 /* No more transfer in this message. */
1242                 if ((data->cur_trans->transfer_list.next) ==
1243                     &(data->current_msg->transfers)) {
1244                         pch_spi_nomore_transfer(data);
1245                 }
1246
1247                 spin_unlock(&data->lock);
1248
1249         } while (data->cur_trans != NULL);
1250
1251 out:
1252         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1253         if (data->use_dma)
1254                 pch_spi_release_dma(data);
1255 }
1256
1257 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1258                                    struct pch_spi_data *data)
1259 {
1260         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1261
1262         flush_work(&data->work);
1263 }
1264
1265 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1266                                  struct pch_spi_data *data)
1267 {
1268         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1269
1270         /* reset PCH SPI h/w */
1271         pch_spi_reset(data->master);
1272         dev_dbg(&board_dat->pdev->dev,
1273                 "%s pch_spi_reset invoked successfully\n", __func__);
1274
1275         dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1276
1277         return 0;
1278 }
1279
1280 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1281                              struct pch_spi_data *data)
1282 {
1283         struct pch_spi_dma_ctrl *dma;
1284
1285         dma = &data->dma;
1286         if (dma->tx_buf_dma)
1287                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1288                                   dma->tx_buf_virt, dma->tx_buf_dma);
1289         if (dma->rx_buf_dma)
1290                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1291                                   dma->rx_buf_virt, dma->rx_buf_dma);
1292 }
1293
1294 static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1295                               struct pch_spi_data *data)
1296 {
1297         struct pch_spi_dma_ctrl *dma;
1298         int ret;
1299
1300         dma = &data->dma;
1301         ret = 0;
1302         /* Get Consistent memory for Tx DMA */
1303         dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1304                                 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1305         if (!dma->tx_buf_virt)
1306                 ret = -ENOMEM;
1307
1308         /* Get Consistent memory for Rx DMA */
1309         dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1310                                 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1311         if (!dma->rx_buf_virt)
1312                 ret = -ENOMEM;
1313
1314         return ret;
1315 }
1316
1317 static int pch_spi_pd_probe(struct platform_device *plat_dev)
1318 {
1319         int ret;
1320         struct spi_master *master;
1321         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1322         struct pch_spi_data *data;
1323
1324         dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1325
1326         master = spi_alloc_master(&board_dat->pdev->dev,
1327                                   sizeof(struct pch_spi_data));
1328         if (!master) {
1329                 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1330                         plat_dev->id);
1331                 return -ENOMEM;
1332         }
1333
1334         data = spi_master_get_devdata(master);
1335         data->master = master;
1336
1337         platform_set_drvdata(plat_dev, data);
1338
1339         /* baseaddress + address offset) */
1340         data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1341                                          PCH_ADDRESS_SIZE * plat_dev->id;
1342         data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1343         if (!data->io_remap_addr) {
1344                 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1345                 ret = -ENOMEM;
1346                 goto err_pci_iomap;
1347         }
1348         data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1349
1350         dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1351                 plat_dev->id, data->io_remap_addr);
1352
1353         /* initialize members of SPI master */
1354         master->num_chipselect = PCH_MAX_CS;
1355         master->transfer = pch_spi_transfer;
1356         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1357         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1358         master->max_speed_hz = PCH_MAX_BAUDRATE;
1359
1360         data->board_dat = board_dat;
1361         data->plat_dev = plat_dev;
1362         data->n_curnt_chip = 255;
1363         data->status = STATUS_RUNNING;
1364         data->ch = plat_dev->id;
1365         data->use_dma = use_dma;
1366
1367         INIT_LIST_HEAD(&data->queue);
1368         spin_lock_init(&data->lock);
1369         INIT_WORK(&data->work, pch_spi_process_messages);
1370         init_waitqueue_head(&data->wait);
1371
1372         ret = pch_spi_get_resources(board_dat, data);
1373         if (ret) {
1374                 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1375                 goto err_spi_get_resources;
1376         }
1377
1378         ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1379                           IRQF_SHARED, KBUILD_MODNAME, data);
1380         if (ret) {
1381                 dev_err(&plat_dev->dev,
1382                         "%s request_irq failed\n", __func__);
1383                 goto err_request_irq;
1384         }
1385         data->irq_reg_sts = true;
1386
1387         pch_spi_set_master_mode(master);
1388
1389         if (use_dma) {
1390                 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1391                 ret = pch_alloc_dma_buf(board_dat, data);
1392                 if (ret)
1393                         goto err_spi_register_master;
1394         }
1395
1396         ret = spi_register_master(master);
1397         if (ret != 0) {
1398                 dev_err(&plat_dev->dev,
1399                         "%s spi_register_master FAILED\n", __func__);
1400                 goto err_spi_register_master;
1401         }
1402
1403         return 0;
1404
1405 err_spi_register_master:
1406         pch_free_dma_buf(board_dat, data);
1407         free_irq(board_dat->pdev->irq, data);
1408 err_request_irq:
1409         pch_spi_free_resources(board_dat, data);
1410 err_spi_get_resources:
1411         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1412 err_pci_iomap:
1413         spi_master_put(master);
1414
1415         return ret;
1416 }
1417
1418 static int pch_spi_pd_remove(struct platform_device *plat_dev)
1419 {
1420         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1421         struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1422         int count;
1423         unsigned long flags;
1424
1425         dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1426                 __func__, plat_dev->id, board_dat->pdev->irq);
1427
1428         if (use_dma)
1429                 pch_free_dma_buf(board_dat, data);
1430
1431         /* check for any pending messages; no action is taken if the queue
1432          * is still full; but at least we tried.  Unload anyway */
1433         count = 500;
1434         spin_lock_irqsave(&data->lock, flags);
1435         data->status = STATUS_EXITING;
1436         while ((list_empty(&data->queue) == 0) && --count) {
1437                 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1438                         __func__);
1439                 spin_unlock_irqrestore(&data->lock, flags);
1440                 msleep(PCH_SLEEP_TIME);
1441                 spin_lock_irqsave(&data->lock, flags);
1442         }
1443         spin_unlock_irqrestore(&data->lock, flags);
1444
1445         pch_spi_free_resources(board_dat, data);
1446         /* disable interrupts & free IRQ */
1447         if (data->irq_reg_sts) {
1448                 /* disable interrupts */
1449                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1450                 data->irq_reg_sts = false;
1451                 free_irq(board_dat->pdev->irq, data);
1452         }
1453
1454         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1455         spi_unregister_master(data->master);
1456
1457         return 0;
1458 }
1459 #ifdef CONFIG_PM
1460 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1461                               pm_message_t state)
1462 {
1463         u8 count;
1464         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1465         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1466
1467         dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1468
1469         if (!board_dat) {
1470                 dev_err(&pd_dev->dev,
1471                         "%s pci_get_drvdata returned NULL\n", __func__);
1472                 return -EFAULT;
1473         }
1474
1475         /* check if the current message is processed:
1476            Only after thats done the transfer will be suspended */
1477         count = 255;
1478         while ((--count) > 0) {
1479                 if (!(data->bcurrent_msg_processing))
1480                         break;
1481                 msleep(PCH_SLEEP_TIME);
1482         }
1483
1484         /* Free IRQ */
1485         if (data->irq_reg_sts) {
1486                 /* disable all interrupts */
1487                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1488                 pch_spi_reset(data->master);
1489                 free_irq(board_dat->pdev->irq, data);
1490
1491                 data->irq_reg_sts = false;
1492                 dev_dbg(&pd_dev->dev,
1493                         "%s free_irq invoked successfully.\n", __func__);
1494         }
1495
1496         return 0;
1497 }
1498
1499 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1500 {
1501         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1502         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1503         int retval;
1504
1505         if (!board_dat) {
1506                 dev_err(&pd_dev->dev,
1507                         "%s pci_get_drvdata returned NULL\n", __func__);
1508                 return -EFAULT;
1509         }
1510
1511         if (!data->irq_reg_sts) {
1512                 /* register IRQ */
1513                 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1514                                      IRQF_SHARED, KBUILD_MODNAME, data);
1515                 if (retval < 0) {
1516                         dev_err(&pd_dev->dev,
1517                                 "%s request_irq failed\n", __func__);
1518                         return retval;
1519                 }
1520
1521                 /* reset PCH SPI h/w */
1522                 pch_spi_reset(data->master);
1523                 pch_spi_set_master_mode(data->master);
1524                 data->irq_reg_sts = true;
1525         }
1526         return 0;
1527 }
1528 #else
1529 #define pch_spi_pd_suspend NULL
1530 #define pch_spi_pd_resume NULL
1531 #endif
1532
1533 static struct platform_driver pch_spi_pd_driver = {
1534         .driver = {
1535                 .name = "pch-spi",
1536         },
1537         .probe = pch_spi_pd_probe,
1538         .remove = pch_spi_pd_remove,
1539         .suspend = pch_spi_pd_suspend,
1540         .resume = pch_spi_pd_resume
1541 };
1542
1543 static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1544 {
1545         struct pch_spi_board_data *board_dat;
1546         struct platform_device *pd_dev = NULL;
1547         int retval;
1548         int i;
1549         struct pch_pd_dev_save *pd_dev_save;
1550
1551         pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL);
1552         if (!pd_dev_save)
1553                 return -ENOMEM;
1554
1555         board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL);
1556         if (!board_dat) {
1557                 retval = -ENOMEM;
1558                 goto err_no_mem;
1559         }
1560
1561         retval = pci_request_regions(pdev, KBUILD_MODNAME);
1562         if (retval) {
1563                 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1564                 goto pci_request_regions;
1565         }
1566
1567         board_dat->pdev = pdev;
1568         board_dat->num = id->driver_data;
1569         pd_dev_save->num = id->driver_data;
1570         pd_dev_save->board_dat = board_dat;
1571
1572         retval = pci_enable_device(pdev);
1573         if (retval) {
1574                 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1575                 goto pci_enable_device;
1576         }
1577
1578         for (i = 0; i < board_dat->num; i++) {
1579                 pd_dev = platform_device_alloc("pch-spi", i);
1580                 if (!pd_dev) {
1581                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
1582                         retval = -ENOMEM;
1583                         goto err_platform_device;
1584                 }
1585                 pd_dev_save->pd_save[i] = pd_dev;
1586                 pd_dev->dev.parent = &pdev->dev;
1587
1588                 retval = platform_device_add_data(pd_dev, board_dat,
1589                                                   sizeof(*board_dat));
1590                 if (retval) {
1591                         dev_err(&pdev->dev,
1592                                 "platform_device_add_data failed\n");
1593                         platform_device_put(pd_dev);
1594                         goto err_platform_device;
1595                 }
1596
1597                 retval = platform_device_add(pd_dev);
1598                 if (retval) {
1599                         dev_err(&pdev->dev, "platform_device_add failed\n");
1600                         platform_device_put(pd_dev);
1601                         goto err_platform_device;
1602                 }
1603         }
1604
1605         pci_set_drvdata(pdev, pd_dev_save);
1606
1607         return 0;
1608
1609 err_platform_device:
1610         while (--i >= 0)
1611                 platform_device_unregister(pd_dev_save->pd_save[i]);
1612         pci_disable_device(pdev);
1613 pci_enable_device:
1614         pci_release_regions(pdev);
1615 pci_request_regions:
1616         kfree(board_dat);
1617 err_no_mem:
1618         kfree(pd_dev_save);
1619
1620         return retval;
1621 }
1622
1623 static void pch_spi_remove(struct pci_dev *pdev)
1624 {
1625         int i;
1626         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1627
1628         dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1629
1630         for (i = 0; i < pd_dev_save->num; i++)
1631                 platform_device_unregister(pd_dev_save->pd_save[i]);
1632
1633         pci_disable_device(pdev);
1634         pci_release_regions(pdev);
1635         kfree(pd_dev_save->board_dat);
1636         kfree(pd_dev_save);
1637 }
1638
1639 static int __maybe_unused pch_spi_suspend(struct device *dev)
1640 {
1641         struct pch_pd_dev_save *pd_dev_save = dev_get_drvdata(dev);
1642
1643         dev_dbg(dev, "%s ENTRY\n", __func__);
1644
1645         pd_dev_save->board_dat->suspend_sts = true;
1646
1647         return 0;
1648 }
1649
1650 static int __maybe_unused pch_spi_resume(struct device *dev)
1651 {
1652         struct pch_pd_dev_save *pd_dev_save = dev_get_drvdata(dev);
1653
1654         dev_dbg(dev, "%s ENTRY\n", __func__);
1655
1656         /* set suspend status to false */
1657         pd_dev_save->board_dat->suspend_sts = false;
1658
1659         return 0;
1660 }
1661
1662 static SIMPLE_DEV_PM_OPS(pch_spi_pm_ops, pch_spi_suspend, pch_spi_resume);
1663
1664 static struct pci_driver pch_spi_pcidev_driver = {
1665         .name = "pch_spi",
1666         .id_table = pch_spi_pcidev_id,
1667         .probe = pch_spi_probe,
1668         .remove = pch_spi_remove,
1669         .driver.pm = &pch_spi_pm_ops,
1670 };
1671
1672 static int __init pch_spi_init(void)
1673 {
1674         int ret;
1675         ret = platform_driver_register(&pch_spi_pd_driver);
1676         if (ret)
1677                 return ret;
1678
1679         ret = pci_register_driver(&pch_spi_pcidev_driver);
1680         if (ret) {
1681                 platform_driver_unregister(&pch_spi_pd_driver);
1682                 return ret;
1683         }
1684
1685         return 0;
1686 }
1687 module_init(pch_spi_init);
1688
1689 static void __exit pch_spi_exit(void)
1690 {
1691         pci_unregister_driver(&pch_spi_pcidev_driver);
1692         platform_driver_unregister(&pch_spi_pd_driver);
1693 }
1694 module_exit(pch_spi_exit);
1695
1696 module_param(use_dma, int, 0644);
1697 MODULE_PARM_DESC(use_dma,
1698                  "to use DMA for data transfers pass 1 else 0; default 1");
1699
1700 MODULE_LICENSE("GPL");
1701 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1702 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1703