drivers/spi/spi-stm32-qspi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/errno.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/reset.h>
  22 #include <linux/sizes.h>
  23 #include <linux/spi/spi-mem.h>
  24
  25 #define QSPI_CR                 0x00
  26 #define CR_EN                   BIT(0)
  27 #define CR_ABORT                BIT(1)
  28 #define CR_DMAEN                BIT(2)
  29 #define CR_TCEN                 BIT(3)
  30 #define CR_SSHIFT               BIT(4)
  31 #define CR_DFM                  BIT(6)
  32 #define CR_FSEL                 BIT(7)
  33 #define CR_FTHRES_SHIFT         8
  34 #define CR_TEIE                 BIT(16)
  35 #define CR_TCIE                 BIT(17)
  36 #define CR_FTIE                 BIT(18)
  37 #define CR_SMIE                 BIT(19)
  38 #define CR_TOIE                 BIT(20)
  39 #define CR_APMS                 BIT(22)
  40 #define CR_PRESC_MASK           GENMASK(31, 24)
  41
  42 #define QSPI_DCR                0x04
  43 #define DCR_FSIZE_MASK          GENMASK(20, 16)
  44
  45 #define QSPI_SR                 0x08
  46 #define SR_TEF                  BIT(0)
  47 #define SR_TCF                  BIT(1)
  48 #define SR_FTF                  BIT(2)
  49 #define SR_SMF                  BIT(3)
  50 #define SR_TOF                  BIT(4)
  51 #define SR_BUSY                 BIT(5)
  52 #define SR_FLEVEL_MASK          GENMASK(13, 8)
  53
  54 #define QSPI_FCR                0x0c
  55 #define FCR_CTEF                BIT(0)
  56 #define FCR_CTCF                BIT(1)
  57 #define FCR_CSMF                BIT(3)
  58
  59 #define QSPI_DLR                0x10
  60
  61 #define QSPI_CCR                0x14
  62 #define CCR_INST_MASK           GENMASK(7, 0)
  63 #define CCR_IMODE_MASK          GENMASK(9, 8)
  64 #define CCR_ADMODE_MASK         GENMASK(11, 10)
  65 #define CCR_ADSIZE_MASK         GENMASK(13, 12)
  66 #define CCR_DCYC_MASK           GENMASK(22, 18)
  67 #define CCR_DMODE_MASK          GENMASK(25, 24)
  68 #define CCR_FMODE_MASK          GENMASK(27, 26)
  69 #define CCR_FMODE_INDW          (0U << 26)
  70 #define CCR_FMODE_INDR          (1U << 26)
  71 #define CCR_FMODE_APM           (2U << 26)
  72 #define CCR_FMODE_MM            (3U << 26)
  73 #define CCR_BUSWIDTH_0          0x0
  74 #define CCR_BUSWIDTH_1          0x1
  75 #define CCR_BUSWIDTH_2          0x2
  76 #define CCR_BUSWIDTH_4          0x3
  77
  78 #define QSPI_AR                 0x18
  79 #define QSPI_ABR                0x1c
  80 #define QSPI_DR                 0x20
  81 #define QSPI_PSMKR              0x24
  82 #define QSPI_PSMAR              0x28
  83 #define QSPI_PIR                0x2c
  84 #define QSPI_LPTR               0x30
  85
  86 #define STM32_QSPI_MAX_MMAP_SZ  SZ_256M
  87 #define STM32_QSPI_MAX_NORCHIP  2
  88
  89 #define STM32_FIFO_TIMEOUT_US 30000
  90 #define STM32_BUSY_TIMEOUT_US 100000
  91 #define STM32_ABT_TIMEOUT_US 100000
  92 #define STM32_COMP_TIMEOUT_MS 1000
  93 #define STM32_AUTOSUSPEND_DELAY -1
  94
  95 struct stm32_qspi_flash {
  96         u32 cs;
  97         u32 presc;
  98 };
  99
 100 struct stm32_qspi {
 101         struct device *dev;
 102         struct spi_controller *ctrl;
 103         phys_addr_t phys_base;
 104         void __iomem *io_base;
 105         void __iomem *mm_base;
 106         resource_size_t mm_size;
 107         struct clk *clk;
 108         u32 clk_rate;
 109         struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
 110         struct completion data_completion;
 111         struct completion match_completion;
 112         u32 fmode;
 113
 114         struct dma_chan *dma_chtx;
 115         struct dma_chan *dma_chrx;
 116         struct completion dma_completion;
 117
 118         u32 cr_reg;
 119         u32 dcr_reg;
 120         unsigned long status_timeout;
 121
 122         /*
 123          * to protect device configuration, could be different between
 124          * 2 flash access (bk1, bk2)
 125          */
 126         struct mutex lock;
 127 };
 128
 129 static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
 130 {
 131         struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
 132         u32 cr, sr;
 133
 134         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 135         sr = readl_relaxed(qspi->io_base + QSPI_SR);
 136
 137         if (cr & CR_SMIE && sr & SR_SMF) {
 138                 /* disable irq */
 139                 cr &= ~CR_SMIE;
 140                 writel_relaxed(cr, qspi->io_base + QSPI_CR);
 141                 complete(&qspi->match_completion);
 142
 143                 return IRQ_HANDLED;
 144         }
 145
 146         if (sr & (SR_TEF | SR_TCF)) {
 147                 /* disable irq */
 148                 cr &= ~CR_TCIE & ~CR_TEIE;
 149                 writel_relaxed(cr, qspi->io_base + QSPI_CR);
 150                 complete(&qspi->data_completion);
 151         }
 152
 153         return IRQ_HANDLED;
 154 }
 155
 156 static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
 157 {
 158         *val = readb_relaxed(addr);
 159 }
 160
 161 static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
 162 {
 163         writeb_relaxed(*val, addr);
 164 }
 165
 166 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
 167                               const struct spi_mem_op *op)
 168 {
 169         void (*tx_fifo)(u8 *val, void __iomem *addr);
 170         u32 len = op->data.nbytes, sr;
 171         u8 *buf;
 172         int ret;
 173
 174         if (op->data.dir == SPI_MEM_DATA_IN) {
 175                 tx_fifo = stm32_qspi_read_fifo;
 176                 buf = op->data.buf.in;
 177
 178         } else {
 179                 tx_fifo = stm32_qspi_write_fifo;
 180                 buf = (u8 *)op->data.buf.out;
 181         }
 182
 183         while (len--) {
 184                 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
 185                                                         sr, (sr & SR_FTF), 1,
 186                                                         STM32_FIFO_TIMEOUT_US);
 187                 if (ret) {
 188                         dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
 189                                 len, sr);
 190                         return ret;
 191                 }
 192                 tx_fifo(buf++, qspi->io_base + QSPI_DR);
 193         }
 194
 195         return 0;
 196 }
 197
 198 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
 199                             const struct spi_mem_op *op)
 200 {
 201         memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
 202                       op->data.nbytes);
 203         return 0;
 204 }
 205
 206 static void stm32_qspi_dma_callback(void *arg)
 207 {
 208         struct completion *dma_completion = arg;
 209
 210         complete(dma_completion);
 211 }
 212
 213 static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
 214                              const struct spi_mem_op *op)
 215 {
 216         struct dma_async_tx_descriptor *desc;
 217         enum dma_transfer_direction dma_dir;
 218         struct dma_chan *dma_ch;
 219         struct sg_table sgt;
 220         dma_cookie_t cookie;
 221         u32 cr, t_out;
 222         int err;
 223
 224         if (op->data.dir == SPI_MEM_DATA_IN) {
 225                 dma_dir = DMA_DEV_TO_MEM;
 226                 dma_ch = qspi->dma_chrx;
 227         } else {
 228                 dma_dir = DMA_MEM_TO_DEV;
 229                 dma_ch = qspi->dma_chtx;
 230         }
 231
 232         /*
 233          * spi_map_buf return -EINVAL if the buffer is not DMA-able
 234          * (DMA-able: in vmalloc | kmap | virt_addr_valid)
 235          */
 236         err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
 237         if (err)
 238                 return err;
 239
 240         desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
 241                                        dma_dir, DMA_PREP_INTERRUPT);
 242         if (!desc) {
 243                 err = -ENOMEM;
 244                 goto out_unmap;
 245         }
 246
 247         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 248
 249         reinit_completion(&qspi->dma_completion);
 250         desc->callback = stm32_qspi_dma_callback;
 251         desc->callback_param = &qspi->dma_completion;
 252         cookie = dmaengine_submit(desc);
 253         err = dma_submit_error(cookie);
 254         if (err)
 255                 goto out;
 256
 257         dma_async_issue_pending(dma_ch);
 258
 259         writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
 260
 261         t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
 262         if (!wait_for_completion_timeout(&qspi->dma_completion,
 263                                          msecs_to_jiffies(t_out)))
 264                 err = -ETIMEDOUT;
 265
 266         if (err)
 267                 dmaengine_terminate_all(dma_ch);
 268
 269 out:
 270         writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
 271 out_unmap:
 272         spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
 273
 274         return err;
 275 }
 276
 277 static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
 278 {
 279         if (!op->data.nbytes)
 280                 return 0;
 281
 282         if (qspi->fmode == CCR_FMODE_MM)
 283                 return stm32_qspi_tx_mm(qspi, op);
 284         else if (((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
 285                  (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx)) &&
 286                   op->data.nbytes > 4)
 287                 if (!stm32_qspi_tx_dma(qspi, op))
 288                         return 0;
 289
 290         return stm32_qspi_tx_poll(qspi, op);
 291 }
 292
 293 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
 294 {
 295         u32 sr;
 296
 297         return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
 298                                                  !(sr & SR_BUSY), 1,
 299                                                  STM32_BUSY_TIMEOUT_US);
 300 }
 301
 302 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
 303                                const struct spi_mem_op *op)
 304 {
 305         u32 cr, sr;
 306         int err = 0;
 307
 308         if (!op->data.nbytes)
 309                 goto wait_nobusy;
 310
 311         if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
 312                 goto out;
 313
 314         reinit_completion(&qspi->data_completion);
 315         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 316         writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
 317
 318         if (!wait_for_completion_timeout(&qspi->data_completion,
 319                                 msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
 320                 err = -ETIMEDOUT;
 321         } else {
 322                 sr = readl_relaxed(qspi->io_base + QSPI_SR);
 323                 if (sr & SR_TEF)
 324                         err = -EIO;
 325         }
 326
 327 out:
 328         /* clear flags */
 329         writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
 330 wait_nobusy:
 331         if (!err)
 332                 err = stm32_qspi_wait_nobusy(qspi);
 333
 334         return err;
 335 }
 336
 337 static int stm32_qspi_wait_poll_status(struct stm32_qspi *qspi,
 338                                        const struct spi_mem_op *op)
 339 {
 340         u32 cr;
 341
 342         reinit_completion(&qspi->match_completion);
 343         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 344         writel_relaxed(cr | CR_SMIE, qspi->io_base + QSPI_CR);
 345
 346         if (!wait_for_completion_timeout(&qspi->match_completion,
 347                                 msecs_to_jiffies(qspi->status_timeout)))
 348                 return -ETIMEDOUT;
 349
 350         writel_relaxed(FCR_CSMF, qspi->io_base + QSPI_FCR);
 351
 352         return 0;
 353 }
 354
 355 static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
 356 {
 357         if (buswidth == 4)
 358                 return CCR_BUSWIDTH_4;
 359
 360         return buswidth;
 361 }
 362
 363 static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
 364 {
 365         struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
 366         struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
 367         u32 ccr, cr;
 368         int timeout, err = 0, err_poll_status = 0;
 369
 370         dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
 371                 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
 372                 op->dummy.buswidth, op->data.buswidth,
 373                 op->addr.val, op->data.nbytes);
 374
 375         err = stm32_qspi_wait_nobusy(qspi);
 376         if (err)
 377                 goto abort;
 378
 379         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 380         cr &= ~CR_PRESC_MASK & ~CR_FSEL;
 381         cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
 382         cr |= FIELD_PREP(CR_FSEL, flash->cs);
 383         writel_relaxed(cr, qspi->io_base + QSPI_CR);
 384
 385         if (op->data.nbytes)
 386                 writel_relaxed(op->data.nbytes - 1,
 387                                qspi->io_base + QSPI_DLR);
 388
 389         ccr = qspi->fmode;
 390         ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
 391         ccr |= FIELD_PREP(CCR_IMODE_MASK,
 392                           stm32_qspi_get_mode(qspi, op->cmd.buswidth));
 393
 394         if (op->addr.nbytes) {
 395                 ccr |= FIELD_PREP(CCR_ADMODE_MASK,
 396                                   stm32_qspi_get_mode(qspi, op->addr.buswidth));
 397                 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
 398         }
 399
 400         if (op->dummy.buswidth && op->dummy.nbytes)
 401                 ccr |= FIELD_PREP(CCR_DCYC_MASK,
 402                                   op->dummy.nbytes * 8 / op->dummy.buswidth);
 403
 404         if (op->data.nbytes) {
 405                 ccr |= FIELD_PREP(CCR_DMODE_MASK,
 406                                   stm32_qspi_get_mode(qspi, op->data.buswidth));
 407         }
 408
 409         writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
 410
 411         if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
 412                 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
 413
 414         if (qspi->fmode == CCR_FMODE_APM)
 415                 err_poll_status = stm32_qspi_wait_poll_status(qspi, op);
 416
 417         err = stm32_qspi_tx(qspi, op);
 418
 419         /*
 420          * Abort in:
 421          * -error case
 422          * -read memory map: prefetching must be stopped if we read the last
 423          *  byte of device (device size - fifo size). like device size is not
 424          *  knows, the prefetching is always stop.
 425          */
 426         if (err || err_poll_status || qspi->fmode == CCR_FMODE_MM)
 427                 goto abort;
 428
 429         /* wait end of tx in indirect mode */
 430         err = stm32_qspi_wait_cmd(qspi, op);
 431         if (err)
 432                 goto abort;
 433
 434         return 0;
 435
 436 abort:
 437         cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
 438         writel_relaxed(cr, qspi->io_base + QSPI_CR);
 439
 440         /* wait clear of abort bit by hw */
 441         timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
 442                                                     cr, !(cr & CR_ABORT), 1,
 443                                                     STM32_ABT_TIMEOUT_US);
 444
 445         writel_relaxed(FCR_CTCF | FCR_CSMF, qspi->io_base + QSPI_FCR);
 446
 447         if (err || err_poll_status || timeout)
 448                 dev_err(qspi->dev, "%s err:%d err_poll_status:%d abort timeout:%d\n",
 449                         __func__, err, err_poll_status, timeout);
 450
 451         return err;
 452 }
 453
 454 static int stm32_qspi_poll_status(struct spi_mem *mem, const struct spi_mem_op *op,
 455                                   u16 mask, u16 match,
 456                                   unsigned long initial_delay_us,
 457                                   unsigned long polling_rate_us,
 458                                   unsigned long timeout_ms)
 459 {
 460         struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
 461         int ret;
 462
 463         if (!spi_mem_supports_op(mem, op))
 464                 return -EOPNOTSUPP;
 465
 466         ret = pm_runtime_get_sync(qspi->dev);
 467         if (ret < 0) {
 468                 pm_runtime_put_noidle(qspi->dev);
 469                 return ret;
 470         }
 471
 472         mutex_lock(&qspi->lock);
 473
 474         writel_relaxed(mask, qspi->io_base + QSPI_PSMKR);
 475         writel_relaxed(match, qspi->io_base + QSPI_PSMAR);
 476         qspi->fmode = CCR_FMODE_APM;
 477         qspi->status_timeout = timeout_ms;
 478
 479         ret = stm32_qspi_send(mem, op);
 480         mutex_unlock(&qspi->lock);
 481
 482         pm_runtime_mark_last_busy(qspi->dev);
 483         pm_runtime_put_autosuspend(qspi->dev);
 484
 485         return ret;
 486 }
 487
 488 static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 489 {
 490         struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
 491         int ret;
 492
 493         ret = pm_runtime_get_sync(qspi->dev);
 494         if (ret < 0) {
 495                 pm_runtime_put_noidle(qspi->dev);
 496                 return ret;
 497         }
 498
 499         mutex_lock(&qspi->lock);
 500         if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes)
 501                 qspi->fmode = CCR_FMODE_INDR;
 502         else
 503                 qspi->fmode = CCR_FMODE_INDW;
 504
 505         ret = stm32_qspi_send(mem, op);
 506         mutex_unlock(&qspi->lock);
 507
 508         pm_runtime_mark_last_busy(qspi->dev);
 509         pm_runtime_put_autosuspend(qspi->dev);
 510
 511         return ret;
 512 }
 513
 514 static int stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc)
 515 {
 516         struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->master);
 517
 518         if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
 519                 return -EOPNOTSUPP;
 520
 521         /* should never happen, as mm_base == null is an error probe exit condition */
 522         if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
 523                 return -EOPNOTSUPP;
 524
 525         if (!qspi->mm_size)
 526                 return -EOPNOTSUPP;
 527
 528         return 0;
 529 }
 530
 531 static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc,
 532                                       u64 offs, size_t len, void *buf)
 533 {
 534         struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->master);
 535         struct spi_mem_op op;
 536         u32 addr_max;
 537         int ret;
 538
 539         ret = pm_runtime_get_sync(qspi->dev);
 540         if (ret < 0) {
 541                 pm_runtime_put_noidle(qspi->dev);
 542                 return ret;
 543         }
 544
 545         mutex_lock(&qspi->lock);
 546         /* make a local copy of desc op_tmpl and complete dirmap rdesc
 547          * spi_mem_op template with offs, len and *buf in  order to get
 548          * all needed transfer information into struct spi_mem_op
 549          */
 550         memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
 551         dev_dbg(qspi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
 552
 553         op.data.nbytes = len;
 554         op.addr.val = desc->info.offset + offs;
 555         op.data.buf.in = buf;
 556
 557         addr_max = op.addr.val + op.data.nbytes + 1;
 558         if (addr_max < qspi->mm_size && op.addr.buswidth)
 559                 qspi->fmode = CCR_FMODE_MM;
 560         else
 561                 qspi->fmode = CCR_FMODE_INDR;
 562
 563         ret = stm32_qspi_send(desc->mem, &op);
 564         mutex_unlock(&qspi->lock);
 565
 566         pm_runtime_mark_last_busy(qspi->dev);
 567         pm_runtime_put_autosuspend(qspi->dev);
 568
 569         return ret ?: len;
 570 }
 571
 572 static int stm32_qspi_setup(struct spi_device *spi)
 573 {
 574         struct spi_controller *ctrl = spi->master;
 575         struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
 576         struct stm32_qspi_flash *flash;
 577         u32 presc;
 578         int ret;
 579
 580         if (ctrl->busy)
 581                 return -EBUSY;
 582
 583         if (!spi->max_speed_hz)
 584                 return -EINVAL;
 585
 586         ret = pm_runtime_get_sync(qspi->dev);
 587         if (ret < 0) {
 588                 pm_runtime_put_noidle(qspi->dev);
 589                 return ret;
 590         }
 591
 592         presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
 593
 594         flash = &qspi->flash[spi->chip_select];
 595         flash->cs = spi->chip_select;
 596         flash->presc = presc;
 597
 598         mutex_lock(&qspi->lock);
 599         qspi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
 600         writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
 601
 602         /* set dcr fsize to max address */
 603         qspi->dcr_reg = DCR_FSIZE_MASK;
 604         writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
 605         mutex_unlock(&qspi->lock);
 606
 607         pm_runtime_mark_last_busy(qspi->dev);
 608         pm_runtime_put_autosuspend(qspi->dev);
 609
 610         return 0;
 611 }
 612
 613 static int stm32_qspi_dma_setup(struct stm32_qspi *qspi)
 614 {
 615         struct dma_slave_config dma_cfg;
 616         struct device *dev = qspi->dev;
 617         int ret = 0;
 618
 619         memset(&dma_cfg, 0, sizeof(dma_cfg));
 620
 621         dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 622         dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 623         dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
 624         dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
 625         dma_cfg.src_maxburst = 4;
 626         dma_cfg.dst_maxburst = 4;
 627
 628         qspi->dma_chrx = dma_request_chan(dev, "rx");
 629         if (IS_ERR(qspi->dma_chrx)) {
 630                 ret = PTR_ERR(qspi->dma_chrx);
 631                 qspi->dma_chrx = NULL;
 632                 if (ret == -EPROBE_DEFER)
 633                         goto out;
 634         } else {
 635                 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
 636                         dev_err(dev, "dma rx config failed\n");
 637                         dma_release_channel(qspi->dma_chrx);
 638                         qspi->dma_chrx = NULL;
 639                 }
 640         }
 641
 642         qspi->dma_chtx = dma_request_chan(dev, "tx");
 643         if (IS_ERR(qspi->dma_chtx)) {
 644                 ret = PTR_ERR(qspi->dma_chtx);
 645                 qspi->dma_chtx = NULL;
 646         } else {
 647                 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
 648                         dev_err(dev, "dma tx config failed\n");
 649                         dma_release_channel(qspi->dma_chtx);
 650                         qspi->dma_chtx = NULL;
 651                 }
 652         }
 653
 654 out:
 655         init_completion(&qspi->dma_completion);
 656
 657         if (ret != -EPROBE_DEFER)
 658                 ret = 0;
 659
 660         return ret;
 661 }
 662
 663 static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
 664 {
 665         if (qspi->dma_chtx)
 666                 dma_release_channel(qspi->dma_chtx);
 667         if (qspi->dma_chrx)
 668                 dma_release_channel(qspi->dma_chrx);
 669 }
 670
 671 /*
 672  * no special host constraint, so use default spi_mem_default_supports_op
 673  * to check supported mode.
 674  */
 675 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
 676         .exec_op        = stm32_qspi_exec_op,
 677         .dirmap_create  = stm32_qspi_dirmap_create,
 678         .dirmap_read    = stm32_qspi_dirmap_read,
 679         .poll_status    = stm32_qspi_poll_status,
 680 };
 681
 682 static int stm32_qspi_probe(struct platform_device *pdev)
 683 {
 684         struct device *dev = &pdev->dev;
 685         struct spi_controller *ctrl;
 686         struct reset_control *rstc;
 687         struct stm32_qspi *qspi;
 688         struct resource *res;
 689         int ret, irq;
 690
 691         ctrl = spi_alloc_master(dev, sizeof(*qspi));
 692         if (!ctrl)
 693                 return -ENOMEM;
 694
 695         qspi = spi_controller_get_devdata(ctrl);
 696         qspi->ctrl = ctrl;
 697
 698         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
 699         qspi->io_base = devm_ioremap_resource(dev, res);
 700         if (IS_ERR(qspi->io_base)) {
 701                 ret = PTR_ERR(qspi->io_base);
 702                 goto err_master_put;
 703         }
 704
 705         qspi->phys_base = res->start;
 706
 707         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
 708         qspi->mm_base = devm_ioremap_resource(dev, res);
 709         if (IS_ERR(qspi->mm_base)) {
 710                 ret = PTR_ERR(qspi->mm_base);
 711                 goto err_master_put;
 712         }
 713
 714         qspi->mm_size = resource_size(res);
 715         if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) {
 716                 ret = -EINVAL;
 717                 goto err_master_put;
 718         }
 719
 720         irq = platform_get_irq(pdev, 0);
 721         if (irq < 0) {
 722                 ret = irq;
 723                 goto err_master_put;
 724         }
 725
 726         ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
 727                                dev_name(dev), qspi);
 728         if (ret) {
 729                 dev_err(dev, "failed to request irq\n");
 730                 goto err_master_put;
 731         }
 732
 733         init_completion(&qspi->data_completion);
 734         init_completion(&qspi->match_completion);
 735
 736         qspi->clk = devm_clk_get(dev, NULL);
 737         if (IS_ERR(qspi->clk)) {
 738                 ret = PTR_ERR(qspi->clk);
 739                 goto err_master_put;
 740         }
 741
 742         qspi->clk_rate = clk_get_rate(qspi->clk);
 743         if (!qspi->clk_rate) {
 744                 ret = -EINVAL;
 745                 goto err_master_put;
 746         }
 747
 748         ret = clk_prepare_enable(qspi->clk);
 749         if (ret) {
 750                 dev_err(dev, "can not enable the clock\n");
 751                 goto err_master_put;
 752         }
 753
 754         rstc = devm_reset_control_get_exclusive(dev, NULL);
 755         if (IS_ERR(rstc)) {
 756                 ret = PTR_ERR(rstc);
 757                 if (ret == -EPROBE_DEFER)
 758                         goto err_clk_disable;
 759         } else {
 760                 reset_control_assert(rstc);
 761                 udelay(2);
 762                 reset_control_deassert(rstc);
 763         }
 764
 765         qspi->dev = dev;
 766         platform_set_drvdata(pdev, qspi);
 767         ret = stm32_qspi_dma_setup(qspi);
 768         if (ret)
 769                 goto err_dma_free;
 770
 771         mutex_init(&qspi->lock);
 772
 773         ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
 774                 | SPI_TX_DUAL | SPI_TX_QUAD;
 775         ctrl->setup = stm32_qspi_setup;
 776         ctrl->bus_num = -1;
 777         ctrl->mem_ops = &stm32_qspi_mem_ops;
 778         ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
 779         ctrl->dev.of_node = dev->of_node;
 780
 781         pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY);
 782         pm_runtime_use_autosuspend(dev);
 783         pm_runtime_set_active(dev);
 784         pm_runtime_enable(dev);
 785         pm_runtime_get_noresume(dev);
 786
 787         ret = devm_spi_register_master(dev, ctrl);
 788         if (ret)
 789                 goto err_pm_runtime_free;
 790
 791         pm_runtime_mark_last_busy(dev);
 792         pm_runtime_put_autosuspend(dev);
 793
 794         return 0;
 795
 796 err_pm_runtime_free:
 797         pm_runtime_get_sync(qspi->dev);
 798         /* disable qspi */
 799         writel_relaxed(0, qspi->io_base + QSPI_CR);
 800         mutex_destroy(&qspi->lock);
 801         pm_runtime_put_noidle(qspi->dev);
 802         pm_runtime_disable(qspi->dev);
 803         pm_runtime_set_suspended(qspi->dev);
 804         pm_runtime_dont_use_autosuspend(qspi->dev);
 805 err_dma_free:
 806         stm32_qspi_dma_free(qspi);
 807 err_clk_disable:
 808         clk_disable_unprepare(qspi->clk);
 809 err_master_put:
 810         spi_master_put(qspi->ctrl);
 811
 812         return ret;
 813 }
 814
 815 static int stm32_qspi_remove(struct platform_device *pdev)
 816 {
 817         struct stm32_qspi *qspi = platform_get_drvdata(pdev);
 818
 819         pm_runtime_get_sync(qspi->dev);
 820         /* disable qspi */
 821         writel_relaxed(0, qspi->io_base + QSPI_CR);
 822         stm32_qspi_dma_free(qspi);
 823         mutex_destroy(&qspi->lock);
 824         pm_runtime_put_noidle(qspi->dev);
 825         pm_runtime_disable(qspi->dev);
 826         pm_runtime_set_suspended(qspi->dev);
 827         pm_runtime_dont_use_autosuspend(qspi->dev);
 828         clk_disable_unprepare(qspi->clk);
 829
 830         return 0;
 831 }
 832
 833 static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev)
 834 {
 835         struct stm32_qspi *qspi = dev_get_drvdata(dev);
 836
 837         clk_disable_unprepare(qspi->clk);
 838
 839         return 0;
 840 }
 841
 842 static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev)
 843 {
 844         struct stm32_qspi *qspi = dev_get_drvdata(dev);
 845
 846         return clk_prepare_enable(qspi->clk);
 847 }
 848
 849 static int __maybe_unused stm32_qspi_suspend(struct device *dev)
 850 {
 851         pinctrl_pm_select_sleep_state(dev);
 852
 853         return pm_runtime_force_suspend(dev);
 854 }
 855
 856 static int __maybe_unused stm32_qspi_resume(struct device *dev)
 857 {
 858         struct stm32_qspi *qspi = dev_get_drvdata(dev);
 859         int ret;
 860
 861         ret = pm_runtime_force_resume(dev);
 862         if (ret < 0)
 863                 return ret;
 864
 865         pinctrl_pm_select_default_state(dev);
 866
 867         ret = pm_runtime_get_sync(dev);
 868         if (ret < 0) {
 869                 pm_runtime_put_noidle(dev);
 870                 return ret;
 871         }
 872
 873         writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
 874         writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
 875
 876         pm_runtime_mark_last_busy(dev);
 877         pm_runtime_put_autosuspend(dev);
 878
 879         return 0;
 880 }
 881
 882 static const struct dev_pm_ops stm32_qspi_pm_ops = {
 883         SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend,
 884                            stm32_qspi_runtime_resume, NULL)
 885         SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume)
 886 };
 887
 888 static const struct of_device_id stm32_qspi_match[] = {
 889         {.compatible = "st,stm32f469-qspi"},
 890         {}
 891 };
 892 MODULE_DEVICE_TABLE(of, stm32_qspi_match);
 893
 894 static struct platform_driver stm32_qspi_driver = {
 895         .probe  = stm32_qspi_probe,
 896         .remove = stm32_qspi_remove,
 897         .driver = {
 898                 .name = "stm32-qspi",
 899                 .of_match_table = stm32_qspi_match,
 900                 .pm = &stm32_qspi_pm_ops,
 901         },
 902 };
 903 module_platform_driver(stm32_qspi_driver);
 904
 905 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
 906 MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
 907 MODULE_LICENSE("GPL v2");