drivers/spi/spi-fsl-spi.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Freescale SPI controller driver.
   4  *
   5  * Maintainer: Kumar Gala
   6  *
   7  * Copyright (C) 2006 Polycom, Inc.
   8  * Copyright 2010 Freescale Semiconductor, Inc.
   9  *
  10  * CPM SPI and QE buffer descriptors mode support:
  11  * Copyright (c) 2009  MontaVista Software, Inc.
  12  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  13  *
  14  * GRLIB support:
  15  * Copyright (c) 2012 Aeroflex Gaisler AB.
  16  * Author: Andreas Larsson <andreas@gaisler.com>
  17  */
  18 #include <linux/delay.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/fsl_devices.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/spi/spi.h>
  34 #include <linux/spi/spi_bitbang.h>
  35 #include <linux/types.h>
  36
  37 #ifdef CONFIG_FSL_SOC
  38 #include <sysdev/fsl_soc.h>
  39 #endif
  40
  41 /* Specific to the MPC8306/MPC8309 */
  42 #define IMMR_SPI_CS_OFFSET 0x14c
  43 #define SPI_BOOT_SEL_BIT   0x80000000
  44
  45 #include "spi-fsl-lib.h"
  46 #include "spi-fsl-cpm.h"
  47 #include "spi-fsl-spi.h"
  48
  49 #define TYPE_FSL        0
  50 #define TYPE_GRLIB      1
  51
  52 struct fsl_spi_match_data {
  53         int type;
  54 };
  55
  56 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  57         .type = TYPE_FSL,
  58 };
  59
  60 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  61         .type = TYPE_GRLIB,
  62 };
  63
  64 static const struct of_device_id of_fsl_spi_match[] = {
  65         {
  66                 .compatible = "fsl,spi",
  67                 .data = &of_fsl_spi_fsl_config,
  68         },
  69         {
  70                 .compatible = "aeroflexgaisler,spictrl",
  71                 .data = &of_fsl_spi_grlib_config,
  72         },
  73         {}
  74 };
  75 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  76
  77 static int fsl_spi_get_type(struct device *dev)
  78 {
  79         const struct of_device_id *match;
  80
  81         if (dev->of_node) {
  82                 match = of_match_node(of_fsl_spi_match, dev->of_node);
  83                 if (match && match->data)
  84                         return ((struct fsl_spi_match_data *)match->data)->type;
  85         }
  86         return TYPE_FSL;
  87 }
  88
  89 static void fsl_spi_change_mode(struct spi_device *spi)
  90 {
  91         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  92         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  93         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  94         __be32 __iomem *mode = &reg_base->mode;
  95         unsigned long flags;
  96
  97         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  98                 return;
  99
 100         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 101         local_irq_save(flags);
 102
 103         /* Turn off SPI unit prior changing mode */
 104         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 105
 106         /* When in CPM mode, we need to reinit tx and rx. */
 107         if (mspi->flags & SPI_CPM_MODE) {
 108                 fsl_spi_cpm_reinit_txrx(mspi);
 109         }
 110         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 111         local_irq_restore(flags);
 112 }
 113
 114 static void fsl_spi_chipselect(struct spi_device *spi, int value)
 115 {
 116         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 117         struct fsl_spi_platform_data *pdata;
 118         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 119
 120         pdata = spi->dev.parent->parent->platform_data;
 121
 122         if (value == BITBANG_CS_INACTIVE) {
 123                 if (pdata->cs_control)
 124                         pdata->cs_control(spi, false);
 125         }
 126
 127         if (value == BITBANG_CS_ACTIVE) {
 128                 mpc8xxx_spi->rx_shift = cs->rx_shift;
 129                 mpc8xxx_spi->tx_shift = cs->tx_shift;
 130                 mpc8xxx_spi->get_rx = cs->get_rx;
 131                 mpc8xxx_spi->get_tx = cs->get_tx;
 132
 133                 fsl_spi_change_mode(spi);
 134
 135                 if (pdata->cs_control)
 136                         pdata->cs_control(spi, true);
 137         }
 138 }
 139
 140 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
 141                                       int bits_per_word, int msb_first)
 142 {
 143         *rx_shift = 0;
 144         *tx_shift = 0;
 145         if (msb_first) {
 146                 if (bits_per_word <= 8) {
 147                         *rx_shift = 16;
 148                         *tx_shift = 24;
 149                 } else if (bits_per_word <= 16) {
 150                         *rx_shift = 16;
 151                         *tx_shift = 16;
 152                 }
 153         } else {
 154                 if (bits_per_word <= 8)
 155                         *rx_shift = 8;
 156         }
 157 }
 158
 159 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
 160                                      int bits_per_word, int msb_first)
 161 {
 162         *rx_shift = 0;
 163         *tx_shift = 0;
 164         if (bits_per_word <= 16) {
 165                 if (msb_first) {
 166                         *rx_shift = 16; /* LSB in bit 16 */
 167                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
 168                 } else {
 169                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
 170                 }
 171         }
 172 }
 173
 174 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 175                                 struct spi_device *spi,
 176                                 struct mpc8xxx_spi *mpc8xxx_spi,
 177                                 int bits_per_word)
 178 {
 179         cs->rx_shift = 0;
 180         cs->tx_shift = 0;
 181         if (bits_per_word <= 8) {
 182                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 183                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 184         } else if (bits_per_word <= 16) {
 185                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 186                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 187         } else if (bits_per_word <= 32) {
 188                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 189                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 190         } else
 191                 return -EINVAL;
 192
 193         if (mpc8xxx_spi->set_shifts)
 194                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 195                                         bits_per_word,
 196                                         !(spi->mode & SPI_LSB_FIRST));
 197
 198         mpc8xxx_spi->rx_shift = cs->rx_shift;
 199         mpc8xxx_spi->tx_shift = cs->tx_shift;
 200         mpc8xxx_spi->get_rx = cs->get_rx;
 201         mpc8xxx_spi->get_tx = cs->get_tx;
 202
 203         return bits_per_word;
 204 }
 205
 206 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
 207                                 struct spi_device *spi,
 208                                 int bits_per_word)
 209 {
 210         /* QE uses Little Endian for words > 8
 211          * so transform all words > 8 into 8 bits
 212          * Unfortnatly that doesn't work for LSB so
 213          * reject these for now */
 214         /* Note: 32 bits word, LSB works iff
 215          * tfcr/rfcr is set to CPMFCR_GBL */
 216         if (spi->mode & SPI_LSB_FIRST &&
 217             bits_per_word > 8)
 218                 return -EINVAL;
 219         if (bits_per_word > 8)
 220                 return 8; /* pretend its 8 bits */
 221         return bits_per_word;
 222 }
 223
 224 static int fsl_spi_setup_transfer(struct spi_device *spi,
 225                                         struct spi_transfer *t)
 226 {
 227         struct mpc8xxx_spi *mpc8xxx_spi;
 228         int bits_per_word = 0;
 229         u8 pm;
 230         u32 hz = 0;
 231         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 232
 233         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 234
 235         if (t) {
 236                 bits_per_word = t->bits_per_word;
 237                 hz = t->speed_hz;
 238         }
 239
 240         /* spi_transfer level calls that work per-word */
 241         if (!bits_per_word)
 242                 bits_per_word = spi->bits_per_word;
 243
 244         if (!hz)
 245                 hz = spi->max_speed_hz;
 246
 247         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 248                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
 249                                                            mpc8xxx_spi,
 250                                                            bits_per_word);
 251         else if (mpc8xxx_spi->flags & SPI_QE)
 252                 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
 253                                                           bits_per_word);
 254
 255         if (bits_per_word < 0)
 256                 return bits_per_word;
 257
 258         if (bits_per_word == 32)
 259                 bits_per_word = 0;
 260         else
 261                 bits_per_word = bits_per_word - 1;
 262
 263         /* mask out bits we are going to set */
 264         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 265                                   | SPMODE_PM(0xF));
 266
 267         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 268
 269         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 270                 cs->hw_mode |= SPMODE_DIV16;
 271                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 272                 WARN_ONCE(pm > 16,
 273                           "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
 274                           dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
 275                 if (pm > 16)
 276                         pm = 16;
 277         } else {
 278                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 279         }
 280         if (pm)
 281                 pm--;
 282
 283         cs->hw_mode |= SPMODE_PM(pm);
 284
 285         fsl_spi_change_mode(spi);
 286         return 0;
 287 }
 288
 289 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 290                                 struct spi_transfer *t, unsigned int len)
 291 {
 292         u32 word;
 293         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 294
 295         mspi->count = len;
 296
 297         /* enable rx ints */
 298         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 299
 300         /* transmit word */
 301         word = mspi->get_tx(mspi);
 302         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 303
 304         return 0;
 305 }
 306
 307 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 308                             bool is_dma_mapped)
 309 {
 310         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 311         struct fsl_spi_reg __iomem *reg_base;
 312         unsigned int len = t->len;
 313         u8 bits_per_word;
 314         int ret;
 315
 316         reg_base = mpc8xxx_spi->reg_base;
 317         bits_per_word = spi->bits_per_word;
 318         if (t->bits_per_word)
 319                 bits_per_word = t->bits_per_word;
 320
 321         if (bits_per_word > 8) {
 322                 /* invalid length? */
 323                 if (len & 1)
 324                         return -EINVAL;
 325                 len /= 2;
 326         }
 327         if (bits_per_word > 16) {
 328                 /* invalid length? */
 329                 if (len & 1)
 330                         return -EINVAL;
 331                 len /= 2;
 332         }
 333
 334         mpc8xxx_spi->tx = t->tx_buf;
 335         mpc8xxx_spi->rx = t->rx_buf;
 336
 337         reinit_completion(&mpc8xxx_spi->done);
 338
 339         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 340                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 341         else
 342                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 343         if (ret)
 344                 return ret;
 345
 346         wait_for_completion(&mpc8xxx_spi->done);
 347
 348         /* disable rx ints */
 349         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 350
 351         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 352                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 353
 354         return mpc8xxx_spi->count;
 355 }
 356
 357 static int fsl_spi_do_one_msg(struct spi_master *master,
 358                               struct spi_message *m)
 359 {
 360         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 361         struct spi_device *spi = m->spi;
 362         struct spi_transfer *t, *first;
 363         unsigned int cs_change;
 364         const int nsecs = 50;
 365         int status, last_bpw;
 366
 367         /*
 368          * In CPU mode, optimize large byte transfers to use larger
 369          * bits_per_word values to reduce number of interrupts taken.
 370          */
 371         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
 372                 list_for_each_entry(t, &m->transfers, transfer_list) {
 373                         if (t->len < 256 || t->bits_per_word != 8)
 374                                 continue;
 375                         if ((t->len & 3) == 0)
 376                                 t->bits_per_word = 32;
 377                         else if ((t->len & 1) == 0)
 378                                 t->bits_per_word = 16;
 379                 }
 380         }
 381
 382         /* Don't allow changes if CS is active */
 383         cs_change = 1;
 384         list_for_each_entry(t, &m->transfers, transfer_list) {
 385                 if (cs_change)
 386                         first = t;
 387                 cs_change = t->cs_change;
 388                 if (first->speed_hz != t->speed_hz) {
 389                         dev_err(&spi->dev,
 390                                 "speed_hz cannot change while CS is active\n");
 391                         return -EINVAL;
 392                 }
 393         }
 394
 395         last_bpw = -1;
 396         cs_change = 1;
 397         status = -EINVAL;
 398         list_for_each_entry(t, &m->transfers, transfer_list) {
 399                 if (cs_change || last_bpw != t->bits_per_word)
 400                         status = fsl_spi_setup_transfer(spi, t);
 401                 if (status < 0)
 402                         break;
 403                 last_bpw = t->bits_per_word;
 404
 405                 if (cs_change) {
 406                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 407                         ndelay(nsecs);
 408                 }
 409                 cs_change = t->cs_change;
 410                 if (t->len)
 411                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
 412                 if (status) {
 413                         status = -EMSGSIZE;
 414                         break;
 415                 }
 416                 m->actual_length += t->len;
 417
 418                 spi_transfer_delay_exec(t);
 419
 420                 if (cs_change) {
 421                         ndelay(nsecs);
 422                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 423                         ndelay(nsecs);
 424                 }
 425         }
 426
 427         m->status = status;
 428
 429         if (status || !cs_change) {
 430                 ndelay(nsecs);
 431                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 432         }
 433
 434         fsl_spi_setup_transfer(spi, NULL);
 435         spi_finalize_current_message(master);
 436         return 0;
 437 }
 438
 439 static int fsl_spi_setup(struct spi_device *spi)
 440 {
 441         struct mpc8xxx_spi *mpc8xxx_spi;
 442         struct fsl_spi_reg __iomem *reg_base;
 443         int retval;
 444         u32 hw_mode;
 445         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 446
 447         if (!spi->max_speed_hz)
 448                 return -EINVAL;
 449
 450         if (!cs) {
 451                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 452                 if (!cs)
 453                         return -ENOMEM;
 454                 spi_set_ctldata(spi, cs);
 455         }
 456         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 457
 458         reg_base = mpc8xxx_spi->reg_base;
 459
 460         hw_mode = cs->hw_mode; /* Save original settings */
 461         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 462         /* mask out bits we are going to set */
 463         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 464                          | SPMODE_REV | SPMODE_LOOP);
 465
 466         if (spi->mode & SPI_CPHA)
 467                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 468         if (spi->mode & SPI_CPOL)
 469                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 470         if (!(spi->mode & SPI_LSB_FIRST))
 471                 cs->hw_mode |= SPMODE_REV;
 472         if (spi->mode & SPI_LOOP)
 473                 cs->hw_mode |= SPMODE_LOOP;
 474
 475         retval = fsl_spi_setup_transfer(spi, NULL);
 476         if (retval < 0) {
 477                 cs->hw_mode = hw_mode; /* Restore settings */
 478                 return retval;
 479         }
 480
 481         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
 482         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 483
 484         return 0;
 485 }
 486
 487 static void fsl_spi_cleanup(struct spi_device *spi)
 488 {
 489         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 490
 491         kfree(cs);
 492         spi_set_ctldata(spi, NULL);
 493 }
 494
 495 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 496 {
 497         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 498
 499         /* We need handle RX first */
 500         if (events & SPIE_NE) {
 501                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 502
 503                 if (mspi->rx)
 504                         mspi->get_rx(rx_data, mspi);
 505         }
 506
 507         if ((events & SPIE_NF) == 0)
 508                 /* spin until TX is done */
 509                 while (((events =
 510                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 511                                                 SPIE_NF) == 0)
 512                         cpu_relax();
 513
 514         /* Clear the events */
 515         mpc8xxx_spi_write_reg(&reg_base->event, events);
 516
 517         mspi->count -= 1;
 518         if (mspi->count) {
 519                 u32 word = mspi->get_tx(mspi);
 520
 521                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 522         } else {
 523                 complete(&mspi->done);
 524         }
 525 }
 526
 527 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 528 {
 529         struct mpc8xxx_spi *mspi = context_data;
 530         irqreturn_t ret = IRQ_NONE;
 531         u32 events;
 532         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 533
 534         /* Get interrupt events(tx/rx) */
 535         events = mpc8xxx_spi_read_reg(&reg_base->event);
 536         if (events)
 537                 ret = IRQ_HANDLED;
 538
 539         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 540
 541         if (mspi->flags & SPI_CPM_MODE)
 542                 fsl_spi_cpm_irq(mspi, events);
 543         else
 544                 fsl_spi_cpu_irq(mspi, events);
 545
 546         return ret;
 547 }
 548
 549 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 550 {
 551         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 552         struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
 553         u32 slvsel;
 554         u16 cs = spi->chip_select;
 555
 556         if (spi->cs_gpiod) {
 557                 gpiod_set_value(spi->cs_gpiod, on);
 558         } else if (cs < mpc8xxx_spi->native_chipselects) {
 559                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
 560                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
 561                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
 562         }
 563 }
 564
 565 static void fsl_spi_grlib_probe(struct device *dev)
 566 {
 567         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 568         struct spi_master *master = dev_get_drvdata(dev);
 569         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 570         struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
 571         int mbits;
 572         u32 capabilities;
 573
 574         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
 575
 576         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
 577         mbits = SPCAP_MAXWLEN(capabilities);
 578         if (mbits)
 579                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
 580
 581         mpc8xxx_spi->native_chipselects = 0;
 582         if (SPCAP_SSEN(capabilities)) {
 583                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
 584                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
 585         }
 586         master->num_chipselect = mpc8xxx_spi->native_chipselects;
 587         pdata->cs_control = fsl_spi_grlib_cs_control;
 588 }
 589
 590 static struct spi_master *fsl_spi_probe(struct device *dev,
 591                 struct resource *mem, unsigned int irq)
 592 {
 593         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 594         struct spi_master *master;
 595         struct mpc8xxx_spi *mpc8xxx_spi;
 596         struct fsl_spi_reg __iomem *reg_base;
 597         u32 regval;
 598         int ret = 0;
 599
 600         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 601         if (master == NULL) {
 602                 ret = -ENOMEM;
 603                 goto err;
 604         }
 605
 606         dev_set_drvdata(dev, master);
 607
 608         mpc8xxx_spi_probe(dev, mem, irq);
 609
 610         master->setup = fsl_spi_setup;
 611         master->cleanup = fsl_spi_cleanup;
 612         master->transfer_one_message = fsl_spi_do_one_msg;
 613         master->use_gpio_descriptors = true;
 614
 615         mpc8xxx_spi = spi_master_get_devdata(master);
 616         mpc8xxx_spi->max_bits_per_word = 32;
 617         mpc8xxx_spi->type = fsl_spi_get_type(dev);
 618
 619         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 620         if (ret)
 621                 goto err_cpm_init;
 622
 623         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 624         if (IS_ERR(mpc8xxx_spi->reg_base)) {
 625                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
 626                 goto err_probe;
 627         }
 628
 629         if (mpc8xxx_spi->type == TYPE_GRLIB)
 630                 fsl_spi_grlib_probe(dev);
 631
 632         master->bits_per_word_mask =
 633                 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
 634                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
 635
 636         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 637                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 638
 639         if (mpc8xxx_spi->set_shifts)
 640                 /* 8 bits per word and MSB first */
 641                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 642                                         &mpc8xxx_spi->tx_shift, 8, 1);
 643
 644         /* Register for SPI Interrupt */
 645         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
 646                                0, "fsl_spi", mpc8xxx_spi);
 647
 648         if (ret != 0)
 649                 goto err_probe;
 650
 651         reg_base = mpc8xxx_spi->reg_base;
 652
 653         /* SPI controller initializations */
 654         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 655         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 656         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 657         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 658
 659         /* Enable SPI interface */
 660         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 661         if (mpc8xxx_spi->max_bits_per_word < 8) {
 662                 regval &= ~SPMODE_LEN(0xF);
 663                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
 664         }
 665         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 666                 regval |= SPMODE_OP;
 667
 668         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 669
 670         ret = devm_spi_register_master(dev, master);
 671         if (ret < 0)
 672                 goto err_probe;
 673
 674         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 675                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 676
 677         return master;
 678
 679 err_probe:
 680         fsl_spi_cpm_free(mpc8xxx_spi);
 681 err_cpm_init:
 682         spi_master_put(master);
 683 err:
 684         return ERR_PTR(ret);
 685 }
 686
 687 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 688 {
 689         if (spi->cs_gpiod) {
 690                 gpiod_set_value(spi->cs_gpiod, on);
 691         } else {
 692                 struct device *dev = spi->dev.parent->parent;
 693                 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 694                 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 695
 696                 if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
 697                         return;
 698                 iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
 699         }
 700 }
 701
 702 static int of_fsl_spi_probe(struct platform_device *ofdev)
 703 {
 704         struct device *dev = &ofdev->dev;
 705         struct device_node *np = ofdev->dev.of_node;
 706         struct spi_master *master;
 707         struct resource mem;
 708         int irq, type;
 709         int ret;
 710         bool spisel_boot = false;
 711 #if IS_ENABLED(CONFIG_FSL_SOC)
 712         struct mpc8xxx_spi_probe_info *pinfo = NULL;
 713 #endif
 714
 715
 716         ret = of_mpc8xxx_spi_probe(ofdev);
 717         if (ret)
 718                 return ret;
 719
 720         type = fsl_spi_get_type(&ofdev->dev);
 721         if (type == TYPE_FSL) {
 722                 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 723 #if IS_ENABLED(CONFIG_FSL_SOC)
 724                 pinfo = to_of_pinfo(pdata);
 725
 726                 spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
 727                 if (spisel_boot) {
 728                         pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
 729                         if (!pinfo->immr_spi_cs)
 730                                 return -ENOMEM;
 731                 }
 732 #endif
 733                 /*
 734                  * Handle the case where we have one hardwired (always selected)
 735                  * device on the first "chipselect". Else we let the core code
 736                  * handle any GPIOs or native chip selects and assign the
 737                  * appropriate callback for dealing with the CS lines. This isn't
 738                  * supported on the GRLIB variant.
 739                  */
 740                 ret = gpiod_count(dev, "cs");
 741                 if (ret < 0)
 742                         ret = 0;
 743                 if (ret == 0 && !spisel_boot) {
 744                         pdata->max_chipselect = 1;
 745                 } else {
 746                         pdata->max_chipselect = ret + spisel_boot;
 747                         pdata->cs_control = fsl_spi_cs_control;
 748                 }
 749         }
 750
 751         ret = of_address_to_resource(np, 0, &mem);
 752         if (ret)
 753                 goto unmap_out;
 754
 755         irq = platform_get_irq(ofdev, 0);
 756         if (irq < 0) {
 757                 ret = irq;
 758                 goto unmap_out;
 759         }
 760
 761         master = fsl_spi_probe(dev, &mem, irq);
 762
 763         return PTR_ERR_OR_ZERO(master);
 764
 765 unmap_out:
 766 #if IS_ENABLED(CONFIG_FSL_SOC)
 767         if (spisel_boot)
 768                 iounmap(pinfo->immr_spi_cs);
 769 #endif
 770         return ret;
 771 }
 772
 773 static int of_fsl_spi_remove(struct platform_device *ofdev)
 774 {
 775         struct spi_master *master = platform_get_drvdata(ofdev);
 776         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 777
 778         fsl_spi_cpm_free(mpc8xxx_spi);
 779         return 0;
 780 }
 781
 782 static struct platform_driver of_fsl_spi_driver = {
 783         .driver = {
 784                 .name = "fsl_spi",
 785                 .of_match_table = of_fsl_spi_match,
 786         },
 787         .probe          = of_fsl_spi_probe,
 788         .remove         = of_fsl_spi_remove,
 789 };
 790
 791 #ifdef CONFIG_MPC832x_RDB
 792 /*
 793  * XXX XXX XXX
 794  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 795  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 796  * tree can work with OpenFirmware driver. But for now we support old trees
 797  * as well.
 798  */
 799 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 800 {
 801         struct resource *mem;
 802         int irq;
 803         struct spi_master *master;
 804
 805         if (!dev_get_platdata(&pdev->dev))
 806                 return -EINVAL;
 807
 808         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 809         if (!mem)
 810                 return -EINVAL;
 811
 812         irq = platform_get_irq(pdev, 0);
 813         if (irq <= 0)
 814                 return -EINVAL;
 815
 816         master = fsl_spi_probe(&pdev->dev, mem, irq);
 817         return PTR_ERR_OR_ZERO(master);
 818 }
 819
 820 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 821 {
 822         struct spi_master *master = platform_get_drvdata(pdev);
 823         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 824
 825         fsl_spi_cpm_free(mpc8xxx_spi);
 826
 827         return 0;
 828 }
 829
 830 MODULE_ALIAS("platform:mpc8xxx_spi");
 831 static struct platform_driver mpc8xxx_spi_driver = {
 832         .probe = plat_mpc8xxx_spi_probe,
 833         .remove = plat_mpc8xxx_spi_remove,
 834         .driver = {
 835                 .name = "mpc8xxx_spi",
 836         },
 837 };
 838
 839 static bool legacy_driver_failed;
 840
 841 static void __init legacy_driver_register(void)
 842 {
 843         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 844 }
 845
 846 static void __exit legacy_driver_unregister(void)
 847 {
 848         if (legacy_driver_failed)
 849                 return;
 850         platform_driver_unregister(&mpc8xxx_spi_driver);
 851 }
 852 #else
 853 static void __init legacy_driver_register(void) {}
 854 static void __exit legacy_driver_unregister(void) {}
 855 #endif /* CONFIG_MPC832x_RDB */
 856
 857 static int __init fsl_spi_init(void)
 858 {
 859         legacy_driver_register();
 860         return platform_driver_register(&of_fsl_spi_driver);
 861 }
 862 module_init(fsl_spi_init);
 863
 864 static void __exit fsl_spi_exit(void)
 865 {
 866         platform_driver_unregister(&of_fsl_spi_driver);
 867         legacy_driver_unregister();
 868 }
 869 module_exit(fsl_spi_exit);
 870
 871 MODULE_AUTHOR("Kumar Gala");
 872 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
 873 MODULE_LICENSE("GPL");