1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale i.MX7ULP LPSPI driver
5 // Copyright 2016 Freescale Semiconductor, Inc.
6 // Copyright 2018 NXP Semiconductors
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/gpio.h>
15 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/platform_device.h>
25 #include <linux/platform_data/dma-imx.h>
26 #include <linux/platform_data/spi-imx.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/slab.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/spi_bitbang.h>
31 #include <linux/types.h>
33 #define DRIVER_NAME "fsl_lpspi"
35 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
37 /* The maximum bytes that edma can transfer once.*/
38 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
40 /* i.MX7ULP LPSPI registers */
41 #define IMX7ULP_VERID 0x0
42 #define IMX7ULP_PARAM 0x4
43 #define IMX7ULP_CR 0x10
44 #define IMX7ULP_SR 0x14
45 #define IMX7ULP_IER 0x18
46 #define IMX7ULP_DER 0x1c
47 #define IMX7ULP_CFGR0 0x20
48 #define IMX7ULP_CFGR1 0x24
49 #define IMX7ULP_DMR0 0x30
50 #define IMX7ULP_DMR1 0x34
51 #define IMX7ULP_CCR 0x40
52 #define IMX7ULP_FCR 0x58
53 #define IMX7ULP_FSR 0x5c
54 #define IMX7ULP_TCR 0x60
55 #define IMX7ULP_TDR 0x64
56 #define IMX7ULP_RSR 0x70
57 #define IMX7ULP_RDR 0x74
59 /* General control register field define */
64 #define SR_MBF BIT(24)
65 #define SR_TCF BIT(10)
69 #define IER_TCIE BIT(10)
70 #define IER_FCIE BIT(9)
71 #define IER_RDIE BIT(1)
72 #define IER_TDIE BIT(0)
73 #define DER_RDDE BIT(1)
74 #define DER_TDDE BIT(0)
75 #define CFGR1_PCSCFG BIT(27)
76 #define CFGR1_PINCFG (BIT(24)|BIT(25))
77 #define CFGR1_PCSPOL BIT(8)
78 #define CFGR1_NOSTALL BIT(3)
79 #define CFGR1_MASTER BIT(0)
80 #define FSR_RXCOUNT (BIT(16)|BIT(17)|BIT(18))
81 #define RSR_RXEMPTY BIT(1)
82 #define TCR_CPOL BIT(31)
83 #define TCR_CPHA BIT(30)
84 #define TCR_CONT BIT(21)
85 #define TCR_CONTC BIT(20)
86 #define TCR_RXMSK BIT(19)
87 #define TCR_TXMSK BIT(18)
89 static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};
99 struct fsl_lpspi_data {
102 unsigned long base_phys;
110 void (*tx)(struct fsl_lpspi_data *);
111 void (*rx)(struct fsl_lpspi_data *);
118 struct lpspi_config config;
119 struct completion xfer_done;
125 struct completion dma_rx_completion;
126 struct completion dma_tx_completion;
131 static const struct of_device_id fsl_lpspi_dt_ids[] = {
132 { .compatible = "fsl,imx7ulp-spi", },
135 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
137 #define LPSPI_BUF_RX(type) \
138 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
140 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
142 if (fsl_lpspi->rx_buf) { \
143 *(type *)fsl_lpspi->rx_buf = val; \
144 fsl_lpspi->rx_buf += sizeof(type); \
148 #define LPSPI_BUF_TX(type) \
149 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
153 if (fsl_lpspi->tx_buf) { \
154 val = *(type *)fsl_lpspi->tx_buf; \
155 fsl_lpspi->tx_buf += sizeof(type); \
158 fsl_lpspi->remain -= sizeof(type); \
159 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
169 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
172 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
175 static int fsl_lpspi_bytes_per_word(const int bpw)
177 return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
180 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
181 struct spi_device *spi,
182 struct spi_transfer *transfer)
184 unsigned int bytes_per_word;
186 if (!controller->dma_rx)
189 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
191 switch (bytes_per_word)
204 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
206 struct fsl_lpspi_data *fsl_lpspi =
207 spi_controller_get_devdata(controller);
210 ret = pm_runtime_get_sync(fsl_lpspi->dev);
212 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
219 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
221 struct fsl_lpspi_data *fsl_lpspi =
222 spi_controller_get_devdata(controller);
224 pm_runtime_mark_last_busy(fsl_lpspi->dev);
225 pm_runtime_put_autosuspend(fsl_lpspi->dev);
230 static int fsl_lpspi_prepare_message(struct spi_controller *controller,
231 struct spi_message *msg)
233 struct fsl_lpspi_data *fsl_lpspi =
234 spi_controller_get_devdata(controller);
235 struct spi_device *spi = msg->spi;
236 int gpio = fsl_lpspi->chipselect[spi->chip_select];
238 if (gpio_is_valid(gpio))
239 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
244 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
249 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
251 while (txfifo_cnt < fsl_lpspi->txfifosize) {
252 if (!fsl_lpspi->remain)
254 fsl_lpspi->tx(fsl_lpspi);
258 if (txfifo_cnt < fsl_lpspi->txfifosize) {
259 if (!fsl_lpspi->is_slave) {
260 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
262 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
265 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
267 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
270 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
272 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
273 fsl_lpspi->rx(fsl_lpspi);
276 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
280 temp |= fsl_lpspi->config.bpw - 1;
281 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
282 if (!fsl_lpspi->is_slave) {
283 temp |= fsl_lpspi->config.prescale << 27;
284 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
287 * Set TCR_CONT will keep SS asserted after current transfer.
288 * For the first transfer, clear TCR_CONTC to assert SS.
289 * For subsequent transfer, set TCR_CONTC to keep SS asserted.
291 if (!fsl_lpspi->usedma) {
293 if (fsl_lpspi->is_first_byte)
299 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
301 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
304 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
308 if (!fsl_lpspi->usedma)
309 temp = fsl_lpspi->watermark >> 1 |
310 (fsl_lpspi->watermark >> 1) << 16;
312 temp = fsl_lpspi->watermark >> 1;
314 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
316 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
319 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
321 struct lpspi_config config = fsl_lpspi->config;
322 unsigned int perclk_rate, scldiv;
325 perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
327 if (config.speed_hz > perclk_rate / 2) {
328 dev_err(fsl_lpspi->dev,
329 "per-clk should be at least two times of transfer speed");
333 for (prescale = 0; prescale < 8; prescale++) {
334 scldiv = perclk_rate /
335 (clkdivs[prescale] * config.speed_hz) - 2;
337 fsl_lpspi->config.prescale = prescale;
342 if (prescale == 8 && scldiv >= 256)
345 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
346 fsl_lpspi->base + IMX7ULP_CCR);
348 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n",
349 perclk_rate, config.speed_hz, prescale, scldiv);
354 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
357 enum dma_slave_buswidth buswidth;
358 struct dma_slave_config rx = {}, tx = {};
359 struct fsl_lpspi_data *fsl_lpspi =
360 spi_controller_get_devdata(controller);
362 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
364 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
367 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
370 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
376 tx.direction = DMA_MEM_TO_DEV;
377 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
378 tx.dst_addr_width = buswidth;
380 ret = dmaengine_slave_config(controller->dma_tx, &tx);
382 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
387 rx.direction = DMA_DEV_TO_MEM;
388 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
389 rx.src_addr_width = buswidth;
391 ret = dmaengine_slave_config(controller->dma_rx, &rx);
393 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
401 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
406 if (!fsl_lpspi->is_slave) {
407 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
412 fsl_lpspi_set_watermark(fsl_lpspi);
414 if (!fsl_lpspi->is_slave)
418 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
419 temp |= CFGR1_PCSPOL;
420 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
422 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
423 temp |= CR_RRF | CR_RTF | CR_MEN;
424 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
427 if (fsl_lpspi->usedma)
428 temp = DER_TDDE | DER_RDDE;
429 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
434 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
435 struct spi_device *spi,
436 struct spi_transfer *t)
438 struct fsl_lpspi_data *fsl_lpspi =
439 spi_controller_get_devdata(spi->controller);
441 fsl_lpspi->config.mode = spi->mode;
442 fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word;
443 fsl_lpspi->config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
444 fsl_lpspi->config.chip_select = spi->chip_select;
446 if (!fsl_lpspi->config.speed_hz)
447 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
448 if (!fsl_lpspi->config.bpw)
449 fsl_lpspi->config.bpw = spi->bits_per_word;
451 /* Initialize the functions for transfer */
452 if (fsl_lpspi->config.bpw <= 8) {
453 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
454 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
455 } else if (fsl_lpspi->config.bpw <= 16) {
456 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
457 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
459 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
460 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
463 if (t->len <= fsl_lpspi->txfifosize)
464 fsl_lpspi->watermark = t->len;
466 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
468 if (fsl_lpspi_can_dma(controller, spi, t))
469 fsl_lpspi->usedma = 1;
471 fsl_lpspi->usedma = 0;
473 return fsl_lpspi_config(fsl_lpspi);
476 static int fsl_lpspi_slave_abort(struct spi_controller *controller)
478 struct fsl_lpspi_data *fsl_lpspi =
479 spi_controller_get_devdata(controller);
481 fsl_lpspi->slave_aborted = true;
482 complete(&fsl_lpspi->xfer_done);
486 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
488 struct fsl_lpspi_data *fsl_lpspi =
489 spi_controller_get_devdata(controller);
491 if (fsl_lpspi->is_slave) {
492 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
493 fsl_lpspi->slave_aborted) {
494 dev_dbg(fsl_lpspi->dev, "interrupted\n");
498 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
499 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
507 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
511 if (!fsl_lpspi->usedma) {
512 /* Disable all interrupt */
513 fsl_lpspi_intctrl(fsl_lpspi, 0);
516 /* W1C for all flags in SR */
518 writel(temp, fsl_lpspi->base + IMX7ULP_SR);
520 /* Clear FIFO and disable module */
521 temp = CR_RRF | CR_RTF;
522 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
527 static void fsl_lpspi_dma_rx_callback(void *cookie)
529 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
531 complete(&fsl_lpspi->dma_rx_completion);
534 static void fsl_lpspi_dma_tx_callback(void *cookie)
536 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
538 complete(&fsl_lpspi->dma_tx_completion);
541 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
544 unsigned long timeout = 0;
546 /* Time with actual data transfer and CS change delay related to HW */
547 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
549 /* Add extra second for scheduler related activities */
552 /* Double calculated timeout */
553 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
556 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
557 struct fsl_lpspi_data *fsl_lpspi,
558 struct spi_transfer *transfer)
560 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
561 unsigned long transfer_timeout;
562 unsigned long timeout;
563 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
566 ret = fsl_lpspi_dma_configure(controller);
570 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
571 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
572 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
576 desc_rx->callback = fsl_lpspi_dma_rx_callback;
577 desc_rx->callback_param = (void *)fsl_lpspi;
578 dmaengine_submit(desc_rx);
579 reinit_completion(&fsl_lpspi->dma_rx_completion);
580 dma_async_issue_pending(controller->dma_rx);
582 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
583 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
584 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
586 dmaengine_terminate_all(controller->dma_tx);
590 desc_tx->callback = fsl_lpspi_dma_tx_callback;
591 desc_tx->callback_param = (void *)fsl_lpspi;
592 dmaengine_submit(desc_tx);
593 reinit_completion(&fsl_lpspi->dma_tx_completion);
594 dma_async_issue_pending(controller->dma_tx);
596 fsl_lpspi->slave_aborted = false;
598 if (!fsl_lpspi->is_slave) {
599 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
602 /* Wait eDMA to finish the data transfer.*/
603 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
606 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
607 dmaengine_terminate_all(controller->dma_tx);
608 dmaengine_terminate_all(controller->dma_rx);
609 fsl_lpspi_reset(fsl_lpspi);
613 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
616 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
617 dmaengine_terminate_all(controller->dma_tx);
618 dmaengine_terminate_all(controller->dma_rx);
619 fsl_lpspi_reset(fsl_lpspi);
623 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
624 fsl_lpspi->slave_aborted) {
625 dev_dbg(fsl_lpspi->dev,
626 "I/O Error in DMA TX interrupted\n");
627 dmaengine_terminate_all(controller->dma_tx);
628 dmaengine_terminate_all(controller->dma_rx);
629 fsl_lpspi_reset(fsl_lpspi);
633 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
634 fsl_lpspi->slave_aborted) {
635 dev_dbg(fsl_lpspi->dev,
636 "I/O Error in DMA RX interrupted\n");
637 dmaengine_terminate_all(controller->dma_tx);
638 dmaengine_terminate_all(controller->dma_rx);
639 fsl_lpspi_reset(fsl_lpspi);
644 fsl_lpspi_reset(fsl_lpspi);
649 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
651 if (controller->dma_rx) {
652 dma_release_channel(controller->dma_rx);
653 controller->dma_rx = NULL;
656 if (controller->dma_tx) {
657 dma_release_channel(controller->dma_tx);
658 controller->dma_tx = NULL;
662 static int fsl_lpspi_dma_init(struct device *dev,
663 struct fsl_lpspi_data *fsl_lpspi,
664 struct spi_controller *controller)
668 /* Prepare for TX DMA: */
669 controller->dma_tx = dma_request_slave_channel_reason(dev, "tx");
670 if (IS_ERR(controller->dma_tx)) {
671 ret = PTR_ERR(controller->dma_tx);
672 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
673 controller->dma_tx = NULL;
677 /* Prepare for RX DMA: */
678 controller->dma_rx = dma_request_slave_channel_reason(dev, "rx");
679 if (IS_ERR(controller->dma_rx)) {
680 ret = PTR_ERR(controller->dma_rx);
681 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
682 controller->dma_rx = NULL;
686 init_completion(&fsl_lpspi->dma_rx_completion);
687 init_completion(&fsl_lpspi->dma_tx_completion);
688 controller->can_dma = fsl_lpspi_can_dma;
689 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
693 fsl_lpspi_dma_exit(controller);
697 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
698 struct spi_transfer *t)
700 struct fsl_lpspi_data *fsl_lpspi =
701 spi_controller_get_devdata(controller);
704 fsl_lpspi->tx_buf = t->tx_buf;
705 fsl_lpspi->rx_buf = t->rx_buf;
706 fsl_lpspi->remain = t->len;
708 reinit_completion(&fsl_lpspi->xfer_done);
709 fsl_lpspi->slave_aborted = false;
711 fsl_lpspi_write_tx_fifo(fsl_lpspi);
713 ret = fsl_lpspi_wait_for_completion(controller);
717 fsl_lpspi_reset(fsl_lpspi);
722 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
723 struct spi_device *spi,
724 struct spi_transfer *t)
726 struct fsl_lpspi_data *fsl_lpspi =
727 spi_controller_get_devdata(controller);
730 fsl_lpspi->is_first_byte = true;
731 ret = fsl_lpspi_setup_transfer(controller, spi, t);
735 fsl_lpspi_set_cmd(fsl_lpspi);
736 fsl_lpspi->is_first_byte = false;
738 if (fsl_lpspi->usedma)
739 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
741 ret = fsl_lpspi_pio_transfer(controller, t);
748 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
750 u32 temp_SR, temp_IER;
751 struct fsl_lpspi_data *fsl_lpspi = dev_id;
753 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
754 fsl_lpspi_intctrl(fsl_lpspi, 0);
755 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
757 fsl_lpspi_read_rx_fifo(fsl_lpspi);
759 if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
760 fsl_lpspi_write_tx_fifo(fsl_lpspi);
764 if (temp_SR & SR_MBF ||
765 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) {
766 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
767 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
771 if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
772 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
773 complete(&fsl_lpspi->xfer_done);
780 int fsl_lpspi_runtime_resume(struct device *dev)
782 struct fsl_lpspi_data *fsl_lpspi = dev_get_drvdata(dev);
785 ret = clk_prepare_enable(fsl_lpspi->clk_per);
789 ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
791 clk_disable_unprepare(fsl_lpspi->clk_per);
798 int fsl_lpspi_runtime_suspend(struct device *dev)
800 struct fsl_lpspi_data *fsl_lpspi = dev_get_drvdata(dev);
802 clk_disable_unprepare(fsl_lpspi->clk_per);
803 clk_disable_unprepare(fsl_lpspi->clk_ipg);
808 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
810 struct device *dev = fsl_lpspi->dev;
812 pm_runtime_enable(dev);
813 pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
814 pm_runtime_use_autosuspend(dev);
819 static int fsl_lpspi_probe(struct platform_device *pdev)
821 struct device_node *np = pdev->dev.of_node;
822 struct fsl_lpspi_data *fsl_lpspi;
823 struct spi_controller *controller;
824 struct spi_imx_master *lpspi_platform_info =
825 dev_get_platdata(&pdev->dev);
826 struct resource *res;
830 if (of_property_read_bool((&pdev->dev)->of_node, "spi-slave"))
831 controller = spi_alloc_slave(&pdev->dev,
832 sizeof(struct fsl_lpspi_data));
834 controller = spi_alloc_master(&pdev->dev,
835 sizeof(struct fsl_lpspi_data));
840 platform_set_drvdata(pdev, controller);
842 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
843 controller->bus_num = pdev->id;
845 fsl_lpspi = spi_controller_get_devdata(controller);
846 fsl_lpspi->dev = &pdev->dev;
847 dev_set_drvdata(&pdev->dev, fsl_lpspi);
848 fsl_lpspi->is_slave = of_property_read_bool((&pdev->dev)->of_node,
851 if (!fsl_lpspi->is_slave) {
852 for (i = 0; i < controller->num_chipselect; i++) {
853 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
855 if (!gpio_is_valid(cs_gpio) && lpspi_platform_info)
856 cs_gpio = lpspi_platform_info->chipselect[i];
858 fsl_lpspi->chipselect[i] = cs_gpio;
859 if (!gpio_is_valid(cs_gpio))
862 ret = devm_gpio_request(&pdev->dev,
863 fsl_lpspi->chipselect[i],
866 dev_err(&pdev->dev, "can't get cs gpios\n");
867 goto out_controller_put;
870 controller->cs_gpios = fsl_lpspi->chipselect;
871 controller->prepare_message = fsl_lpspi_prepare_message;
874 controller->transfer_one = fsl_lpspi_transfer_one;
875 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
876 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
877 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
878 controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
879 controller->dev.of_node = pdev->dev.of_node;
880 controller->bus_num = pdev->id;
881 controller->slave_abort = fsl_lpspi_slave_abort;
883 init_completion(&fsl_lpspi->xfer_done);
885 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
886 fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
887 if (IS_ERR(fsl_lpspi->base)) {
888 ret = PTR_ERR(fsl_lpspi->base);
889 goto out_controller_put;
891 fsl_lpspi->base_phys = res->start;
893 irq = platform_get_irq(pdev, 0);
896 goto out_controller_put;
899 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
900 dev_name(&pdev->dev), fsl_lpspi);
902 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
903 goto out_controller_put;
906 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
907 if (IS_ERR(fsl_lpspi->clk_per)) {
908 ret = PTR_ERR(fsl_lpspi->clk_per);
909 goto out_controller_put;
912 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
913 if (IS_ERR(fsl_lpspi->clk_ipg)) {
914 ret = PTR_ERR(fsl_lpspi->clk_ipg);
915 goto out_controller_put;
918 /* enable the clock */
919 ret = fsl_lpspi_init_rpm(fsl_lpspi);
921 goto out_controller_put;
923 ret = pm_runtime_get_sync(fsl_lpspi->dev);
925 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
929 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
930 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
931 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
933 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
934 if (ret == -EPROBE_DEFER)
935 goto out_controller_put;
938 dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
940 ret = devm_spi_register_controller(&pdev->dev, controller);
942 dev_err(&pdev->dev, "spi_register_controller error.\n");
943 goto out_controller_put;
949 spi_controller_put(controller);
954 static int fsl_lpspi_remove(struct platform_device *pdev)
956 struct spi_controller *controller = platform_get_drvdata(pdev);
957 struct fsl_lpspi_data *fsl_lpspi =
958 spi_controller_get_devdata(controller);
960 pm_runtime_disable(fsl_lpspi->dev);
962 spi_master_put(controller);
967 #ifdef CONFIG_PM_SLEEP
968 static int fsl_lpspi_suspend(struct device *dev)
972 pinctrl_pm_select_sleep_state(dev);
973 ret = pm_runtime_force_suspend(dev);
977 static int fsl_lpspi_resume(struct device *dev)
981 ret = pm_runtime_force_resume(dev);
983 dev_err(dev, "Error in resume: %d\n", ret);
987 pinctrl_pm_select_default_state(dev);
991 #endif /* CONFIG_PM_SLEEP */
993 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
994 SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
995 fsl_lpspi_runtime_resume, NULL)
996 SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
999 static struct platform_driver fsl_lpspi_driver = {
1001 .name = DRIVER_NAME,
1002 .of_match_table = fsl_lpspi_dt_ids,
1003 .pm = &fsl_lpspi_pm_ops,
1005 .probe = fsl_lpspi_probe,
1006 .remove = fsl_lpspi_remove,
1008 module_platform_driver(fsl_lpspi_driver);
1010 MODULE_DESCRIPTION("LPSPI Controller driver");
1011 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
1012 MODULE_LICENSE("GPL");