drivers/spi/spi-fsl-lpspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Freescale i.MX7ULP LPSPI driver
   4 //
   5 // Copyright 2016 Freescale Semiconductor, Inc.
   6 // Copyright 2018 NXP Semiconductors
   7
   8 #include <linux/clk.h>
   9 #include <linux/completion.h>
  10 #include <linux/delay.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/platform_data/dma-imx.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/slab.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/spi/spi_bitbang.h>
  28 #include <linux/types.h>
  29
  30 #define DRIVER_NAME "fsl_lpspi"
  31
  32 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
  33
  34 /* The maximum bytes that edma can transfer once.*/
  35 #define FSL_LPSPI_MAX_EDMA_BYTES  ((1 << 15) - 1)
  36
  37 /* i.MX7ULP LPSPI registers */
  38 #define IMX7ULP_VERID   0x0
  39 #define IMX7ULP_PARAM   0x4
  40 #define IMX7ULP_CR      0x10
  41 #define IMX7ULP_SR      0x14
  42 #define IMX7ULP_IER     0x18
  43 #define IMX7ULP_DER     0x1c
  44 #define IMX7ULP_CFGR0   0x20
  45 #define IMX7ULP_CFGR1   0x24
  46 #define IMX7ULP_DMR0    0x30
  47 #define IMX7ULP_DMR1    0x34
  48 #define IMX7ULP_CCR     0x40
  49 #define IMX7ULP_FCR     0x58
  50 #define IMX7ULP_FSR     0x5c
  51 #define IMX7ULP_TCR     0x60
  52 #define IMX7ULP_TDR     0x64
  53 #define IMX7ULP_RSR     0x70
  54 #define IMX7ULP_RDR     0x74
  55
  56 /* General control register field define */
  57 #define CR_RRF          BIT(9)
  58 #define CR_RTF          BIT(8)
  59 #define CR_RST          BIT(1)
  60 #define CR_MEN          BIT(0)
  61 #define SR_MBF          BIT(24)
  62 #define SR_TCF          BIT(10)
  63 #define SR_FCF          BIT(9)
  64 #define SR_RDF          BIT(1)
  65 #define SR_TDF          BIT(0)
  66 #define IER_TCIE        BIT(10)
  67 #define IER_FCIE        BIT(9)
  68 #define IER_RDIE        BIT(1)
  69 #define IER_TDIE        BIT(0)
  70 #define DER_RDDE        BIT(1)
  71 #define DER_TDDE        BIT(0)
  72 #define CFGR1_PCSCFG    BIT(27)
  73 #define CFGR1_PINCFG    (BIT(24)|BIT(25))
  74 #define CFGR1_PCSPOL    BIT(8)
  75 #define CFGR1_NOSTALL   BIT(3)
  76 #define CFGR1_MASTER    BIT(0)
  77 #define FSR_TXCOUNT     (0xFF)
  78 #define RSR_RXEMPTY     BIT(1)
  79 #define TCR_CPOL        BIT(31)
  80 #define TCR_CPHA        BIT(30)
  81 #define TCR_CONT        BIT(21)
  82 #define TCR_CONTC       BIT(20)
  83 #define TCR_RXMSK       BIT(19)
  84 #define TCR_TXMSK       BIT(18)
  85
  86 struct lpspi_config {
  87         u8 bpw;
  88         u8 chip_select;
  89         u8 prescale;
  90         u16 mode;
  91         u32 speed_hz;
  92 };
  93
  94 struct fsl_lpspi_data {
  95         struct device *dev;
  96         void __iomem *base;
  97         unsigned long base_phys;
  98         struct clk *clk_ipg;
  99         struct clk *clk_per;
 100         bool is_slave;
 101         bool is_only_cs1;
 102         bool is_first_byte;
 103
 104         void *rx_buf;
 105         const void *tx_buf;
 106         void (*tx)(struct fsl_lpspi_data *);
 107         void (*rx)(struct fsl_lpspi_data *);
 108
 109         u32 remain;
 110         u8 watermark;
 111         u8 txfifosize;
 112         u8 rxfifosize;
 113
 114         struct lpspi_config config;
 115         struct completion xfer_done;
 116
 117         bool slave_aborted;
 118
 119         /* DMA */
 120         bool usedma;
 121         struct completion dma_rx_completion;
 122         struct completion dma_tx_completion;
 123 };
 124
 125 static const struct of_device_id fsl_lpspi_dt_ids[] = {
 126         { .compatible = "fsl,imx7ulp-spi", },
 127         { /* sentinel */ }
 128 };
 129 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
 130
 131 #define LPSPI_BUF_RX(type)                                              \
 132 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 133 {                                                                       \
 134         unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR);        \
 135                                                                         \
 136         if (fsl_lpspi->rx_buf) {                                        \
 137                 *(type *)fsl_lpspi->rx_buf = val;                       \
 138                 fsl_lpspi->rx_buf += sizeof(type);                      \
 139         }                                                               \
 140 }
 141
 142 #define LPSPI_BUF_TX(type)                                              \
 143 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 144 {                                                                       \
 145         type val = 0;                                                   \
 146                                                                         \
 147         if (fsl_lpspi->tx_buf) {                                        \
 148                 val = *(type *)fsl_lpspi->tx_buf;                       \
 149                 fsl_lpspi->tx_buf += sizeof(type);                      \
 150         }                                                               \
 151                                                                         \
 152         fsl_lpspi->remain -= sizeof(type);                              \
 153         writel(val, fsl_lpspi->base + IMX7ULP_TDR);                     \
 154 }
 155
 156 LPSPI_BUF_RX(u8)
 157 LPSPI_BUF_TX(u8)
 158 LPSPI_BUF_RX(u16)
 159 LPSPI_BUF_TX(u16)
 160 LPSPI_BUF_RX(u32)
 161 LPSPI_BUF_TX(u32)
 162
 163 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
 164                               unsigned int enable)
 165 {
 166         writel(enable, fsl_lpspi->base + IMX7ULP_IER);
 167 }
 168
 169 static int fsl_lpspi_bytes_per_word(const int bpw)
 170 {
 171         return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
 172 }
 173
 174 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
 175                               struct spi_device *spi,
 176                               struct spi_transfer *transfer)
 177 {
 178         unsigned int bytes_per_word;
 179
 180         if (!controller->dma_rx)
 181                 return false;
 182
 183         bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
 184
 185         switch (bytes_per_word) {
 186         case 1:
 187         case 2:
 188         case 4:
 189                 break;
 190         default:
 191                 return false;
 192         }
 193
 194         return true;
 195 }
 196
 197 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
 198 {
 199         struct fsl_lpspi_data *fsl_lpspi =
 200                                 spi_controller_get_devdata(controller);
 201         int ret;
 202
 203         ret = pm_runtime_get_sync(fsl_lpspi->dev);
 204         if (ret < 0) {
 205                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 206                 return ret;
 207         }
 208
 209         return 0;
 210 }
 211
 212 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
 213 {
 214         struct fsl_lpspi_data *fsl_lpspi =
 215                                 spi_controller_get_devdata(controller);
 216
 217         pm_runtime_mark_last_busy(fsl_lpspi->dev);
 218         pm_runtime_put_autosuspend(fsl_lpspi->dev);
 219
 220         return 0;
 221 }
 222
 223 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 224 {
 225         u8 txfifo_cnt;
 226         u32 temp;
 227
 228         txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
 229
 230         while (txfifo_cnt < fsl_lpspi->txfifosize) {
 231                 if (!fsl_lpspi->remain)
 232                         break;
 233                 fsl_lpspi->tx(fsl_lpspi);
 234                 txfifo_cnt++;
 235         }
 236
 237         if (txfifo_cnt < fsl_lpspi->txfifosize) {
 238                 if (!fsl_lpspi->is_slave) {
 239                         temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
 240                         temp &= ~TCR_CONTC;
 241                         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 242                 }
 243
 244                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 245         } else
 246                 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
 247 }
 248
 249 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 250 {
 251         while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
 252                 fsl_lpspi->rx(fsl_lpspi);
 253 }
 254
 255 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
 256 {
 257         u32 temp = 0;
 258
 259         temp |= fsl_lpspi->config.bpw - 1;
 260         temp |= (fsl_lpspi->config.mode & 0x3) << 30;
 261         temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
 262         if (!fsl_lpspi->is_slave) {
 263                 temp |= fsl_lpspi->config.prescale << 27;
 264                 /*
 265                  * Set TCR_CONT will keep SS asserted after current transfer.
 266                  * For the first transfer, clear TCR_CONTC to assert SS.
 267                  * For subsequent transfer, set TCR_CONTC to keep SS asserted.
 268                  */
 269                 if (!fsl_lpspi->usedma) {
 270                         temp |= TCR_CONT;
 271                         if (fsl_lpspi->is_first_byte)
 272                                 temp &= ~TCR_CONTC;
 273                         else
 274                                 temp |= TCR_CONTC;
 275                 }
 276         }
 277         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 278
 279         dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
 280 }
 281
 282 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
 283 {
 284         u32 temp;
 285
 286         if (!fsl_lpspi->usedma)
 287                 temp = fsl_lpspi->watermark >> 1 |
 288                        (fsl_lpspi->watermark >> 1) << 16;
 289         else
 290                 temp = fsl_lpspi->watermark >> 1;
 291
 292         writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
 293
 294         dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
 295 }
 296
 297 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
 298 {
 299         struct lpspi_config config = fsl_lpspi->config;
 300         unsigned int perclk_rate, scldiv;
 301         u8 prescale;
 302
 303         perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
 304
 305         if (config.speed_hz > perclk_rate / 2) {
 306                 dev_err(fsl_lpspi->dev,
 307                       "per-clk should be at least two times of transfer speed");
 308                 return -EINVAL;
 309         }
 310
 311         for (prescale = 0; prescale < 8; prescale++) {
 312                 scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2;
 313                 if (scldiv < 256) {
 314                         fsl_lpspi->config.prescale = prescale;
 315                         break;
 316                 }
 317         }
 318
 319         if (scldiv >= 256)
 320                 return -EINVAL;
 321
 322         writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
 323                                         fsl_lpspi->base + IMX7ULP_CCR);
 324
 325         dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
 326                 perclk_rate, config.speed_hz, prescale, scldiv);
 327
 328         return 0;
 329 }
 330
 331 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
 332 {
 333         int ret;
 334         enum dma_slave_buswidth buswidth;
 335         struct dma_slave_config rx = {}, tx = {};
 336         struct fsl_lpspi_data *fsl_lpspi =
 337                                 spi_controller_get_devdata(controller);
 338
 339         switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
 340         case 4:
 341                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
 342                 break;
 343         case 2:
 344                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
 345                 break;
 346         case 1:
 347                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
 348                 break;
 349         default:
 350                 return -EINVAL;
 351         }
 352
 353         tx.direction = DMA_MEM_TO_DEV;
 354         tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
 355         tx.dst_addr_width = buswidth;
 356         tx.dst_maxburst = 1;
 357         ret = dmaengine_slave_config(controller->dma_tx, &tx);
 358         if (ret) {
 359                 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
 360                         ret);
 361                 return ret;
 362         }
 363
 364         rx.direction = DMA_DEV_TO_MEM;
 365         rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
 366         rx.src_addr_width = buswidth;
 367         rx.src_maxburst = 1;
 368         ret = dmaengine_slave_config(controller->dma_rx, &rx);
 369         if (ret) {
 370                 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
 371                         ret);
 372                 return ret;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
 379 {
 380         u32 temp;
 381         int ret;
 382
 383         if (!fsl_lpspi->is_slave) {
 384                 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
 385                 if (ret)
 386                         return ret;
 387         }
 388
 389         fsl_lpspi_set_watermark(fsl_lpspi);
 390
 391         if (!fsl_lpspi->is_slave)
 392                 temp = CFGR1_MASTER;
 393         else
 394                 temp = CFGR1_PINCFG;
 395         if (fsl_lpspi->config.mode & SPI_CS_HIGH)
 396                 temp |= CFGR1_PCSPOL;
 397         writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
 398
 399         temp = readl(fsl_lpspi->base + IMX7ULP_CR);
 400         temp |= CR_RRF | CR_RTF | CR_MEN;
 401         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 402
 403         temp = 0;
 404         if (fsl_lpspi->usedma)
 405                 temp = DER_TDDE | DER_RDDE;
 406         writel(temp, fsl_lpspi->base + IMX7ULP_DER);
 407
 408         return 0;
 409 }
 410
 411 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
 412                                      struct spi_device *spi,
 413                                      struct spi_transfer *t)
 414 {
 415         struct fsl_lpspi_data *fsl_lpspi =
 416                                 spi_controller_get_devdata(spi->controller);
 417
 418         if (t == NULL)
 419                 return -EINVAL;
 420
 421         fsl_lpspi->config.mode = spi->mode;
 422         fsl_lpspi->config.bpw = t->bits_per_word;
 423         fsl_lpspi->config.speed_hz = t->speed_hz;
 424         if (fsl_lpspi->is_only_cs1)
 425                 fsl_lpspi->config.chip_select = 1;
 426         else
 427                 fsl_lpspi->config.chip_select = spi->chip_select;
 428
 429         if (!fsl_lpspi->config.speed_hz)
 430                 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
 431         if (!fsl_lpspi->config.bpw)
 432                 fsl_lpspi->config.bpw = spi->bits_per_word;
 433
 434         /* Initialize the functions for transfer */
 435         if (fsl_lpspi->config.bpw <= 8) {
 436                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
 437                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
 438         } else if (fsl_lpspi->config.bpw <= 16) {
 439                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
 440                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
 441         } else {
 442                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
 443                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
 444         }
 445
 446         if (t->len <= fsl_lpspi->txfifosize)
 447                 fsl_lpspi->watermark = t->len;
 448         else
 449                 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
 450
 451         if (fsl_lpspi_can_dma(controller, spi, t))
 452                 fsl_lpspi->usedma = true;
 453         else
 454                 fsl_lpspi->usedma = false;
 455
 456         return fsl_lpspi_config(fsl_lpspi);
 457 }
 458
 459 static int fsl_lpspi_slave_abort(struct spi_controller *controller)
 460 {
 461         struct fsl_lpspi_data *fsl_lpspi =
 462                                 spi_controller_get_devdata(controller);
 463
 464         fsl_lpspi->slave_aborted = true;
 465         if (!fsl_lpspi->usedma)
 466                 complete(&fsl_lpspi->xfer_done);
 467         else {
 468                 complete(&fsl_lpspi->dma_tx_completion);
 469                 complete(&fsl_lpspi->dma_rx_completion);
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
 476 {
 477         struct fsl_lpspi_data *fsl_lpspi =
 478                                 spi_controller_get_devdata(controller);
 479
 480         if (fsl_lpspi->is_slave) {
 481                 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
 482                         fsl_lpspi->slave_aborted) {
 483                         dev_dbg(fsl_lpspi->dev, "interrupted\n");
 484                         return -EINTR;
 485                 }
 486         } else {
 487                 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
 488                         dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
 489                         return -ETIMEDOUT;
 490                 }
 491         }
 492
 493         return 0;
 494 }
 495
 496 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
 497 {
 498         u32 temp;
 499
 500         if (!fsl_lpspi->usedma) {
 501                 /* Disable all interrupt */
 502                 fsl_lpspi_intctrl(fsl_lpspi, 0);
 503         }
 504
 505         /* W1C for all flags in SR */
 506         temp = 0x3F << 8;
 507         writel(temp, fsl_lpspi->base + IMX7ULP_SR);
 508
 509         /* Clear FIFO and disable module */
 510         temp = CR_RRF | CR_RTF;
 511         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 512
 513         return 0;
 514 }
 515
 516 static void fsl_lpspi_dma_rx_callback(void *cookie)
 517 {
 518         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 519
 520         complete(&fsl_lpspi->dma_rx_completion);
 521 }
 522
 523 static void fsl_lpspi_dma_tx_callback(void *cookie)
 524 {
 525         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 526
 527         complete(&fsl_lpspi->dma_tx_completion);
 528 }
 529
 530 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
 531                                        int size)
 532 {
 533         unsigned long timeout = 0;
 534
 535         /* Time with actual data transfer and CS change delay related to HW */
 536         timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
 537
 538         /* Add extra second for scheduler related activities */
 539         timeout += 1;
 540
 541         /* Double calculated timeout */
 542         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
 543 }
 544
 545 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
 546                                 struct fsl_lpspi_data *fsl_lpspi,
 547                                 struct spi_transfer *transfer)
 548 {
 549         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
 550         unsigned long transfer_timeout;
 551         unsigned long timeout;
 552         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
 553         int ret;
 554
 555         ret = fsl_lpspi_dma_configure(controller);
 556         if (ret)
 557                 return ret;
 558
 559         desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
 560                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
 561                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 562         if (!desc_rx)
 563                 return -EINVAL;
 564
 565         desc_rx->callback = fsl_lpspi_dma_rx_callback;
 566         desc_rx->callback_param = (void *)fsl_lpspi;
 567         dmaengine_submit(desc_rx);
 568         reinit_completion(&fsl_lpspi->dma_rx_completion);
 569         dma_async_issue_pending(controller->dma_rx);
 570
 571         desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
 572                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
 573                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 574         if (!desc_tx) {
 575                 dmaengine_terminate_all(controller->dma_tx);
 576                 return -EINVAL;
 577         }
 578
 579         desc_tx->callback = fsl_lpspi_dma_tx_callback;
 580         desc_tx->callback_param = (void *)fsl_lpspi;
 581         dmaengine_submit(desc_tx);
 582         reinit_completion(&fsl_lpspi->dma_tx_completion);
 583         dma_async_issue_pending(controller->dma_tx);
 584
 585         fsl_lpspi->slave_aborted = false;
 586
 587         if (!fsl_lpspi->is_slave) {
 588                 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
 589                                                                transfer->len);
 590
 591                 /* Wait eDMA to finish the data transfer.*/
 592                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
 593                                                       transfer_timeout);
 594                 if (!timeout) {
 595                         dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
 596                         dmaengine_terminate_all(controller->dma_tx);
 597                         dmaengine_terminate_all(controller->dma_rx);
 598                         fsl_lpspi_reset(fsl_lpspi);
 599                         return -ETIMEDOUT;
 600                 }
 601
 602                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
 603                                                       transfer_timeout);
 604                 if (!timeout) {
 605                         dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
 606                         dmaengine_terminate_all(controller->dma_tx);
 607                         dmaengine_terminate_all(controller->dma_rx);
 608                         fsl_lpspi_reset(fsl_lpspi);
 609                         return -ETIMEDOUT;
 610                 }
 611         } else {
 612                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
 613                         fsl_lpspi->slave_aborted) {
 614                         dev_dbg(fsl_lpspi->dev,
 615                                 "I/O Error in DMA TX interrupted\n");
 616                         dmaengine_terminate_all(controller->dma_tx);
 617                         dmaengine_terminate_all(controller->dma_rx);
 618                         fsl_lpspi_reset(fsl_lpspi);
 619                         return -EINTR;
 620                 }
 621
 622                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
 623                         fsl_lpspi->slave_aborted) {
 624                         dev_dbg(fsl_lpspi->dev,
 625                                 "I/O Error in DMA RX interrupted\n");
 626                         dmaengine_terminate_all(controller->dma_tx);
 627                         dmaengine_terminate_all(controller->dma_rx);
 628                         fsl_lpspi_reset(fsl_lpspi);
 629                         return -EINTR;
 630                 }
 631         }
 632
 633         fsl_lpspi_reset(fsl_lpspi);
 634
 635         return 0;
 636 }
 637
 638 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
 639 {
 640         if (controller->dma_rx) {
 641                 dma_release_channel(controller->dma_rx);
 642                 controller->dma_rx = NULL;
 643         }
 644
 645         if (controller->dma_tx) {
 646                 dma_release_channel(controller->dma_tx);
 647                 controller->dma_tx = NULL;
 648         }
 649 }
 650
 651 static int fsl_lpspi_dma_init(struct device *dev,
 652                               struct fsl_lpspi_data *fsl_lpspi,
 653                               struct spi_controller *controller)
 654 {
 655         int ret;
 656
 657         /* Prepare for TX DMA: */
 658         controller->dma_tx = dma_request_chan(dev, "tx");
 659         if (IS_ERR(controller->dma_tx)) {
 660                 ret = PTR_ERR(controller->dma_tx);
 661                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
 662                 controller->dma_tx = NULL;
 663                 goto err;
 664         }
 665
 666         /* Prepare for RX DMA: */
 667         controller->dma_rx = dma_request_chan(dev, "rx");
 668         if (IS_ERR(controller->dma_rx)) {
 669                 ret = PTR_ERR(controller->dma_rx);
 670                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
 671                 controller->dma_rx = NULL;
 672                 goto err;
 673         }
 674
 675         init_completion(&fsl_lpspi->dma_rx_completion);
 676         init_completion(&fsl_lpspi->dma_tx_completion);
 677         controller->can_dma = fsl_lpspi_can_dma;
 678         controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
 679
 680         return 0;
 681 err:
 682         fsl_lpspi_dma_exit(controller);
 683         return ret;
 684 }
 685
 686 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
 687                                   struct spi_transfer *t)
 688 {
 689         struct fsl_lpspi_data *fsl_lpspi =
 690                                 spi_controller_get_devdata(controller);
 691         int ret;
 692
 693         fsl_lpspi->tx_buf = t->tx_buf;
 694         fsl_lpspi->rx_buf = t->rx_buf;
 695         fsl_lpspi->remain = t->len;
 696
 697         reinit_completion(&fsl_lpspi->xfer_done);
 698         fsl_lpspi->slave_aborted = false;
 699
 700         fsl_lpspi_write_tx_fifo(fsl_lpspi);
 701
 702         ret = fsl_lpspi_wait_for_completion(controller);
 703         if (ret)
 704                 return ret;
 705
 706         fsl_lpspi_reset(fsl_lpspi);
 707
 708         return 0;
 709 }
 710
 711 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
 712                                   struct spi_device *spi,
 713                                   struct spi_transfer *t)
 714 {
 715         struct fsl_lpspi_data *fsl_lpspi =
 716                                         spi_controller_get_devdata(controller);
 717         int ret;
 718
 719         fsl_lpspi->is_first_byte = true;
 720         ret = fsl_lpspi_setup_transfer(controller, spi, t);
 721         if (ret < 0)
 722                 return ret;
 723
 724         fsl_lpspi_set_cmd(fsl_lpspi);
 725         fsl_lpspi->is_first_byte = false;
 726
 727         if (fsl_lpspi->usedma)
 728                 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
 729         else
 730                 ret = fsl_lpspi_pio_transfer(controller, t);
 731         if (ret < 0)
 732                 return ret;
 733
 734         return 0;
 735 }
 736
 737 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
 738 {
 739         u32 temp_SR, temp_IER;
 740         struct fsl_lpspi_data *fsl_lpspi = dev_id;
 741
 742         temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
 743         fsl_lpspi_intctrl(fsl_lpspi, 0);
 744         temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
 745
 746         fsl_lpspi_read_rx_fifo(fsl_lpspi);
 747
 748         if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
 749                 fsl_lpspi_write_tx_fifo(fsl_lpspi);
 750                 return IRQ_HANDLED;
 751         }
 752
 753         if (temp_SR & SR_MBF ||
 754             readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
 755                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 756                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 757                 return IRQ_HANDLED;
 758         }
 759
 760         if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
 761                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 762                 complete(&fsl_lpspi->xfer_done);
 763                 return IRQ_HANDLED;
 764         }
 765
 766         return IRQ_NONE;
 767 }
 768
 769 #ifdef CONFIG_PM
 770 static int fsl_lpspi_runtime_resume(struct device *dev)
 771 {
 772         struct spi_controller *controller = dev_get_drvdata(dev);
 773         struct fsl_lpspi_data *fsl_lpspi;
 774         int ret;
 775
 776         fsl_lpspi = spi_controller_get_devdata(controller);
 777
 778         ret = clk_prepare_enable(fsl_lpspi->clk_per);
 779         if (ret)
 780                 return ret;
 781
 782         ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
 783         if (ret) {
 784                 clk_disable_unprepare(fsl_lpspi->clk_per);
 785                 return ret;
 786         }
 787
 788         return 0;
 789 }
 790
 791 static int fsl_lpspi_runtime_suspend(struct device *dev)
 792 {
 793         struct spi_controller *controller = dev_get_drvdata(dev);
 794         struct fsl_lpspi_data *fsl_lpspi;
 795
 796         fsl_lpspi = spi_controller_get_devdata(controller);
 797
 798         clk_disable_unprepare(fsl_lpspi->clk_per);
 799         clk_disable_unprepare(fsl_lpspi->clk_ipg);
 800
 801         return 0;
 802 }
 803 #endif
 804
 805 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
 806 {
 807         struct device *dev = fsl_lpspi->dev;
 808
 809         pm_runtime_enable(dev);
 810         pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
 811         pm_runtime_use_autosuspend(dev);
 812
 813         return 0;
 814 }
 815
 816 static int fsl_lpspi_probe(struct platform_device *pdev)
 817 {
 818         struct fsl_lpspi_data *fsl_lpspi;
 819         struct spi_controller *controller;
 820         struct resource *res;
 821         int ret, irq;
 822         u32 temp;
 823         bool is_slave;
 824
 825         is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
 826         if (is_slave)
 827                 controller = spi_alloc_slave(&pdev->dev,
 828                                         sizeof(struct fsl_lpspi_data));
 829         else
 830                 controller = spi_alloc_master(&pdev->dev,
 831                                         sizeof(struct fsl_lpspi_data));
 832
 833         if (!controller)
 834                 return -ENOMEM;
 835
 836         platform_set_drvdata(pdev, controller);
 837
 838         fsl_lpspi = spi_controller_get_devdata(controller);
 839         fsl_lpspi->dev = &pdev->dev;
 840         fsl_lpspi->is_slave = is_slave;
 841         fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
 842                                                 "fsl,spi-only-use-cs1-sel");
 843
 844         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
 845         controller->transfer_one = fsl_lpspi_transfer_one;
 846         controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
 847         controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
 848         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 849         controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
 850         controller->dev.of_node = pdev->dev.of_node;
 851         controller->bus_num = pdev->id;
 852         controller->slave_abort = fsl_lpspi_slave_abort;
 853         if (!fsl_lpspi->is_slave)
 854                 controller->use_gpio_descriptors = true;
 855
 856         init_completion(&fsl_lpspi->xfer_done);
 857
 858         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 859         fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
 860         if (IS_ERR(fsl_lpspi->base)) {
 861                 ret = PTR_ERR(fsl_lpspi->base);
 862                 goto out_controller_put;
 863         }
 864         fsl_lpspi->base_phys = res->start;
 865
 866         irq = platform_get_irq(pdev, 0);
 867         if (irq < 0) {
 868                 ret = irq;
 869                 goto out_controller_put;
 870         }
 871
 872         ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
 873                                dev_name(&pdev->dev), fsl_lpspi);
 874         if (ret) {
 875                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
 876                 goto out_controller_put;
 877         }
 878
 879         fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
 880         if (IS_ERR(fsl_lpspi->clk_per)) {
 881                 ret = PTR_ERR(fsl_lpspi->clk_per);
 882                 goto out_controller_put;
 883         }
 884
 885         fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 886         if (IS_ERR(fsl_lpspi->clk_ipg)) {
 887                 ret = PTR_ERR(fsl_lpspi->clk_ipg);
 888                 goto out_controller_put;
 889         }
 890
 891         /* enable the clock */
 892         ret = fsl_lpspi_init_rpm(fsl_lpspi);
 893         if (ret)
 894                 goto out_controller_put;
 895
 896         ret = pm_runtime_get_sync(fsl_lpspi->dev);
 897         if (ret < 0) {
 898                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 899                 goto out_pm_get;
 900         }
 901
 902         temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
 903         fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
 904         fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
 905
 906         ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
 907         if (ret == -EPROBE_DEFER)
 908                 goto out_pm_get;
 909
 910         if (ret < 0)
 911                 dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
 912
 913         ret = devm_spi_register_controller(&pdev->dev, controller);
 914         if (ret < 0) {
 915                 dev_err(&pdev->dev, "spi_register_controller error.\n");
 916                 goto out_pm_get;
 917         }
 918
 919         pm_runtime_mark_last_busy(fsl_lpspi->dev);
 920         pm_runtime_put_autosuspend(fsl_lpspi->dev);
 921
 922         return 0;
 923
 924 out_pm_get:
 925         pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
 926         pm_runtime_put_sync(fsl_lpspi->dev);
 927         pm_runtime_disable(fsl_lpspi->dev);
 928 out_controller_put:
 929         spi_controller_put(controller);
 930
 931         return ret;
 932 }
 933
 934 static int fsl_lpspi_remove(struct platform_device *pdev)
 935 {
 936         struct spi_controller *controller = platform_get_drvdata(pdev);
 937         struct fsl_lpspi_data *fsl_lpspi =
 938                                 spi_controller_get_devdata(controller);
 939
 940         pm_runtime_disable(fsl_lpspi->dev);
 941         return 0;
 942 }
 943
 944 static int __maybe_unused fsl_lpspi_suspend(struct device *dev)
 945 {
 946         int ret;
 947
 948         pinctrl_pm_select_sleep_state(dev);
 949         ret = pm_runtime_force_suspend(dev);
 950         return ret;
 951 }
 952
 953 static int __maybe_unused fsl_lpspi_resume(struct device *dev)
 954 {
 955         int ret;
 956
 957         ret = pm_runtime_force_resume(dev);
 958         if (ret) {
 959                 dev_err(dev, "Error in resume: %d\n", ret);
 960                 return ret;
 961         }
 962
 963         pinctrl_pm_select_default_state(dev);
 964
 965         return 0;
 966 }
 967
 968 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
 969         SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
 970                                 fsl_lpspi_runtime_resume, NULL)
 971         SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
 972 };
 973
 974 static struct platform_driver fsl_lpspi_driver = {
 975         .driver = {
 976                 .name = DRIVER_NAME,
 977                 .of_match_table = fsl_lpspi_dt_ids,
 978                 .pm = &fsl_lpspi_pm_ops,
 979         },
 980         .probe = fsl_lpspi_probe,
 981         .remove = fsl_lpspi_remove,
 982 };
 983 module_platform_driver(fsl_lpspi_driver);
 984
 985 MODULE_DESCRIPTION("LPSPI Controller driver");
 986 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
 987 MODULE_LICENSE("GPL");