drivers/soc/tegra/fuse/fuse-tegra20.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * Based on drivers/misc/eeprom/sunxi_sid.c
   6  */
   7
   8 #include <linux/device.h>
   9 #include <linux/clk.h>
  10 #include <linux/completion.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/kernel.h>
  16 #include <linux/kobject.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/random.h>
  21
  22 #include <soc/tegra/fuse.h>
  23
  24 #include "fuse.h"
  25
  26 #define FUSE_BEGIN      0x100
  27 #define FUSE_UID_LOW    0x08
  28 #define FUSE_UID_HIGH   0x0c
  29
  30 static u32 tegra20_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
  31 {
  32         return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
  33 }
  34
  35 static void apb_dma_complete(void *args)
  36 {
  37         struct tegra_fuse *fuse = args;
  38
  39         complete(&fuse->apbdma.wait);
  40 }
  41
  42 static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
  43 {
  44         unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
  45         struct dma_async_tx_descriptor *dma_desc;
  46         unsigned long time_left;
  47         u32 value = 0;
  48         int err;
  49
  50         err = pm_runtime_resume_and_get(fuse->dev);
  51         if (err)
  52                 return err;
  53
  54         mutex_lock(&fuse->apbdma.lock);
  55
  56         fuse->apbdma.config.src_addr = fuse->phys + FUSE_BEGIN + offset;
  57
  58         err = dmaengine_slave_config(fuse->apbdma.chan, &fuse->apbdma.config);
  59         if (err)
  60                 goto out;
  61
  62         dma_desc = dmaengine_prep_slave_single(fuse->apbdma.chan,
  63                                                fuse->apbdma.phys,
  64                                                sizeof(u32), DMA_DEV_TO_MEM,
  65                                                flags);
  66         if (!dma_desc)
  67                 goto out;
  68
  69         dma_desc->callback = apb_dma_complete;
  70         dma_desc->callback_param = fuse;
  71
  72         reinit_completion(&fuse->apbdma.wait);
  73
  74         dmaengine_submit(dma_desc);
  75         dma_async_issue_pending(fuse->apbdma.chan);
  76         time_left = wait_for_completion_timeout(&fuse->apbdma.wait,
  77                                                 msecs_to_jiffies(50));
  78
  79         if (WARN(time_left == 0, "apb read dma timed out"))
  80                 dmaengine_terminate_all(fuse->apbdma.chan);
  81         else
  82                 value = *fuse->apbdma.virt;
  83
  84 out:
  85         mutex_unlock(&fuse->apbdma.lock);
  86         pm_runtime_put(fuse->dev);
  87         return value;
  88 }
  89
  90 static bool dma_filter(struct dma_chan *chan, void *filter_param)
  91 {
  92         struct device_node *np = chan->device->dev->of_node;
  93
  94         return of_device_is_compatible(np, "nvidia,tegra20-apbdma");
  95 }
  96
  97 static int tegra20_fuse_probe(struct tegra_fuse *fuse)
  98 {
  99         dma_cap_mask_t mask;
 100
 101         dma_cap_zero(mask);
 102         dma_cap_set(DMA_SLAVE, mask);
 103
 104         fuse->apbdma.chan = dma_request_channel(mask, dma_filter, NULL);
 105         if (!fuse->apbdma.chan)
 106                 return -EPROBE_DEFER;
 107
 108         fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32),
 109                                                &fuse->apbdma.phys,
 110                                                GFP_KERNEL);
 111         if (!fuse->apbdma.virt) {
 112                 dma_release_channel(fuse->apbdma.chan);
 113                 return -ENOMEM;
 114         }
 115
 116         fuse->apbdma.config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 117         fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 118         fuse->apbdma.config.src_maxburst = 1;
 119         fuse->apbdma.config.dst_maxburst = 1;
 120         fuse->apbdma.config.direction = DMA_DEV_TO_MEM;
 121         fuse->apbdma.config.device_fc = false;
 122
 123         init_completion(&fuse->apbdma.wait);
 124         mutex_init(&fuse->apbdma.lock);
 125         fuse->read = tegra20_fuse_read;
 126
 127         return 0;
 128 }
 129
 130 static const struct tegra_fuse_info tegra20_fuse_info = {
 131         .read = tegra20_fuse_read,
 132         .size = 0x1f8,
 133         .spare = 0x100,
 134 };
 135
 136 /* Early boot code. This code is called before the devices are created */
 137
 138 static void __init tegra20_fuse_add_randomness(void)
 139 {
 140         u32 randomness[7];
 141
 142         randomness[0] = tegra_sku_info.sku_id;
 143         randomness[1] = tegra_read_straps();
 144         randomness[2] = tegra_read_chipid();
 145         randomness[3] = tegra_sku_info.cpu_process_id << 16;
 146         randomness[3] |= tegra_sku_info.soc_process_id;
 147         randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
 148         randomness[4] |= tegra_sku_info.soc_speedo_id;
 149         randomness[5] = tegra_fuse_read_early(FUSE_UID_LOW);
 150         randomness[6] = tegra_fuse_read_early(FUSE_UID_HIGH);
 151
 152         add_device_randomness(randomness, sizeof(randomness));
 153 }
 154
 155 static void __init tegra20_fuse_init(struct tegra_fuse *fuse)
 156 {
 157         fuse->read_early = tegra20_fuse_read_early;
 158
 159         tegra_init_revision();
 160         fuse->soc->speedo_init(&tegra_sku_info);
 161         tegra20_fuse_add_randomness();
 162 }
 163
 164 const struct tegra_fuse_soc tegra20_fuse_soc = {
 165         .init = tegra20_fuse_init,
 166         .speedo_init = tegra20_init_speedo_data,
 167         .probe = tegra20_fuse_probe,
 168         .info = &tegra20_fuse_info,
 169         .soc_attr_group = &tegra_soc_attr_group,
 170         .clk_suspend_on = false,
 171 };