drivers/soc/mediatek/mtk-mmsys.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __SOC_MEDIATEK_MTK_MMSYS_H
   4 #define __SOC_MEDIATEK_MTK_MMSYS_H
   5
   6 #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN       0x040
   7 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN       0x044
   8 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN         0x048
   9 #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN      0x04c
  10 #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN       0x050
  11 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN      0x084
  12 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN      0x088
  13 #define DISP_REG_CONFIG_DSIE_SEL_IN             0x0a4
  14 #define DISP_REG_CONFIG_DSIO_SEL_IN             0x0a8
  15 #define DISP_REG_CONFIG_DPI_SEL_IN              0x0ac
  16 #define DISP_REG_CONFIG_DISP_RDMA2_SOUT         0x0b8
  17 #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN      0x0c4
  18 #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN      0x0c8
  19 #define DISP_REG_CONFIG_MMSYS_CG_CON0           0x100
  20
  21 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN        0x030
  22 #define DISP_REG_CONFIG_OUT_SEL                 0x04c
  23 #define DISP_REG_CONFIG_DSI_SEL                 0x050
  24 #define DISP_REG_CONFIG_DPI_SEL                 0x064
  25
  26 #define OVL0_MOUT_EN_COLOR0                     0x1
  27 #define OD_MOUT_EN_RDMA0                        0x1
  28 #define OD1_MOUT_EN_RDMA1                       BIT(16)
  29 #define UFOE_MOUT_EN_DSI0                       0x1
  30 #define COLOR0_SEL_IN_OVL0                      0x1
  31 #define OVL1_MOUT_EN_COLOR1                     0x1
  32 #define GAMMA_MOUT_EN_RDMA1                     0x1
  33 #define RDMA0_SOUT_DPI0                         0x2
  34 #define RDMA0_SOUT_DPI1                         0x3
  35 #define RDMA0_SOUT_DSI1                         0x1
  36 #define RDMA0_SOUT_DSI2                         0x4
  37 #define RDMA0_SOUT_DSI3                         0x5
  38 #define RDMA0_SOUT_MASK                         0x7
  39 #define RDMA1_SOUT_DPI0                         0x2
  40 #define RDMA1_SOUT_DPI1                         0x3
  41 #define RDMA1_SOUT_DSI1                         0x1
  42 #define RDMA1_SOUT_DSI2                         0x4
  43 #define RDMA1_SOUT_DSI3                         0x5
  44 #define RDMA1_SOUT_MASK                         0x7
  45 #define RDMA2_SOUT_DPI0                         0x2
  46 #define RDMA2_SOUT_DPI1                         0x3
  47 #define RDMA2_SOUT_DSI1                         0x1
  48 #define RDMA2_SOUT_DSI2                         0x4
  49 #define RDMA2_SOUT_DSI3                         0x5
  50 #define RDMA2_SOUT_MASK                         0x7
  51 #define DPI0_SEL_IN_RDMA1                       0x1
  52 #define DPI0_SEL_IN_RDMA2                       0x3
  53 #define DPI0_SEL_IN_MASK                        0x3
  54 #define DPI1_SEL_IN_RDMA1                       (0x1 << 8)
  55 #define DPI1_SEL_IN_RDMA2                       (0x3 << 8)
  56 #define DPI1_SEL_IN_MASK                        (0x3 << 8)
  57 #define DSI0_SEL_IN_RDMA1                       0x1
  58 #define DSI0_SEL_IN_RDMA2                       0x4
  59 #define DSI0_SEL_IN_MASK                        0x7
  60 #define DSI1_SEL_IN_RDMA1                       0x1
  61 #define DSI1_SEL_IN_RDMA2                       0x4
  62 #define DSI1_SEL_IN_MASK                        0x7
  63 #define DSI2_SEL_IN_RDMA1                       (0x1 << 16)
  64 #define DSI2_SEL_IN_RDMA2                       (0x4 << 16)
  65 #define DSI2_SEL_IN_MASK                        (0x7 << 16)
  66 #define DSI3_SEL_IN_RDMA1                       (0x1 << 16)
  67 #define DSI3_SEL_IN_RDMA2                       (0x4 << 16)
  68 #define DSI3_SEL_IN_MASK                        (0x7 << 16)
  69 #define COLOR1_SEL_IN_OVL1                      0x1
  70
  71 #define OVL_MOUT_EN_RDMA                        0x1
  72 #define BLS_TO_DSI_RDMA1_TO_DPI1                0x8
  73 #define BLS_TO_DPI_RDMA1_TO_DSI                 0x2
  74 #define BLS_RDMA1_DSI_DPI_MASK                  0xf
  75 #define DSI_SEL_IN_BLS                          0x0
  76 #define DPI_SEL_IN_BLS                          0x0
  77 #define DPI_SEL_IN_MASK                         0x1
  78 #define DSI_SEL_IN_RDMA                         0x1
  79 #define DSI_SEL_IN_MASK                         0x1
  80
  81 struct mtk_mmsys_routes {
  82         u32 from_comp;
  83         u32 to_comp;
  84         u32 addr;
  85         u32 mask;
  86         u32 val;
  87 };
  88
  89 struct mtk_mmsys_driver_data {
  90         const char *clk_driver;
  91         const struct mtk_mmsys_routes *routes;
  92         const unsigned int num_routes;
  93 };
  94
  95 /*
  96  * Routes in mt8173, mt2701, mt2712 are different. That means
  97  * in the same register address, it controls different input/output
  98  * selection for each SoC. But, right now, they use the same table as
  99  * default routes meet their requirements. But we don't have the complete
 100  * route information for these three SoC, so just keep them in the same
 101  * table. After we've more information, we could separate mt2701, mt2712
 102  * to an independent table.
 103  */
 104 static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
 105         {
 106                 DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
 107                 DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
 108                 BLS_TO_DSI_RDMA1_TO_DPI1
 109         }, {
 110                 DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
 111                 DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
 112                 DSI_SEL_IN_BLS
 113         }, {
 114                 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
 115                 DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
 116                 BLS_TO_DPI_RDMA1_TO_DSI
 117         }, {
 118                 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
 119                 DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
 120                 DSI_SEL_IN_RDMA
 121         }, {
 122                 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
 123                 DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
 124                 DPI_SEL_IN_BLS
 125         }, {
 126                 DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
 127                 DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
 128                 GAMMA_MOUT_EN_RDMA1
 129         }, {
 130                 DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
 131                 DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
 132                 OD_MOUT_EN_RDMA0
 133         }, {
 134                 DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
 135                 DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
 136                 OD1_MOUT_EN_RDMA1
 137         }, {
 138                 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
 139                 DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
 140                 OVL0_MOUT_EN_COLOR0
 141         }, {
 142                 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
 143                 DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
 144                 COLOR0_SEL_IN_OVL0
 145         }, {
 146                 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
 147                 DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
 148                 OVL_MOUT_EN_RDMA
 149         }, {
 150                 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
 151                 DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
 152                 OVL1_MOUT_EN_COLOR1
 153         }, {
 154                 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
 155                 DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
 156                 COLOR1_SEL_IN_OVL1
 157         }, {
 158                 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
 159                 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
 160                 RDMA0_SOUT_DPI0
 161         }, {
 162                 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
 163                 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
 164                 RDMA0_SOUT_DPI1
 165         }, {
 166                 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
 167                 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
 168                 RDMA0_SOUT_DSI1
 169         }, {
 170                 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
 171                 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
 172                 RDMA0_SOUT_DSI2
 173         }, {
 174                 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
 175                 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
 176                 RDMA0_SOUT_DSI3
 177         }, {
 178                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
 179                 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
 180                 RDMA1_SOUT_DPI0
 181         }, {
 182                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
 183                 DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
 184                 DPI0_SEL_IN_RDMA1
 185         }, {
 186                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
 187                 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
 188                 RDMA1_SOUT_DPI1
 189         }, {
 190                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
 191                 DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
 192                 DPI1_SEL_IN_RDMA1
 193         }, {
 194                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
 195                 DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
 196                 DSI0_SEL_IN_RDMA1
 197         }, {
 198                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
 199                 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
 200                 RDMA1_SOUT_DSI1
 201         }, {
 202                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
 203                 DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
 204                 DSI1_SEL_IN_RDMA1
 205         }, {
 206                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
 207                 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
 208                 RDMA1_SOUT_DSI2
 209         }, {
 210                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
 211                 DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
 212                 DSI2_SEL_IN_RDMA1
 213         }, {
 214                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
 215                 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
 216                 RDMA1_SOUT_DSI3
 217         }, {
 218                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
 219                 DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
 220                 DSI3_SEL_IN_RDMA1
 221         }, {
 222                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
 223                 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
 224                 RDMA2_SOUT_DPI0
 225         }, {
 226                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
 227                 DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
 228                 DPI0_SEL_IN_RDMA2
 229         }, {
 230                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
 231                 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
 232                 RDMA2_SOUT_DPI1
 233         }, {
 234                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
 235                 DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
 236                 DPI1_SEL_IN_RDMA2
 237         }, {
 238                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
 239                 DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
 240                 DSI0_SEL_IN_RDMA2
 241         }, {
 242                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
 243                 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
 244                 RDMA2_SOUT_DSI1
 245         }, {
 246                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
 247                 DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
 248                 DSI1_SEL_IN_RDMA2
 249         }, {
 250                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
 251                 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
 252                 RDMA2_SOUT_DSI2
 253         }, {
 254                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
 255                 DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
 256                 DSI2_SEL_IN_RDMA2
 257         }, {
 258                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
 259                 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
 260                 RDMA2_SOUT_DSI3
 261         }, {
 262                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
 263                 DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
 264                 DSI3_SEL_IN_RDMA2
 265         }, {
 266                 DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
 267                 DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
 268                 UFOE_MOUT_EN_DSI0
 269         }
 270 };
 271
 272 #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */