drivers/scsi/ufs/ufshcd-pltfrm.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Universal Flash Storage Host controller Platform bus based glue driver
   4  * Copyright (C) 2011-2013 Samsung India Software Operations
   5  *
   6  * Authors:
   7  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   8  *      Vinayak Holikatti <h.vinayak@samsung.com>
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/of.h>
  14
  15 #include "ufshcd.h"
  16 #include "ufshcd-pltfrm.h"
  17 #include "unipro.h"
  18
  19 #define UFSHCD_DEFAULT_LANES_PER_DIRECTION              2
  20
  21 static int ufshcd_parse_clock_info(struct ufs_hba *hba)
  22 {
  23         int ret = 0;
  24         int cnt;
  25         int i;
  26         struct device *dev = hba->dev;
  27         struct device_node *np = dev->of_node;
  28         char *name;
  29         u32 *clkfreq = NULL;
  30         struct ufs_clk_info *clki;
  31         int len = 0;
  32         size_t sz = 0;
  33
  34         if (!np)
  35                 goto out;
  36
  37         cnt = of_property_count_strings(np, "clock-names");
  38         if (!cnt || (cnt == -EINVAL)) {
  39                 dev_info(dev, "%s: Unable to find clocks, assuming enabled\n",
  40                                 __func__);
  41         } else if (cnt < 0) {
  42                 dev_err(dev, "%s: count clock strings failed, err %d\n",
  43                                 __func__, cnt);
  44                 ret = cnt;
  45         }
  46
  47         if (cnt <= 0)
  48                 goto out;
  49
  50         if (!of_get_property(np, "freq-table-hz", &len)) {
  51                 dev_info(dev, "freq-table-hz property not specified\n");
  52                 goto out;
  53         }
  54
  55         if (len <= 0)
  56                 goto out;
  57
  58         sz = len / sizeof(*clkfreq);
  59         if (sz != 2 * cnt) {
  60                 dev_err(dev, "%s len mismatch\n", "freq-table-hz");
  61                 ret = -EINVAL;
  62                 goto out;
  63         }
  64
  65         clkfreq = devm_kcalloc(dev, sz, sizeof(*clkfreq),
  66                                GFP_KERNEL);
  67         if (!clkfreq) {
  68                 ret = -ENOMEM;
  69                 goto out;
  70         }
  71
  72         ret = of_property_read_u32_array(np, "freq-table-hz",
  73                         clkfreq, sz);
  74         if (ret && (ret != -EINVAL)) {
  75                 dev_err(dev, "%s: error reading array %d\n",
  76                                 "freq-table-hz", ret);
  77                 return ret;
  78         }
  79
  80         for (i = 0; i < sz; i += 2) {
  81                 ret = of_property_read_string_index(np,
  82                                 "clock-names", i/2, (const char **)&name);
  83                 if (ret)
  84                         goto out;
  85
  86                 clki = devm_kzalloc(dev, sizeof(*clki), GFP_KERNEL);
  87                 if (!clki) {
  88                         ret = -ENOMEM;
  89                         goto out;
  90                 }
  91
  92                 clki->min_freq = clkfreq[i];
  93                 clki->max_freq = clkfreq[i+1];
  94                 clki->name = devm_kstrdup(dev, name, GFP_KERNEL);
  95                 if (!clki->name) {
  96                         ret = -ENOMEM;
  97                         goto out;
  98                 }
  99
 100                 if (!strcmp(name, "ref_clk"))
 101                         clki->keep_link_active = true;
 102                 dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz",
 103                                 clki->min_freq, clki->max_freq, clki->name);
 104                 list_add_tail(&clki->list, &hba->clk_list_head);
 105         }
 106 out:
 107         return ret;
 108 }
 109
 110 #define MAX_PROP_SIZE 32
 111 static int ufshcd_populate_vreg(struct device *dev, const char *name,
 112                 struct ufs_vreg **out_vreg)
 113 {
 114         char prop_name[MAX_PROP_SIZE];
 115         struct ufs_vreg *vreg = NULL;
 116         struct device_node *np = dev->of_node;
 117
 118         if (!np) {
 119                 dev_err(dev, "%s: non DT initialization\n", __func__);
 120                 goto out;
 121         }
 122
 123         snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", name);
 124         if (!of_parse_phandle(np, prop_name, 0)) {
 125                 dev_info(dev, "%s: Unable to find %s regulator, assuming enabled\n",
 126                                 __func__, prop_name);
 127                 goto out;
 128         }
 129
 130         vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
 131         if (!vreg)
 132                 return -ENOMEM;
 133
 134         vreg->name = devm_kstrdup(dev, name, GFP_KERNEL);
 135         if (!vreg->name)
 136                 return -ENOMEM;
 137
 138         snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", name);
 139         if (of_property_read_u32(np, prop_name, &vreg->max_uA)) {
 140                 dev_info(dev, "%s: unable to find %s\n", __func__, prop_name);
 141                 vreg->max_uA = 0;
 142         }
 143 out:
 144         *out_vreg = vreg;
 145         return 0;
 146 }
 147
 148 /**
 149  * ufshcd_parse_regulator_info - get regulator info from device tree
 150  * @hba: per adapter instance
 151  *
 152  * Get regulator info from device tree for vcc, vccq, vccq2 power supplies.
 153  * If any of the supplies are not defined it is assumed that they are always-on
 154  * and hence return zero. If the property is defined but parsing is failed
 155  * then return corresponding error.
 156  */
 157 static int ufshcd_parse_regulator_info(struct ufs_hba *hba)
 158 {
 159         int err;
 160         struct device *dev = hba->dev;
 161         struct ufs_vreg_info *info = &hba->vreg_info;
 162
 163         err = ufshcd_populate_vreg(dev, "vdd-hba", &info->vdd_hba);
 164         if (err)
 165                 goto out;
 166
 167         err = ufshcd_populate_vreg(dev, "vcc", &info->vcc);
 168         if (err)
 169                 goto out;
 170
 171         err = ufshcd_populate_vreg(dev, "vccq", &info->vccq);
 172         if (err)
 173                 goto out;
 174
 175         err = ufshcd_populate_vreg(dev, "vccq2", &info->vccq2);
 176 out:
 177         return err;
 178 }
 179
 180 void ufshcd_pltfrm_shutdown(struct platform_device *pdev)
 181 {
 182         ufshcd_shutdown((struct ufs_hba *)platform_get_drvdata(pdev));
 183 }
 184 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_shutdown);
 185
 186 static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
 187 {
 188         struct device *dev = hba->dev;
 189         int ret;
 190
 191         ret = of_property_read_u32(dev->of_node, "lanes-per-direction",
 192                 &hba->lanes_per_direction);
 193         if (ret) {
 194                 dev_dbg(hba->dev,
 195                         "%s: failed to read lanes-per-direction, ret=%d\n",
 196                         __func__, ret);
 197                 hba->lanes_per_direction = UFSHCD_DEFAULT_LANES_PER_DIRECTION;
 198         }
 199 }
 200
 201 /**
 202  * ufshcd_get_pwr_dev_param - get finally agreed attributes for
 203  *                            power mode change
 204  * @pltfrm_param: pointer to platform parameters
 205  * @dev_max: pointer to device attributes
 206  * @agreed_pwr: returned agreed attributes
 207  *
 208  * Returns 0 on success, non-zero value on failure
 209  */
 210 int ufshcd_get_pwr_dev_param(struct ufs_dev_params *pltfrm_param,
 211                              struct ufs_pa_layer_attr *dev_max,
 212                              struct ufs_pa_layer_attr *agreed_pwr)
 213 {
 214         int min_pltfrm_gear;
 215         int min_dev_gear;
 216         bool is_dev_sup_hs = false;
 217         bool is_pltfrm_max_hs = false;
 218
 219         if (dev_max->pwr_rx == FAST_MODE)
 220                 is_dev_sup_hs = true;
 221
 222         if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
 223                 is_pltfrm_max_hs = true;
 224                 min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
 225                                         pltfrm_param->hs_tx_gear);
 226         } else {
 227                 min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
 228                                         pltfrm_param->pwm_tx_gear);
 229         }
 230
 231         /*
 232          * device doesn't support HS but
 233          * pltfrm_param->desired_working_mode is HS,
 234          * thus device and pltfrm_param don't agree
 235          */
 236         if (!is_dev_sup_hs && is_pltfrm_max_hs) {
 237                 pr_info("%s: device doesn't support HS\n",
 238                         __func__);
 239                 return -ENOTSUPP;
 240         } else if (is_dev_sup_hs && is_pltfrm_max_hs) {
 241                 /*
 242                  * since device supports HS, it supports FAST_MODE.
 243                  * since pltfrm_param->desired_working_mode is also HS
 244                  * then final decision (FAST/FASTAUTO) is done according
 245                  * to pltfrm_params as it is the restricting factor
 246                  */
 247                 agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
 248                 agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
 249         } else {
 250                 /*
 251                  * here pltfrm_param->desired_working_mode is PWM.
 252                  * it doesn't matter whether device supports HS or PWM,
 253                  * in both cases pltfrm_param->desired_working_mode will
 254                  * determine the mode
 255                  */
 256                 agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
 257                 agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
 258         }
 259
 260         /*
 261          * we would like tx to work in the minimum number of lanes
 262          * between device capability and vendor preferences.
 263          * the same decision will be made for rx
 264          */
 265         agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
 266                                     pltfrm_param->tx_lanes);
 267         agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
 268                                     pltfrm_param->rx_lanes);
 269
 270         /* device maximum gear is the minimum between device rx and tx gears */
 271         min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
 272
 273         /*
 274          * if both device capabilities and vendor pre-defined preferences are
 275          * both HS or both PWM then set the minimum gear to be the chosen
 276          * working gear.
 277          * if one is PWM and one is HS then the one that is PWM get to decide
 278          * what is the gear, as it is the one that also decided previously what
 279          * pwr the device will be configured to.
 280          */
 281         if ((is_dev_sup_hs && is_pltfrm_max_hs) ||
 282             (!is_dev_sup_hs && !is_pltfrm_max_hs)) {
 283                 agreed_pwr->gear_rx =
 284                         min_t(u32, min_dev_gear, min_pltfrm_gear);
 285         } else if (!is_dev_sup_hs) {
 286                 agreed_pwr->gear_rx = min_dev_gear;
 287         } else {
 288                 agreed_pwr->gear_rx = min_pltfrm_gear;
 289         }
 290         agreed_pwr->gear_tx = agreed_pwr->gear_rx;
 291
 292         agreed_pwr->hs_rate = pltfrm_param->hs_rate;
 293
 294         return 0;
 295 }
 296 EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
 297
 298 void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
 299 {
 300         dev_param->tx_lanes = 2;
 301         dev_param->rx_lanes = 2;
 302         dev_param->hs_rx_gear = UFS_HS_G3;
 303         dev_param->hs_tx_gear = UFS_HS_G3;
 304         dev_param->pwm_rx_gear = UFS_PWM_G4;
 305         dev_param->pwm_tx_gear = UFS_PWM_G4;
 306         dev_param->rx_pwr_pwm = SLOW_MODE;
 307         dev_param->tx_pwr_pwm = SLOW_MODE;
 308         dev_param->rx_pwr_hs = FAST_MODE;
 309         dev_param->tx_pwr_hs = FAST_MODE;
 310         dev_param->hs_rate = PA_HS_MODE_B;
 311         dev_param->desired_working_mode = UFS_HS_MODE;
 312 }
 313 EXPORT_SYMBOL_GPL(ufshcd_init_pwr_dev_param);
 314
 315 /**
 316  * ufshcd_pltfrm_init - probe routine of the driver
 317  * @pdev: pointer to Platform device handle
 318  * @vops: pointer to variant ops
 319  *
 320  * Returns 0 on success, non-zero value on failure
 321  */
 322 int ufshcd_pltfrm_init(struct platform_device *pdev,
 323                        const struct ufs_hba_variant_ops *vops)
 324 {
 325         struct ufs_hba *hba;
 326         void __iomem *mmio_base;
 327         int irq, err;
 328         struct device *dev = &pdev->dev;
 329
 330         mmio_base = devm_platform_ioremap_resource(pdev, 0);
 331         if (IS_ERR(mmio_base)) {
 332                 err = PTR_ERR(mmio_base);
 333                 goto out;
 334         }
 335
 336         irq = platform_get_irq(pdev, 0);
 337         if (irq < 0) {
 338                 err = irq;
 339                 goto out;
 340         }
 341
 342         err = ufshcd_alloc_host(dev, &hba);
 343         if (err) {
 344                 dev_err(&pdev->dev, "Allocation failed\n");
 345                 goto out;
 346         }
 347
 348         hba->vops = vops;
 349
 350         err = ufshcd_parse_clock_info(hba);
 351         if (err) {
 352                 dev_err(&pdev->dev, "%s: clock parse failed %d\n",
 353                                 __func__, err);
 354                 goto dealloc_host;
 355         }
 356         err = ufshcd_parse_regulator_info(hba);
 357         if (err) {
 358                 dev_err(&pdev->dev, "%s: regulator init failed %d\n",
 359                                 __func__, err);
 360                 goto dealloc_host;
 361         }
 362
 363         ufshcd_init_lanes_per_dir(hba);
 364
 365         err = ufshcd_init(hba, mmio_base, irq);
 366         if (err) {
 367                 dev_err(dev, "Initialization failed\n");
 368                 goto dealloc_host;
 369         }
 370
 371         pm_runtime_set_active(&pdev->dev);
 372         pm_runtime_enable(&pdev->dev);
 373
 374         return 0;
 375
 376 dealloc_host:
 377         ufshcd_dealloc_host(hba);
 378 out:
 379         return err;
 380 }
 381 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_init);
 382
 383 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
 384 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
 385 MODULE_DESCRIPTION("UFS host controller Platform bus based glue driver");
 386 MODULE_LICENSE("GPL");
 387 MODULE_VERSION(UFSHCD_DRIVER_VERSION);