drivers/scsi/ufs/ufshcd-pci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Universal Flash Storage Host controller PCI glue driver
   4  *
   5  * This code is based on drivers/scsi/ufs/ufshcd-pci.c
   6  * Copyright (C) 2011-2013 Samsung India Software Operations
   7  *
   8  * Authors:
   9  *      Santosh Yaraganavi <santosh.sy@samsung.com>
  10  *      Vinayak Holikatti <h.vinayak@samsung.com>
  11  */
  12
  13 #include "ufshcd.h"
  14 #include <linux/pci.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/pm_qos.h>
  17 #include <linux/debugfs.h>
  18
  19 struct intel_host {
  20         u32             active_ltr;
  21         u32             idle_ltr;
  22         struct dentry   *debugfs_root;
  23 };
  24
  25 static int ufs_intel_disable_lcc(struct ufs_hba *hba)
  26 {
  27         u32 attr = UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE);
  28         u32 lcc_enable = 0;
  29
  30         ufshcd_dme_get(hba, attr, &lcc_enable);
  31         if (lcc_enable)
  32                 ufshcd_disable_host_tx_lcc(hba);
  33
  34         return 0;
  35 }
  36
  37 static int ufs_intel_link_startup_notify(struct ufs_hba *hba,
  38                                          enum ufs_notify_change_status status)
  39 {
  40         int err = 0;
  41
  42         switch (status) {
  43         case PRE_CHANGE:
  44                 err = ufs_intel_disable_lcc(hba);
  45                 break;
  46         case POST_CHANGE:
  47                 break;
  48         default:
  49                 break;
  50         }
  51
  52         return err;
  53 }
  54
  55 #define INTEL_ACTIVELTR         0x804
  56 #define INTEL_IDLELTR           0x808
  57
  58 #define INTEL_LTR_REQ           BIT(15)
  59 #define INTEL_LTR_SCALE_MASK    GENMASK(11, 10)
  60 #define INTEL_LTR_SCALE_1US     (2 << 10)
  61 #define INTEL_LTR_SCALE_32US    (3 << 10)
  62 #define INTEL_LTR_VALUE_MASK    GENMASK(9, 0)
  63
  64 static void intel_cache_ltr(struct ufs_hba *hba)
  65 {
  66         struct intel_host *host = ufshcd_get_variant(hba);
  67
  68         host->active_ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
  69         host->idle_ltr = readl(hba->mmio_base + INTEL_IDLELTR);
  70 }
  71
  72 static void intel_ltr_set(struct device *dev, s32 val)
  73 {
  74         struct ufs_hba *hba = dev_get_drvdata(dev);
  75         struct intel_host *host = ufshcd_get_variant(hba);
  76         u32 ltr;
  77
  78         pm_runtime_get_sync(dev);
  79
  80         /*
  81          * Program latency tolerance (LTR) accordingly what has been asked
  82          * by the PM QoS layer or disable it in case we were passed
  83          * negative value or PM_QOS_LATENCY_ANY.
  84          */
  85         ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
  86
  87         if (val == PM_QOS_LATENCY_ANY || val < 0) {
  88                 ltr &= ~INTEL_LTR_REQ;
  89         } else {
  90                 ltr |= INTEL_LTR_REQ;
  91                 ltr &= ~INTEL_LTR_SCALE_MASK;
  92                 ltr &= ~INTEL_LTR_VALUE_MASK;
  93
  94                 if (val > INTEL_LTR_VALUE_MASK) {
  95                         val >>= 5;
  96                         if (val > INTEL_LTR_VALUE_MASK)
  97                                 val = INTEL_LTR_VALUE_MASK;
  98                         ltr |= INTEL_LTR_SCALE_32US | val;
  99                 } else {
 100                         ltr |= INTEL_LTR_SCALE_1US | val;
 101                 }
 102         }
 103
 104         if (ltr == host->active_ltr)
 105                 goto out;
 106
 107         writel(ltr, hba->mmio_base + INTEL_ACTIVELTR);
 108         writel(ltr, hba->mmio_base + INTEL_IDLELTR);
 109
 110         /* Cache the values into intel_host structure */
 111         intel_cache_ltr(hba);
 112 out:
 113         pm_runtime_put(dev);
 114 }
 115
 116 static void intel_ltr_expose(struct device *dev)
 117 {
 118         dev->power.set_latency_tolerance = intel_ltr_set;
 119         dev_pm_qos_expose_latency_tolerance(dev);
 120 }
 121
 122 static void intel_ltr_hide(struct device *dev)
 123 {
 124         dev_pm_qos_hide_latency_tolerance(dev);
 125         dev->power.set_latency_tolerance = NULL;
 126 }
 127
 128 static void intel_add_debugfs(struct ufs_hba *hba)
 129 {
 130         struct dentry *dir = debugfs_create_dir(dev_name(hba->dev), NULL);
 131         struct intel_host *host = ufshcd_get_variant(hba);
 132
 133         intel_cache_ltr(hba);
 134
 135         host->debugfs_root = dir;
 136         debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr);
 137         debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr);
 138 }
 139
 140 static void intel_remove_debugfs(struct ufs_hba *hba)
 141 {
 142         struct intel_host *host = ufshcd_get_variant(hba);
 143
 144         debugfs_remove_recursive(host->debugfs_root);
 145 }
 146
 147 static int ufs_intel_common_init(struct ufs_hba *hba)
 148 {
 149         struct intel_host *host;
 150
 151         host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL);
 152         if (!host)
 153                 return -ENOMEM;
 154         ufshcd_set_variant(hba, host);
 155         intel_ltr_expose(hba->dev);
 156         intel_add_debugfs(hba);
 157         return 0;
 158 }
 159
 160 static void ufs_intel_common_exit(struct ufs_hba *hba)
 161 {
 162         intel_remove_debugfs(hba);
 163         intel_ltr_hide(hba->dev);
 164 }
 165
 166 static int ufs_intel_ehl_init(struct ufs_hba *hba)
 167 {
 168         hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
 169         return ufs_intel_common_init(hba);
 170 }
 171
 172 static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = {
 173         .name                   = "intel-pci",
 174         .init                   = ufs_intel_common_init,
 175         .exit                   = ufs_intel_common_exit,
 176         .link_startup_notify    = ufs_intel_link_startup_notify,
 177 };
 178
 179 static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = {
 180         .name                   = "intel-pci",
 181         .init                   = ufs_intel_ehl_init,
 182         .exit                   = ufs_intel_common_exit,
 183         .link_startup_notify    = ufs_intel_link_startup_notify,
 184 };
 185
 186 #ifdef CONFIG_PM_SLEEP
 187 /**
 188  * ufshcd_pci_suspend - suspend power management function
 189  * @dev: pointer to PCI device handle
 190  *
 191  * Returns 0 if successful
 192  * Returns non-zero otherwise
 193  */
 194 static int ufshcd_pci_suspend(struct device *dev)
 195 {
 196         return ufshcd_system_suspend(dev_get_drvdata(dev));
 197 }
 198
 199 /**
 200  * ufshcd_pci_resume - resume power management function
 201  * @dev: pointer to PCI device handle
 202  *
 203  * Returns 0 if successful
 204  * Returns non-zero otherwise
 205  */
 206 static int ufshcd_pci_resume(struct device *dev)
 207 {
 208         return ufshcd_system_resume(dev_get_drvdata(dev));
 209 }
 210 #endif /* !CONFIG_PM_SLEEP */
 211
 212 #ifdef CONFIG_PM
 213 static int ufshcd_pci_runtime_suspend(struct device *dev)
 214 {
 215         return ufshcd_runtime_suspend(dev_get_drvdata(dev));
 216 }
 217 static int ufshcd_pci_runtime_resume(struct device *dev)
 218 {
 219         return ufshcd_runtime_resume(dev_get_drvdata(dev));
 220 }
 221 static int ufshcd_pci_runtime_idle(struct device *dev)
 222 {
 223         return ufshcd_runtime_idle(dev_get_drvdata(dev));
 224 }
 225 #endif /* !CONFIG_PM */
 226
 227 /**
 228  * ufshcd_pci_shutdown - main function to put the controller in reset state
 229  * @pdev: pointer to PCI device handle
 230  */
 231 static void ufshcd_pci_shutdown(struct pci_dev *pdev)
 232 {
 233         ufshcd_shutdown((struct ufs_hba *)pci_get_drvdata(pdev));
 234 }
 235
 236 /**
 237  * ufshcd_pci_remove - de-allocate PCI/SCSI host and host memory space
 238  *              data structure memory
 239  * @pdev: pointer to PCI handle
 240  */
 241 static void ufshcd_pci_remove(struct pci_dev *pdev)
 242 {
 243         struct ufs_hba *hba = pci_get_drvdata(pdev);
 244
 245         pm_runtime_forbid(&pdev->dev);
 246         pm_runtime_get_noresume(&pdev->dev);
 247         ufshcd_remove(hba);
 248         ufshcd_dealloc_host(hba);
 249 }
 250
 251 /**
 252  * ufshcd_pci_probe - probe routine of the driver
 253  * @pdev: pointer to PCI device handle
 254  * @id: PCI device id
 255  *
 256  * Returns 0 on success, non-zero value on failure
 257  */
 258 static int
 259 ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 260 {
 261         struct ufs_hba *hba;
 262         void __iomem *mmio_base;
 263         int err;
 264
 265         err = pcim_enable_device(pdev);
 266         if (err) {
 267                 dev_err(&pdev->dev, "pcim_enable_device failed\n");
 268                 return err;
 269         }
 270
 271         pci_set_master(pdev);
 272
 273         err = pcim_iomap_regions(pdev, 1 << 0, UFSHCD);
 274         if (err < 0) {
 275                 dev_err(&pdev->dev, "request and iomap failed\n");
 276                 return err;
 277         }
 278
 279         mmio_base = pcim_iomap_table(pdev)[0];
 280
 281         err = ufshcd_alloc_host(&pdev->dev, &hba);
 282         if (err) {
 283                 dev_err(&pdev->dev, "Allocation failed\n");
 284                 return err;
 285         }
 286
 287         pci_set_drvdata(pdev, hba);
 288
 289         hba->vops = (struct ufs_hba_variant_ops *)id->driver_data;
 290
 291         err = ufshcd_init(hba, mmio_base, pdev->irq);
 292         if (err) {
 293                 dev_err(&pdev->dev, "Initialization failed\n");
 294                 ufshcd_dealloc_host(hba);
 295                 return err;
 296         }
 297
 298         pm_runtime_put_noidle(&pdev->dev);
 299         pm_runtime_allow(&pdev->dev);
 300
 301         return 0;
 302 }
 303
 304 static const struct dev_pm_ops ufshcd_pci_pm_ops = {
 305         SET_SYSTEM_SLEEP_PM_OPS(ufshcd_pci_suspend,
 306                                 ufshcd_pci_resume)
 307         SET_RUNTIME_PM_OPS(ufshcd_pci_runtime_suspend,
 308                            ufshcd_pci_runtime_resume,
 309                            ufshcd_pci_runtime_idle)
 310 };
 311
 312 static const struct pci_device_id ufshcd_pci_tbl[] = {
 313         { PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 314         { PCI_VDEVICE(INTEL, 0x9DFA), (kernel_ulong_t)&ufs_intel_cnl_hba_vops },
 315         { PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
 316         { PCI_VDEVICE(INTEL, 0x4B43), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
 317         { }     /* terminate list */
 318 };
 319
 320 MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl);
 321
 322 static struct pci_driver ufshcd_pci_driver = {
 323         .name = UFSHCD,
 324         .id_table = ufshcd_pci_tbl,
 325         .probe = ufshcd_pci_probe,
 326         .remove = ufshcd_pci_remove,
 327         .shutdown = ufshcd_pci_shutdown,
 328         .driver = {
 329                 .pm = &ufshcd_pci_pm_ops
 330         },
 331 };
 332
 333 module_pci_driver(ufshcd_pci_driver);
 334
 335 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
 336 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
 337 MODULE_DESCRIPTION("UFS host controller PCI glue driver");
 338 MODULE_LICENSE("GPL");
 339 MODULE_VERSION(UFSHCD_DRIVER_VERSION);