drivers/scsi/pm8001/pm80xx_hwi.c

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions, and the following disclaimer,
  12  * without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  * substantially similar to the "NO WARRANTY" disclaimer below
  15  * ("Disclaimer") and any redistribution must be conditioned upon
  16  * including a substantially similar Disclaimer requirement for further
  17  * binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  * of any contributors may be used to endorse or promote products derived
  20  * from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm80xx_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45 #include "pm80xx_tracepoints.h"
  46
  47 #define SMP_DIRECT 1
  48 #define SMP_INDIRECT 2
  49
  50
  51 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
  52 {
  53         u32 reg_val;
  54         unsigned long start;
  55         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
  56         /* confirm the setting is written */
  57         start = jiffies + HZ; /* 1 sec */
  58         do {
  59                 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
  60         } while ((reg_val != shift_value) && time_before(jiffies, start));
  61         if (reg_val != shift_value) {
  62                 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",
  63                            reg_val);
  64                 return -1;
  65         }
  66         return 0;
  67 }
  68
  69 static void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
  70                                 __le32 *destination,
  71                                 u32 dw_count, u32 bus_base_number)
  72 {
  73         u32 index, value, offset;
  74
  75         for (index = 0; index < dw_count; index += 4, destination++) {
  76                 offset = (soffset + index);
  77                 if (offset < (64 * 1024)) {
  78                         value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
  79                         *destination = cpu_to_le32(value);
  80                 }
  81         }
  82         return;
  83 }
  84
  85 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  86         struct device_attribute *attr, char *buf)
  87 {
  88         struct Scsi_Host *shost = class_to_shost(cdev);
  89         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  90         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  91         void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
  92         u32 accum_len, reg_val, index, *temp;
  93         u32 status = 1;
  94         unsigned long start;
  95         u8 *direct_data;
  96         char *fatal_error_data = buf;
  97         u32 length_to_read;
  98         u32 offset;
  99
 100         pm8001_ha->forensic_info.data_buf.direct_data = buf;
 101         if (pm8001_ha->chip_id == chip_8001) {
 102                 pm8001_ha->forensic_info.data_buf.direct_data +=
 103                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 104                         "Not supported for SPC controller");
 105                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 106                         (char *)buf;
 107         }
 108         /* initialize variables for very first call from host application */
 109         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 110                 pm8001_dbg(pm8001_ha, IO,
 111                            "forensic_info TYPE_NON_FATAL..............\n");
 112                 direct_data = (u8 *)fatal_error_data;
 113                 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
 114                 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
 115                 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 116                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 117                 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
 118
 119                 /* Write signature to fatal dump table */
 120                 pm8001_mw32(fatal_table_address,
 121                                 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
 122
 123                 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
 124                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status);
 125                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",
 126                            pm8001_ha->forensic_info.data_buf.read_len);
 127                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",
 128                            pm8001_ha->forensic_info.data_buf.direct_len);
 129                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",
 130                            pm8001_ha->forensic_info.data_buf.direct_offset);
 131         }
 132         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 133                 /* start to get data */
 134                 /* Program the MEMBASE II Shifting Register with 0x00.*/
 135                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 136                                 pm8001_ha->fatal_forensic_shift_offset);
 137                 pm8001_ha->forensic_last_offset = 0;
 138                 pm8001_ha->forensic_fatal_step = 0;
 139                 pm8001_ha->fatal_bar_loc = 0;
 140         }
 141
 142         /* Read until accum_len is retrieved */
 143         accum_len = pm8001_mr32(fatal_table_address,
 144                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 145         /* Determine length of data between previously stored transfer length
 146          * and current accumulated transfer length
 147          */
 148         length_to_read =
 149                 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
 150         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",
 151                    accum_len);
 152         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",
 153                    length_to_read);
 154         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",
 155                    pm8001_ha->forensic_last_offset);
 156         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",
 157                    pm8001_ha->forensic_info.data_buf.read_len);
 158         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",
 159                    pm8001_ha->forensic_info.data_buf.direct_len);
 160         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",
 161                    pm8001_ha->forensic_info.data_buf.direct_offset);
 162
 163         /* If accumulated length failed to read correctly fail the attempt.*/
 164         if (accum_len == 0xFFFFFFFF) {
 165                 pm8001_dbg(pm8001_ha, IO,
 166                            "Possible PCI issue 0x%x not expected\n",
 167                            accum_len);
 168                 return status;
 169         }
 170         /* If accumulated length is zero fail the attempt */
 171         if (accum_len == 0) {
 172                 pm8001_ha->forensic_info.data_buf.direct_data +=
 173                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 174                         "%08x ", 0xFFFFFFFF);
 175                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 176                         (char *)buf;
 177         }
 178         /* Accumulated length is good so start capturing the first data */
 179         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 180         if (pm8001_ha->forensic_fatal_step == 0) {
 181 moreData:
 182                 /* If data to read is less than SYSFS_OFFSET then reduce the
 183                  * length of dataLen
 184                  */
 185                 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
 186                                 > length_to_read) {
 187                         pm8001_ha->forensic_info.data_buf.direct_len =
 188                                 length_to_read -
 189                                 pm8001_ha->forensic_last_offset;
 190                 } else {
 191                         pm8001_ha->forensic_info.data_buf.direct_len =
 192                                 SYSFS_OFFSET;
 193                 }
 194                 if (pm8001_ha->forensic_info.data_buf.direct_data) {
 195                         /* Data is in bar, copy to host memory */
 196                         pm80xx_pci_mem_copy(pm8001_ha,
 197                         pm8001_ha->fatal_bar_loc,
 198                         pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
 199                         pm8001_ha->forensic_info.data_buf.direct_len, 1);
 200                 }
 201                 pm8001_ha->fatal_bar_loc +=
 202                         pm8001_ha->forensic_info.data_buf.direct_len;
 203                 pm8001_ha->forensic_info.data_buf.direct_offset +=
 204                         pm8001_ha->forensic_info.data_buf.direct_len;
 205                 pm8001_ha->forensic_last_offset +=
 206                         pm8001_ha->forensic_info.data_buf.direct_len;
 207                 pm8001_ha->forensic_info.data_buf.read_len =
 208                         pm8001_ha->forensic_info.data_buf.direct_len;
 209
 210                 if (pm8001_ha->forensic_last_offset  >= length_to_read) {
 211                         pm8001_ha->forensic_info.data_buf.direct_data +=
 212                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 213                                 "%08x ", 3);
 214                         for (index = 0; index <
 215                                 (pm8001_ha->forensic_info.data_buf.direct_len
 216                                  / 4); index++) {
 217                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 218                                 sprintf(
 219                                 pm8001_ha->forensic_info.data_buf.direct_data,
 220                                 "%08x ", *(temp + index));
 221                         }
 222
 223                         pm8001_ha->fatal_bar_loc = 0;
 224                         pm8001_ha->forensic_fatal_step = 1;
 225                         pm8001_ha->fatal_forensic_shift_offset = 0;
 226                         pm8001_ha->forensic_last_offset = 0;
 227                         status = 0;
 228                         offset = (int)
 229                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 230                         - (char *)buf);
 231                         pm8001_dbg(pm8001_ha, IO,
 232                                    "get_fatal_spcv:return1 0x%x\n", offset);
 233                         return (char *)pm8001_ha->
 234                                 forensic_info.data_buf.direct_data -
 235                                 (char *)buf;
 236                 }
 237                 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
 238                         pm8001_ha->forensic_info.data_buf.direct_data +=
 239                                 sprintf(pm8001_ha->
 240                                         forensic_info.data_buf.direct_data,
 241                                         "%08x ", 2);
 242                         for (index = 0; index <
 243                                 (pm8001_ha->forensic_info.data_buf.direct_len
 244                                  / 4); index++) {
 245                                 pm8001_ha->forensic_info.data_buf.direct_data
 246                                         += sprintf(pm8001_ha->
 247                                         forensic_info.data_buf.direct_data,
 248                                         "%08x ", *(temp + index));
 249                         }
 250                         status = 0;
 251                         offset = (int)
 252                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 253                         - (char *)buf);
 254                         pm8001_dbg(pm8001_ha, IO,
 255                                    "get_fatal_spcv:return2 0x%x\n", offset);
 256                         return (char *)pm8001_ha->
 257                                 forensic_info.data_buf.direct_data -
 258                                 (char *)buf;
 259                 }
 260
 261                 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
 262                 pm8001_ha->forensic_info.data_buf.direct_data +=
 263                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 264                                 "%08x ", 2);
 265                 for (index = 0; index <
 266                         (pm8001_ha->forensic_info.data_buf.direct_len
 267                          / 4) ; index++) {
 268                         pm8001_ha->forensic_info.data_buf.direct_data +=
 269                                 sprintf(pm8001_ha->
 270                                 forensic_info.data_buf.direct_data,
 271                                 "%08x ", *(temp + index));
 272                 }
 273                 pm8001_ha->fatal_forensic_shift_offset += 0x100;
 274                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 275                         pm8001_ha->fatal_forensic_shift_offset);
 276                 pm8001_ha->fatal_bar_loc = 0;
 277                 status = 0;
 278                 offset = (int)
 279                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 280                         - (char *)buf);
 281                 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",
 282                            offset);
 283                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 284                         (char *)buf;
 285         }
 286         if (pm8001_ha->forensic_fatal_step == 1) {
 287                 /* store previous accumulated length before triggering next
 288                  * accumulated length update
 289                  */
 290                 pm8001_ha->forensic_preserved_accumulated_transfer =
 291                         pm8001_mr32(fatal_table_address,
 292                         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 293
 294                 /* continue capturing the fatal log until Dump status is 0x3 */
 295                 if (pm8001_mr32(fatal_table_address,
 296                         MPI_FATAL_EDUMP_TABLE_STATUS) <
 297                         MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
 298
 299                         /* reset fddstat bit by writing to zero*/
 300                         pm8001_mw32(fatal_table_address,
 301                                         MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
 302
 303                         /* set dump control value to '1' so that new data will
 304                          * be transferred to shared memory
 305                          */
 306                         pm8001_mw32(fatal_table_address,
 307                                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
 308                                 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 309
 310                         /*Poll FDDHSHK  until clear */
 311                         start = jiffies + (2 * HZ); /* 2 sec */
 312
 313                         do {
 314                                 reg_val = pm8001_mr32(fatal_table_address,
 315                                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
 316                         } while ((reg_val) && time_before(jiffies, start));
 317
 318                         if (reg_val != 0) {
 319                                 pm8001_dbg(pm8001_ha, FAIL,
 320                                            "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
 321                                            reg_val);
 322                                /* Fail the dump if a timeout occurs */
 323                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 324                                 sprintf(
 325                                 pm8001_ha->forensic_info.data_buf.direct_data,
 326                                 "%08x ", 0xFFFFFFFF);
 327                                 return((char *)
 328                                 pm8001_ha->forensic_info.data_buf.direct_data
 329                                 - (char *)buf);
 330                         }
 331                         /* Poll status register until set to 2 or
 332                          * 3 for up to 2 seconds
 333                          */
 334                         start = jiffies + (2 * HZ); /* 2 sec */
 335
 336                         do {
 337                                 reg_val = pm8001_mr32(fatal_table_address,
 338                                         MPI_FATAL_EDUMP_TABLE_STATUS);
 339                         } while (((reg_val != 2) && (reg_val != 3)) &&
 340                                         time_before(jiffies, start));
 341
 342                         if (reg_val < 2) {
 343                                 pm8001_dbg(pm8001_ha, FAIL,
 344                                            "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
 345                                            reg_val);
 346                                 /* Fail the dump if a timeout occurs */
 347                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 348                                 sprintf(
 349                                 pm8001_ha->forensic_info.data_buf.direct_data,
 350                                 "%08x ", 0xFFFFFFFF);
 351                                 return((char *)pm8001_ha->forensic_info.data_buf.direct_data -
 352                                                 (char *)buf);
 353                         }
 354         /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */
 355                         pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */
 356                         pm8001_cw32(pm8001_ha, 0,
 357                                         MEMBASE_II_SHIFT_REGISTER,
 358                                         pm8001_ha->fatal_forensic_shift_offset);
 359                 }
 360                 /* Read the next block of the debug data.*/
 361                 length_to_read = pm8001_mr32(fatal_table_address,
 362                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
 363                 pm8001_ha->forensic_preserved_accumulated_transfer;
 364                 if (length_to_read != 0x0) {
 365                         pm8001_ha->forensic_fatal_step = 0;
 366                         goto moreData;
 367                 } else {
 368                         pm8001_ha->forensic_info.data_buf.direct_data +=
 369                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 370                                 "%08x ", 4);
 371                         pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
 372                         pm8001_ha->forensic_info.data_buf.direct_len =  0;
 373                         pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 374                         pm8001_ha->forensic_info.data_buf.read_len = 0;
 375                 }
 376         }
 377         offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
 378                         - (char *)buf);
 379         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);
 380         return ((char *)pm8001_ha->forensic_info.data_buf.direct_data -
 381                 (char *)buf);
 382 }
 383
 384 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
 385  * location by the firmware.
 386  */
 387 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
 388         struct device_attribute *attr, char *buf)
 389 {
 390         struct Scsi_Host *shost = class_to_shost(cdev);
 391         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 392         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
 393         void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
 394         u32 accum_len = 0;
 395         u32 total_len = 0;
 396         u32 reg_val = 0;
 397         u32 *temp = NULL;
 398         u32 index = 0;
 399         u32 output_length;
 400         unsigned long start = 0;
 401         char *buf_copy = buf;
 402
 403         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 404         if (++pm8001_ha->non_fatal_count == 1) {
 405                 if (pm8001_ha->chip_id == chip_8001) {
 406                         snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 407                                 PAGE_SIZE, "Not supported for SPC controller");
 408                         return 0;
 409                 }
 410                 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n");
 411                 /*
 412                  * Step 1: Write the host buffer parameters in the MPI Fatal and
 413                  * Non-Fatal Error Dump Capture Table.This is the buffer
 414                  * where debug data will be DMAed to.
 415                  */
 416                 pm8001_mw32(nonfatal_table_address,
 417                 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
 418                 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
 419
 420                 pm8001_mw32(nonfatal_table_address,
 421                 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
 422                 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
 423
 424                 pm8001_mw32(nonfatal_table_address,
 425                 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
 426
 427                 /* Optionally, set the DUMPCTRL bit to 1 if the host
 428                  * keeps sending active I/Os while capturing the non-fatal
 429                  * debug data. Otherwise, leave this bit set to zero
 430                  */
 431                 pm8001_mw32(nonfatal_table_address,
 432                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 433
 434                 /*
 435                  * Step 2: Clear Accumulative Length of Debug Data Transferred
 436                  * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
 437                  * Capture Table to zero.
 438                  */
 439                 pm8001_mw32(nonfatal_table_address,
 440                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
 441
 442                 /* initiallize previous accumulated length to 0 */
 443                 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
 444                 pm8001_ha->non_fatal_read_length = 0;
 445         }
 446
 447         total_len = pm8001_mr32(nonfatal_table_address,
 448                         MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
 449         /*
 450          * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
 451          * field and then request that the SPCv controller transfer the debug
 452          * data by setting bit 7 of the Inbound Doorbell Set Register.
 453          */
 454         pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
 455         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
 456                         SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
 457
 458         /*
 459          * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
 460          * 2 seconds) until register bit 7 is cleared.
 461          * This step only indicates the request is accepted by the controller.
 462          */
 463         start = jiffies + (2 * HZ); /* 2 sec */
 464         do {
 465                 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
 466                         SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
 467         } while ((reg_val != 0) && time_before(jiffies, start));
 468
 469         /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
 470          * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
 471          * the MPI Fatal and Non-Fatal Error Dump Capture Table.
 472          */
 473         start = jiffies + (2 * HZ); /* 2 sec */
 474         do {
 475                 reg_val = pm8001_mr32(nonfatal_table_address,
 476                                 MPI_FATAL_EDUMP_TABLE_STATUS);
 477         } while ((!reg_val) && time_before(jiffies, start));
 478
 479         if ((reg_val == 0x00) ||
 480                 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
 481                 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
 482                 pm8001_ha->non_fatal_read_length = 0;
 483                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
 484                 pm8001_ha->non_fatal_count = 0;
 485                 return (buf_copy - buf);
 486         } else if (reg_val ==
 487                         MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
 488                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
 489         } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
 490                 (pm8001_ha->non_fatal_read_length >= total_len)) {
 491                 pm8001_ha->non_fatal_read_length = 0;
 492                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
 493                 pm8001_ha->non_fatal_count = 0;
 494         }
 495         accum_len = pm8001_mr32(nonfatal_table_address,
 496                         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 497         output_length = accum_len -
 498                 pm8001_ha->forensic_preserved_accumulated_transfer;
 499
 500         for (index = 0; index < output_length/4; index++)
 501                 buf_copy += snprintf(buf_copy, PAGE_SIZE,
 502                                 "%08x ", *(temp+index));
 503
 504         pm8001_ha->non_fatal_read_length += output_length;
 505
 506         /* store current accumulated length to use in next iteration as
 507          * the previous accumulated length
 508          */
 509         pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
 510         return (buf_copy - buf);
 511 }
 512
 513 /**
 514  * read_main_config_table - read the configure table and save it.
 515  * @pm8001_ha: our hba card information
 516  */
 517 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
 518 {
 519         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 520
 521         pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
 522                 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
 523         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
 524                 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
 525         pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
 526                 pm8001_mr32(address, MAIN_FW_REVISION);
 527         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
 528                 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
 529         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl      =
 530                 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
 531         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
 532                 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
 533         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
 534                 pm8001_mr32(address, MAIN_GST_OFFSET);
 535         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
 536                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
 537         pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
 538                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
 539
 540         /* read Error Dump Offset and Length */
 541         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
 542                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
 543         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
 544                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
 545         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
 546                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
 547         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
 548                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
 549
 550         /* read GPIO LED settings from the configuration table */
 551         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
 552                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
 553
 554         /* read analog Setting offset from the configuration table */
 555         pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
 556                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
 557
 558         pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
 559                 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
 560         pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
 561                 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
 562         /* read port recover and reset timeout */
 563         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
 564                 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
 565         /* read ILA and inactive firmware version */
 566         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
 567                 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
 568         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
 569                 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
 570
 571         pm8001_dbg(pm8001_ha, DEV,
 572                    "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
 573                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
 574                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
 575                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
 576
 577         pm8001_dbg(pm8001_ha, DEV,
 578                    "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
 579                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
 580                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
 581                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
 582                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
 583                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
 584
 585         pm8001_dbg(pm8001_ha, DEV,
 586                    "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
 587                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
 588                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
 589 }
 590
 591 /**
 592  * read_general_status_table - read the general status table and save it.
 593  * @pm8001_ha: our hba card information
 594  */
 595 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
 596 {
 597         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
 598         pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
 599                         pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
 600         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
 601                         pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
 602         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
 603                         pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
 604         pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt          =
 605                         pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
 606         pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt           =
 607                         pm8001_mr32(address, GST_IOPTCNT_OFFSET);
 608         pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val     =
 609                         pm8001_mr32(address, GST_GPIO_INPUT_VAL);
 610         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
 611                         pm8001_mr32(address, GST_RERRINFO_OFFSET0);
 612         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
 613                         pm8001_mr32(address, GST_RERRINFO_OFFSET1);
 614         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
 615                         pm8001_mr32(address, GST_RERRINFO_OFFSET2);
 616         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
 617                         pm8001_mr32(address, GST_RERRINFO_OFFSET3);
 618         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
 619                         pm8001_mr32(address, GST_RERRINFO_OFFSET4);
 620         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
 621                         pm8001_mr32(address, GST_RERRINFO_OFFSET5);
 622         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
 623                         pm8001_mr32(address, GST_RERRINFO_OFFSET6);
 624         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
 625                          pm8001_mr32(address, GST_RERRINFO_OFFSET7);
 626 }
 627 /**
 628  * read_phy_attr_table - read the phy attribute table and save it.
 629  * @pm8001_ha: our hba card information
 630  */
 631 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
 632 {
 633         void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
 634         pm8001_ha->phy_attr_table.phystart1_16[0] =
 635                         pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
 636         pm8001_ha->phy_attr_table.phystart1_16[1] =
 637                         pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
 638         pm8001_ha->phy_attr_table.phystart1_16[2] =
 639                         pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
 640         pm8001_ha->phy_attr_table.phystart1_16[3] =
 641                         pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
 642         pm8001_ha->phy_attr_table.phystart1_16[4] =
 643                         pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
 644         pm8001_ha->phy_attr_table.phystart1_16[5] =
 645                         pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
 646         pm8001_ha->phy_attr_table.phystart1_16[6] =
 647                         pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
 648         pm8001_ha->phy_attr_table.phystart1_16[7] =
 649                         pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
 650         pm8001_ha->phy_attr_table.phystart1_16[8] =
 651                         pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
 652         pm8001_ha->phy_attr_table.phystart1_16[9] =
 653                         pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
 654         pm8001_ha->phy_attr_table.phystart1_16[10] =
 655                         pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
 656         pm8001_ha->phy_attr_table.phystart1_16[11] =
 657                         pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
 658         pm8001_ha->phy_attr_table.phystart1_16[12] =
 659                         pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
 660         pm8001_ha->phy_attr_table.phystart1_16[13] =
 661                         pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
 662         pm8001_ha->phy_attr_table.phystart1_16[14] =
 663                         pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
 664         pm8001_ha->phy_attr_table.phystart1_16[15] =
 665                         pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
 666
 667         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
 668                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
 669         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
 670                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
 671         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
 672                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
 673         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
 674                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
 675         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
 676                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
 677         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
 678                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
 679         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
 680                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
 681         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
 682                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
 683         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
 684                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
 685         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
 686                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
 687         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
 688                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
 689         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
 690                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
 691         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
 692                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
 693         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
 694                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
 695         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
 696                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
 697         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
 698                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
 699
 700 }
 701
 702 /**
 703  * read_inbnd_queue_table - read the inbound queue table and save it.
 704  * @pm8001_ha: our hba card information
 705  */
 706 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 707 {
 708         int i;
 709         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 710         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 711                 u32 offset = i * 0x20;
 712                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 713                         get_pci_bar_index(pm8001_mr32(address,
 714                                 (offset + IB_PIPCI_BAR)));
 715                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 716                         pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
 717         }
 718 }
 719
 720 /**
 721  * read_outbnd_queue_table - read the outbound queue table and save it.
 722  * @pm8001_ha: our hba card information
 723  */
 724 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 725 {
 726         int i;
 727         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 728         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 729                 u32 offset = i * 0x24;
 730                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 731                         get_pci_bar_index(pm8001_mr32(address,
 732                                 (offset + OB_CIPCI_BAR)));
 733                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 734                         pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
 735         }
 736 }
 737
 738 /**
 739  * init_default_table_values - init the default table.
 740  * @pm8001_ha: our hba card information
 741  */
 742 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 743 {
 744         int i;
 745         u32 offsetib, offsetob;
 746         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 747         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 748         u32 ib_offset = pm8001_ha->ib_offset;
 749         u32 ob_offset = pm8001_ha->ob_offset;
 750         u32 ci_offset = pm8001_ha->ci_offset;
 751         u32 pi_offset = pm8001_ha->pi_offset;
 752
 753         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr         =
 754                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 755         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr         =
 756                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 757         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size               =
 758                                                         PM8001_EVENT_LOG_SIZE;
 759         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity           = 0x01;
 760         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr     =
 761                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 762         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr     =
 763                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 764         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size           =
 765                                                         PM8001_EVENT_LOG_SIZE;
 766         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
 767         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
 768
 769         /* Disable end to end CRC checking */
 770         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 771
 772         for (i = 0; i < pm8001_ha->max_q_num; i++) {
 773                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 774                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 775                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 776                         pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
 777                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 778                 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
 779                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 780                   (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
 781                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 782                         pm8001_ha->memoryMap.region[ib_offset + i].total_len;
 783                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 784                         pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
 785                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 786                         pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
 787                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 788                         pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
 789                 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
 790                 offsetib = i * 0x20;
 791                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 792                         get_pci_bar_index(pm8001_mr32(addressib,
 793                                 (offsetib + 0x14)));
 794                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 795                         pm8001_mr32(addressib, (offsetib + 0x18));
 796                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 797                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 798
 799                 pm8001_dbg(pm8001_ha, DEV,
 800                            "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
 801                            pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
 802                            pm8001_ha->inbnd_q_tbl[i].pi_offset);
 803         }
 804         for (i = 0; i < pm8001_ha->max_q_num; i++) {
 805                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 806                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 807                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 808                         pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
 809                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 810                         pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
 811                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 812                   (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
 813                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 814                         pm8001_ha->memoryMap.region[ob_offset + i].total_len;
 815                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 816                         pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
 817                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 818                         pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
 819                 /* interrupt vector based on oq */
 820                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
 821                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 822                         pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
 823                 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
 824                 offsetob = i * 0x24;
 825                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 826                         get_pci_bar_index(pm8001_mr32(addressob,
 827                         offsetob + 0x14));
 828                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 829                         pm8001_mr32(addressob, (offsetob + 0x18));
 830                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 831                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 832
 833                 pm8001_dbg(pm8001_ha, DEV,
 834                            "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
 835                            pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
 836                            pm8001_ha->outbnd_q_tbl[i].ci_offset);
 837         }
 838 }
 839
 840 /**
 841  * update_main_config_table - update the main default table to the HBA.
 842  * @pm8001_ha: our hba card information
 843  */
 844 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 845 {
 846         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 847         pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
 848                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
 849         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
 850                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
 851         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
 852                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
 853         pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
 854                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
 855         pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
 856                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
 857         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
 858                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
 859         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
 860                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
 861         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
 862                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
 863         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
 864                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
 865         /* Update Fatal error interrupt vector */
 866         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
 867                                         ((pm8001_ha->max_q_num - 1) << 8);
 868         pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
 869                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
 870         pm8001_dbg(pm8001_ha, DEV,
 871                    "Updated Fatal error interrupt vector 0x%x\n",
 872                    pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT));
 873
 874         pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
 875                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
 876
 877         /* SPCv specific */
 878         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
 879         /* Set GPIOLED to 0x2 for LED indicator */
 880         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
 881         pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
 882                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
 883         pm8001_dbg(pm8001_ha, DEV,
 884                    "Programming DW 0x21 in main cfg table with 0x%x\n",
 885                    pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET));
 886
 887         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 888                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 889         pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
 890                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
 891
 892         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
 893         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 894                                                         PORT_RECOVERY_TIMEOUT;
 895         if (pm8001_ha->chip_id == chip_8006) {
 896                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
 897                                         0x0000ffff;
 898                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 899                                         CHIP_8006_PORT_RECOVERY_TIMEOUT;
 900         }
 901         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 902                         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 903 }
 904
 905 /**
 906  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 907  * @pm8001_ha: our hba card information
 908  * @number: entry in the queue
 909  */
 910 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 911                                          int number)
 912 {
 913         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 914         u16 offset = number * 0x20;
 915         pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
 916                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 917         pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
 918                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 919         pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
 920                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 921         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
 922                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 923         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
 924                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 925
 926         pm8001_dbg(pm8001_ha, DEV,
 927                    "IQ %d: Element pri size 0x%x\n",
 928                    number,
 929                    pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 930
 931         pm8001_dbg(pm8001_ha, DEV,
 932                    "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
 933                    pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
 934                    pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 935
 936         pm8001_dbg(pm8001_ha, DEV,
 937                    "CI upper base addr 0x%x CI lower base addr 0x%x\n",
 938                    pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
 939                    pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 940 }
 941
 942 /**
 943  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 944  * @pm8001_ha: our hba card information
 945  * @number: entry in the queue
 946  */
 947 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 948                                                  int number)
 949 {
 950         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 951         u16 offset = number * 0x24;
 952         pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
 953                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 954         pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
 955                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 956         pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
 957                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 958         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
 959                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 960         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
 961                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 962         pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
 963                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 964
 965         pm8001_dbg(pm8001_ha, DEV,
 966                    "OQ %d: Element pri size 0x%x\n",
 967                    number,
 968                    pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 969
 970         pm8001_dbg(pm8001_ha, DEV,
 971                    "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
 972                    pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
 973                    pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 974
 975         pm8001_dbg(pm8001_ha, DEV,
 976                    "PI upper base addr 0x%x PI lower base addr 0x%x\n",
 977                    pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
 978                    pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 979 }
 980
 981 /**
 982  * mpi_init_check - check firmware initialization status.
 983  * @pm8001_ha: our hba card information
 984  */
 985 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 986 {
 987         u32 max_wait_count;
 988         u32 value;
 989         u32 gst_len_mpistate;
 990
 991         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 992         table is updated */
 993         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
 994         /* wait until Inbound DoorBell Clear Register toggled */
 995         if (IS_SPCV_12G(pm8001_ha->pdev)) {
 996                 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
 997         } else {
 998                 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
 999         }
1000         do {
1001                 msleep(FW_READY_INTERVAL);
1002                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1003                 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1004         } while ((value != 0) && (--max_wait_count));
1005
1006         if (!max_wait_count) {
1007                 /* additional check */
1008                 pm8001_dbg(pm8001_ha, FAIL,
1009                            "Inb doorbell clear not toggled[value:%x]\n",
1010                            value);
1011                 return -EBUSY;
1012         }
1013         /* check the MPI-State for initialization up to 100ms*/
1014         max_wait_count = 5;/* 100 msec */
1015         do {
1016                 msleep(FW_READY_INTERVAL);
1017                 gst_len_mpistate =
1018                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1019                                         GST_GSTLEN_MPIS_OFFSET);
1020         } while ((GST_MPI_STATE_INIT !=
1021                 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1022         if (!max_wait_count)
1023                 return -EBUSY;
1024
1025         /* check MPI Initialization error */
1026         gst_len_mpistate = gst_len_mpistate >> 16;
1027         if (0x0000 != gst_len_mpistate)
1028                 return -EBUSY;
1029
1030         return 0;
1031 }
1032
1033 /**
1034  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1035  * This function sleeps hence it must not be used in atomic context.
1036  * @pm8001_ha: our hba card information
1037  */
1038 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1039 {
1040         u32 value;
1041         u32 max_wait_count;
1042         u32 max_wait_time;
1043         u32 expected_mask;
1044         int ret = 0;
1045
1046         /* reset / PCIe ready */
1047         max_wait_time = max_wait_count = 5;     /* 100 milli sec */
1048         do {
1049                 msleep(FW_READY_INTERVAL);
1050                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1051         } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1052
1053         /* check ila, RAAE and iops status */
1054         if ((pm8001_ha->chip_id != chip_8008) &&
1055                         (pm8001_ha->chip_id != chip_8009)) {
1056                 max_wait_time = max_wait_count = 180;   /* 3600 milli sec */
1057                 expected_mask = SCRATCH_PAD_ILA_READY |
1058                         SCRATCH_PAD_RAAE_READY |
1059                         SCRATCH_PAD_IOP0_READY |
1060                         SCRATCH_PAD_IOP1_READY;
1061         } else {
1062                 max_wait_time = max_wait_count = 170;   /* 3400 milli sec */
1063                 expected_mask = SCRATCH_PAD_ILA_READY |
1064                         SCRATCH_PAD_RAAE_READY |
1065                         SCRATCH_PAD_IOP0_READY;
1066         }
1067         do {
1068                 msleep(FW_READY_INTERVAL);
1069                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1070         } while (((value & expected_mask) !=
1071                                  expected_mask) && (--max_wait_count));
1072         if (!max_wait_count) {
1073                 pm8001_dbg(pm8001_ha, INIT,
1074                 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n",
1075                         max_wait_time * FW_READY_INTERVAL, value);
1076                 ret = -1;
1077         } else {
1078                 pm8001_dbg(pm8001_ha, MSG,
1079                         "All FW components ready by %d ms\n",
1080                         (max_wait_time - max_wait_count) * FW_READY_INTERVAL);
1081         }
1082         return ret;
1083 }
1084
1085 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1086 {
1087         void __iomem *base_addr;
1088         u32     value;
1089         u32     offset;
1090         u32     pcibar;
1091         u32     pcilogic;
1092
1093         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1094
1095         /*
1096          * lower 26 bits of SCRATCHPAD0 register describes offset within the
1097          * PCIe BAR where the MPI configuration table is present
1098          */
1099         offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1100
1101         pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",
1102                    offset, value);
1103         /*
1104          * Upper 6 bits describe the offset within PCI config space where BAR
1105          * is located.
1106          */
1107         pcilogic = (value & 0xFC000000) >> 26;
1108         pcibar = get_pci_bar_index(pcilogic);
1109         pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
1110
1111         /*
1112          * Make sure the offset falls inside the ioremapped PCI BAR
1113          */
1114         if (offset > pm8001_ha->io_mem[pcibar].memsize) {
1115                 pm8001_dbg(pm8001_ha, FAIL,
1116                         "Main cfg tbl offset outside %u > %u\n",
1117                                 offset, pm8001_ha->io_mem[pcibar].memsize);
1118                 return -EBUSY;
1119         }
1120         pm8001_ha->main_cfg_tbl_addr = base_addr =
1121                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1122
1123         /*
1124          * Validate main configuration table address: first DWord should read
1125          * "PMCS"
1126          */
1127         value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0);
1128         if (memcmp(&value, "PMCS", 4) != 0) {
1129                 pm8001_dbg(pm8001_ha, FAIL,
1130                         "BAD main config signature 0x%x\n",
1131                                 value);
1132                 return -EBUSY;
1133         }
1134         pm8001_dbg(pm8001_ha, INIT,
1135                         "VALID main config signature 0x%x\n", value);
1136         pm8001_ha->general_stat_tbl_addr =
1137                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1138                                         0xFFFFFF);
1139         pm8001_ha->inbnd_q_tbl_addr =
1140                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1141                                         0xFFFFFF);
1142         pm8001_ha->outbnd_q_tbl_addr =
1143                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1144                                         0xFFFFFF);
1145         pm8001_ha->ivt_tbl_addr =
1146                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1147                                         0xFFFFFF);
1148         pm8001_ha->pspa_q_tbl_addr =
1149                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1150                                         0xFFFFFF);
1151         pm8001_ha->fatal_tbl_addr =
1152                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1153                                         0xFFFFFF);
1154
1155         pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",
1156                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));
1157         pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",
1158                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));
1159         pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",
1160                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));
1161         pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",
1162                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));
1163         pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",
1164                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));
1165         pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",
1166                    pm8001_ha->main_cfg_tbl_addr,
1167                    pm8001_ha->general_stat_tbl_addr);
1168         pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",
1169                    pm8001_ha->inbnd_q_tbl_addr,
1170                    pm8001_ha->outbnd_q_tbl_addr);
1171         pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",
1172                    pm8001_ha->pspa_q_tbl_addr,
1173                    pm8001_ha->ivt_tbl_addr);
1174         return 0;
1175 }
1176
1177 /**
1178  * pm80xx_set_thermal_config - support the thermal configuration
1179  * @pm8001_ha: our hba card information.
1180  */
1181 int
1182 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1183 {
1184         struct set_ctrl_cfg_req payload;
1185         int rc;
1186         u32 tag;
1187         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1188         u32 page_code;
1189
1190         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1191         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1192         if (rc)
1193                 return rc;
1194
1195         payload.tag = cpu_to_le32(tag);
1196
1197         if (IS_SPCV_12G(pm8001_ha->pdev))
1198                 page_code = THERMAL_PAGE_CODE_7H;
1199         else
1200                 page_code = THERMAL_PAGE_CODE_8H;
1201
1202         payload.cfg_pg[0] =
1203                 cpu_to_le32((THERMAL_LOG_ENABLE << 9) |
1204                             (THERMAL_ENABLE << 8) | page_code);
1205         payload.cfg_pg[1] =
1206                 cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8));
1207
1208         pm8001_dbg(pm8001_ha, DEV,
1209                    "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1210                    payload.cfg_pg[0], payload.cfg_pg[1]);
1211
1212         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1213                         sizeof(payload), 0);
1214         if (rc)
1215                 pm8001_tag_free(pm8001_ha, tag);
1216         return rc;
1217
1218 }
1219
1220 /**
1221 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1222 * Timer configuration page
1223 * @pm8001_ha: our hba card information.
1224 */
1225 static int
1226 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1227 {
1228         struct set_ctrl_cfg_req payload;
1229         SASProtocolTimerConfig_t SASConfigPage;
1230         int rc;
1231         u32 tag;
1232         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1233
1234         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1235         memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1236
1237         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1238         if (rc)
1239                 return rc;
1240
1241         payload.tag = cpu_to_le32(tag);
1242
1243         SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE);
1244         SASConfigPage.MST_MSI = cpu_to_le32(3 << 15);
1245         SASConfigPage.STP_SSP_MCT_TMO =
1246                 cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO);
1247         SASConfigPage.STP_FRM_TMO =
1248                 cpu_to_le32((SAS_MAX_OPEN_TIME << 24) |
1249                             (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER);
1250         SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME);
1251
1252         SASConfigPage.OPNRJT_RTRY_INTVL =
1253                 cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL);
1254         SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =
1255                 cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO);
1256         SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =
1257                 cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR);
1258         SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP);
1259
1260         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",
1261                    le32_to_cpu(SASConfigPage.pageCode));
1262         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI  0x%08x\n",
1263                    le32_to_cpu(SASConfigPage.MST_MSI));
1264         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO  0x%08x\n",
1265                    le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO));
1266         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO  0x%08x\n",
1267                    le32_to_cpu(SASConfigPage.STP_FRM_TMO));
1268         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO  0x%08x\n",
1269                    le32_to_cpu(SASConfigPage.STP_IDLE_TMO));
1270         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL  0x%08x\n",
1271                    le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL));
1272         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO  0x%08x\n",
1273                    le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1274         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR  0x%08x\n",
1275                    le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1276         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP  0x%08x\n",
1277                    le32_to_cpu(SASConfigPage.MAX_AIP));
1278
1279         memcpy(&payload.cfg_pg, &SASConfigPage,
1280                          sizeof(SASProtocolTimerConfig_t));
1281
1282         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1283                         sizeof(payload), 0);
1284         if (rc)
1285                 pm8001_tag_free(pm8001_ha, tag);
1286
1287         return rc;
1288 }
1289
1290 /**
1291  * pm80xx_get_encrypt_info - Check for encryption
1292  * @pm8001_ha: our hba card information.
1293  */
1294 static int
1295 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1296 {
1297         u32 scratch3_value;
1298         int ret = -1;
1299
1300         /* Read encryption status from SCRATCH PAD 3 */
1301         scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1302
1303         if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1304                                         SCRATCH_PAD3_ENC_READY) {
1305                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1306                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1307                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1308                                                 SCRATCH_PAD3_SMF_ENABLED)
1309                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1310                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1311                                                 SCRATCH_PAD3_SMA_ENABLED)
1312                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1313                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1314                                                 SCRATCH_PAD3_SMB_ENABLED)
1315                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1316                 pm8001_ha->encrypt_info.status = 0;
1317                 pm8001_dbg(pm8001_ha, INIT,
1318                            "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1319                            scratch3_value,
1320                            pm8001_ha->encrypt_info.cipher_mode,
1321                            pm8001_ha->encrypt_info.sec_mode,
1322                            pm8001_ha->encrypt_info.status);
1323                 ret = 0;
1324         } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1325                                         SCRATCH_PAD3_ENC_DISABLED) {
1326                 pm8001_dbg(pm8001_ha, INIT,
1327                            "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1328                            scratch3_value);
1329                 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1330                 pm8001_ha->encrypt_info.cipher_mode = 0;
1331                 pm8001_ha->encrypt_info.sec_mode = 0;
1332                 ret = 0;
1333         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1334                                 SCRATCH_PAD3_ENC_DIS_ERR) {
1335                 pm8001_ha->encrypt_info.status =
1336                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1337                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1338                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1339                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1340                                         SCRATCH_PAD3_SMF_ENABLED)
1341                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1342                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1343                                         SCRATCH_PAD3_SMA_ENABLED)
1344                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1345                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1346                                         SCRATCH_PAD3_SMB_ENABLED)
1347                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1348                 pm8001_dbg(pm8001_ha, INIT,
1349                            "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1350                            scratch3_value,
1351                            pm8001_ha->encrypt_info.cipher_mode,
1352                            pm8001_ha->encrypt_info.sec_mode,
1353                            pm8001_ha->encrypt_info.status);
1354         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1355                                  SCRATCH_PAD3_ENC_ENA_ERR) {
1356
1357                 pm8001_ha->encrypt_info.status =
1358                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1359                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1360                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1361                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1362                                         SCRATCH_PAD3_SMF_ENABLED)
1363                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1364                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1365                                         SCRATCH_PAD3_SMA_ENABLED)
1366                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1367                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1368                                         SCRATCH_PAD3_SMB_ENABLED)
1369                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1370
1371                 pm8001_dbg(pm8001_ha, INIT,
1372                            "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1373                            scratch3_value,
1374                            pm8001_ha->encrypt_info.cipher_mode,
1375                            pm8001_ha->encrypt_info.sec_mode,
1376                            pm8001_ha->encrypt_info.status);
1377         }
1378         return ret;
1379 }
1380
1381 /**
1382  * pm80xx_encrypt_update - update flash with encryption information
1383  * @pm8001_ha: our hba card information.
1384  */
1385 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1386 {
1387         struct kek_mgmt_req payload;
1388         int rc;
1389         u32 tag;
1390         u32 opc = OPC_INB_KEK_MANAGEMENT;
1391
1392         memset(&payload, 0, sizeof(struct kek_mgmt_req));
1393         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1394         if (rc)
1395                 return rc;
1396
1397         payload.tag = cpu_to_le32(tag);
1398         /* Currently only one key is used. New KEK index is 1.
1399          * Current KEK index is 1. Store KEK to NVRAM is 1.
1400          */
1401         payload.new_curidx_ksop =
1402                 cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) |
1403                              KEK_MGMT_SUBOP_KEYCARDUPDATE));
1404
1405         pm8001_dbg(pm8001_ha, DEV,
1406                    "Saving Encryption info to flash. payload 0x%x\n",
1407                    le32_to_cpu(payload.new_curidx_ksop));
1408
1409         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1410                         sizeof(payload), 0);
1411         if (rc)
1412                 pm8001_tag_free(pm8001_ha, tag);
1413
1414         return rc;
1415 }
1416
1417 /**
1418  * pm80xx_chip_init - the main init function that initializes whole PM8001 chip.
1419  * @pm8001_ha: our hba card information
1420  */
1421 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1422 {
1423         int ret;
1424         u8 i = 0;
1425
1426         /* check the firmware status */
1427         if (-1 == check_fw_ready(pm8001_ha)) {
1428                 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1429                 return -EBUSY;
1430         }
1431
1432         /* Initialize the controller fatal error flag */
1433         pm8001_ha->controller_fatal_error = false;
1434
1435         /* Initialize pci space address eg: mpi offset */
1436         ret = init_pci_device_addresses(pm8001_ha);
1437         if (ret) {
1438                 pm8001_dbg(pm8001_ha, FAIL,
1439                         "Failed to init pci addresses");
1440                 return ret;
1441         }
1442         init_default_table_values(pm8001_ha);
1443         read_main_config_table(pm8001_ha);
1444         read_general_status_table(pm8001_ha);
1445         read_inbnd_queue_table(pm8001_ha);
1446         read_outbnd_queue_table(pm8001_ha);
1447         read_phy_attr_table(pm8001_ha);
1448
1449         /* update main config table ,inbound table and outbound table */
1450         update_main_config_table(pm8001_ha);
1451         for (i = 0; i < pm8001_ha->max_q_num; i++) {
1452                 update_inbnd_queue_table(pm8001_ha, i);
1453                 update_outbnd_queue_table(pm8001_ha, i);
1454         }
1455         /* notify firmware update finished and check initialization status */
1456         if (0 == mpi_init_check(pm8001_ha)) {
1457                 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
1458         } else
1459                 return -EBUSY;
1460
1461         /* send SAS protocol timer configuration page to FW */
1462         ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1463
1464         /* Check for encryption */
1465         if (pm8001_ha->chip->encrypt) {
1466                 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n");
1467                 ret = pm80xx_get_encrypt_info(pm8001_ha);
1468                 if (ret == -1) {
1469                         pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n");
1470                         if (pm8001_ha->encrypt_info.status == 0x81) {
1471                                 pm8001_dbg(pm8001_ha, INIT,
1472                                            "Encryption enabled with error.Saving encryption key to flash\n");
1473                                 pm80xx_encrypt_update(pm8001_ha);
1474                         }
1475                 }
1476         }
1477         return 0;
1478 }
1479
1480 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1481 {
1482         u32 max_wait_count;
1483         u32 value;
1484         u32 gst_len_mpistate;
1485         int ret;
1486
1487         ret = init_pci_device_addresses(pm8001_ha);
1488         if (ret) {
1489                 pm8001_dbg(pm8001_ha, FAIL,
1490                         "Failed to init pci addresses");
1491                 return ret;
1492         }
1493
1494         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1495         table is stop */
1496         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1497
1498         /* wait until Inbound DoorBell Clear Register toggled */
1499         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1500                 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1501         } else {
1502                 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1503         }
1504         do {
1505                 msleep(FW_READY_INTERVAL);
1506                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1507                 value &= SPCv_MSGU_CFG_TABLE_RESET;
1508         } while ((value != 0) && (--max_wait_count));
1509
1510         if (!max_wait_count) {
1511                 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value);
1512                 return -1;
1513         }
1514
1515         /* check the MPI-State for termination in progress */
1516         /* wait until Inbound DoorBell Clear Register toggled */
1517         max_wait_count = 100; /* 2 sec for spcv/ve */
1518         do {
1519                 msleep(FW_READY_INTERVAL);
1520                 gst_len_mpistate =
1521                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1522                         GST_GSTLEN_MPIS_OFFSET);
1523                 if (GST_MPI_STATE_UNINIT ==
1524                         (gst_len_mpistate & GST_MPI_STATE_MASK))
1525                         break;
1526         } while (--max_wait_count);
1527         if (!max_wait_count) {
1528                 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
1529                            gst_len_mpistate & GST_MPI_STATE_MASK);
1530                 return -1;
1531         }
1532
1533         return 0;
1534 }
1535
1536 /**
1537  * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors
1538  * @pm8001_ha: our hba card information
1539  *
1540  * Fatal errors are recoverable only after a host reboot.
1541  */
1542 int
1543 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha)
1544 {
1545         int ret = 0;
1546         u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0,
1547                                             MSGU_SCRATCH_PAD_RSVD_0);
1548         u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0,
1549                                             MSGU_SCRATCH_PAD_RSVD_1);
1550         u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1551         u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1552         u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1553
1554         if (pm8001_ha->chip_id != chip_8006 &&
1555                         pm8001_ha->chip_id != chip_8074 &&
1556                         pm8001_ha->chip_id != chip_8076) {
1557                 return 0;
1558         }
1559
1560         if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) {
1561                 pm8001_dbg(pm8001_ha, FAIL,
1562                         "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n",
1563                                 scratch_pad1, scratch_pad2, scratch_pad3,
1564                                 scratch_pad_rsvd0, scratch_pad_rsvd1);
1565                 ret = 1;
1566         }
1567
1568         return ret;
1569 }
1570
1571 /**
1572  * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all
1573  * FW register status are reset to the originated status.
1574  * @pm8001_ha: our hba card information
1575  */
1576
1577 static int
1578 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1579 {
1580         u32 regval;
1581         u32 bootloader_state;
1582         u32 ibutton0, ibutton1;
1583
1584         /* Process MPI table uninitialization only if FW is ready */
1585         if (!pm8001_ha->controller_fatal_error) {
1586                 /* Check if MPI is in ready state to reset */
1587                 if (mpi_uninit_check(pm8001_ha) != 0) {
1588                         u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1589                         u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1590                         u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1591                         u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1592                         pm8001_dbg(pm8001_ha, FAIL,
1593                                    "MPI state is not ready scratch: %x:%x:%x:%x\n",
1594                                    r0, r1, r2, r3);
1595                         /* if things aren't ready but the bootloader is ok then
1596                          * try the reset anyway.
1597                          */
1598                         if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1599                                 return -1;
1600                 }
1601         }
1602         /* checked for reset register normal state; 0x0 */
1603         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1604         pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",
1605                    regval);
1606
1607         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1608         msleep(500);
1609
1610         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1611         pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",
1612                    regval);
1613
1614         if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1615                         SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1616                 pm8001_dbg(pm8001_ha, MSG,
1617                            " soft reset successful [regval: 0x%x]\n",
1618                            regval);
1619         } else {
1620                 pm8001_dbg(pm8001_ha, MSG,
1621                            " soft reset failed [regval: 0x%x]\n",
1622                            regval);
1623
1624                 /* check bootloader is successfully executed or in HDA mode */
1625                 bootloader_state =
1626                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1627                         SCRATCH_PAD1_BOOTSTATE_MASK;
1628
1629                 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1630                         pm8001_dbg(pm8001_ha, MSG,
1631                                    "Bootloader state - HDA mode SEEPROM\n");
1632                 } else if (bootloader_state ==
1633                                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1634                         pm8001_dbg(pm8001_ha, MSG,
1635                                    "Bootloader state - HDA mode Bootstrap Pin\n");
1636                 } else if (bootloader_state ==
1637                                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1638                         pm8001_dbg(pm8001_ha, MSG,
1639                                    "Bootloader state - HDA mode soft reset\n");
1640                 } else if (bootloader_state ==
1641                                         SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1642                         pm8001_dbg(pm8001_ha, MSG,
1643                                    "Bootloader state-HDA mode critical error\n");
1644                 }
1645                 return -EBUSY;
1646         }
1647
1648         /* check the firmware status after reset */
1649         if (-1 == check_fw_ready(pm8001_ha)) {
1650                 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1651                 /* check iButton feature support for motherboard controller */
1652                 if (pm8001_ha->pdev->subsystem_vendor !=
1653                         PCI_VENDOR_ID_ADAPTEC2 &&
1654                         pm8001_ha->pdev->subsystem_vendor !=
1655                         PCI_VENDOR_ID_ATTO &&
1656                         pm8001_ha->pdev->subsystem_vendor != 0) {
1657                         ibutton0 = pm8001_cr32(pm8001_ha, 0,
1658                                                MSGU_SCRATCH_PAD_RSVD_0);
1659                         ibutton1 = pm8001_cr32(pm8001_ha, 0,
1660                                                MSGU_SCRATCH_PAD_RSVD_1);
1661                         if (!ibutton0 && !ibutton1) {
1662                                 pm8001_dbg(pm8001_ha, FAIL,
1663                                            "iButton Feature is not Available!!!\n");
1664                                 return -EBUSY;
1665                         }
1666                         if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1667                                 pm8001_dbg(pm8001_ha, FAIL,
1668                                            "CRC Check for iButton Feature Failed!!!\n");
1669                                 return -EBUSY;
1670                         }
1671                 }
1672         }
1673         pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n");
1674         return 0;
1675 }
1676
1677 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1678 {
1679         u32 i;
1680
1681         pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1682
1683         /* do SPCv chip reset. */
1684         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1685         pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1686
1687         /* Check this ..whether delay is required or no */
1688         /* delay 10 usec */
1689         udelay(10);
1690
1691         /* wait for 20 msec until the firmware gets reloaded */
1692         i = 20;
1693         do {
1694                 mdelay(1);
1695         } while ((--i) != 0);
1696
1697         pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1698 }
1699
1700 /**
1701  * pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1702  * @pm8001_ha: our hba card information
1703  */
1704 static void
1705 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1706 {
1707         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1708         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1709 }
1710
1711 /**
1712  * pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1713  * @pm8001_ha: our hba card information
1714  */
1715 static void
1716 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1717 {
1718         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1719 }
1720
1721 /**
1722  * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt
1723  * @pm8001_ha: our hba card information
1724  * @vec: interrupt number to enable
1725  */
1726 static void
1727 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1728 {
1729 #ifdef PM8001_USE_MSIX
1730         u32 mask;
1731         mask = (u32)(1 << vec);
1732
1733         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1734         return;
1735 #endif
1736         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1737
1738 }
1739
1740 /**
1741  * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt
1742  * @pm8001_ha: our hba card information
1743  * @vec: interrupt number to disable
1744  */
1745 static void
1746 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1747 {
1748 #ifdef PM8001_USE_MSIX
1749         u32 mask;
1750         if (vec == 0xFF)
1751                 mask = 0xFFFFFFFF;
1752         else
1753                 mask = (u32)(1 << vec);
1754         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1755         return;
1756 #endif
1757         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1758 }
1759
1760 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1761                 struct pm8001_device *pm8001_ha_dev)
1762 {
1763         struct pm8001_ccb_info *ccb;
1764         struct sas_task *task;
1765         struct task_abort_req task_abort;
1766         u32 opc = OPC_INB_SATA_ABORT;
1767         int ret;
1768
1769         pm8001_ha_dev->id |= NCQ_ABORT_ALL_FLAG;
1770         pm8001_ha_dev->id &= ~NCQ_READ_LOG_FLAG;
1771
1772         task = sas_alloc_slow_task(GFP_ATOMIC);
1773         if (!task) {
1774                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1775                 return;
1776         }
1777         task->task_done = pm8001_task_done;
1778
1779         ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1780         if (!ccb) {
1781                 sas_free_task(task);
1782                 return;
1783         }
1784
1785         memset(&task_abort, 0, sizeof(task_abort));
1786         task_abort.abort_all = cpu_to_le32(1);
1787         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1788         task_abort.tag = cpu_to_le32(ccb->ccb_tag);
1789
1790         ret = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort,
1791                                    sizeof(task_abort), 0);
1792         pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n");
1793         if (ret) {
1794                 sas_free_task(task);
1795                 pm8001_ccb_free(pm8001_ha, ccb);
1796         }
1797 }
1798
1799 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1800                 struct pm8001_device *pm8001_ha_dev)
1801 {
1802         struct sata_start_req sata_cmd;
1803         int res;
1804         struct pm8001_ccb_info *ccb;
1805         struct sas_task *task = NULL;
1806         struct host_to_dev_fis fis;
1807         struct domain_device *dev;
1808         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1809
1810         task = sas_alloc_slow_task(GFP_ATOMIC);
1811         if (!task) {
1812                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1813                 return;
1814         }
1815         task->task_done = pm8001_task_done;
1816
1817         /*
1818          * Allocate domain device by ourselves as libsas is not going to
1819          * provide any.
1820          */
1821         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1822         if (!dev) {
1823                 sas_free_task(task);
1824                 pm8001_dbg(pm8001_ha, FAIL,
1825                            "Domain device cannot be allocated\n");
1826                 return;
1827         }
1828
1829         task->dev = dev;
1830         task->dev->lldd_dev = pm8001_ha_dev;
1831
1832         ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1833         if (!ccb) {
1834                 sas_free_task(task);
1835                 kfree(dev);
1836                 return;
1837         }
1838
1839         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1840         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1841
1842         memset(&sata_cmd, 0, sizeof(sata_cmd));
1843
1844         /* construct read log FIS */
1845         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1846         fis.fis_type = 0x27;
1847         fis.flags = 0x80;
1848         fis.command = ATA_CMD_READ_LOG_EXT;
1849         fis.lbal = 0x10;
1850         fis.sector_count = 0x1;
1851
1852         sata_cmd.tag = cpu_to_le32(ccb->ccb_tag);
1853         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1854         sata_cmd.ncqtag_atap_dir_m_dad = cpu_to_le32(((0x1 << 7) | (0x5 << 9)));
1855         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1856
1857         res = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd,
1858                                    sizeof(sata_cmd), 0);
1859         pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n");
1860         if (res) {
1861                 sas_free_task(task);
1862                 pm8001_ccb_free(pm8001_ha, ccb);
1863                 kfree(dev);
1864         }
1865 }
1866
1867 /**
1868  * mpi_ssp_completion - process the event that FW response to the SSP request.
1869  * @pm8001_ha: our hba card information
1870  * @piomb: the message contents of this outbound message.
1871  *
1872  * When FW has completed a ssp request for example a IO request, after it has
1873  * filled the SG data with the data, it will trigger this event representing
1874  * that he has finished the job; please check the corresponding buffer.
1875  * So we will tell the caller who maybe waiting the result to tell upper layer
1876  * that the task has been finished.
1877  */
1878 static void
1879 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1880 {
1881         struct sas_task *t;
1882         struct pm8001_ccb_info *ccb;
1883         unsigned long flags;
1884         u32 status;
1885         u32 param;
1886         u32 tag;
1887         struct ssp_completion_resp *psspPayload;
1888         struct task_status_struct *ts;
1889         struct ssp_response_iu *iu;
1890         struct pm8001_device *pm8001_dev;
1891         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1892         status = le32_to_cpu(psspPayload->status);
1893         tag = le32_to_cpu(psspPayload->tag);
1894         ccb = &pm8001_ha->ccb_info[tag];
1895         if ((status == IO_ABORTED) && ccb->open_retry) {
1896                 /* Being completed by another */
1897                 ccb->open_retry = 0;
1898                 return;
1899         }
1900         pm8001_dev = ccb->device;
1901         param = le32_to_cpu(psspPayload->param);
1902         t = ccb->task;
1903
1904         if (status && status != IO_UNDERFLOW)
1905                 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1906         if (unlikely(!t || !t->lldd_task || !t->dev))
1907                 return;
1908         ts = &t->task_status;
1909
1910         pm8001_dbg(pm8001_ha, DEV,
1911                    "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);
1912
1913         /* Print sas address of IO failed device */
1914         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1915                 (status != IO_UNDERFLOW))
1916                 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1917                            SAS_ADDR(t->dev->sas_addr));
1918
1919         switch (status) {
1920         case IO_SUCCESS:
1921                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",
1922                            param);
1923                 if (param == 0) {
1924                         ts->resp = SAS_TASK_COMPLETE;
1925                         ts->stat = SAS_SAM_STAT_GOOD;
1926                 } else {
1927                         ts->resp = SAS_TASK_COMPLETE;
1928                         ts->stat = SAS_PROTO_RESPONSE;
1929                         ts->residual = param;
1930                         iu = &psspPayload->ssp_resp_iu;
1931                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1932                 }
1933                 if (pm8001_dev)
1934                         atomic_dec(&pm8001_dev->running_req);
1935                 break;
1936         case IO_ABORTED:
1937                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1938                 ts->resp = SAS_TASK_COMPLETE;
1939                 ts->stat = SAS_ABORTED_TASK;
1940                 if (pm8001_dev)
1941                         atomic_dec(&pm8001_dev->running_req);
1942                 break;
1943         case IO_UNDERFLOW:
1944                 /* SSP Completion with error */
1945                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",
1946                            param);
1947                 ts->resp = SAS_TASK_COMPLETE;
1948                 ts->stat = SAS_DATA_UNDERRUN;
1949                 ts->residual = param;
1950                 if (pm8001_dev)
1951                         atomic_dec(&pm8001_dev->running_req);
1952                 break;
1953         case IO_NO_DEVICE:
1954                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1955                 ts->resp = SAS_TASK_UNDELIVERED;
1956                 ts->stat = SAS_PHY_DOWN;
1957                 if (pm8001_dev)
1958                         atomic_dec(&pm8001_dev->running_req);
1959                 break;
1960         case IO_XFER_ERROR_BREAK:
1961                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1962                 ts->resp = SAS_TASK_COMPLETE;
1963                 ts->stat = SAS_OPEN_REJECT;
1964                 /* Force the midlayer to retry */
1965                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1966                 if (pm8001_dev)
1967                         atomic_dec(&pm8001_dev->running_req);
1968                 break;
1969         case IO_XFER_ERROR_PHY_NOT_READY:
1970                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1971                 ts->resp = SAS_TASK_COMPLETE;
1972                 ts->stat = SAS_OPEN_REJECT;
1973                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1974                 if (pm8001_dev)
1975                         atomic_dec(&pm8001_dev->running_req);
1976                 break;
1977         case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1978                 pm8001_dbg(pm8001_ha, IO,
1979                            "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n");
1980                 ts->resp = SAS_TASK_COMPLETE;
1981                 ts->stat = SAS_OPEN_REJECT;
1982                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1983                 if (pm8001_dev)
1984                         atomic_dec(&pm8001_dev->running_req);
1985                 break;
1986         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1987                 pm8001_dbg(pm8001_ha, IO,
1988                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1989                 ts->resp = SAS_TASK_COMPLETE;
1990                 ts->stat = SAS_OPEN_REJECT;
1991                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1992                 if (pm8001_dev)
1993                         atomic_dec(&pm8001_dev->running_req);
1994                 break;
1995         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1996                 pm8001_dbg(pm8001_ha, IO,
1997                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1998                 ts->resp = SAS_TASK_COMPLETE;
1999                 ts->stat = SAS_OPEN_REJECT;
2000                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2001                 if (pm8001_dev)
2002                         atomic_dec(&pm8001_dev->running_req);
2003                 break;
2004         case IO_OPEN_CNX_ERROR_BREAK:
2005                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2006                 ts->resp = SAS_TASK_COMPLETE;
2007                 ts->stat = SAS_OPEN_REJECT;
2008                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2009                 if (pm8001_dev)
2010                         atomic_dec(&pm8001_dev->running_req);
2011                 break;
2012         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2013         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2014         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2015         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2016         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2017         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2018                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2019                 ts->resp = SAS_TASK_COMPLETE;
2020                 ts->stat = SAS_OPEN_REJECT;
2021                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2022                 if (!t->uldd_task)
2023                         pm8001_handle_event(pm8001_ha,
2024                                 pm8001_dev,
2025                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2026                 break;
2027         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2028                 pm8001_dbg(pm8001_ha, IO,
2029                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2030                 ts->resp = SAS_TASK_COMPLETE;
2031                 ts->stat = SAS_OPEN_REJECT;
2032                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2033                 if (pm8001_dev)
2034                         atomic_dec(&pm8001_dev->running_req);
2035                 break;
2036         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2037                 pm8001_dbg(pm8001_ha, IO,
2038                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2039                 ts->resp = SAS_TASK_COMPLETE;
2040                 ts->stat = SAS_OPEN_REJECT;
2041                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2042                 if (pm8001_dev)
2043                         atomic_dec(&pm8001_dev->running_req);
2044                 break;
2045         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2046                 pm8001_dbg(pm8001_ha, IO,
2047                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2048                 ts->resp = SAS_TASK_UNDELIVERED;
2049                 ts->stat = SAS_OPEN_REJECT;
2050                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2051                 if (pm8001_dev)
2052                         atomic_dec(&pm8001_dev->running_req);
2053                 break;
2054         case IO_XFER_ERROR_NAK_RECEIVED:
2055                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2056                 ts->resp = SAS_TASK_COMPLETE;
2057                 ts->stat = SAS_OPEN_REJECT;
2058                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2059                 if (pm8001_dev)
2060                         atomic_dec(&pm8001_dev->running_req);
2061                 break;
2062         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2063                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2064                 ts->resp = SAS_TASK_COMPLETE;
2065                 ts->stat = SAS_NAK_R_ERR;
2066                 if (pm8001_dev)
2067                         atomic_dec(&pm8001_dev->running_req);
2068                 break;
2069         case IO_XFER_ERROR_DMA:
2070                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2071                 ts->resp = SAS_TASK_COMPLETE;
2072                 ts->stat = SAS_OPEN_REJECT;
2073                 if (pm8001_dev)
2074                         atomic_dec(&pm8001_dev->running_req);
2075                 break;
2076         case IO_XFER_OPEN_RETRY_TIMEOUT:
2077                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2078                 ts->resp = SAS_TASK_COMPLETE;
2079                 ts->stat = SAS_OPEN_REJECT;
2080                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2081                 if (pm8001_dev)
2082                         atomic_dec(&pm8001_dev->running_req);
2083                 break;
2084         case IO_XFER_ERROR_OFFSET_MISMATCH:
2085                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2086                 ts->resp = SAS_TASK_COMPLETE;
2087                 ts->stat = SAS_OPEN_REJECT;
2088                 if (pm8001_dev)
2089                         atomic_dec(&pm8001_dev->running_req);
2090                 break;
2091         case IO_PORT_IN_RESET:
2092                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2093                 ts->resp = SAS_TASK_COMPLETE;
2094                 ts->stat = SAS_OPEN_REJECT;
2095                 if (pm8001_dev)
2096                         atomic_dec(&pm8001_dev->running_req);
2097                 break;
2098         case IO_DS_NON_OPERATIONAL:
2099                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2100                 ts->resp = SAS_TASK_COMPLETE;
2101                 ts->stat = SAS_OPEN_REJECT;
2102                 if (!t->uldd_task)
2103                         pm8001_handle_event(pm8001_ha,
2104                                 pm8001_dev,
2105                                 IO_DS_NON_OPERATIONAL);
2106                 break;
2107         case IO_DS_IN_RECOVERY:
2108                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2109                 ts->resp = SAS_TASK_COMPLETE;
2110                 ts->stat = SAS_OPEN_REJECT;
2111                 if (pm8001_dev)
2112                         atomic_dec(&pm8001_dev->running_req);
2113                 break;
2114         case IO_TM_TAG_NOT_FOUND:
2115                 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2116                 ts->resp = SAS_TASK_COMPLETE;
2117                 ts->stat = SAS_OPEN_REJECT;
2118                 if (pm8001_dev)
2119                         atomic_dec(&pm8001_dev->running_req);
2120                 break;
2121         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2122                 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2123                 ts->resp = SAS_TASK_COMPLETE;
2124                 ts->stat = SAS_OPEN_REJECT;
2125                 if (pm8001_dev)
2126                         atomic_dec(&pm8001_dev->running_req);
2127                 break;
2128         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2129                 pm8001_dbg(pm8001_ha, IO,
2130                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2131                 ts->resp = SAS_TASK_COMPLETE;
2132                 ts->stat = SAS_OPEN_REJECT;
2133                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2134                 if (pm8001_dev)
2135                         atomic_dec(&pm8001_dev->running_req);
2136                 break;
2137         default:
2138                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2139                 /* not allowed case. Therefore, return failed status */
2140                 ts->resp = SAS_TASK_COMPLETE;
2141                 ts->stat = SAS_OPEN_REJECT;
2142                 if (pm8001_dev)
2143                         atomic_dec(&pm8001_dev->running_req);
2144                 break;
2145         }
2146         pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ",
2147                    psspPayload->ssp_resp_iu.status);
2148         spin_lock_irqsave(&t->task_state_lock, flags);
2149         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2150         t->task_state_flags |= SAS_TASK_STATE_DONE;
2151         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2152                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2153                 pm8001_dbg(pm8001_ha, FAIL,
2154                            "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2155                            t, status, ts->resp, ts->stat);
2156                 pm8001_ccb_task_free(pm8001_ha, ccb);
2157                 if (t->slow_task)
2158                         complete(&t->slow_task->completion);
2159         } else {
2160                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2161                 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2162         }
2163 }
2164
2165 /*See the comments for mpi_ssp_completion */
2166 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2167 {
2168         struct sas_task *t;
2169         unsigned long flags;
2170         struct task_status_struct *ts;
2171         struct pm8001_ccb_info *ccb;
2172         struct pm8001_device *pm8001_dev;
2173         struct ssp_event_resp *psspPayload =
2174                 (struct ssp_event_resp *)(piomb + 4);
2175         u32 event = le32_to_cpu(psspPayload->event);
2176         u32 tag = le32_to_cpu(psspPayload->tag);
2177         u32 port_id = le32_to_cpu(psspPayload->port_id);
2178
2179         ccb = &pm8001_ha->ccb_info[tag];
2180         t = ccb->task;
2181         pm8001_dev = ccb->device;
2182         if (event)
2183                 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2184         if (unlikely(!t || !t->lldd_task || !t->dev))
2185                 return;
2186         ts = &t->task_status;
2187         pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2188                    port_id, tag, event);
2189         switch (event) {
2190         case IO_OVERFLOW:
2191                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2192                 ts->resp = SAS_TASK_COMPLETE;
2193                 ts->stat = SAS_DATA_OVERRUN;
2194                 ts->residual = 0;
2195                 if (pm8001_dev)
2196                         atomic_dec(&pm8001_dev->running_req);
2197                 break;
2198         case IO_XFER_ERROR_BREAK:
2199                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2200                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2201                 return;
2202         case IO_XFER_ERROR_PHY_NOT_READY:
2203                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2204                 ts->resp = SAS_TASK_COMPLETE;
2205                 ts->stat = SAS_OPEN_REJECT;
2206                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2207                 break;
2208         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2209                 pm8001_dbg(pm8001_ha, IO,
2210                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2211                 ts->resp = SAS_TASK_COMPLETE;
2212                 ts->stat = SAS_OPEN_REJECT;
2213                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2214                 break;
2215         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2216                 pm8001_dbg(pm8001_ha, IO,
2217                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2218                 ts->resp = SAS_TASK_COMPLETE;
2219                 ts->stat = SAS_OPEN_REJECT;
2220                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2221                 break;
2222         case IO_OPEN_CNX_ERROR_BREAK:
2223                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2224                 ts->resp = SAS_TASK_COMPLETE;
2225                 ts->stat = SAS_OPEN_REJECT;
2226                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2227                 break;
2228         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2229         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2230         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2231         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2232         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2233         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2234                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2235                 ts->resp = SAS_TASK_COMPLETE;
2236                 ts->stat = SAS_OPEN_REJECT;
2237                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2238                 if (!t->uldd_task)
2239                         pm8001_handle_event(pm8001_ha,
2240                                 pm8001_dev,
2241                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2242                 break;
2243         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2244                 pm8001_dbg(pm8001_ha, IO,
2245                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2246                 ts->resp = SAS_TASK_COMPLETE;
2247                 ts->stat = SAS_OPEN_REJECT;
2248                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2249                 break;
2250         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2251                 pm8001_dbg(pm8001_ha, IO,
2252                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2253                 ts->resp = SAS_TASK_COMPLETE;
2254                 ts->stat = SAS_OPEN_REJECT;
2255                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2256                 break;
2257         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2258                 pm8001_dbg(pm8001_ha, IO,
2259                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2260                 ts->resp = SAS_TASK_COMPLETE;
2261                 ts->stat = SAS_OPEN_REJECT;
2262                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2263                 break;
2264         case IO_XFER_ERROR_NAK_RECEIVED:
2265                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2266                 ts->resp = SAS_TASK_COMPLETE;
2267                 ts->stat = SAS_OPEN_REJECT;
2268                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2269                 break;
2270         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2271                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2272                 ts->resp = SAS_TASK_COMPLETE;
2273                 ts->stat = SAS_NAK_R_ERR;
2274                 break;
2275         case IO_XFER_OPEN_RETRY_TIMEOUT:
2276                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2277                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2278                 return;
2279         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2280                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2281                 ts->resp = SAS_TASK_COMPLETE;
2282                 ts->stat = SAS_DATA_OVERRUN;
2283                 break;
2284         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2285                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2286                 ts->resp = SAS_TASK_COMPLETE;
2287                 ts->stat = SAS_DATA_OVERRUN;
2288                 break;
2289         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2290                 pm8001_dbg(pm8001_ha, IO,
2291                            "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2292                 ts->resp = SAS_TASK_COMPLETE;
2293                 ts->stat = SAS_DATA_OVERRUN;
2294                 break;
2295         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2296                 pm8001_dbg(pm8001_ha, IO,
2297                            "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2298                 ts->resp = SAS_TASK_COMPLETE;
2299                 ts->stat = SAS_DATA_OVERRUN;
2300                 break;
2301         case IO_XFER_ERROR_OFFSET_MISMATCH:
2302                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2303                 ts->resp = SAS_TASK_COMPLETE;
2304                 ts->stat = SAS_DATA_OVERRUN;
2305                 break;
2306         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2307                 pm8001_dbg(pm8001_ha, IO,
2308                            "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2309                 ts->resp = SAS_TASK_COMPLETE;
2310                 ts->stat = SAS_DATA_OVERRUN;
2311                 break;
2312         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2313                 pm8001_dbg(pm8001_ha, IOERR,
2314                            "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2315                 /* TBC: used default set values */
2316                 ts->resp = SAS_TASK_COMPLETE;
2317                 ts->stat = SAS_DATA_OVERRUN;
2318                 break;
2319         case IO_XFER_CMD_FRAME_ISSUED:
2320                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2321                 return;
2322         default:
2323                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2324                 /* not allowed case. Therefore, return failed status */
2325                 ts->resp = SAS_TASK_COMPLETE;
2326                 ts->stat = SAS_DATA_OVERRUN;
2327                 break;
2328         }
2329         spin_lock_irqsave(&t->task_state_lock, flags);
2330         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2331         t->task_state_flags |= SAS_TASK_STATE_DONE;
2332         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2333                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2334                 pm8001_dbg(pm8001_ha, FAIL,
2335                            "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2336                            t, event, ts->resp, ts->stat);
2337                 pm8001_ccb_task_free(pm8001_ha, ccb);
2338         } else {
2339                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2340                 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2341         }
2342 }
2343
2344 /*See the comments for mpi_ssp_completion */
2345 static void
2346 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha,
2347                 struct outbound_queue_table *circularQ, void *piomb)
2348 {
2349         struct sas_task *t;
2350         struct pm8001_ccb_info *ccb;
2351         u32 param;
2352         u32 status;
2353         u32 tag;
2354         int i, j;
2355         u8 sata_addr_low[4];
2356         u32 temp_sata_addr_low, temp_sata_addr_hi;
2357         u8 sata_addr_hi[4];
2358         struct sata_completion_resp *psataPayload;
2359         struct task_status_struct *ts;
2360         struct ata_task_resp *resp ;
2361         u32 *sata_resp;
2362         struct pm8001_device *pm8001_dev;
2363         unsigned long flags;
2364
2365         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2366         status = le32_to_cpu(psataPayload->status);
2367         param = le32_to_cpu(psataPayload->param);
2368         tag = le32_to_cpu(psataPayload->tag);
2369
2370         ccb = &pm8001_ha->ccb_info[tag];
2371         t = ccb->task;
2372         pm8001_dev = ccb->device;
2373
2374         if (t) {
2375                 if (t->dev && (t->dev->lldd_dev))
2376                         pm8001_dev = t->dev->lldd_dev;
2377         } else {
2378                 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2379                 return;
2380         }
2381
2382         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2383                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2384                 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2385                 return;
2386         }
2387
2388         ts = &t->task_status;
2389
2390         if (status != IO_SUCCESS) {
2391                 pm8001_dbg(pm8001_ha, FAIL,
2392                         "IO failed device_id %u status 0x%x tag %d\n",
2393                         pm8001_dev->device_id, status, tag);
2394         }
2395
2396         /* Print sas address of IO failed device */
2397         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2398                 (status != IO_UNDERFLOW)) {
2399                 if (!((t->dev->parent) &&
2400                         (dev_is_expander(t->dev->parent->dev_type)))) {
2401                         for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++)
2402                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2403                         for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++)
2404                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2405                         memcpy(&temp_sata_addr_low, sata_addr_low,
2406                                 sizeof(sata_addr_low));
2407                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2408                                 sizeof(sata_addr_hi));
2409                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2410                                                 |((temp_sata_addr_hi << 8) &
2411                                                 0xff0000) |
2412                                                 ((temp_sata_addr_hi >> 8)
2413                                                 & 0xff00) |
2414                                                 ((temp_sata_addr_hi << 24) &
2415                                                 0xff000000));
2416                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2417                                                 & 0xff) |
2418                                                 ((temp_sata_addr_low << 8)
2419                                                 & 0xff0000) |
2420                                                 ((temp_sata_addr_low >> 8)
2421                                                 & 0xff00) |
2422                                                 ((temp_sata_addr_low << 24)
2423                                                 & 0xff000000)) +
2424                                                 pm8001_dev->attached_phy +
2425                                                 0x10);
2426                         pm8001_dbg(pm8001_ha, FAIL,
2427                                    "SAS Address of IO Failure Drive:%08x%08x\n",
2428                                    temp_sata_addr_hi,
2429                                    temp_sata_addr_low);
2430
2431                 } else {
2432                         pm8001_dbg(pm8001_ha, FAIL,
2433                                    "SAS Address of IO Failure Drive:%016llx\n",
2434                                    SAS_ADDR(t->dev->sas_addr));
2435                 }
2436         }
2437         switch (status) {
2438         case IO_SUCCESS:
2439                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2440                 if (param == 0) {
2441                         ts->resp = SAS_TASK_COMPLETE;
2442                         ts->stat = SAS_SAM_STAT_GOOD;
2443                         /* check if response is for SEND READ LOG */
2444                         if (pm8001_dev &&
2445                             (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2446                                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2447                                 /* Free the tag */
2448                                 pm8001_tag_free(pm8001_ha, tag);
2449                                 sas_free_task(t);
2450                                 return;
2451                         }
2452                 } else {
2453                         u8 len;
2454                         ts->resp = SAS_TASK_COMPLETE;
2455                         ts->stat = SAS_PROTO_RESPONSE;
2456                         ts->residual = param;
2457                         pm8001_dbg(pm8001_ha, IO,
2458                                    "SAS_PROTO_RESPONSE len = %d\n",
2459                                    param);
2460                         sata_resp = &psataPayload->sata_resp[0];
2461                         resp = (struct ata_task_resp *)ts->buf;
2462                         if (t->ata_task.dma_xfer == 0 &&
2463                             t->data_dir == DMA_FROM_DEVICE) {
2464                                 len = sizeof(struct pio_setup_fis);
2465                                 pm8001_dbg(pm8001_ha, IO,
2466                                            "PIO read len = %d\n", len);
2467                         } else if (t->ata_task.use_ncq &&
2468                                    t->data_dir != DMA_NONE) {
2469                                 len = sizeof(struct set_dev_bits_fis);
2470                                 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2471                                            len);
2472                         } else {
2473                                 len = sizeof(struct dev_to_host_fis);
2474                                 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2475                                            len);
2476                         }
2477                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2478                                 resp->frame_len = len;
2479                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2480                                 ts->buf_valid_size = sizeof(*resp);
2481                         } else
2482                                 pm8001_dbg(pm8001_ha, IO,
2483                                            "response too large\n");
2484                 }
2485                 if (pm8001_dev)
2486                         atomic_dec(&pm8001_dev->running_req);
2487                 break;
2488         case IO_ABORTED:
2489                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2490                 ts->resp = SAS_TASK_COMPLETE;
2491                 ts->stat = SAS_ABORTED_TASK;
2492                 if (pm8001_dev)
2493                         atomic_dec(&pm8001_dev->running_req);
2494                 break;
2495                 /* following cases are to do cases */
2496         case IO_UNDERFLOW:
2497                 /* SATA Completion with error */
2498                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2499                 ts->resp = SAS_TASK_COMPLETE;
2500                 ts->stat = SAS_DATA_UNDERRUN;
2501                 ts->residual = param;
2502                 if (pm8001_dev)
2503                         atomic_dec(&pm8001_dev->running_req);
2504                 break;
2505         case IO_NO_DEVICE:
2506                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2507                 ts->resp = SAS_TASK_UNDELIVERED;
2508                 ts->stat = SAS_PHY_DOWN;
2509                 if (pm8001_dev)
2510                         atomic_dec(&pm8001_dev->running_req);
2511                 break;
2512         case IO_XFER_ERROR_BREAK:
2513                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2514                 ts->resp = SAS_TASK_COMPLETE;
2515                 ts->stat = SAS_INTERRUPTED;
2516                 if (pm8001_dev)
2517                         atomic_dec(&pm8001_dev->running_req);
2518                 break;
2519         case IO_XFER_ERROR_PHY_NOT_READY:
2520                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2521                 ts->resp = SAS_TASK_COMPLETE;
2522                 ts->stat = SAS_OPEN_REJECT;
2523                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2524                 if (pm8001_dev)
2525                         atomic_dec(&pm8001_dev->running_req);
2526                 break;
2527         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2528                 pm8001_dbg(pm8001_ha, IO,
2529                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2530                 ts->resp = SAS_TASK_COMPLETE;
2531                 ts->stat = SAS_OPEN_REJECT;
2532                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2533                 if (pm8001_dev)
2534                         atomic_dec(&pm8001_dev->running_req);
2535                 break;
2536         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2537                 pm8001_dbg(pm8001_ha, IO,
2538                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2539                 ts->resp = SAS_TASK_COMPLETE;
2540                 ts->stat = SAS_OPEN_REJECT;
2541                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2542                 if (pm8001_dev)
2543                         atomic_dec(&pm8001_dev->running_req);
2544                 break;
2545         case IO_OPEN_CNX_ERROR_BREAK:
2546                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2547                 ts->resp = SAS_TASK_COMPLETE;
2548                 ts->stat = SAS_OPEN_REJECT;
2549                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2550                 if (pm8001_dev)
2551                         atomic_dec(&pm8001_dev->running_req);
2552                 break;
2553         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2554         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2555         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2556         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2557         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2558         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2559                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2560                 ts->resp = SAS_TASK_COMPLETE;
2561                 ts->stat = SAS_DEV_NO_RESPONSE;
2562                 if (!t->uldd_task) {
2563                         pm8001_handle_event(pm8001_ha,
2564                                 pm8001_dev,
2565                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2566                         ts->resp = SAS_TASK_UNDELIVERED;
2567                         ts->stat = SAS_QUEUE_FULL;
2568                         spin_unlock_irqrestore(&circularQ->oq_lock,
2569                                         circularQ->lock_flags);
2570                         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2571                         spin_lock_irqsave(&circularQ->oq_lock,
2572                                         circularQ->lock_flags);
2573                         return;
2574                 }
2575                 break;
2576         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2577                 pm8001_dbg(pm8001_ha, IO,
2578                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2579                 ts->resp = SAS_TASK_UNDELIVERED;
2580                 ts->stat = SAS_OPEN_REJECT;
2581                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2582                 if (!t->uldd_task) {
2583                         pm8001_handle_event(pm8001_ha,
2584                                 pm8001_dev,
2585                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2586                         ts->resp = SAS_TASK_UNDELIVERED;
2587                         ts->stat = SAS_QUEUE_FULL;
2588                         spin_unlock_irqrestore(&circularQ->oq_lock,
2589                                         circularQ->lock_flags);
2590                         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2591                         spin_lock_irqsave(&circularQ->oq_lock,
2592                                         circularQ->lock_flags);
2593                         return;
2594                 }
2595                 break;
2596         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2597                 pm8001_dbg(pm8001_ha, IO,
2598                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2599                 ts->resp = SAS_TASK_COMPLETE;
2600                 ts->stat = SAS_OPEN_REJECT;
2601                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2602                 if (pm8001_dev)
2603                         atomic_dec(&pm8001_dev->running_req);
2604                 break;
2605         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2606                 pm8001_dbg(pm8001_ha, IO,
2607                            "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2608                 ts->resp = SAS_TASK_COMPLETE;
2609                 ts->stat = SAS_DEV_NO_RESPONSE;
2610                 if (!t->uldd_task) {
2611                         pm8001_handle_event(pm8001_ha,
2612                                 pm8001_dev,
2613                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2614                         ts->resp = SAS_TASK_UNDELIVERED;
2615                         ts->stat = SAS_QUEUE_FULL;
2616                         spin_unlock_irqrestore(&circularQ->oq_lock,
2617                                         circularQ->lock_flags);
2618                         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2619                         spin_lock_irqsave(&circularQ->oq_lock,
2620                                         circularQ->lock_flags);
2621                         return;
2622                 }
2623                 break;
2624         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2625                 pm8001_dbg(pm8001_ha, IO,
2626                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2627                 ts->resp = SAS_TASK_COMPLETE;
2628                 ts->stat = SAS_OPEN_REJECT;
2629                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2630                 if (pm8001_dev)
2631                         atomic_dec(&pm8001_dev->running_req);
2632                 break;
2633         case IO_XFER_ERROR_NAK_RECEIVED:
2634                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2635                 ts->resp = SAS_TASK_COMPLETE;
2636                 ts->stat = SAS_NAK_R_ERR;
2637                 if (pm8001_dev)
2638                         atomic_dec(&pm8001_dev->running_req);
2639                 break;
2640         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2641                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2642                 ts->resp = SAS_TASK_COMPLETE;
2643                 ts->stat = SAS_NAK_R_ERR;
2644                 if (pm8001_dev)
2645                         atomic_dec(&pm8001_dev->running_req);
2646                 break;
2647         case IO_XFER_ERROR_DMA:
2648                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2649                 ts->resp = SAS_TASK_COMPLETE;
2650                 ts->stat = SAS_ABORTED_TASK;
2651                 if (pm8001_dev)
2652                         atomic_dec(&pm8001_dev->running_req);
2653                 break;
2654         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2655                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2656                 ts->resp = SAS_TASK_UNDELIVERED;
2657                 ts->stat = SAS_DEV_NO_RESPONSE;
2658                 if (pm8001_dev)
2659                         atomic_dec(&pm8001_dev->running_req);
2660                 break;
2661         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2662                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2663                 ts->resp = SAS_TASK_COMPLETE;
2664                 ts->stat = SAS_DATA_UNDERRUN;
2665                 if (pm8001_dev)
2666                         atomic_dec(&pm8001_dev->running_req);
2667                 break;
2668         case IO_XFER_OPEN_RETRY_TIMEOUT:
2669                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2670                 ts->resp = SAS_TASK_COMPLETE;
2671                 ts->stat = SAS_OPEN_TO;
2672                 if (pm8001_dev)
2673                         atomic_dec(&pm8001_dev->running_req);
2674                 break;
2675         case IO_PORT_IN_RESET:
2676                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2677                 ts->resp = SAS_TASK_COMPLETE;
2678                 ts->stat = SAS_DEV_NO_RESPONSE;
2679                 if (pm8001_dev)
2680                         atomic_dec(&pm8001_dev->running_req);
2681                 break;
2682         case IO_DS_NON_OPERATIONAL:
2683                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2684                 ts->resp = SAS_TASK_COMPLETE;
2685                 ts->stat = SAS_DEV_NO_RESPONSE;
2686                 if (!t->uldd_task) {
2687                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2688                                         IO_DS_NON_OPERATIONAL);
2689                         ts->resp = SAS_TASK_UNDELIVERED;
2690                         ts->stat = SAS_QUEUE_FULL;
2691                         spin_unlock_irqrestore(&circularQ->oq_lock,
2692                                         circularQ->lock_flags);
2693                         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2694                         spin_lock_irqsave(&circularQ->oq_lock,
2695                                         circularQ->lock_flags);
2696                         return;
2697                 }
2698                 break;
2699         case IO_DS_IN_RECOVERY:
2700                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2701                 ts->resp = SAS_TASK_COMPLETE;
2702                 ts->stat = SAS_DEV_NO_RESPONSE;
2703                 if (pm8001_dev)
2704                         atomic_dec(&pm8001_dev->running_req);
2705                 break;
2706         case IO_DS_IN_ERROR:
2707                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2708                 ts->resp = SAS_TASK_COMPLETE;
2709                 ts->stat = SAS_DEV_NO_RESPONSE;
2710                 if (!t->uldd_task) {
2711                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2712                                         IO_DS_IN_ERROR);
2713                         ts->resp = SAS_TASK_UNDELIVERED;
2714                         ts->stat = SAS_QUEUE_FULL;
2715                         spin_unlock_irqrestore(&circularQ->oq_lock,
2716                                         circularQ->lock_flags);
2717                         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2718                         spin_lock_irqsave(&circularQ->oq_lock,
2719                                         circularQ->lock_flags);
2720                         return;
2721                 }
2722                 break;
2723         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2724                 pm8001_dbg(pm8001_ha, IO,
2725                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2726                 ts->resp = SAS_TASK_COMPLETE;
2727                 ts->stat = SAS_OPEN_REJECT;
2728                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2729                 if (pm8001_dev)
2730                         atomic_dec(&pm8001_dev->running_req);
2731                 break;
2732         default:
2733                 pm8001_dbg(pm8001_ha, DEVIO,
2734                                 "Unknown status device_id %u status 0x%x tag %d\n",
2735                         pm8001_dev->device_id, status, tag);
2736                 /* not allowed case. Therefore, return failed status */
2737                 ts->resp = SAS_TASK_COMPLETE;
2738                 ts->stat = SAS_DEV_NO_RESPONSE;
2739                 if (pm8001_dev)
2740                         atomic_dec(&pm8001_dev->running_req);
2741                 break;
2742         }
2743         spin_lock_irqsave(&t->task_state_lock, flags);
2744         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2745         t->task_state_flags |= SAS_TASK_STATE_DONE;
2746         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2747                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2748                 pm8001_dbg(pm8001_ha, FAIL,
2749                            "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2750                            t, status, ts->resp, ts->stat);
2751                 pm8001_ccb_task_free(pm8001_ha, ccb);
2752                 if (t->slow_task)
2753                         complete(&t->slow_task->completion);
2754         } else {
2755                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2756                 spin_unlock_irqrestore(&circularQ->oq_lock,
2757                                 circularQ->lock_flags);
2758                 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2759                 spin_lock_irqsave(&circularQ->oq_lock,
2760                                 circularQ->lock_flags);
2761         }
2762 }
2763
2764 /*See the comments for mpi_ssp_completion */
2765 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha,
2766                 struct outbound_queue_table *circularQ, void *piomb)
2767 {
2768         struct sas_task *t;
2769         struct task_status_struct *ts;
2770         struct pm8001_ccb_info *ccb;
2771         struct pm8001_device *pm8001_dev;
2772         struct sata_event_resp *psataPayload =
2773                 (struct sata_event_resp *)(piomb + 4);
2774         u32 event = le32_to_cpu(psataPayload->event);
2775         u32 tag = le32_to_cpu(psataPayload->tag);
2776         u32 port_id = le32_to_cpu(psataPayload->port_id);
2777         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2778
2779         if (event)
2780                 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2781
2782         /* Check if this is NCQ error */
2783         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2784                 /* find device using device id */
2785                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2786                 /* send read log extension */
2787                 if (pm8001_dev)
2788                         pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2789                 return;
2790         }
2791
2792         ccb = &pm8001_ha->ccb_info[tag];
2793         t = ccb->task;
2794         pm8001_dev = ccb->device;
2795
2796         if (unlikely(!t || !t->lldd_task || !t->dev)) {
2797                 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2798                 return;
2799         }
2800
2801         ts = &t->task_status;
2802         pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2803                    port_id, tag, event);
2804         switch (event) {
2805         case IO_OVERFLOW:
2806                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2807                 ts->resp = SAS_TASK_COMPLETE;
2808                 ts->stat = SAS_DATA_OVERRUN;
2809                 ts->residual = 0;
2810                 break;
2811         case IO_XFER_ERROR_BREAK:
2812                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2813                 ts->resp = SAS_TASK_COMPLETE;
2814                 ts->stat = SAS_INTERRUPTED;
2815                 break;
2816         case IO_XFER_ERROR_PHY_NOT_READY:
2817                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2818                 ts->resp = SAS_TASK_COMPLETE;
2819                 ts->stat = SAS_OPEN_REJECT;
2820                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2821                 break;
2822         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2823                 pm8001_dbg(pm8001_ha, IO,
2824                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2825                 ts->resp = SAS_TASK_COMPLETE;
2826                 ts->stat = SAS_OPEN_REJECT;
2827                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2828                 break;
2829         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2830                 pm8001_dbg(pm8001_ha, IO,
2831                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2832                 ts->resp = SAS_TASK_COMPLETE;
2833                 ts->stat = SAS_OPEN_REJECT;
2834                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2835                 break;
2836         case IO_OPEN_CNX_ERROR_BREAK:
2837                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2838                 ts->resp = SAS_TASK_COMPLETE;
2839                 ts->stat = SAS_OPEN_REJECT;
2840                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2841                 break;
2842         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2843         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2844         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2845         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2846         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2847         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2848                 pm8001_dbg(pm8001_ha, FAIL,
2849                            "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2850                 ts->resp = SAS_TASK_UNDELIVERED;
2851                 ts->stat = SAS_DEV_NO_RESPONSE;
2852                 if (!t->uldd_task) {
2853                         pm8001_handle_event(pm8001_ha,
2854                                 pm8001_dev,
2855                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2856                         ts->resp = SAS_TASK_COMPLETE;
2857                         ts->stat = SAS_QUEUE_FULL;
2858                         return;
2859                 }
2860                 break;
2861         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2862                 pm8001_dbg(pm8001_ha, IO,
2863                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2864                 ts->resp = SAS_TASK_UNDELIVERED;
2865                 ts->stat = SAS_OPEN_REJECT;
2866                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2867                 break;
2868         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2869                 pm8001_dbg(pm8001_ha, IO,
2870                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2871                 ts->resp = SAS_TASK_COMPLETE;
2872                 ts->stat = SAS_OPEN_REJECT;
2873                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2874                 break;
2875         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2876                 pm8001_dbg(pm8001_ha, IO,
2877                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2878                 ts->resp = SAS_TASK_COMPLETE;
2879                 ts->stat = SAS_OPEN_REJECT;
2880                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2881                 break;
2882         case IO_XFER_ERROR_NAK_RECEIVED:
2883                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2884                 ts->resp = SAS_TASK_COMPLETE;
2885                 ts->stat = SAS_NAK_R_ERR;
2886                 break;
2887         case IO_XFER_ERROR_PEER_ABORTED:
2888                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2889                 ts->resp = SAS_TASK_COMPLETE;
2890                 ts->stat = SAS_NAK_R_ERR;
2891                 break;
2892         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2893                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2894                 ts->resp = SAS_TASK_COMPLETE;
2895                 ts->stat = SAS_DATA_UNDERRUN;
2896                 break;
2897         case IO_XFER_OPEN_RETRY_TIMEOUT:
2898                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2899                 ts->resp = SAS_TASK_COMPLETE;
2900                 ts->stat = SAS_OPEN_TO;
2901                 break;
2902         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2903                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2904                 ts->resp = SAS_TASK_COMPLETE;
2905                 ts->stat = SAS_OPEN_TO;
2906                 break;
2907         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2908                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2909                 ts->resp = SAS_TASK_COMPLETE;
2910                 ts->stat = SAS_OPEN_TO;
2911                 break;
2912         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2913                 pm8001_dbg(pm8001_ha, IO,
2914                            "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2915                 ts->resp = SAS_TASK_COMPLETE;
2916                 ts->stat = SAS_OPEN_TO;
2917                 break;
2918         case IO_XFER_ERROR_OFFSET_MISMATCH:
2919                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2920                 ts->resp = SAS_TASK_COMPLETE;
2921                 ts->stat = SAS_OPEN_TO;
2922                 break;
2923         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2924                 pm8001_dbg(pm8001_ha, IO,
2925                            "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2926                 ts->resp = SAS_TASK_COMPLETE;
2927                 ts->stat = SAS_OPEN_TO;
2928                 break;
2929         case IO_XFER_CMD_FRAME_ISSUED:
2930                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2931                 break;
2932         case IO_XFER_PIO_SETUP_ERROR:
2933                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2934                 ts->resp = SAS_TASK_COMPLETE;
2935                 ts->stat = SAS_OPEN_TO;
2936                 break;
2937         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2938                 pm8001_dbg(pm8001_ha, FAIL,
2939                            "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2940                 /* TBC: used default set values */
2941                 ts->resp = SAS_TASK_COMPLETE;
2942                 ts->stat = SAS_OPEN_TO;
2943                 break;
2944         case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2945                 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n");
2946                 /* TBC: used default set values */
2947                 ts->resp = SAS_TASK_COMPLETE;
2948                 ts->stat = SAS_OPEN_TO;
2949                 break;
2950         default:
2951                 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);
2952                 /* not allowed case. Therefore, return failed status */
2953                 ts->resp = SAS_TASK_COMPLETE;
2954                 ts->stat = SAS_OPEN_TO;
2955                 break;
2956         }
2957 }
2958
2959 /*See the comments for mpi_ssp_completion */
2960 static void
2961 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2962 {
2963         u32 param, i;
2964         struct sas_task *t;
2965         struct pm8001_ccb_info *ccb;
2966         unsigned long flags;
2967         u32 status;
2968         u32 tag;
2969         struct smp_completion_resp *psmpPayload;
2970         struct task_status_struct *ts;
2971         struct pm8001_device *pm8001_dev;
2972
2973         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2974         status = le32_to_cpu(psmpPayload->status);
2975         tag = le32_to_cpu(psmpPayload->tag);
2976
2977         ccb = &pm8001_ha->ccb_info[tag];
2978         param = le32_to_cpu(psmpPayload->param);
2979         t = ccb->task;
2980         ts = &t->task_status;
2981         pm8001_dev = ccb->device;
2982         if (status)
2983                 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2984         if (unlikely(!t || !t->lldd_task || !t->dev))
2985                 return;
2986
2987         pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);
2988
2989         switch (status) {
2990
2991         case IO_SUCCESS:
2992                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2993                 ts->resp = SAS_TASK_COMPLETE;
2994                 ts->stat = SAS_SAM_STAT_GOOD;
2995                 if (pm8001_dev)
2996                         atomic_dec(&pm8001_dev->running_req);
2997                 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2998                         struct scatterlist *sg_resp = &t->smp_task.smp_resp;
2999                         u8 *payload;
3000                         void *to;
3001
3002                         pm8001_dbg(pm8001_ha, IO,
3003                                    "DIRECT RESPONSE Length:%d\n",
3004                                    param);
3005                         to = kmap_atomic(sg_page(sg_resp));
3006                         payload = to + sg_resp->offset;
3007                         for (i = 0; i < param; i++) {
3008                                 *(payload + i) = psmpPayload->_r_a[i];
3009                                 pm8001_dbg(pm8001_ha, IO,
3010                                            "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
3011                                            i, *(payload + i),
3012                                            psmpPayload->_r_a[i]);
3013                         }
3014                         kunmap_atomic(to);
3015                 }
3016                 break;
3017         case IO_ABORTED:
3018                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
3019                 ts->resp = SAS_TASK_COMPLETE;
3020                 ts->stat = SAS_ABORTED_TASK;
3021                 if (pm8001_dev)
3022                         atomic_dec(&pm8001_dev->running_req);
3023                 break;
3024         case IO_OVERFLOW:
3025                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
3026                 ts->resp = SAS_TASK_COMPLETE;
3027                 ts->stat = SAS_DATA_OVERRUN;
3028                 ts->residual = 0;
3029                 if (pm8001_dev)
3030                         atomic_dec(&pm8001_dev->running_req);
3031                 break;
3032         case IO_NO_DEVICE:
3033                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
3034                 ts->resp = SAS_TASK_COMPLETE;
3035                 ts->stat = SAS_PHY_DOWN;
3036                 break;
3037         case IO_ERROR_HW_TIMEOUT:
3038                 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
3039                 ts->resp = SAS_TASK_COMPLETE;
3040                 ts->stat = SAS_SAM_STAT_BUSY;
3041                 break;
3042         case IO_XFER_ERROR_BREAK:
3043                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
3044                 ts->resp = SAS_TASK_COMPLETE;
3045                 ts->stat = SAS_SAM_STAT_BUSY;
3046                 break;
3047         case IO_XFER_ERROR_PHY_NOT_READY:
3048                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
3049                 ts->resp = SAS_TASK_COMPLETE;
3050                 ts->stat = SAS_SAM_STAT_BUSY;
3051                 break;
3052         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3053                 pm8001_dbg(pm8001_ha, IO,
3054                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
3055                 ts->resp = SAS_TASK_COMPLETE;
3056                 ts->stat = SAS_OPEN_REJECT;
3057                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3058                 break;
3059         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3060                 pm8001_dbg(pm8001_ha, IO,
3061                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
3062                 ts->resp = SAS_TASK_COMPLETE;
3063                 ts->stat = SAS_OPEN_REJECT;
3064                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3065                 break;
3066         case IO_OPEN_CNX_ERROR_BREAK:
3067                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
3068                 ts->resp = SAS_TASK_COMPLETE;
3069                 ts->stat = SAS_OPEN_REJECT;
3070                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3071                 break;
3072         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3073         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3074         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3075         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3076         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3077         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3078                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
3079                 ts->resp = SAS_TASK_COMPLETE;
3080                 ts->stat = SAS_OPEN_REJECT;
3081                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3082                 pm8001_handle_event(pm8001_ha,
3083                                 pm8001_dev,
3084                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3085                 break;
3086         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3087                 pm8001_dbg(pm8001_ha, IO,
3088                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
3089                 ts->resp = SAS_TASK_COMPLETE;
3090                 ts->stat = SAS_OPEN_REJECT;
3091                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3092                 break;
3093         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3094                 pm8001_dbg(pm8001_ha, IO,
3095                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
3096                 ts->resp = SAS_TASK_COMPLETE;
3097                 ts->stat = SAS_OPEN_REJECT;
3098                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3099                 break;
3100         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3101                 pm8001_dbg(pm8001_ha, IO,
3102                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
3103                 ts->resp = SAS_TASK_COMPLETE;
3104                 ts->stat = SAS_OPEN_REJECT;
3105                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3106                 break;
3107         case IO_XFER_ERROR_RX_FRAME:
3108                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
3109                 ts->resp = SAS_TASK_COMPLETE;
3110                 ts->stat = SAS_DEV_NO_RESPONSE;
3111                 break;
3112         case IO_XFER_OPEN_RETRY_TIMEOUT:
3113                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3114                 ts->resp = SAS_TASK_COMPLETE;
3115                 ts->stat = SAS_OPEN_REJECT;
3116                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3117                 break;
3118         case IO_ERROR_INTERNAL_SMP_RESOURCE:
3119                 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3120                 ts->resp = SAS_TASK_COMPLETE;
3121                 ts->stat = SAS_QUEUE_FULL;
3122                 break;
3123         case IO_PORT_IN_RESET:
3124                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3125                 ts->resp = SAS_TASK_COMPLETE;
3126                 ts->stat = SAS_OPEN_REJECT;
3127                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3128                 break;
3129         case IO_DS_NON_OPERATIONAL:
3130                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3131                 ts->resp = SAS_TASK_COMPLETE;
3132                 ts->stat = SAS_DEV_NO_RESPONSE;
3133                 break;
3134         case IO_DS_IN_RECOVERY:
3135                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3136                 ts->resp = SAS_TASK_COMPLETE;
3137                 ts->stat = SAS_OPEN_REJECT;
3138                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3139                 break;
3140         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3141                 pm8001_dbg(pm8001_ha, IO,
3142                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3143                 ts->resp = SAS_TASK_COMPLETE;
3144                 ts->stat = SAS_OPEN_REJECT;
3145                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3146                 break;
3147         default:
3148                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3149                 ts->resp = SAS_TASK_COMPLETE;
3150                 ts->stat = SAS_DEV_NO_RESPONSE;
3151                 /* not allowed case. Therefore, return failed status */
3152                 break;
3153         }
3154         spin_lock_irqsave(&t->task_state_lock, flags);
3155         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3156         t->task_state_flags |= SAS_TASK_STATE_DONE;
3157         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3158                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3159                 pm8001_dbg(pm8001_ha, FAIL,
3160                            "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",
3161                            t, status, ts->resp, ts->stat);
3162                 pm8001_ccb_task_free(pm8001_ha, ccb);
3163         } else {
3164                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3165                 pm8001_ccb_task_free(pm8001_ha, ccb);
3166                 mb();/* in order to force CPU ordering */
3167                 t->task_done(t);
3168         }
3169 }
3170
3171 /**
3172  * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW.
3173  * @pm8001_ha: our hba card information
3174  * @Qnum: the outbound queue message number.
3175  * @SEA: source of event to ack
3176  * @port_id: port id.
3177  * @phyId: phy id.
3178  * @param0: parameter 0.
3179  * @param1: parameter 1.
3180  */
3181 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3182         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3183 {
3184         struct hw_event_ack_req  payload;
3185         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3186
3187         memset((u8 *)&payload, 0, sizeof(payload));
3188         payload.tag = cpu_to_le32(1);
3189         payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3190                 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3191         payload.param0 = cpu_to_le32(param0);
3192         payload.param1 = cpu_to_le32(param1);
3193
3194         pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload,
3195                              sizeof(payload), 0);
3196 }
3197
3198 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3199         u32 phyId, u32 phy_op);
3200
3201 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3202                                         void *piomb)
3203 {
3204         struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3205         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3206         u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3207         u32 lr_status_evt_portid =
3208                 le32_to_cpu(pPayload->lr_status_evt_portid);
3209         u8 deviceType = pPayload->sas_identify.dev_type;
3210         u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3211         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3212         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3213         struct pm8001_port *port = &pm8001_ha->port[port_id];
3214
3215         if (deviceType == SAS_END_DEVICE) {
3216                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3217                                         PHY_NOTIFY_ENABLE_SPINUP);
3218         }
3219
3220         port->wide_port_phymap |= (1U << phy_id);
3221         pm8001_get_lrate_mode(phy, link_rate);
3222         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3223         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3224         phy->phy_attached = 1;
3225 }
3226
3227 /**
3228  * hw_event_sas_phy_up - FW tells me a SAS phy up event.
3229  * @pm8001_ha: our hba card information
3230  * @piomb: IO message buffer
3231  */
3232 static void
3233 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3234 {
3235         struct hw_event_resp *pPayload =
3236                 (struct hw_event_resp *)(piomb + 4);
3237         u32 lr_status_evt_portid =
3238                 le32_to_cpu(pPayload->lr_status_evt_portid);
3239         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3240
3241         u8 link_rate =
3242                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3243         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3244         u8 phy_id =
3245                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3246         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3247
3248         struct pm8001_port *port = &pm8001_ha->port[port_id];
3249         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3250         unsigned long flags;
3251         u8 deviceType = pPayload->sas_identify.dev_type;
3252         phy->port = port;
3253         port->port_id = port_id;
3254         port->port_state = portstate;
3255         port->wide_port_phymap |= (1U << phy_id);
3256         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3257         pm8001_dbg(pm8001_ha, MSG,
3258                    "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n",
3259                    port_id, phy_id, link_rate, portstate, deviceType);
3260
3261         switch (deviceType) {
3262         case SAS_PHY_UNUSED:
3263                 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3264                 break;
3265         case SAS_END_DEVICE:
3266                 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3267                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3268                         PHY_NOTIFY_ENABLE_SPINUP);
3269                 port->port_attached = 1;
3270                 pm8001_get_lrate_mode(phy, link_rate);
3271                 break;
3272         case SAS_EDGE_EXPANDER_DEVICE:
3273                 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3274                 port->port_attached = 1;
3275                 pm8001_get_lrate_mode(phy, link_rate);
3276                 break;
3277         case SAS_FANOUT_EXPANDER_DEVICE:
3278                 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3279                 port->port_attached = 1;
3280                 pm8001_get_lrate_mode(phy, link_rate);
3281                 break;
3282         default:
3283                 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3284                            deviceType);
3285                 break;
3286         }
3287         phy->phy_type |= PORT_TYPE_SAS;
3288         phy->identify.device_type = deviceType;
3289         phy->phy_attached = 1;
3290         if (phy->identify.device_type == SAS_END_DEVICE)
3291                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3292         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3293                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3294         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3295         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3296         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3297         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3298                 sizeof(struct sas_identify_frame)-4);
3299         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3300         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3301         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3302         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3303                 mdelay(200); /* delay a moment to wait for disk to spin up */
3304         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3305 }
3306
3307 /**
3308  * hw_event_sata_phy_up - FW tells me a SATA phy up event.
3309  * @pm8001_ha: our hba card information
3310  * @piomb: IO message buffer
3311  */
3312 static void
3313 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3314 {
3315         struct hw_event_resp *pPayload =
3316                 (struct hw_event_resp *)(piomb + 4);
3317         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3318         u32 lr_status_evt_portid =
3319                 le32_to_cpu(pPayload->lr_status_evt_portid);
3320         u8 link_rate =
3321                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3322         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3323         u8 phy_id =
3324                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3325
3326         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3327
3328         struct pm8001_port *port = &pm8001_ha->port[port_id];
3329         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3330         unsigned long flags;
3331         pm8001_dbg(pm8001_ha, DEVIO,
3332                    "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3333                    port_id, phy_id, link_rate, portstate);
3334
3335         phy->port = port;
3336         port->port_id = port_id;
3337         port->port_state = portstate;
3338         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3339         port->port_attached = 1;
3340         pm8001_get_lrate_mode(phy, link_rate);
3341         phy->phy_type |= PORT_TYPE_SATA;
3342         phy->phy_attached = 1;
3343         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3344         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3345         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3346         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3347                 sizeof(struct dev_to_host_fis));
3348         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3349         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3350         phy->identify.device_type = SAS_SATA_DEV;
3351         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3352         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3353         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3354 }
3355
3356 /**
3357  * hw_event_phy_down - we should notify the libsas the phy is down.
3358  * @pm8001_ha: our hba card information
3359  * @piomb: IO message buffer
3360  */
3361 static void
3362 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3363 {
3364         struct hw_event_resp *pPayload =
3365                 (struct hw_event_resp *)(piomb + 4);
3366
3367         u32 lr_status_evt_portid =
3368                 le32_to_cpu(pPayload->lr_status_evt_portid);
3369         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3370         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3371         u8 phy_id =
3372                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3373         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3374
3375         struct pm8001_port *port = &pm8001_ha->port[port_id];
3376         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3377         u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3378         port->port_state = portstate;
3379         phy->identify.device_type = 0;
3380         phy->phy_attached = 0;
3381         switch (portstate) {
3382         case PORT_VALID:
3383                 break;
3384         case PORT_INVALID:
3385                 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3386                            port_id);
3387                 pm8001_dbg(pm8001_ha, MSG,
3388                            " Last phy Down and port invalid\n");
3389                 if (port_sata) {
3390                         phy->phy_type = 0;
3391                         port->port_attached = 0;
3392                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3393                                         port_id, phy_id, 0, 0);
3394                 }
3395                 sas_phy_disconnected(&phy->sas_phy);
3396                 break;
3397         case PORT_IN_RESET:
3398                 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3399                            port_id);
3400                 break;
3401         case PORT_NOT_ESTABLISHED:
3402                 pm8001_dbg(pm8001_ha, MSG,
3403                            " Phy Down and PORT_NOT_ESTABLISHED\n");
3404                 port->port_attached = 0;
3405                 break;
3406         case PORT_LOSTCOMM:
3407                 pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n");
3408                 pm8001_dbg(pm8001_ha, MSG,
3409                            " Last phy Down and port invalid\n");
3410                 if (port_sata) {
3411                         port->port_attached = 0;
3412                         phy->phy_type = 0;
3413                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3414                                         port_id, phy_id, 0, 0);
3415                 }
3416                 sas_phy_disconnected(&phy->sas_phy);
3417                 break;
3418         default:
3419                 port->port_attached = 0;
3420                 pm8001_dbg(pm8001_ha, DEVIO,
3421                            " Phy Down and(default) = 0x%x\n",
3422                            portstate);
3423                 break;
3424
3425         }
3426         if (port_sata && (portstate != PORT_IN_RESET))
3427                 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3428                                 GFP_ATOMIC);
3429 }
3430
3431 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3432 {
3433         struct phy_start_resp *pPayload =
3434                 (struct phy_start_resp *)(piomb + 4);
3435         u32 status =
3436                 le32_to_cpu(pPayload->status);
3437         u32 phy_id =
3438                 le32_to_cpu(pPayload->phyid) & 0xFF;
3439         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3440
3441         pm8001_dbg(pm8001_ha, INIT,
3442                    "phy start resp status:0x%x, phyid:0x%x\n",
3443                    status, phy_id);
3444         if (status == 0)
3445                 phy->phy_state = PHY_LINK_DOWN;
3446
3447         if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3448                         phy->enable_completion != NULL) {
3449                 complete(phy->enable_completion);
3450                 phy->enable_completion = NULL;
3451         }
3452         return 0;
3453
3454 }
3455
3456 /**
3457  * mpi_thermal_hw_event - a thermal hw event has come.
3458  * @pm8001_ha: our hba card information
3459  * @piomb: IO message buffer
3460  */
3461 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3462 {
3463         struct thermal_hw_event *pPayload =
3464                 (struct thermal_hw_event *)(piomb + 4);
3465
3466         u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3467         u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3468
3469         if (thermal_event & 0x40) {
3470                 pm8001_dbg(pm8001_ha, IO,
3471                            "Thermal Event: Local high temperature violated!\n");
3472                 pm8001_dbg(pm8001_ha, IO,
3473                            "Thermal Event: Measured local high temperature %d\n",
3474                            ((rht_lht & 0xFF00) >> 8));
3475         }
3476         if (thermal_event & 0x10) {
3477                 pm8001_dbg(pm8001_ha, IO,
3478                            "Thermal Event: Remote high temperature violated!\n");
3479                 pm8001_dbg(pm8001_ha, IO,
3480                            "Thermal Event: Measured remote high temperature %d\n",
3481                            ((rht_lht & 0xFF000000) >> 24));
3482         }
3483         return 0;
3484 }
3485
3486 /**
3487  * mpi_hw_event - The hw event has come.
3488  * @pm8001_ha: our hba card information
3489  * @piomb: IO message buffer
3490  */
3491 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3492 {
3493         unsigned long flags, i;
3494         struct hw_event_resp *pPayload =
3495                 (struct hw_event_resp *)(piomb + 4);
3496         u32 lr_status_evt_portid =
3497                 le32_to_cpu(pPayload->lr_status_evt_portid);
3498         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3499         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3500         u8 phy_id =
3501                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3502         u16 eventType =
3503                 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3504         u8 status =
3505                 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3506         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3507         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3508         struct pm8001_port *port = &pm8001_ha->port[port_id];
3509         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3510         pm8001_dbg(pm8001_ha, DEV,
3511                    "portid:%d phyid:%d event:0x%x status:0x%x\n",
3512                    port_id, phy_id, eventType, status);
3513
3514         switch (eventType) {
3515
3516         case HW_EVENT_SAS_PHY_UP:
3517                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3518                 hw_event_sas_phy_up(pm8001_ha, piomb);
3519                 break;
3520         case HW_EVENT_SATA_PHY_UP:
3521                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3522                 hw_event_sata_phy_up(pm8001_ha, piomb);
3523                 break;
3524         case HW_EVENT_SATA_SPINUP_HOLD:
3525                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3526                 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3527                         GFP_ATOMIC);
3528                 break;
3529         case HW_EVENT_PHY_DOWN:
3530                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3531                 hw_event_phy_down(pm8001_ha, piomb);
3532                 if (pm8001_ha->reset_in_progress) {
3533                         pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n");
3534                         return 0;
3535                 }
3536                 phy->phy_attached = 0;
3537                 phy->phy_state = PHY_LINK_DISABLE;
3538                 break;
3539         case HW_EVENT_PORT_INVALID:
3540                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3541                 sas_phy_disconnected(sas_phy);
3542                 phy->phy_attached = 0;
3543                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3544                         GFP_ATOMIC);
3545                 break;
3546         /* the broadcast change primitive received, tell the LIBSAS this event
3547         to revalidate the sas domain*/
3548         case HW_EVENT_BROADCAST_CHANGE:
3549                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3550                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3551                         port_id, phy_id, 1, 0);
3552                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3553                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3554                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3555                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3556                         GFP_ATOMIC);
3557                 break;
3558         case HW_EVENT_PHY_ERROR:
3559                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3560                 sas_phy_disconnected(&phy->sas_phy);
3561                 phy->phy_attached = 0;
3562                 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3563                 break;
3564         case HW_EVENT_BROADCAST_EXP:
3565                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3566                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3567                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3568                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3569                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3570                         GFP_ATOMIC);
3571                 break;
3572         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3573                 pm8001_dbg(pm8001_ha, MSG,
3574                            "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3575                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3576                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3577                 break;
3578         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3579                 pm8001_dbg(pm8001_ha, MSG,
3580                            "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3581                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3582                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3583                         port_id, phy_id, 0, 0);
3584                 break;
3585         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3586                 pm8001_dbg(pm8001_ha, MSG,
3587                            "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3588                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3589                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3590                         port_id, phy_id, 0, 0);
3591                 break;
3592         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3593                 pm8001_dbg(pm8001_ha, MSG,
3594                            "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3595                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3596                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3597                         port_id, phy_id, 0, 0);
3598                 break;
3599         case HW_EVENT_MALFUNCTION:
3600                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3601                 break;
3602         case HW_EVENT_BROADCAST_SES:
3603                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3604                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3605                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3606                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3607                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3608                         GFP_ATOMIC);
3609                 break;
3610         case HW_EVENT_INBOUND_CRC_ERROR:
3611                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3612                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3613                         HW_EVENT_INBOUND_CRC_ERROR,
3614                         port_id, phy_id, 0, 0);
3615                 break;
3616         case HW_EVENT_HARD_RESET_RECEIVED:
3617                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3618                 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3619                 break;
3620         case HW_EVENT_ID_FRAME_TIMEOUT:
3621                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3622                 sas_phy_disconnected(sas_phy);
3623                 phy->phy_attached = 0;
3624                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3625                         GFP_ATOMIC);
3626                 break;
3627         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3628                 pm8001_dbg(pm8001_ha, MSG,
3629                            "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3630                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3631                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3632                         port_id, phy_id, 0, 0);
3633                 sas_phy_disconnected(sas_phy);
3634                 phy->phy_attached = 0;
3635                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3636                         GFP_ATOMIC);
3637                 break;
3638         case HW_EVENT_PORT_RESET_TIMER_TMO:
3639                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3640                 if (!pm8001_ha->phy[phy_id].reset_completion) {
3641                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3642                                 port_id, phy_id, 0, 0);
3643                 }
3644                 sas_phy_disconnected(sas_phy);
3645                 phy->phy_attached = 0;
3646                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3647                         GFP_ATOMIC);
3648                 if (pm8001_ha->phy[phy_id].reset_completion) {
3649                         pm8001_ha->phy[phy_id].port_reset_status =
3650                                         PORT_RESET_TMO;
3651                         complete(pm8001_ha->phy[phy_id].reset_completion);
3652                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3653                 }
3654                 break;
3655         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3656                 pm8001_dbg(pm8001_ha, MSG,
3657                            "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3658                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3659                         HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3660                         port_id, phy_id, 0, 0);
3661                 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3662                         if (port->wide_port_phymap & (1 << i)) {
3663                                 phy = &pm8001_ha->phy[i];
3664                                 sas_notify_phy_event(&phy->sas_phy,
3665                                         PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC);
3666                                 port->wide_port_phymap &= ~(1 << i);
3667                         }
3668                 }
3669                 break;
3670         case HW_EVENT_PORT_RECOVER:
3671                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3672                 hw_event_port_recover(pm8001_ha, piomb);
3673                 break;
3674         case HW_EVENT_PORT_RESET_COMPLETE:
3675                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3676                 if (pm8001_ha->phy[phy_id].reset_completion) {
3677                         pm8001_ha->phy[phy_id].port_reset_status =
3678                                         PORT_RESET_SUCCESS;
3679                         complete(pm8001_ha->phy[phy_id].reset_completion);
3680                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3681                 }
3682                 break;
3683         case EVENT_BROADCAST_ASYNCH_EVENT:
3684                 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3685                 break;
3686         default:
3687                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n",
3688                            eventType);
3689                 break;
3690         }
3691         return 0;
3692 }
3693
3694 /**
3695  * mpi_phy_stop_resp - SPCv specific
3696  * @pm8001_ha: our hba card information
3697  * @piomb: IO message buffer
3698  */
3699 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3700 {
3701         struct phy_stop_resp *pPayload =
3702                 (struct phy_stop_resp *)(piomb + 4);
3703         u32 status =
3704                 le32_to_cpu(pPayload->status);
3705         u32 phyid =
3706                 le32_to_cpu(pPayload->phyid) & 0xFF;
3707         struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3708         pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n",
3709                    phyid, status);
3710         if (status == PHY_STOP_SUCCESS ||
3711                 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3712                 phy->phy_state = PHY_LINK_DISABLE;
3713         return 0;
3714 }
3715
3716 /**
3717  * mpi_set_controller_config_resp - SPCv specific
3718  * @pm8001_ha: our hba card information
3719  * @piomb: IO message buffer
3720  */
3721 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3722                         void *piomb)
3723 {
3724         struct set_ctrl_cfg_resp *pPayload =
3725                         (struct set_ctrl_cfg_resp *)(piomb + 4);
3726         u32 status = le32_to_cpu(pPayload->status);
3727         u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3728
3729         pm8001_dbg(pm8001_ha, MSG,
3730                    "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3731                    status, err_qlfr_pgcd);
3732
3733         return 0;
3734 }
3735
3736 /**
3737  * mpi_get_controller_config_resp - SPCv specific
3738  * @pm8001_ha: our hba card information
3739  * @piomb: IO message buffer
3740  */
3741 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3742                         void *piomb)
3743 {
3744         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3745
3746         return 0;
3747 }
3748
3749 /**
3750  * mpi_get_phy_profile_resp - SPCv specific
3751  * @pm8001_ha: our hba card information
3752  * @piomb: IO message buffer
3753  */
3754 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3755                         void *piomb)
3756 {
3757         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3758
3759         return 0;
3760 }
3761
3762 /**
3763  * mpi_flash_op_ext_resp - SPCv specific
3764  * @pm8001_ha: our hba card information
3765  * @piomb: IO message buffer
3766  */
3767 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3768 {
3769         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3770
3771         return 0;
3772 }
3773
3774 /**
3775  * mpi_set_phy_profile_resp - SPCv specific
3776  * @pm8001_ha: our hba card information
3777  * @piomb: IO message buffer
3778  */
3779 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3780                         void *piomb)
3781 {
3782         u32 tag;
3783         u8 page_code;
3784         int rc = 0;
3785         struct set_phy_profile_resp *pPayload =
3786                 (struct set_phy_profile_resp *)(piomb + 4);
3787         u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3788         u32 status = le32_to_cpu(pPayload->status);
3789
3790         tag = le32_to_cpu(pPayload->tag);
3791         page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3792         if (status) {
3793                 /* status is FAILED */
3794                 pm8001_dbg(pm8001_ha, FAIL,
3795                            "PhyProfile command failed  with status 0x%08X\n",
3796                            status);
3797                 rc = -1;
3798         } else {
3799                 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3800                         pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",
3801                                    page_code);
3802                         rc = -1;
3803                 }
3804         }
3805         pm8001_tag_free(pm8001_ha, tag);
3806         return rc;
3807 }
3808
3809 /**
3810  * mpi_kek_management_resp - SPCv specific
3811  * @pm8001_ha: our hba card information
3812  * @piomb: IO message buffer
3813  */
3814 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3815                         void *piomb)
3816 {
3817         struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3818
3819         u32 status = le32_to_cpu(pPayload->status);
3820         u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3821         u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3822
3823         pm8001_dbg(pm8001_ha, MSG,
3824                    "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3825                    status, kidx_new_curr_ksop, err_qlfr);
3826
3827         return 0;
3828 }
3829
3830 /**
3831  * mpi_dek_management_resp - SPCv specific
3832  * @pm8001_ha: our hba card information
3833  * @piomb: IO message buffer
3834  */
3835 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3836                         void *piomb)
3837 {
3838         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3839
3840         return 0;
3841 }
3842
3843 /**
3844  * ssp_coalesced_comp_resp - SPCv specific
3845  * @pm8001_ha: our hba card information
3846  * @piomb: IO message buffer
3847  */
3848 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3849                         void *piomb)
3850 {
3851         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3852
3853         return 0;
3854 }
3855
3856 /**
3857  * process_one_iomb - process one outbound Queue memory block
3858  * @pm8001_ha: our hba card information
3859  * @circularQ: outbound circular queue
3860  * @piomb: IO message buffer
3861  */
3862 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha,
3863                 struct outbound_queue_table *circularQ, void *piomb)
3864 {
3865         __le32 pHeader = *(__le32 *)piomb;
3866         u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3867
3868         switch (opc) {
3869         case OPC_OUB_ECHO:
3870                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3871                 break;
3872         case OPC_OUB_HW_EVENT:
3873                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3874                 mpi_hw_event(pm8001_ha, piomb);
3875                 break;
3876         case OPC_OUB_THERM_HW_EVENT:
3877                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n");
3878                 mpi_thermal_hw_event(pm8001_ha, piomb);
3879                 break;
3880         case OPC_OUB_SSP_COMP:
3881                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3882                 mpi_ssp_completion(pm8001_ha, piomb);
3883                 break;
3884         case OPC_OUB_SMP_COMP:
3885                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3886                 mpi_smp_completion(pm8001_ha, piomb);
3887                 break;
3888         case OPC_OUB_LOCAL_PHY_CNTRL:
3889                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3890                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3891                 break;
3892         case OPC_OUB_DEV_REGIST:
3893                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3894                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3895                 break;
3896         case OPC_OUB_DEREG_DEV:
3897                 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3898                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3899                 break;
3900         case OPC_OUB_GET_DEV_HANDLE:
3901                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3902                 break;
3903         case OPC_OUB_SATA_COMP:
3904                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3905                 mpi_sata_completion(pm8001_ha, circularQ, piomb);
3906                 break;
3907         case OPC_OUB_SATA_EVENT:
3908                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3909                 mpi_sata_event(pm8001_ha, circularQ, piomb);
3910                 break;
3911         case OPC_OUB_SSP_EVENT:
3912                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3913                 mpi_ssp_event(pm8001_ha, piomb);
3914                 break;
3915         case OPC_OUB_DEV_HANDLE_ARRIV:
3916                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3917                 /*This is for target*/
3918                 break;
3919         case OPC_OUB_SSP_RECV_EVENT:
3920                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3921                 /*This is for target*/
3922                 break;
3923         case OPC_OUB_FW_FLASH_UPDATE:
3924                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3925                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3926                 break;
3927         case OPC_OUB_GPIO_RESPONSE:
3928                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3929                 break;
3930         case OPC_OUB_GPIO_EVENT:
3931                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3932                 break;
3933         case OPC_OUB_GENERAL_EVENT:
3934                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3935                 pm8001_mpi_general_event(pm8001_ha, piomb);
3936                 break;
3937         case OPC_OUB_SSP_ABORT_RSP:
3938                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3939                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3940                 break;
3941         case OPC_OUB_SATA_ABORT_RSP:
3942                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3943                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3944                 break;
3945         case OPC_OUB_SAS_DIAG_MODE_START_END:
3946                 pm8001_dbg(pm8001_ha, MSG,
3947                            "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3948                 break;
3949         case OPC_OUB_SAS_DIAG_EXECUTE:
3950                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3951                 break;
3952         case OPC_OUB_GET_TIME_STAMP:
3953                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3954                 break;
3955         case OPC_OUB_SAS_HW_EVENT_ACK:
3956                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3957                 break;
3958         case OPC_OUB_PORT_CONTROL:
3959                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3960                 break;
3961         case OPC_OUB_SMP_ABORT_RSP:
3962                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3963                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3964                 break;
3965         case OPC_OUB_GET_NVMD_DATA:
3966                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3967                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3968                 break;
3969         case OPC_OUB_SET_NVMD_DATA:
3970                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3971                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3972                 break;
3973         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3974                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
3975                 break;
3976         case OPC_OUB_SET_DEVICE_STATE:
3977                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
3978                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3979                 break;
3980         case OPC_OUB_GET_DEVICE_STATE:
3981                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
3982                 break;
3983         case OPC_OUB_SET_DEV_INFO:
3984                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
3985                 break;
3986         /* spcv specific commands */
3987         case OPC_OUB_PHY_START_RESP:
3988                 pm8001_dbg(pm8001_ha, MSG,
3989                            "OPC_OUB_PHY_START_RESP opcode:%x\n", opc);
3990                 mpi_phy_start_resp(pm8001_ha, piomb);
3991                 break;
3992         case OPC_OUB_PHY_STOP_RESP:
3993                 pm8001_dbg(pm8001_ha, MSG,
3994                            "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc);
3995                 mpi_phy_stop_resp(pm8001_ha, piomb);
3996                 break;
3997         case OPC_OUB_SET_CONTROLLER_CONFIG:
3998                 pm8001_dbg(pm8001_ha, MSG,
3999                            "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc);
4000                 mpi_set_controller_config_resp(pm8001_ha, piomb);
4001                 break;
4002         case OPC_OUB_GET_CONTROLLER_CONFIG:
4003                 pm8001_dbg(pm8001_ha, MSG,
4004                            "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc);
4005                 mpi_get_controller_config_resp(pm8001_ha, piomb);
4006                 break;
4007         case OPC_OUB_GET_PHY_PROFILE:
4008                 pm8001_dbg(pm8001_ha, MSG,
4009                            "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc);
4010                 mpi_get_phy_profile_resp(pm8001_ha, piomb);
4011                 break;
4012         case OPC_OUB_FLASH_OP_EXT:
4013                 pm8001_dbg(pm8001_ha, MSG,
4014                            "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc);
4015                 mpi_flash_op_ext_resp(pm8001_ha, piomb);
4016                 break;
4017         case OPC_OUB_SET_PHY_PROFILE:
4018                 pm8001_dbg(pm8001_ha, MSG,
4019                            "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc);
4020                 mpi_set_phy_profile_resp(pm8001_ha, piomb);
4021                 break;
4022         case OPC_OUB_KEK_MANAGEMENT_RESP:
4023                 pm8001_dbg(pm8001_ha, MSG,
4024                            "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc);
4025                 mpi_kek_management_resp(pm8001_ha, piomb);
4026                 break;
4027         case OPC_OUB_DEK_MANAGEMENT_RESP:
4028                 pm8001_dbg(pm8001_ha, MSG,
4029                            "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc);
4030                 mpi_dek_management_resp(pm8001_ha, piomb);
4031                 break;
4032         case OPC_OUB_SSP_COALESCED_COMP_RESP:
4033                 pm8001_dbg(pm8001_ha, MSG,
4034                            "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc);
4035                 ssp_coalesced_comp_resp(pm8001_ha, piomb);
4036                 break;
4037         default:
4038                 pm8001_dbg(pm8001_ha, DEVIO,
4039                            "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);
4040                 break;
4041         }
4042 }
4043
4044 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4045 {
4046         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",
4047                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
4048         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",
4049                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));
4050         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",
4051                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));
4052         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",
4053                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
4054         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4055                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));
4056         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4057                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));
4058         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4059                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));
4060         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4061                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));
4062         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4063                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));
4064         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4065                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));
4066         pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4067                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_0));
4068         pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4069                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_1));
4070 }
4071
4072 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4073 {
4074         struct outbound_queue_table *circularQ;
4075         void *pMsg1 = NULL;
4076         u8 bc;
4077         u32 ret = MPI_IO_STATUS_FAIL;
4078         u32 regval;
4079
4080         /*
4081          * Fatal errors are programmed to be signalled in irq vector
4082          * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl.
4083          * fatal_err_interrupt
4084          */
4085         if (vec == (pm8001_ha->max_q_num - 1)) {
4086                 u32 mipsall_ready;
4087
4088                 if (pm8001_ha->chip_id == chip_8008 ||
4089                     pm8001_ha->chip_id == chip_8009)
4090                         mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT;
4091                 else
4092                         mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT;
4093
4094                 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4095                 if ((regval & mipsall_ready) != mipsall_ready) {
4096                         pm8001_ha->controller_fatal_error = true;
4097                         pm8001_dbg(pm8001_ha, FAIL,
4098                                    "Firmware Fatal error! Regval:0x%x\n",
4099                                    regval);
4100                         pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR);
4101                         print_scratchpad_registers(pm8001_ha);
4102                         return ret;
4103                 } else {
4104                         /*read scratchpad rsvd 0 register*/
4105                         regval = pm8001_cr32(pm8001_ha, 0,
4106                                              MSGU_SCRATCH_PAD_RSVD_0);
4107                         switch (regval) {
4108                         case NON_FATAL_SPBC_LBUS_ECC_ERR:
4109                         case NON_FATAL_BDMA_ERR:
4110                         case NON_FATAL_THERM_OVERTEMP_ERR:
4111                                 /*Clear the register*/
4112                                 pm8001_cw32(pm8001_ha, 0,
4113                                             MSGU_SCRATCH_PAD_RSVD_0,
4114                                             0x00000000);
4115                                 break;
4116                         default:
4117                                 break;
4118                         }
4119                 }
4120         }
4121         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4122         spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags);
4123         do {
4124                 /* spurious interrupt during setup if kexec-ing and
4125                  * driver doing a doorbell access w/ the pre-kexec oq
4126                  * interrupt setup.
4127                  */
4128                 if (!circularQ->pi_virt)
4129                         break;
4130                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4131                 if (MPI_IO_STATUS_SUCCESS == ret) {
4132                         /* process the outbound message */
4133                         process_one_iomb(pm8001_ha, circularQ,
4134                                                 (void *)(pMsg1 - 4));
4135                         /* free the message from the outbound circular buffer */
4136                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4137                                                         circularQ, bc);
4138                 }
4139                 if (MPI_IO_STATUS_BUSY == ret) {
4140                         /* Update the producer index from SPC */
4141                         circularQ->producer_index =
4142                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4143                         if (le32_to_cpu(circularQ->producer_index) ==
4144                                 circularQ->consumer_idx)
4145                                 /* OQ is empty */
4146                                 break;
4147                 }
4148         } while (1);
4149         spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags);
4150         return ret;
4151 }
4152
4153 /* DMA_... to our direction translation. */
4154 static const u8 data_dir_flags[] = {
4155         [DMA_BIDIRECTIONAL]     = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4156         [DMA_TO_DEVICE]         = DATA_DIR_OUT,         /* OUTBOUND */
4157         [DMA_FROM_DEVICE]       = DATA_DIR_IN,          /* INBOUND */
4158         [DMA_NONE]              = DATA_DIR_NONE,        /* NO TRANSFER */
4159 };
4160
4161 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4162                         struct smp_req *psmp_cmd, int mode, int length)
4163 {
4164         psmp_cmd->tag = hTag;
4165         psmp_cmd->device_id = cpu_to_le32(deviceID);
4166         if (mode == SMP_DIRECT) {
4167                 length = length - 4; /* subtract crc */
4168                 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4169         } else {
4170                 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4171         }
4172 }
4173
4174 /**
4175  * pm80xx_chip_smp_req - send an SMP task to FW
4176  * @pm8001_ha: our hba card information.
4177  * @ccb: the ccb information this request used.
4178  */
4179 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4180         struct pm8001_ccb_info *ccb)
4181 {
4182         int elem, rc;
4183         struct sas_task *task = ccb->task;
4184         struct domain_device *dev = task->dev;
4185         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4186         struct scatterlist *sg_req, *sg_resp, *smp_req;
4187         u32 req_len, resp_len;
4188         struct smp_req smp_cmd;
4189         u32 opc;
4190         u32 i, length;
4191         u8 *payload;
4192         u8 *to;
4193
4194         memset(&smp_cmd, 0, sizeof(smp_cmd));
4195         /*
4196          * DMA-map SMP request, response buffers
4197          */
4198         sg_req = &task->smp_task.smp_req;
4199         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4200         if (!elem)
4201                 return -ENOMEM;
4202         req_len = sg_dma_len(sg_req);
4203
4204         sg_resp = &task->smp_task.smp_resp;
4205         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4206         if (!elem) {
4207                 rc = -ENOMEM;
4208                 goto err_out;
4209         }
4210         resp_len = sg_dma_len(sg_resp);
4211         /* must be in dwords */
4212         if ((req_len & 0x3) || (resp_len & 0x3)) {
4213                 rc = -EINVAL;
4214                 goto err_out_2;
4215         }
4216
4217         opc = OPC_INB_SMP_REQUEST;
4218         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4219
4220         length = sg_req->length;
4221         pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);
4222         if (!(length - 8))
4223                 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4224         else
4225                 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4226
4227
4228         smp_req = &task->smp_task.smp_req;
4229         to = kmap_atomic(sg_page(smp_req));
4230         payload = to + smp_req->offset;
4231
4232         /* INDIRECT MODE command settings. Use DMA */
4233         if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4234                 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n");
4235                 /* for SPCv indirect mode. Place the top 4 bytes of
4236                  * SMP Request header here. */
4237                 for (i = 0; i < 4; i++)
4238                         smp_cmd.smp_req16[i] = *(payload + i);
4239                 /* exclude top 4 bytes for SMP req header */
4240                 smp_cmd.long_smp_req.long_req_addr =
4241                         cpu_to_le64((u64)sg_dma_address
4242                                 (&task->smp_task.smp_req) + 4);
4243                 /* exclude 4 bytes for SMP req header and CRC */
4244                 smp_cmd.long_smp_req.long_req_size =
4245                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4246                 smp_cmd.long_smp_req.long_resp_addr =
4247                                 cpu_to_le64((u64)sg_dma_address
4248                                         (&task->smp_task.smp_resp));
4249                 smp_cmd.long_smp_req.long_resp_size =
4250                                 cpu_to_le32((u32)sg_dma_len
4251                                         (&task->smp_task.smp_resp)-4);
4252         } else { /* DIRECT MODE */
4253                 smp_cmd.long_smp_req.long_req_addr =
4254                         cpu_to_le64((u64)sg_dma_address
4255                                         (&task->smp_task.smp_req));
4256                 smp_cmd.long_smp_req.long_req_size =
4257                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4258                 smp_cmd.long_smp_req.long_resp_addr =
4259                         cpu_to_le64((u64)sg_dma_address
4260                                 (&task->smp_task.smp_resp));
4261                 smp_cmd.long_smp_req.long_resp_size =
4262                         cpu_to_le32
4263                         ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4264         }
4265         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4266                 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n");
4267                 for (i = 0; i < length; i++)
4268                         if (i < 16) {
4269                                 smp_cmd.smp_req16[i] = *(payload + i);
4270                                 pm8001_dbg(pm8001_ha, IO,
4271                                            "Byte[%d]:%x (DMA data:%x)\n",
4272                                            i, smp_cmd.smp_req16[i],
4273                                            *(payload));
4274                         } else {
4275                                 smp_cmd.smp_req[i] = *(payload + i);
4276                                 pm8001_dbg(pm8001_ha, IO,
4277                                            "Byte[%d]:%x (DMA data:%x)\n",
4278                                            i, smp_cmd.smp_req[i],
4279                                            *(payload));
4280                         }
4281         }
4282         kunmap_atomic(to);
4283         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4284                                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4285         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &smp_cmd,
4286                                   sizeof(smp_cmd), 0);
4287         if (rc)
4288                 goto err_out_2;
4289         return 0;
4290
4291 err_out_2:
4292         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4293                         DMA_FROM_DEVICE);
4294 err_out:
4295         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4296                         DMA_TO_DEVICE);
4297         return rc;
4298 }
4299
4300 static int check_enc_sas_cmd(struct sas_task *task)
4301 {
4302         u8 cmd = task->ssp_task.cmd->cmnd[0];
4303
4304         if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4305                 return 1;
4306         else
4307                 return 0;
4308 }
4309
4310 static int check_enc_sat_cmd(struct sas_task *task)
4311 {
4312         int ret = 0;
4313         switch (task->ata_task.fis.command) {
4314         case ATA_CMD_FPDMA_READ:
4315         case ATA_CMD_READ_EXT:
4316         case ATA_CMD_READ:
4317         case ATA_CMD_FPDMA_WRITE:
4318         case ATA_CMD_WRITE_EXT:
4319         case ATA_CMD_WRITE:
4320         case ATA_CMD_PIO_READ:
4321         case ATA_CMD_PIO_READ_EXT:
4322         case ATA_CMD_PIO_WRITE:
4323         case ATA_CMD_PIO_WRITE_EXT:
4324                 ret = 1;
4325                 break;
4326         default:
4327                 ret = 0;
4328                 break;
4329         }
4330         return ret;
4331 }
4332
4333 /**
4334  * pm80xx_chip_ssp_io_req - send an SSP task to FW
4335  * @pm8001_ha: our hba card information.
4336  * @ccb: the ccb information this request used.
4337  */
4338 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4339         struct pm8001_ccb_info *ccb)
4340 {
4341         struct sas_task *task = ccb->task;
4342         struct domain_device *dev = task->dev;
4343         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4344         struct ssp_ini_io_start_req ssp_cmd;
4345         u32 tag = ccb->ccb_tag;
4346         u64 phys_addr, end_addr;
4347         u32 end_addr_high, end_addr_low;
4348         u32 q_index, cpu_id;
4349         u32 opc = OPC_INB_SSPINIIOSTART;
4350
4351         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4352         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4353
4354         /* data address domain added for spcv; set to 0 by host,
4355          * used internally by controller
4356          * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4357          */
4358         ssp_cmd.dad_dir_m_tlr =
4359                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4360         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4361         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4362         ssp_cmd.tag = cpu_to_le32(tag);
4363         if (task->ssp_task.enable_first_burst)
4364                 ssp_cmd.ssp_iu.efb_prio_attr = 0x80;
4365         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4366         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4367         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4368                        task->ssp_task.cmd->cmd_len);
4369         cpu_id = smp_processor_id();
4370         q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4371
4372         /* Check if encryption is set */
4373         if (pm8001_ha->chip->encrypt &&
4374                 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4375                 pm8001_dbg(pm8001_ha, IO,
4376                            "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4377                            task->ssp_task.cmd->cmnd[0]);
4378                 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4379                 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4380                 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4381                         ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4382
4383                 /* fill in PRD (scatter/gather) table, if any */
4384                 if (task->num_scatter > 1) {
4385                         pm8001_chip_make_sg(task->scatter,
4386                                                 ccb->n_elem, ccb->buf_prd);
4387                         phys_addr = ccb->ccb_dma_handle;
4388                         ssp_cmd.enc_addr_low =
4389                                 cpu_to_le32(lower_32_bits(phys_addr));
4390                         ssp_cmd.enc_addr_high =
4391                                 cpu_to_le32(upper_32_bits(phys_addr));
4392                         ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4393                 } else if (task->num_scatter == 1) {
4394                         u64 dma_addr = sg_dma_address(task->scatter);
4395
4396                         ssp_cmd.enc_addr_low =
4397                                 cpu_to_le32(lower_32_bits(dma_addr));
4398                         ssp_cmd.enc_addr_high =
4399                                 cpu_to_le32(upper_32_bits(dma_addr));
4400                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4401                         ssp_cmd.enc_esgl = 0;
4402
4403                         /* Check 4G Boundary */
4404                         end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1;
4405                         end_addr_low = lower_32_bits(end_addr);
4406                         end_addr_high = upper_32_bits(end_addr);
4407
4408                         if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) {
4409                                 pm8001_dbg(pm8001_ha, FAIL,
4410                                            "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4411                                            dma_addr,
4412                                            le32_to_cpu(ssp_cmd.enc_len),
4413                                            end_addr_high, end_addr_low);
4414                                 pm8001_chip_make_sg(task->scatter, 1,
4415                                         ccb->buf_prd);
4416                                 phys_addr = ccb->ccb_dma_handle;
4417                                 ssp_cmd.enc_addr_low =
4418                                         cpu_to_le32(lower_32_bits(phys_addr));
4419                                 ssp_cmd.enc_addr_high =
4420                                         cpu_to_le32(upper_32_bits(phys_addr));
4421                                 ssp_cmd.enc_esgl = cpu_to_le32(1U<<31);
4422                         }
4423                 } else if (task->num_scatter == 0) {
4424                         ssp_cmd.enc_addr_low = 0;
4425                         ssp_cmd.enc_addr_high = 0;
4426                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4427                         ssp_cmd.enc_esgl = 0;
4428                 }
4429
4430                 /* XTS mode. All other fields are 0 */
4431                 ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4);
4432
4433                 /* set tweak values. Should be the start lba */
4434                 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4435                                                 (task->ssp_task.cmd->cmnd[3] << 16) |
4436                                                 (task->ssp_task.cmd->cmnd[4] << 8) |
4437                                                 (task->ssp_task.cmd->cmnd[5]));
4438         } else {
4439                 pm8001_dbg(pm8001_ha, IO,
4440                            "Sending Normal SAS command 0x%x inb q %x\n",
4441                            task->ssp_task.cmd->cmnd[0], q_index);
4442                 /* fill in PRD (scatter/gather) table, if any */
4443                 if (task->num_scatter > 1) {
4444                         pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4445                                         ccb->buf_prd);
4446                         phys_addr = ccb->ccb_dma_handle;
4447                         ssp_cmd.addr_low =
4448                                 cpu_to_le32(lower_32_bits(phys_addr));
4449                         ssp_cmd.addr_high =
4450                                 cpu_to_le32(upper_32_bits(phys_addr));
4451                         ssp_cmd.esgl = cpu_to_le32(1<<31);
4452                 } else if (task->num_scatter == 1) {
4453                         u64 dma_addr = sg_dma_address(task->scatter);
4454
4455                         ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4456                         ssp_cmd.addr_high =
4457                                 cpu_to_le32(upper_32_bits(dma_addr));
4458                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4459                         ssp_cmd.esgl = 0;
4460
4461                         /* Check 4G Boundary */
4462                         end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1;
4463                         end_addr_low = lower_32_bits(end_addr);
4464                         end_addr_high = upper_32_bits(end_addr);
4465                         if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) {
4466                                 pm8001_dbg(pm8001_ha, FAIL,
4467                                            "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4468                                            dma_addr,
4469                                            le32_to_cpu(ssp_cmd.len),
4470                                            end_addr_high, end_addr_low);
4471                                 pm8001_chip_make_sg(task->scatter, 1,
4472                                         ccb->buf_prd);
4473                                 phys_addr = ccb->ccb_dma_handle;
4474                                 ssp_cmd.addr_low =
4475                                         cpu_to_le32(lower_32_bits(phys_addr));
4476                                 ssp_cmd.addr_high =
4477                                         cpu_to_le32(upper_32_bits(phys_addr));
4478                                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4479                         }
4480                 } else if (task->num_scatter == 0) {
4481                         ssp_cmd.addr_low = 0;
4482                         ssp_cmd.addr_high = 0;
4483                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4484                         ssp_cmd.esgl = 0;
4485                 }
4486         }
4487
4488         return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &ssp_cmd,
4489                                     sizeof(ssp_cmd), q_index);
4490 }
4491
4492 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4493         struct pm8001_ccb_info *ccb)
4494 {
4495         struct sas_task *task = ccb->task;
4496         struct domain_device *dev = task->dev;
4497         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4498         struct ata_queued_cmd *qc = task->uldd_task;
4499         u32 tag = ccb->ccb_tag;
4500         u32 q_index, cpu_id;
4501         struct sata_start_req sata_cmd;
4502         u32 hdr_tag, ncg_tag = 0;
4503         u64 phys_addr, end_addr;
4504         u32 end_addr_high, end_addr_low;
4505         u32 ATAP = 0x0;
4506         u32 dir;
4507         unsigned long flags;
4508         u32 opc = OPC_INB_SATA_HOST_OPSTART;
4509         memset(&sata_cmd, 0, sizeof(sata_cmd));
4510         cpu_id = smp_processor_id();
4511         q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4512
4513         if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4514                 ATAP = 0x04; /* no data*/
4515                 pm8001_dbg(pm8001_ha, IO, "no data\n");
4516         } else if (likely(!task->ata_task.device_control_reg_update)) {
4517                 if (task->ata_task.use_ncq &&
4518                     dev->sata_dev.class != ATA_DEV_ATAPI) {
4519                         ATAP = 0x07; /* FPDMA */
4520                         pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4521                 } else if (task->ata_task.dma_xfer) {
4522                         ATAP = 0x06; /* DMA */
4523                         pm8001_dbg(pm8001_ha, IO, "DMA\n");
4524                 } else {
4525                         ATAP = 0x05; /* PIO*/
4526                         pm8001_dbg(pm8001_ha, IO, "PIO\n");
4527                 }
4528         }
4529         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4530                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4531                 ncg_tag = hdr_tag;
4532         }
4533         dir = data_dir_flags[task->data_dir] << 8;
4534         sata_cmd.tag = cpu_to_le32(tag);
4535         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4536         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4537
4538         sata_cmd.sata_fis = task->ata_task.fis;
4539         if (likely(!task->ata_task.device_control_reg_update))
4540                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4541         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4542
4543         /* Check if encryption is set */
4544         if (pm8001_ha->chip->encrypt &&
4545                 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4546                 pm8001_dbg(pm8001_ha, IO,
4547                            "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4548                            sata_cmd.sata_fis.command);
4549                 opc = OPC_INB_SATA_DIF_ENC_IO;
4550
4551                 /* set encryption bit */
4552                 sata_cmd.ncqtag_atap_dir_m_dad =
4553                         cpu_to_le32(((ncg_tag & 0xff)<<16)|
4554                                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4555                                                         /* dad (bit 0-1) is 0 */
4556                 /* fill in PRD (scatter/gather) table, if any */
4557                 if (task->num_scatter > 1) {
4558                         pm8001_chip_make_sg(task->scatter,
4559                                                 ccb->n_elem, ccb->buf_prd);
4560                         phys_addr = ccb->ccb_dma_handle;
4561                         sata_cmd.enc_addr_low =
4562                                 cpu_to_le32(lower_32_bits(phys_addr));
4563                         sata_cmd.enc_addr_high =
4564                                 cpu_to_le32(upper_32_bits(phys_addr));
4565                         sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4566                 } else if (task->num_scatter == 1) {
4567                         u64 dma_addr = sg_dma_address(task->scatter);
4568
4569                         sata_cmd.enc_addr_low =
4570                                 cpu_to_le32(lower_32_bits(dma_addr));
4571                         sata_cmd.enc_addr_high =
4572                                 cpu_to_le32(upper_32_bits(dma_addr));
4573                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4574                         sata_cmd.enc_esgl = 0;
4575
4576                         /* Check 4G Boundary */
4577                         end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1;
4578                         end_addr_low = lower_32_bits(end_addr);
4579                         end_addr_high = upper_32_bits(end_addr);
4580                         if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) {
4581                                 pm8001_dbg(pm8001_ha, FAIL,
4582                                            "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4583                                            dma_addr,
4584                                            le32_to_cpu(sata_cmd.enc_len),
4585                                            end_addr_high, end_addr_low);
4586                                 pm8001_chip_make_sg(task->scatter, 1,
4587                                         ccb->buf_prd);
4588                                 phys_addr = ccb->ccb_dma_handle;
4589                                 sata_cmd.enc_addr_low =
4590                                         cpu_to_le32(lower_32_bits(phys_addr));
4591                                 sata_cmd.enc_addr_high =
4592                                         cpu_to_le32(upper_32_bits(phys_addr));
4593                                 sata_cmd.enc_esgl =
4594                                         cpu_to_le32(1 << 31);
4595                         }
4596                 } else if (task->num_scatter == 0) {
4597                         sata_cmd.enc_addr_low = 0;
4598                         sata_cmd.enc_addr_high = 0;
4599                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4600                         sata_cmd.enc_esgl = 0;
4601                 }
4602                 /* XTS mode. All other fields are 0 */
4603                 sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4);
4604
4605                 /* set tweak values. Should be the start lba */
4606                 sata_cmd.twk_val0 =
4607                         cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4608                                         (sata_cmd.sata_fis.lbah << 16) |
4609                                         (sata_cmd.sata_fis.lbam << 8) |
4610                                         (sata_cmd.sata_fis.lbal));
4611                 sata_cmd.twk_val1 =
4612                         cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4613                                          (sata_cmd.sata_fis.lbam_exp));
4614         } else {
4615                 pm8001_dbg(pm8001_ha, IO,
4616                            "Sending Normal SATA command 0x%x inb %x\n",
4617                            sata_cmd.sata_fis.command, q_index);
4618                 /* dad (bit 0-1) is 0 */
4619                 sata_cmd.ncqtag_atap_dir_m_dad =
4620                         cpu_to_le32(((ncg_tag & 0xff)<<16) |
4621                                         ((ATAP & 0x3f) << 10) | dir);
4622
4623                 /* fill in PRD (scatter/gather) table, if any */
4624                 if (task->num_scatter > 1) {
4625                         pm8001_chip_make_sg(task->scatter,
4626                                         ccb->n_elem, ccb->buf_prd);
4627                         phys_addr = ccb->ccb_dma_handle;
4628                         sata_cmd.addr_low = lower_32_bits(phys_addr);
4629                         sata_cmd.addr_high = upper_32_bits(phys_addr);
4630                         sata_cmd.esgl = cpu_to_le32(1U << 31);
4631                 } else if (task->num_scatter == 1) {
4632                         u64 dma_addr = sg_dma_address(task->scatter);
4633
4634                         sata_cmd.addr_low = lower_32_bits(dma_addr);
4635                         sata_cmd.addr_high = upper_32_bits(dma_addr);
4636                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4637                         sata_cmd.esgl = 0;
4638
4639                         /* Check 4G Boundary */
4640                         end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1;
4641                         end_addr_low = lower_32_bits(end_addr);
4642                         end_addr_high = upper_32_bits(end_addr);
4643                         if (end_addr_high != sata_cmd.addr_high) {
4644                                 pm8001_dbg(pm8001_ha, FAIL,
4645                                            "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4646                                            dma_addr,
4647                                            le32_to_cpu(sata_cmd.len),
4648                                            end_addr_high, end_addr_low);
4649                                 pm8001_chip_make_sg(task->scatter, 1,
4650                                         ccb->buf_prd);
4651                                 phys_addr = ccb->ccb_dma_handle;
4652                                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4653                                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4654                                 sata_cmd.esgl = cpu_to_le32(1U << 31);
4655                         }
4656                 } else if (task->num_scatter == 0) {
4657                         sata_cmd.addr_low = 0;
4658                         sata_cmd.addr_high = 0;
4659                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4660                         sata_cmd.esgl = 0;
4661                 }
4662
4663                 /* scsi cdb */
4664                 sata_cmd.atapi_scsi_cdb[0] =
4665                         cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4666                                      (task->ata_task.atapi_packet[1] << 8) |
4667                                      (task->ata_task.atapi_packet[2] << 16) |
4668                                      (task->ata_task.atapi_packet[3] << 24)));
4669                 sata_cmd.atapi_scsi_cdb[1] =
4670                         cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4671                                      (task->ata_task.atapi_packet[5] << 8) |
4672                                      (task->ata_task.atapi_packet[6] << 16) |
4673                                      (task->ata_task.atapi_packet[7] << 24)));
4674                 sata_cmd.atapi_scsi_cdb[2] =
4675                         cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4676                                      (task->ata_task.atapi_packet[9] << 8) |
4677                                      (task->ata_task.atapi_packet[10] << 16) |
4678                                      (task->ata_task.atapi_packet[11] << 24)));
4679                 sata_cmd.atapi_scsi_cdb[3] =
4680                         cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4681                                      (task->ata_task.atapi_packet[13] << 8) |
4682                                      (task->ata_task.atapi_packet[14] << 16) |
4683                                      (task->ata_task.atapi_packet[15] << 24)));
4684         }
4685
4686         /* Check for read log for failed drive and return */
4687         if (sata_cmd.sata_fis.command == 0x2f) {
4688                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4689                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4690                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4691                         struct task_status_struct *ts;
4692
4693                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4694                         ts = &task->task_status;
4695
4696                         spin_lock_irqsave(&task->task_state_lock, flags);
4697                         ts->resp = SAS_TASK_COMPLETE;
4698                         ts->stat = SAS_SAM_STAT_GOOD;
4699                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4700                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4701                         if (unlikely((task->task_state_flags &
4702                                         SAS_TASK_STATE_ABORTED))) {
4703                                 spin_unlock_irqrestore(&task->task_state_lock,
4704                                                         flags);
4705                                 pm8001_dbg(pm8001_ha, FAIL,
4706                                            "task 0x%p resp 0x%x  stat 0x%x but aborted by upper layer\n",
4707                                            task, ts->resp,
4708                                            ts->stat);
4709                                 pm8001_ccb_task_free(pm8001_ha, ccb);
4710                                 return 0;
4711                         } else {
4712                                 spin_unlock_irqrestore(&task->task_state_lock,
4713                                                         flags);
4714                                 pm8001_ccb_task_free_done(pm8001_ha, ccb);
4715                                 atomic_dec(&pm8001_ha_dev->running_req);
4716                                 return 0;
4717                         }
4718                 }
4719         }
4720         trace_pm80xx_request_issue(pm8001_ha->id,
4721                                 ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS,
4722                                 ccb->ccb_tag, opc,
4723                                 qc ? qc->tf.command : 0, // ata opcode
4724                                 ccb->device ? atomic_read(&ccb->device->running_req) : 0);
4725         return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &sata_cmd,
4726                                     sizeof(sata_cmd), q_index);
4727 }
4728
4729 /**
4730  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4731  * @pm8001_ha: our hba card information.
4732  * @phy_id: the phy id which we wanted to start up.
4733  */
4734 static int
4735 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4736 {
4737         struct phy_start_req payload;
4738         u32 tag = 0x01;
4739         u32 opcode = OPC_INB_PHYSTART;
4740
4741         memset(&payload, 0, sizeof(payload));
4742         payload.tag = cpu_to_le32(tag);
4743
4744         pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id);
4745
4746         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4747                         LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4748         /* SSC Disable and SAS Analog ST configuration */
4749         /*
4750         payload.ase_sh_lm_slr_phyid =
4751                 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4752                 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4753                 phy_id);
4754         Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4755         */
4756
4757         payload.sas_identify.dev_type = SAS_END_DEVICE;
4758         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4759         memcpy(payload.sas_identify.sas_addr,
4760           &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4761         payload.sas_identify.phy_id = phy_id;
4762
4763         return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4764                                     sizeof(payload), 0);
4765 }
4766
4767 /**
4768  * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4769  * @pm8001_ha: our hba card information.
4770  * @phy_id: the phy id which we wanted to start up.
4771  */
4772 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4773         u8 phy_id)
4774 {
4775         struct phy_stop_req payload;
4776         u32 tag = 0x01;
4777         u32 opcode = OPC_INB_PHYSTOP;
4778
4779         memset(&payload, 0, sizeof(payload));
4780         payload.tag = cpu_to_le32(tag);
4781         payload.phy_id = cpu_to_le32(phy_id);
4782
4783         return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4784                                     sizeof(payload), 0);
4785 }
4786
4787 /*
4788  * see comments on pm8001_mpi_reg_resp.
4789  */
4790 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4791         struct pm8001_device *pm8001_dev, u32 flag)
4792 {
4793         struct reg_dev_req payload;
4794         u32     opc;
4795         u32 stp_sspsmp_sata = 0x4;
4796         u32 linkrate, phy_id;
4797         int rc;
4798         struct pm8001_ccb_info *ccb;
4799         u8 retryFlag = 0x1;
4800         u16 firstBurstSize = 0;
4801         u16 ITNT = 2000;
4802         struct domain_device *dev = pm8001_dev->sas_device;
4803         struct domain_device *parent_dev = dev->parent;
4804         struct pm8001_port *port = dev->port->lldd_port;
4805
4806         memset(&payload, 0, sizeof(payload));
4807         ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4808         if (!ccb)
4809                 return -SAS_QUEUE_FULL;
4810
4811         payload.tag = cpu_to_le32(ccb->ccb_tag);
4812
4813         if (flag == 1) {
4814                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4815         } else {
4816                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4817                         stp_sspsmp_sata = 0x00; /* stp*/
4818                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4819                         dev_is_expander(pm8001_dev->dev_type))
4820                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4821         }
4822         if (parent_dev && dev_is_expander(parent_dev->dev_type))
4823                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4824         else
4825                 phy_id = pm8001_dev->attached_phy;
4826
4827         opc = OPC_INB_REG_DEV;
4828
4829         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4830                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4831
4832         payload.phyid_portid =
4833                 cpu_to_le32(((port->port_id) & 0xFF) |
4834                 ((phy_id & 0xFF) << 8));
4835
4836         payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4837                 ((linkrate & 0x0F) << 24) |
4838                 ((stp_sspsmp_sata & 0x03) << 28));
4839         payload.firstburstsize_ITNexustimeout =
4840                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4841
4842         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4843                 SAS_ADDR_SIZE);
4844
4845         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4846                         sizeof(payload), 0);
4847         if (rc)
4848                 pm8001_ccb_free(pm8001_ha, ccb);
4849
4850         return rc;
4851 }
4852
4853 /**
4854  * pm80xx_chip_phy_ctl_req - support the local phy operation
4855  * @pm8001_ha: our hba card information.
4856  * @phyId: the phy id which we wanted to operate
4857  * @phy_op: phy operation to request
4858  */
4859 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4860         u32 phyId, u32 phy_op)
4861 {
4862         u32 tag;
4863         int rc;
4864         struct local_phy_ctl_req payload;
4865         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4866
4867         memset(&payload, 0, sizeof(payload));
4868         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4869         if (rc)
4870                 return rc;
4871
4872         payload.tag = cpu_to_le32(tag);
4873         payload.phyop_phyid =
4874                 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4875
4876         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4877                                   sizeof(payload), 0);
4878         if (rc)
4879                 pm8001_tag_free(pm8001_ha, tag);
4880
4881         return rc;
4882 }
4883
4884 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4885 {
4886 #ifdef PM8001_USE_MSIX
4887         return 1;
4888 #else
4889         u32 value;
4890
4891         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4892         if (value)
4893                 return 1;
4894         return 0;
4895 #endif
4896 }
4897
4898 /**
4899  * pm80xx_chip_isr - PM8001 isr handler.
4900  * @pm8001_ha: our hba card information.
4901  * @vec: irq number.
4902  */
4903 static irqreturn_t
4904 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4905 {
4906         pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4907         pm8001_dbg(pm8001_ha, DEVIO,
4908                    "irq vec %d, ODMR:0x%x\n",
4909                    vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4910         process_oq(pm8001_ha, vec);
4911         pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4912         return IRQ_HANDLED;
4913 }
4914
4915 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4916                                     u32 operation, u32 phyid,
4917                                     u32 length, u32 *buf)
4918 {
4919         u32 tag, i, j = 0;
4920         int rc;
4921         struct set_phy_profile_req payload;
4922         u32 opc = OPC_INB_SET_PHY_PROFILE;
4923
4924         memset(&payload, 0, sizeof(payload));
4925         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4926         if (rc) {
4927                 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n");
4928                 return;
4929         }
4930
4931         payload.tag = cpu_to_le32(tag);
4932         payload.ppc_phyid =
4933                 cpu_to_le32(((operation & 0xF) << 8) | (phyid  & 0xFF));
4934         pm8001_dbg(pm8001_ha, INIT,
4935                    " phy profile command for phy %x ,length is %d\n",
4936                    le32_to_cpu(payload.ppc_phyid), length);
4937         for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4938                 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4939                 j++;
4940         }
4941         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4942                                   sizeof(payload), 0);
4943         if (rc)
4944                 pm8001_tag_free(pm8001_ha, tag);
4945 }
4946
4947 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4948         u32 length, u8 *buf)
4949 {
4950         u32 i;
4951
4952         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4953                 mpi_set_phy_profile_req(pm8001_ha,
4954                         SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4955                 length = length + PHY_DWORD_LENGTH;
4956         }
4957         pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n");
4958 }
4959
4960 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4961                 u32 phy, u32 length, u32 *buf)
4962 {
4963         u32 tag, opc;
4964         int rc, i;
4965         struct set_phy_profile_req payload;
4966
4967         memset(&payload, 0, sizeof(payload));
4968
4969         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4970         if (rc) {
4971                 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n");
4972                 return;
4973         }
4974
4975         opc = OPC_INB_SET_PHY_PROFILE;
4976
4977         payload.tag = cpu_to_le32(tag);
4978         payload.ppc_phyid =
4979                 cpu_to_le32(((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4980                             | (phy & 0xFF));
4981
4982         for (i = 0; i < length; i++)
4983                 payload.reserved[i] = cpu_to_le32(*(buf + i));
4984
4985         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4986                         sizeof(payload), 0);
4987         if (rc)
4988                 pm8001_tag_free(pm8001_ha, tag);
4989
4990         pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy);
4991 }
4992 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4993         .name                   = "pmc80xx",
4994         .chip_init              = pm80xx_chip_init,
4995         .chip_soft_rst          = pm80xx_chip_soft_rst,
4996         .chip_rst               = pm80xx_hw_chip_rst,
4997         .chip_iounmap           = pm8001_chip_iounmap,
4998         .isr                    = pm80xx_chip_isr,
4999         .is_our_interrupt       = pm80xx_chip_is_our_interrupt,
5000         .isr_process_oq         = process_oq,
5001         .interrupt_enable       = pm80xx_chip_interrupt_enable,
5002         .interrupt_disable      = pm80xx_chip_interrupt_disable,
5003         .make_prd               = pm8001_chip_make_sg,
5004         .smp_req                = pm80xx_chip_smp_req,
5005         .ssp_io_req             = pm80xx_chip_ssp_io_req,
5006         .sata_req               = pm80xx_chip_sata_req,
5007         .phy_start_req          = pm80xx_chip_phy_start_req,
5008         .phy_stop_req           = pm80xx_chip_phy_stop_req,
5009         .reg_dev_req            = pm80xx_chip_reg_dev_req,
5010         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
5011         .phy_ctl_req            = pm80xx_chip_phy_ctl_req,
5012         .task_abort             = pm8001_chip_abort_task,
5013         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
5014         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
5015         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
5016         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5017         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
5018         .fatal_errors           = pm80xx_fatal_errors,
5019         .hw_event_ack_req       = pm80xx_hw_event_ack_req,
5020 };