2 * Marvell 88SE64xx/88SE94xx main function head file
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
8 * This file is licensed under GPLv2.
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/spinlock.h>
32 #include <linux/delay.h>
33 #include <linux/types.h>
34 #include <linux/ctype.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/pci.h>
37 #include <linux/platform_device.h>
38 #include <linux/interrupt.h>
39 #include <linux/irq.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <asm/unaligned.h>
43 #include <scsi/libsas.h>
44 #include <scsi/scsi.h>
45 #include <scsi/scsi_tcq.h>
46 #include <scsi/sas_ata.h>
49 #define DRV_NAME "mvsas"
50 #define DRV_VERSION "0.8.16"
51 #define MVS_ID_NOT_MAPPED 0x7f
52 #define WIDE_PORT_MAX_PHY 4
53 #define mv_printk(fmt, arg ...) \
54 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
56 #define mv_dprintk(format, arg...) \
57 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
59 #define mv_dprintk(format, arg...)
61 #define MV_MAX_U32 0xffffffff
63 extern int interrupt_coalescing;
64 extern struct mvs_tgt_initiator mvs_tgt;
65 extern struct mvs_info *tgt_mvi;
66 extern const struct mvs_dispatch mvs_64xx_dispatch;
67 extern const struct mvs_dispatch mvs_94xx_dispatch;
69 #define bit(n) ((u64)1 << n)
71 #define for_each_phy(__lseq_mask, __mc, __lseq) \
72 for ((__mc) = (__lseq_mask), (__lseq) = 0; \
74 (++__lseq), (__mc) >>= 1)
76 #define MVS_PHY_ID (1U << sas_phy->id)
77 #define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
78 #define UNASSOC_D2H_FIS(id) \
79 ((void *) mvi->rx_fis + 0x100 * id)
80 #define SATA_RECEIVED_FIS_LIST(reg_set) \
81 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
82 #define SATA_RECEIVED_SDB_FIS(reg_set) \
83 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
84 #define SATA_RECEIVED_D2H_FIS(reg_set) \
85 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
86 #define SATA_RECEIVED_PIO_FIS(reg_set) \
87 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
88 #define SATA_RECEIVED_DMA_FIS(reg_set) \
89 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
105 struct mvs_dispatch {
107 int (*chip_init)(struct mvs_info *mvi);
108 int (*spi_init)(struct mvs_info *mvi);
109 int (*chip_ioremap)(struct mvs_info *mvi);
110 void (*chip_iounmap)(struct mvs_info *mvi);
111 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
112 u32 (*isr_status)(struct mvs_info *mvi, int irq);
113 void (*interrupt_enable)(struct mvs_info *mvi);
114 void (*interrupt_disable)(struct mvs_info *mvi);
116 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
117 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
119 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
120 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
121 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
123 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
124 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
125 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
127 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
128 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
130 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
131 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
133 void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
134 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
135 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
137 void (*start_delivery)(struct mvs_info *mvi, u32 tx);
138 u32 (*rx_update)(struct mvs_info *mvi);
139 void (*int_full)(struct mvs_info *mvi);
140 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
141 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
142 u32 (*prd_size)(void);
143 u32 (*prd_count)(void);
144 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
145 void (*detect_porttype)(struct mvs_info *mvi, int i);
146 int (*oob_done)(struct mvs_info *mvi, int i);
147 void (*fix_phy_info)(struct mvs_info *mvi, int i,
148 struct sas_identify_frame *id);
149 void (*phy_work_around)(struct mvs_info *mvi, int i);
150 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
151 struct sas_phy_linkrates *rates);
152 u32 (*phy_max_link_rate)(void);
153 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
154 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
155 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
156 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
157 void (*clear_active_cmds)(struct mvs_info *mvi);
158 u32 (*spi_read_data)(struct mvs_info *mvi);
159 void (*spi_write_data)(struct mvs_info *mvi, u32 data);
160 int (*spi_buildcmd)(struct mvs_info *mvi,
167 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
168 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
169 void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
170 int buf_len, int from, void *prd);
171 void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
172 void (*non_spec_ncq_error)(struct mvs_info *mvi);
173 int (*gpio_write)(struct mvs_prv_info *mvs_prv, u8 reg_type,
174 u8 reg_index, u8 reg_count, u8 *write_data);
178 struct mvs_chip_info {
186 const struct mvs_dispatch *dispatch;
188 #define MVS_MAX_SG (1U << mvi->chip->sg_width)
189 #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
190 #define MVS_RX_FISL_SZ \
191 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
192 #define MVS_CHIP_DISP (mvi->chip->dispatch)
194 struct mvs_err_info {
200 __le32 flags; /* PRD tbl len; SAS, SATA ctl */
201 __le32 lens; /* cmd, max resp frame len */
202 __le32 tags; /* targ port xfer tag; tag */
203 __le32 data_len; /* data xfer len */
204 __le64 cmd_tbl; /* command table address */
205 __le64 open_frame; /* open addr frame address */
206 __le64 status_buf; /* status buffer address */
207 __le64 prd_tbl; /* PRD tbl address */
212 struct asd_sas_port sas_port;
215 struct list_head list;
219 struct mvs_info *mvi;
220 struct mvs_port *port;
221 struct asd_sas_phy sas_phy;
222 struct sas_identify identify;
223 struct scsi_device *sdev;
224 struct timer_list timer;
226 u64 att_dev_sas_addr;
238 enum sas_linkrate minimum_linkrate;
239 enum sas_linkrate maximum_linkrate;
243 struct list_head dev_entry;
244 enum sas_device_type dev_type;
245 struct mvs_info *mvi_info;
246 struct domain_device *sas_device;
255 /* Generate PHY tunning parameters */
257 /* 1 bit, transmitter emphasis enable */
259 /* 4 bits, transmitter emphasis amplitude */
261 /* 3 bits, reserved space */
262 u8 Reserved_2bit_1:3;
263 /* 5 bits, transmitter amplitude */
265 /* 2 bits, transmitter amplitude adjust */
267 /* 1 bit, reserved space */
269 /* 2 bytes, reserved space */
274 /* 4 bits, FFE Capacitor Select (value range 0~F) */
276 /* 3 bits, FFE Resistor Select (value range 0~7) */
283 * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
284 * The data area is valid only Signature="MRVL".
285 * If any member fills with 0xFF, the member is invalid.
287 struct hba_info_page {
289 /* 4 bytes, structure signature,should be "MRVL" at first initial */
296 /* 64 bytes, SAS address for each port */
300 /* 8 bytes for vanir 8 port PHY FFE seeting
301 * BIT 0~3 : FFE Capacitor select(value range 0~F)
302 * BIT 4~6 : FFE Resistor select(value range 0~7)
306 struct ffe_control ffe_ctl[8];
311 /* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */
315 /* 32 bytes, PHY tuning parameters for each PHY*/
316 struct phy_tuning phy_tuning[8];
320 }; /* total 256 bytes */
322 struct mvs_slot_info {
323 struct list_head entry;
325 struct sas_task *task;
332 /* DMA buffer for storing cmd tbl, open addr frame, status buffer,
338 struct mvs_port *port;
339 struct mvs_device *device;
350 struct pci_dev *pdev;
353 /* enhanced mode registers */
356 /* peripheral or soc registers */
357 void __iomem *regs_ex;
358 u8 sas_addr[SAS_ADDR_SIZE];
361 struct sas_ha_struct *sas;
362 struct Scsi_Host *shost;
364 /* TX (delivery) DMA ring */
368 /* cached next-producer idx */
371 /* RX (completion) DMA ring */
375 /* RX consumer idx */
380 dma_addr_t rx_fis_dma;
382 /* DMA command header slots */
383 struct mvs_cmd_hdr *slot;
387 const struct mvs_chip_info *chip;
391 /* further per-slot information */
392 struct mvs_phy phy[MVS_MAX_PHYS];
393 struct mvs_port port[MVS_MAX_PHYS];
396 struct list_head *hba_list;
397 struct list_head soc_entry;
398 struct list_head wq_list;
399 unsigned long instance;
405 struct hba_info_page hba_info_param;
406 struct mvs_device devices[MVS_MAX_DEVICES];
408 dma_addr_t bulk_buffer_dma;
410 dma_addr_t bulk_buffer_dma1;
411 #define TRASH_BUCKET_SIZE 0x20000
413 struct mvs_slot_info slot_info[0];
421 struct mvs_info *mvi[2];
422 struct tasklet_struct mv_tasklet;
426 struct delayed_work work_q;
427 struct mvs_info *mvi;
430 struct list_head entry;
433 struct mvs_task_exec_info {
434 struct sas_task *task;
435 struct mvs_cmd_hdr *hdr;
436 struct mvs_port *port;
441 /******************** function prototype *********************/
442 void mvs_get_sas_addr(void *buf, u32 buflen);
443 void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
444 void mvs_tag_free(struct mvs_info *mvi, u32 tag);
445 void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
446 int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
447 void mvs_tag_init(struct mvs_info *mvi);
448 void mvs_iounmap(void __iomem *regs);
449 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
450 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
451 int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
453 void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
454 u32 off_hi, u64 sas_addr);
455 void mvs_scan_start(struct Scsi_Host *shost);
456 int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
457 int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags);
458 int mvs_abort_task(struct sas_task *task);
459 int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
460 int mvs_clear_aca(struct domain_device *dev, u8 *lun);
461 int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
462 void mvs_port_formed(struct asd_sas_phy *sas_phy);
463 void mvs_port_deformed(struct asd_sas_phy *sas_phy);
464 int mvs_dev_found(struct domain_device *dev);
465 void mvs_dev_gone(struct domain_device *dev);
466 int mvs_lu_reset(struct domain_device *dev, u8 *lun);
467 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
468 int mvs_I_T_nexus_reset(struct domain_device *dev);
469 int mvs_query_task(struct sas_task *task);
470 void mvs_release_task(struct mvs_info *mvi,
471 struct domain_device *dev);
472 void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
473 struct domain_device *dev);
474 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
475 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
476 int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
477 struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
478 int mvs_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
479 u8 reg_count, u8 *write_data);