drivers/scsi/mpt3sas/mpt3sas_base.c

   1 /*
   2  * This is the Fusion MPT base driver providing common API layer interface
   3  * for access to MPT (Message Passing Technology) firmware.
   4  *
   5  * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
   6  * Copyright (C) 2012-2014  LSI Corporation
   7  * Copyright (C) 2013-2014 Avago Technologies
   8  *  (mailto: MPT-FusionLinux.pdl@avagotech.com)
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * NO WARRANTY
  21  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  22  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  23  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  24  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  25  * solely responsible for determining the appropriateness of using and
  26  * distributing the Program and assumes all risks associated with its
  27  * exercise of rights under this Agreement, including but not limited to
  28  * the risks and costs of program errors, damage to or loss of data,
  29  * programs or equipment, and unavailability or interruption of operations.
  30
  31  * DISCLAIMER OF LIABILITY
  32  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  33  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  35  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  36  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  37  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  38  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  39
  40  * You should have received a copy of the GNU General Public License
  41  * along with this program; if not, write to the Free Software
  42  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
  43  * USA.
  44  */
  45
  46 #include <linux/kernel.h>
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/init.h>
  50 #include <linux/slab.h>
  51 #include <linux/types.h>
  52 #include <linux/pci.h>
  53 #include <linux/kdev_t.h>
  54 #include <linux/blkdev.h>
  55 #include <linux/delay.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/dma-mapping.h>
  58 #include <linux/io.h>
  59 #include <linux/time.h>
  60 #include <linux/ktime.h>
  61 #include <linux/kthread.h>
  62 #include <asm/page.h>        /* To get host page size per arch */
  63 #include <linux/aer.h>
  64
  65
  66 #include "mpt3sas_base.h"
  67
  68 static MPT_CALLBACK     mpt_callbacks[MPT_MAX_CALLBACKS];
  69
  70
  71 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  72
  73  /* maximum controller queue depth */
  74 #define MAX_HBA_QUEUE_DEPTH     30000
  75 #define MAX_CHAIN_DEPTH         100000
  76 static int max_queue_depth = -1;
  77 module_param(max_queue_depth, int, 0444);
  78 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  79
  80 static int max_sgl_entries = -1;
  81 module_param(max_sgl_entries, int, 0444);
  82 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  83
  84 static int msix_disable = -1;
  85 module_param(msix_disable, int, 0444);
  86 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  87
  88 static int smp_affinity_enable = 1;
  89 module_param(smp_affinity_enable, int, 0444);
  90 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)");
  91
  92 static int max_msix_vectors = -1;
  93 module_param(max_msix_vectors, int, 0444);
  94 MODULE_PARM_DESC(max_msix_vectors,
  95         " max msix vectors");
  96
  97 static int irqpoll_weight = -1;
  98 module_param(irqpoll_weight, int, 0444);
  99 MODULE_PARM_DESC(irqpoll_weight,
 100         "irq poll weight (default= one fourth of HBA queue depth)");
 101
 102 static int mpt3sas_fwfault_debug;
 103 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
 104         " enable detection of firmware fault and halt firmware - (default=0)");
 105
 106 static int perf_mode = -1;
 107 module_param(perf_mode, int, 0444);
 108 MODULE_PARM_DESC(perf_mode,
 109         "Performance mode (only for Aero/Sea Generation), options:\n\t\t"
 110         "0 - balanced: high iops mode is enabled &\n\t\t"
 111         "interrupt coalescing is enabled only on high iops queues,\n\t\t"
 112         "1 - iops: high iops mode is disabled &\n\t\t"
 113         "interrupt coalescing is enabled on all queues,\n\t\t"
 114         "2 - latency: high iops mode is disabled &\n\t\t"
 115         "interrupt coalescing is enabled on all queues with timeout value 0xA,\n"
 116         "\t\tdefault - default perf_mode is 'balanced'"
 117         );
 118
 119 enum mpt3sas_perf_mode {
 120         MPT_PERF_MODE_DEFAULT   = -1,
 121         MPT_PERF_MODE_BALANCED  = 0,
 122         MPT_PERF_MODE_IOPS      = 1,
 123         MPT_PERF_MODE_LATENCY   = 2,
 124 };
 125
 126 static int
 127 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc,
 128                 u32 ioc_state, int timeout);
 129 static int
 130 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
 131 static void
 132 _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc);
 133
 134 /**
 135  * mpt3sas_base_check_cmd_timeout - Function
 136  *              to check timeout and command termination due
 137  *              to Host reset.
 138  *
 139  * @ioc:        per adapter object.
 140  * @status:     Status of issued command.
 141  * @mpi_request:mf request pointer.
 142  * @sz:         size of buffer.
 143  *
 144  * @Returns - 1/0 Reset to be done or Not
 145  */
 146 u8
 147 mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc,
 148                 u8 status, void *mpi_request, int sz)
 149 {
 150         u8 issue_reset = 0;
 151
 152         if (!(status & MPT3_CMD_RESET))
 153                 issue_reset = 1;
 154
 155         ioc_err(ioc, "Command %s\n",
 156                 issue_reset == 0 ? "terminated due to Host Reset" : "Timeout");
 157         _debug_dump_mf(mpi_request, sz);
 158
 159         return issue_reset;
 160 }
 161
 162 /**
 163  * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
 164  * @val: ?
 165  * @kp: ?
 166  *
 167  * Return: ?
 168  */
 169 static int
 170 _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp)
 171 {
 172         int ret = param_set_int(val, kp);
 173         struct MPT3SAS_ADAPTER *ioc;
 174
 175         if (ret)
 176                 return ret;
 177
 178         /* global ioc spinlock to protect controller list on list operations */
 179         pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
 180         spin_lock(&gioc_lock);
 181         list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
 182                 ioc->fwfault_debug = mpt3sas_fwfault_debug;
 183         spin_unlock(&gioc_lock);
 184         return 0;
 185 }
 186 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
 187         param_get_int, &mpt3sas_fwfault_debug, 0644);
 188
 189 /**
 190  * _base_readl_aero - retry readl for max three times.
 191  * @addr: MPT Fusion system interface register address
 192  *
 193  * Retry the readl() for max three times if it gets zero value
 194  * while reading the system interface register.
 195  */
 196 static inline u32
 197 _base_readl_aero(const volatile void __iomem *addr)
 198 {
 199         u32 i = 0, ret_val;
 200
 201         do {
 202                 ret_val = readl(addr);
 203                 i++;
 204         } while (ret_val == 0 && i < 3);
 205
 206         return ret_val;
 207 }
 208
 209 static inline u32
 210 _base_readl(const volatile void __iomem *addr)
 211 {
 212         return readl(addr);
 213 }
 214
 215 /**
 216  * _base_clone_reply_to_sys_mem - copies reply to reply free iomem
 217  *                                in BAR0 space.
 218  *
 219  * @ioc: per adapter object
 220  * @reply: reply message frame(lower 32bit addr)
 221  * @index: System request message index.
 222  */
 223 static void
 224 _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply,
 225                 u32 index)
 226 {
 227         /*
 228          * 256 is offset within sys register.
 229          * 256 offset MPI frame starts. Max MPI frame supported is 32.
 230          * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts
 231          */
 232         u16 cmd_credit = ioc->facts.RequestCredit + 1;
 233         void __iomem *reply_free_iomem = (void __iomem *)ioc->chip +
 234                         MPI_FRAME_START_OFFSET +
 235                         (cmd_credit * ioc->request_sz) + (index * sizeof(u32));
 236
 237         writel(reply, reply_free_iomem);
 238 }
 239
 240 /**
 241  * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames
 242  *                              to system/BAR0 region.
 243  *
 244  * @dst_iomem: Pointer to the destination location in BAR0 space.
 245  * @src: Pointer to the Source data.
 246  * @size: Size of data to be copied.
 247  */
 248 static void
 249 _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size)
 250 {
 251         int i;
 252         u32 *src_virt_mem = (u32 *)src;
 253
 254         for (i = 0; i < size/4; i++)
 255                 writel((u32)src_virt_mem[i],
 256                                 (void __iomem *)dst_iomem + (i * 4));
 257 }
 258
 259 /**
 260  * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region
 261  *
 262  * @dst_iomem: Pointer to the destination location in BAR0 space.
 263  * @src: Pointer to the Source data.
 264  * @size: Size of data to be copied.
 265  */
 266 static void
 267 _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size)
 268 {
 269         int i;
 270         u32 *src_virt_mem = (u32 *)(src);
 271
 272         for (i = 0; i < size/4; i++)
 273                 writel((u32)src_virt_mem[i],
 274                         (void __iomem *)dst_iomem + (i * 4));
 275 }
 276
 277 /**
 278  * _base_get_chain - Calculates and Returns virtual chain address
 279  *                       for the provided smid in BAR0 space.
 280  *
 281  * @ioc: per adapter object
 282  * @smid: system request message index
 283  * @sge_chain_count: Scatter gather chain count.
 284  *
 285  * Return: the chain address.
 286  */
 287 static inline void __iomem*
 288 _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid,
 289                 u8 sge_chain_count)
 290 {
 291         void __iomem *base_chain, *chain_virt;
 292         u16 cmd_credit = ioc->facts.RequestCredit + 1;
 293
 294         base_chain  = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET +
 295                 (cmd_credit * ioc->request_sz) +
 296                 REPLY_FREE_POOL_SIZE;
 297         chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth *
 298                         ioc->request_sz) + (sge_chain_count * ioc->request_sz);
 299         return chain_virt;
 300 }
 301
 302 /**
 303  * _base_get_chain_phys - Calculates and Returns physical address
 304  *                      in BAR0 for scatter gather chains, for
 305  *                      the provided smid.
 306  *
 307  * @ioc: per adapter object
 308  * @smid: system request message index
 309  * @sge_chain_count: Scatter gather chain count.
 310  *
 311  * Return: Physical chain address.
 312  */
 313 static inline phys_addr_t
 314 _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid,
 315                 u8 sge_chain_count)
 316 {
 317         phys_addr_t base_chain_phys, chain_phys;
 318         u16 cmd_credit = ioc->facts.RequestCredit + 1;
 319
 320         base_chain_phys  = ioc->chip_phys + MPI_FRAME_START_OFFSET +
 321                 (cmd_credit * ioc->request_sz) +
 322                 REPLY_FREE_POOL_SIZE;
 323         chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth *
 324                         ioc->request_sz) + (sge_chain_count * ioc->request_sz);
 325         return chain_phys;
 326 }
 327
 328 /**
 329  * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host
 330  *                      buffer address for the provided smid.
 331  *                      (Each smid can have 64K starts from 17024)
 332  *
 333  * @ioc: per adapter object
 334  * @smid: system request message index
 335  *
 336  * Return: Pointer to buffer location in BAR0.
 337  */
 338
 339 static void __iomem *
 340 _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
 341 {
 342         u16 cmd_credit = ioc->facts.RequestCredit + 1;
 343         // Added extra 1 to reach end of chain.
 344         void __iomem *chain_end = _base_get_chain(ioc,
 345                         cmd_credit + 1,
 346                         ioc->facts.MaxChainDepth);
 347         return chain_end + (smid * 64 * 1024);
 348 }
 349
 350 /**
 351  * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped
 352  *              Host buffer Physical address for the provided smid.
 353  *              (Each smid can have 64K starts from 17024)
 354  *
 355  * @ioc: per adapter object
 356  * @smid: system request message index
 357  *
 358  * Return: Pointer to buffer location in BAR0.
 359  */
 360 static phys_addr_t
 361 _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
 362 {
 363         u16 cmd_credit = ioc->facts.RequestCredit + 1;
 364         phys_addr_t chain_end_phys = _base_get_chain_phys(ioc,
 365                         cmd_credit + 1,
 366                         ioc->facts.MaxChainDepth);
 367         return chain_end_phys + (smid * 64 * 1024);
 368 }
 369
 370 /**
 371  * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain
 372  *                      lookup list and Provides chain_buffer
 373  *                      address for the matching dma address.
 374  *                      (Each smid can have 64K starts from 17024)
 375  *
 376  * @ioc: per adapter object
 377  * @chain_buffer_dma: Chain buffer dma address.
 378  *
 379  * Return: Pointer to chain buffer. Or Null on Failure.
 380  */
 381 static void *
 382 _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc,
 383                 dma_addr_t chain_buffer_dma)
 384 {
 385         u16 index, j;
 386         struct chain_tracker *ct;
 387
 388         for (index = 0; index < ioc->scsiio_depth; index++) {
 389                 for (j = 0; j < ioc->chains_needed_per_io; j++) {
 390                         ct = &ioc->chain_lookup[index].chains_per_smid[j];
 391                         if (ct && ct->chain_buffer_dma == chain_buffer_dma)
 392                                 return ct->chain_buffer;
 393                 }
 394         }
 395         ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n");
 396         return NULL;
 397 }
 398
 399 /**
 400  * _clone_sg_entries -  MPI EP's scsiio and config requests
 401  *                      are handled here. Base function for
 402  *                      double buffering, before submitting
 403  *                      the requests.
 404  *
 405  * @ioc: per adapter object.
 406  * @mpi_request: mf request pointer.
 407  * @smid: system request message index.
 408  */
 409 static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc,
 410                 void *mpi_request, u16 smid)
 411 {
 412         Mpi2SGESimple32_t *sgel, *sgel_next;
 413         u32  sgl_flags, sge_chain_count = 0;
 414         bool is_write = false;
 415         u16 i = 0;
 416         void __iomem *buffer_iomem;
 417         phys_addr_t buffer_iomem_phys;
 418         void __iomem *buff_ptr;
 419         phys_addr_t buff_ptr_phys;
 420         void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO];
 421         void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO];
 422         phys_addr_t dst_addr_phys;
 423         MPI2RequestHeader_t *request_hdr;
 424         struct scsi_cmnd *scmd;
 425         struct scatterlist *sg_scmd = NULL;
 426         int is_scsiio_req = 0;
 427
 428         request_hdr = (MPI2RequestHeader_t *) mpi_request;
 429
 430         if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
 431                 Mpi25SCSIIORequest_t *scsiio_request =
 432                         (Mpi25SCSIIORequest_t *)mpi_request;
 433                 sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL;
 434                 is_scsiio_req = 1;
 435         } else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
 436                 Mpi2ConfigRequest_t  *config_req =
 437                         (Mpi2ConfigRequest_t *)mpi_request;
 438                 sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE;
 439         } else
 440                 return;
 441
 442         /* From smid we can get scsi_cmd, once we have sg_scmd,
 443          * we just need to get sg_virt and sg_next to get virual
 444          * address associated with sgel->Address.
 445          */
 446
 447         if (is_scsiio_req) {
 448                 /* Get scsi_cmd using smid */
 449                 scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
 450                 if (scmd == NULL) {
 451                         ioc_err(ioc, "scmd is NULL\n");
 452                         return;
 453                 }
 454
 455                 /* Get sg_scmd from scmd provided */
 456                 sg_scmd = scsi_sglist(scmd);
 457         }
 458
 459         /*
 460          * 0 - 255      System register
 461          * 256 - 4352   MPI Frame. (This is based on maxCredit 32)
 462          * 4352 - 4864  Reply_free pool (512 byte is reserved
 463          *              considering maxCredit 32. Reply need extra
 464          *              room, for mCPU case kept four times of
 465          *              maxCredit).
 466          * 4864 - 17152 SGE chain element. (32cmd * 3 chain of
 467          *              128 byte size = 12288)
 468          * 17152 - x    Host buffer mapped with smid.
 469          *              (Each smid can have 64K Max IO.)
 470          * BAR0+Last 1K MSIX Addr and Data
 471          * Total size in use 2113664 bytes of 4MB BAR0
 472          */
 473
 474         buffer_iomem = _base_get_buffer_bar0(ioc, smid);
 475         buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid);
 476
 477         buff_ptr = buffer_iomem;
 478         buff_ptr_phys = buffer_iomem_phys;
 479         WARN_ON(buff_ptr_phys > U32_MAX);
 480
 481         if (le32_to_cpu(sgel->FlagsLength) &
 482                         (MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT))
 483                 is_write = true;
 484
 485         for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) {
 486
 487                 sgl_flags =
 488                     (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT);
 489
 490                 switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) {
 491                 case MPI2_SGE_FLAGS_CHAIN_ELEMENT:
 492                         /*
 493                          * Helper function which on passing
 494                          * chain_buffer_dma returns chain_buffer. Get
 495                          * the virtual address for sgel->Address
 496                          */
 497                         sgel_next =
 498                                 _base_get_chain_buffer_dma_to_chain_buffer(ioc,
 499                                                 le32_to_cpu(sgel->Address));
 500                         if (sgel_next == NULL)
 501                                 return;
 502                         /*
 503                          * This is coping 128 byte chain
 504                          * frame (not a host buffer)
 505                          */
 506                         dst_chain_addr[sge_chain_count] =
 507                                 _base_get_chain(ioc,
 508                                         smid, sge_chain_count);
 509                         src_chain_addr[sge_chain_count] =
 510                                                 (void *) sgel_next;
 511                         dst_addr_phys = _base_get_chain_phys(ioc,
 512                                                 smid, sge_chain_count);
 513                         WARN_ON(dst_addr_phys > U32_MAX);
 514                         sgel->Address =
 515                                 cpu_to_le32(lower_32_bits(dst_addr_phys));
 516                         sgel = sgel_next;
 517                         sge_chain_count++;
 518                         break;
 519                 case MPI2_SGE_FLAGS_SIMPLE_ELEMENT:
 520                         if (is_write) {
 521                                 if (is_scsiio_req) {
 522                                         _base_clone_to_sys_mem(buff_ptr,
 523                                             sg_virt(sg_scmd),
 524                                             (le32_to_cpu(sgel->FlagsLength) &
 525                                             0x00ffffff));
 526                                         /*
 527                                          * FIXME: this relies on a a zero
 528                                          * PCI mem_offset.
 529                                          */
 530                                         sgel->Address =
 531                                             cpu_to_le32((u32)buff_ptr_phys);
 532                                 } else {
 533                                         _base_clone_to_sys_mem(buff_ptr,
 534                                             ioc->config_vaddr,
 535                                             (le32_to_cpu(sgel->FlagsLength) &
 536                                             0x00ffffff));
 537                                         sgel->Address =
 538                                             cpu_to_le32((u32)buff_ptr_phys);
 539                                 }
 540                         }
 541                         buff_ptr += (le32_to_cpu(sgel->FlagsLength) &
 542                             0x00ffffff);
 543                         buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) &
 544                             0x00ffffff);
 545                         if ((le32_to_cpu(sgel->FlagsLength) &
 546                             (MPI2_SGE_FLAGS_END_OF_BUFFER
 547                                         << MPI2_SGE_FLAGS_SHIFT)))
 548                                 goto eob_clone_chain;
 549                         else {
 550                                 /*
 551                                  * Every single element in MPT will have
 552                                  * associated sg_next. Better to sanity that
 553                                  * sg_next is not NULL, but it will be a bug
 554                                  * if it is null.
 555                                  */
 556                                 if (is_scsiio_req) {
 557                                         sg_scmd = sg_next(sg_scmd);
 558                                         if (sg_scmd)
 559                                                 sgel++;
 560                                         else
 561                                                 goto eob_clone_chain;
 562                                 }
 563                         }
 564                         break;
 565                 }
 566         }
 567
 568 eob_clone_chain:
 569         for (i = 0; i < sge_chain_count; i++) {
 570                 if (is_scsiio_req)
 571                         _base_clone_to_sys_mem(dst_chain_addr[i],
 572                                 src_chain_addr[i], ioc->request_sz);
 573         }
 574 }
 575
 576 /**
 577  *  mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
 578  * @arg: input argument, used to derive ioc
 579  *
 580  * Return:
 581  * 0 if controller is removed from pci subsystem.
 582  * -1 for other case.
 583  */
 584 static int mpt3sas_remove_dead_ioc_func(void *arg)
 585 {
 586         struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
 587         struct pci_dev *pdev;
 588
 589         if (!ioc)
 590                 return -1;
 591
 592         pdev = ioc->pdev;
 593         if (!pdev)
 594                 return -1;
 595         pci_stop_and_remove_bus_device_locked(pdev);
 596         return 0;
 597 }
 598
 599 /**
 600  * _base_sync_drv_fw_timestamp - Sync Drive-Fw TimeStamp.
 601  * @ioc: Per Adapter Object
 602  *
 603  * Return nothing.
 604  */
 605 static void _base_sync_drv_fw_timestamp(struct MPT3SAS_ADAPTER *ioc)
 606 {
 607         Mpi26IoUnitControlRequest_t *mpi_request;
 608         Mpi26IoUnitControlReply_t *mpi_reply;
 609         u16 smid;
 610         ktime_t current_time;
 611         u64 TimeStamp = 0;
 612         u8 issue_reset = 0;
 613
 614         mutex_lock(&ioc->scsih_cmds.mutex);
 615         if (ioc->scsih_cmds.status != MPT3_CMD_NOT_USED) {
 616                 ioc_err(ioc, "scsih_cmd in use %s\n", __func__);
 617                 goto out;
 618         }
 619         ioc->scsih_cmds.status = MPT3_CMD_PENDING;
 620         smid = mpt3sas_base_get_smid(ioc, ioc->scsih_cb_idx);
 621         if (!smid) {
 622                 ioc_err(ioc, "Failed obtaining a smid %s\n", __func__);
 623                 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
 624                 goto out;
 625         }
 626         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
 627         ioc->scsih_cmds.smid = smid;
 628         memset(mpi_request, 0, sizeof(Mpi26IoUnitControlRequest_t));
 629         mpi_request->Function = MPI2_FUNCTION_IO_UNIT_CONTROL;
 630         mpi_request->Operation = MPI26_CTRL_OP_SET_IOC_PARAMETER;
 631         mpi_request->IOCParameter = MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP;
 632         current_time = ktime_get_real();
 633         TimeStamp = ktime_to_ms(current_time);
 634         mpi_request->Reserved7 = cpu_to_le32(TimeStamp & 0xFFFFFFFF);
 635         mpi_request->IOCParameterValue = cpu_to_le32(TimeStamp >> 32);
 636         init_completion(&ioc->scsih_cmds.done);
 637         ioc->put_smid_default(ioc, smid);
 638         dinitprintk(ioc, ioc_info(ioc,
 639             "Io Unit Control Sync TimeStamp (sending), @time %lld ms\n",
 640             TimeStamp));
 641         wait_for_completion_timeout(&ioc->scsih_cmds.done,
 642                 MPT3SAS_TIMESYNC_TIMEOUT_SECONDS*HZ);
 643         if (!(ioc->scsih_cmds.status & MPT3_CMD_COMPLETE)) {
 644                 mpt3sas_check_cmd_timeout(ioc,
 645                     ioc->scsih_cmds.status, mpi_request,
 646                     sizeof(Mpi2SasIoUnitControlRequest_t)/4, issue_reset);
 647                 goto issue_host_reset;
 648         }
 649         if (ioc->scsih_cmds.status & MPT3_CMD_REPLY_VALID) {
 650                 mpi_reply = ioc->scsih_cmds.reply;
 651                 dinitprintk(ioc, ioc_info(ioc,
 652                     "Io Unit Control sync timestamp (complete): ioc_status(0x%04x), loginfo(0x%08x)\n",
 653                     le16_to_cpu(mpi_reply->IOCStatus),
 654                     le32_to_cpu(mpi_reply->IOCLogInfo)));
 655         }
 656 issue_host_reset:
 657         if (issue_reset)
 658                 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
 659         ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
 660 out:
 661         mutex_unlock(&ioc->scsih_cmds.mutex);
 662 }
 663
 664 /**
 665  * _base_fault_reset_work - workq handling ioc fault conditions
 666  * @work: input argument, used to derive ioc
 667  *
 668  * Context: sleep.
 669  */
 670 static void
 671 _base_fault_reset_work(struct work_struct *work)
 672 {
 673         struct MPT3SAS_ADAPTER *ioc =
 674             container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
 675         unsigned long    flags;
 676         u32 doorbell;
 677         int rc;
 678         struct task_struct *p;
 679
 680
 681         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 682         if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) ||
 683                         ioc->pci_error_recovery)
 684                 goto rearm_timer;
 685         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 686
 687         doorbell = mpt3sas_base_get_iocstate(ioc, 0);
 688         if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
 689                 ioc_err(ioc, "SAS host is non-operational !!!!\n");
 690
 691                 /* It may be possible that EEH recovery can resolve some of
 692                  * pci bus failure issues rather removing the dead ioc function
 693                  * by considering controller is in a non-operational state. So
 694                  * here priority is given to the EEH recovery. If it doesn't
 695                  * not resolve this issue, mpt3sas driver will consider this
 696                  * controller to non-operational state and remove the dead ioc
 697                  * function.
 698                  */
 699                 if (ioc->non_operational_loop++ < 5) {
 700                         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
 701                                                          flags);
 702                         goto rearm_timer;
 703                 }
 704
 705                 /*
 706                  * Call _scsih_flush_pending_cmds callback so that we flush all
 707                  * pending commands back to OS. This call is required to aovid
 708                  * deadlock at block layer. Dead IOC will fail to do diag reset,
 709                  * and this call is safe since dead ioc will never return any
 710                  * command back from HW.
 711                  */
 712                 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
 713                 /*
 714                  * Set remove_host flag early since kernel thread will
 715                  * take some time to execute.
 716                  */
 717                 ioc->remove_host = 1;
 718                 /*Remove the Dead Host */
 719                 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
 720                     "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
 721                 if (IS_ERR(p))
 722                         ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
 723                                 __func__);
 724                 else
 725                         ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
 726                                 __func__);
 727                 return; /* don't rearm timer */
 728         }
 729
 730         if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
 731                 u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
 732                     ioc->manu_pg11.CoreDumpTOSec :
 733                     MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
 734
 735                 timeout /= (FAULT_POLLING_INTERVAL/1000);
 736
 737                 if (ioc->ioc_coredump_loop == 0) {
 738                         mpt3sas_print_coredump_info(ioc,
 739                             doorbell & MPI2_DOORBELL_DATA_MASK);
 740                         /* do not accept any IOs and disable the interrupts */
 741                         spin_lock_irqsave(
 742                             &ioc->ioc_reset_in_progress_lock, flags);
 743                         ioc->shost_recovery = 1;
 744                         spin_unlock_irqrestore(
 745                             &ioc->ioc_reset_in_progress_lock, flags);
 746                         mpt3sas_base_mask_interrupts(ioc);
 747                         _base_clear_outstanding_commands(ioc);
 748                 }
 749
 750                 ioc_info(ioc, "%s: CoreDump loop %d.",
 751                     __func__, ioc->ioc_coredump_loop);
 752
 753                 /* Wait until CoreDump completes or times out */
 754                 if (ioc->ioc_coredump_loop++ < timeout) {
 755                         spin_lock_irqsave(
 756                             &ioc->ioc_reset_in_progress_lock, flags);
 757                         goto rearm_timer;
 758                 }
 759         }
 760
 761         if (ioc->ioc_coredump_loop) {
 762                 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP)
 763                         ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d",
 764                             __func__, ioc->ioc_coredump_loop);
 765                 else
 766                         ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d",
 767                             __func__, ioc->ioc_coredump_loop);
 768                 ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE;
 769         }
 770         ioc->non_operational_loop = 0;
 771         if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
 772                 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
 773                 ioc_warn(ioc, "%s: hard reset: %s\n",
 774                          __func__, rc == 0 ? "success" : "failed");
 775                 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
 776                 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
 777                         mpt3sas_print_fault_code(ioc, doorbell &
 778                             MPI2_DOORBELL_DATA_MASK);
 779                 } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
 780                     MPI2_IOC_STATE_COREDUMP)
 781                         mpt3sas_print_coredump_info(ioc, doorbell &
 782                             MPI2_DOORBELL_DATA_MASK);
 783                 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
 784                     MPI2_IOC_STATE_OPERATIONAL)
 785                         return; /* don't rearm timer */
 786         }
 787         ioc->ioc_coredump_loop = 0;
 788         if (ioc->time_sync_interval &&
 789             ++ioc->timestamp_update_count >= ioc->time_sync_interval) {
 790                 ioc->timestamp_update_count = 0;
 791                 _base_sync_drv_fw_timestamp(ioc);
 792         }
 793         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 794  rearm_timer:
 795         if (ioc->fault_reset_work_q)
 796                 queue_delayed_work(ioc->fault_reset_work_q,
 797                     &ioc->fault_reset_work,
 798                     msecs_to_jiffies(FAULT_POLLING_INTERVAL));
 799         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 800 }
 801
 802 /**
 803  * mpt3sas_base_start_watchdog - start the fault_reset_work_q
 804  * @ioc: per adapter object
 805  *
 806  * Context: sleep.
 807  */
 808 void
 809 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
 810 {
 811         unsigned long    flags;
 812
 813         if (ioc->fault_reset_work_q)
 814                 return;
 815
 816         ioc->timestamp_update_count = 0;
 817         /* initialize fault polling */
 818
 819         INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
 820         snprintf(ioc->fault_reset_work_q_name,
 821             sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
 822             ioc->driver_name, ioc->id);
 823         ioc->fault_reset_work_q =
 824                 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
 825         if (!ioc->fault_reset_work_q) {
 826                 ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__);
 827                 return;
 828         }
 829         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 830         if (ioc->fault_reset_work_q)
 831                 queue_delayed_work(ioc->fault_reset_work_q,
 832                     &ioc->fault_reset_work,
 833                     msecs_to_jiffies(FAULT_POLLING_INTERVAL));
 834         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 835 }
 836
 837 /**
 838  * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
 839  * @ioc: per adapter object
 840  *
 841  * Context: sleep.
 842  */
 843 void
 844 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
 845 {
 846         unsigned long flags;
 847         struct workqueue_struct *wq;
 848
 849         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 850         wq = ioc->fault_reset_work_q;
 851         ioc->fault_reset_work_q = NULL;
 852         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 853         if (wq) {
 854                 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
 855                         flush_workqueue(wq);
 856                 destroy_workqueue(wq);
 857         }
 858 }
 859
 860 /**
 861  * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
 862  * @ioc: per adapter object
 863  * @fault_code: fault code
 864  */
 865 void
 866 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
 867 {
 868         ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code);
 869 }
 870
 871 /**
 872  * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state
 873  * @ioc: per adapter object
 874  * @fault_code: fault code
 875  *
 876  * Return nothing.
 877  */
 878 void
 879 mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code)
 880 {
 881         ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code);
 882 }
 883
 884 /**
 885  * mpt3sas_base_wait_for_coredump_completion - Wait until coredump
 886  * completes or times out
 887  * @ioc: per adapter object
 888  * @caller: caller function name
 889  *
 890  * Returns 0 for success, non-zero for failure.
 891  */
 892 int
 893 mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc,
 894                 const char *caller)
 895 {
 896         u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
 897                         ioc->manu_pg11.CoreDumpTOSec :
 898                         MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
 899
 900         int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT,
 901                                         timeout);
 902
 903         if (ioc_state)
 904                 ioc_err(ioc,
 905                     "%s: CoreDump timed out. (ioc_state=0x%x)\n",
 906                     caller, ioc_state);
 907         else
 908                 ioc_info(ioc,
 909                     "%s: CoreDump completed. (ioc_state=0x%x)\n",
 910                     caller, ioc_state);
 911
 912         return ioc_state;
 913 }
 914
 915 /**
 916  * mpt3sas_halt_firmware - halt's mpt controller firmware
 917  * @ioc: per adapter object
 918  *
 919  * For debugging timeout related issues.  Writing 0xCOFFEE00
 920  * to the doorbell register will halt controller firmware. With
 921  * the purpose to stop both driver and firmware, the enduser can
 922  * obtain a ring buffer from controller UART.
 923  */
 924 void
 925 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
 926 {
 927         u32 doorbell;
 928
 929         if (!ioc->fwfault_debug)
 930                 return;
 931
 932         dump_stack();
 933
 934         doorbell = ioc->base_readl(&ioc->chip->Doorbell);
 935         if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
 936                 mpt3sas_print_fault_code(ioc, doorbell &
 937                     MPI2_DOORBELL_DATA_MASK);
 938         } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
 939             MPI2_IOC_STATE_COREDUMP) {
 940                 mpt3sas_print_coredump_info(ioc, doorbell &
 941                     MPI2_DOORBELL_DATA_MASK);
 942         } else {
 943                 writel(0xC0FFEE00, &ioc->chip->Doorbell);
 944                 ioc_err(ioc, "Firmware is halted due to command timeout\n");
 945         }
 946
 947         if (ioc->fwfault_debug == 2)
 948                 for (;;)
 949                         ;
 950         else
 951                 panic("panic in %s\n", __func__);
 952 }
 953
 954 /**
 955  * _base_sas_ioc_info - verbose translation of the ioc status
 956  * @ioc: per adapter object
 957  * @mpi_reply: reply mf payload returned from firmware
 958  * @request_hdr: request mf
 959  */
 960 static void
 961 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
 962         MPI2RequestHeader_t *request_hdr)
 963 {
 964         u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
 965             MPI2_IOCSTATUS_MASK;
 966         char *desc = NULL;
 967         u16 frame_sz;
 968         char *func_str = NULL;
 969
 970         /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
 971         if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
 972             request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
 973             request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
 974                 return;
 975
 976         if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
 977                 return;
 978         /*
 979          * Older Firmware version doesn't support driver trigger pages.
 980          * So, skip displaying 'config invalid type' type
 981          * of error message.
 982          */
 983         if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
 984                 Mpi2ConfigRequest_t *rqst = (Mpi2ConfigRequest_t *)request_hdr;
 985
 986                 if ((rqst->ExtPageType ==
 987                     MPI2_CONFIG_EXTPAGETYPE_DRIVER_PERSISTENT_TRIGGER) &&
 988                     !(ioc->logging_level & MPT_DEBUG_CONFIG)) {
 989                         return;
 990                 }
 991         }
 992
 993         switch (ioc_status) {
 994
 995 /****************************************************************************
 996 *  Common IOCStatus values for all replies
 997 ****************************************************************************/
 998
 999         case MPI2_IOCSTATUS_INVALID_FUNCTION:
1000                 desc = "invalid function";
1001                 break;
1002         case MPI2_IOCSTATUS_BUSY:
1003                 desc = "busy";
1004                 break;
1005         case MPI2_IOCSTATUS_INVALID_SGL:
1006                 desc = "invalid sgl";
1007                 break;
1008         case MPI2_IOCSTATUS_INTERNAL_ERROR:
1009                 desc = "internal error";
1010                 break;
1011         case MPI2_IOCSTATUS_INVALID_VPID:
1012                 desc = "invalid vpid";
1013                 break;
1014         case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
1015                 desc = "insufficient resources";
1016                 break;
1017         case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
1018                 desc = "insufficient power";
1019                 break;
1020         case MPI2_IOCSTATUS_INVALID_FIELD:
1021                 desc = "invalid field";
1022                 break;
1023         case MPI2_IOCSTATUS_INVALID_STATE:
1024                 desc = "invalid state";
1025                 break;
1026         case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
1027                 desc = "op state not supported";
1028                 break;
1029
1030 /****************************************************************************
1031 *  Config IOCStatus values
1032 ****************************************************************************/
1033
1034         case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
1035                 desc = "config invalid action";
1036                 break;
1037         case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
1038                 desc = "config invalid type";
1039                 break;
1040         case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
1041                 desc = "config invalid page";
1042                 break;
1043         case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
1044                 desc = "config invalid data";
1045                 break;
1046         case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
1047                 desc = "config no defaults";
1048                 break;
1049         case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
1050                 desc = "config cant commit";
1051                 break;
1052
1053 /****************************************************************************
1054 *  SCSI IO Reply
1055 ****************************************************************************/
1056
1057         case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
1058         case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
1059         case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
1060         case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
1061         case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
1062         case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
1063         case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
1064         case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
1065         case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
1066         case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
1067         case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
1068         case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
1069                 break;
1070
1071 /****************************************************************************
1072 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
1073 ****************************************************************************/
1074
1075         case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
1076                 desc = "eedp guard error";
1077                 break;
1078         case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
1079                 desc = "eedp ref tag error";
1080                 break;
1081         case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
1082                 desc = "eedp app tag error";
1083                 break;
1084
1085 /****************************************************************************
1086 *  SCSI Target values
1087 ****************************************************************************/
1088
1089         case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
1090                 desc = "target invalid io index";
1091                 break;
1092         case MPI2_IOCSTATUS_TARGET_ABORTED:
1093                 desc = "target aborted";
1094                 break;
1095         case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
1096                 desc = "target no conn retryable";
1097                 break;
1098         case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
1099                 desc = "target no connection";
1100                 break;
1101         case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
1102                 desc = "target xfer count mismatch";
1103                 break;
1104         case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
1105                 desc = "target data offset error";
1106                 break;
1107         case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
1108                 desc = "target too much write data";
1109                 break;
1110         case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
1111                 desc = "target iu too short";
1112                 break;
1113         case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
1114                 desc = "target ack nak timeout";
1115                 break;
1116         case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
1117                 desc = "target nak received";
1118                 break;
1119
1120 /****************************************************************************
1121 *  Serial Attached SCSI values
1122 ****************************************************************************/
1123
1124         case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
1125                 desc = "smp request failed";
1126                 break;
1127         case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
1128                 desc = "smp data overrun";
1129                 break;
1130
1131 /****************************************************************************
1132 *  Diagnostic Buffer Post / Diagnostic Release values
1133 ****************************************************************************/
1134
1135         case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
1136                 desc = "diagnostic released";
1137                 break;
1138         default:
1139                 break;
1140         }
1141
1142         if (!desc)
1143                 return;
1144
1145         switch (request_hdr->Function) {
1146         case MPI2_FUNCTION_CONFIG:
1147                 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
1148                 func_str = "config_page";
1149                 break;
1150         case MPI2_FUNCTION_SCSI_TASK_MGMT:
1151                 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
1152                 func_str = "task_mgmt";
1153                 break;
1154         case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
1155                 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
1156                 func_str = "sas_iounit_ctl";
1157                 break;
1158         case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
1159                 frame_sz = sizeof(Mpi2SepRequest_t);
1160                 func_str = "enclosure";
1161                 break;
1162         case MPI2_FUNCTION_IOC_INIT:
1163                 frame_sz = sizeof(Mpi2IOCInitRequest_t);
1164                 func_str = "ioc_init";
1165                 break;
1166         case MPI2_FUNCTION_PORT_ENABLE:
1167                 frame_sz = sizeof(Mpi2PortEnableRequest_t);
1168                 func_str = "port_enable";
1169                 break;
1170         case MPI2_FUNCTION_SMP_PASSTHROUGH:
1171                 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
1172                 func_str = "smp_passthru";
1173                 break;
1174         case MPI2_FUNCTION_NVME_ENCAPSULATED:
1175                 frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) +
1176                     ioc->sge_size;
1177                 func_str = "nvme_encapsulated";
1178                 break;
1179         default:
1180                 frame_sz = 32;
1181                 func_str = "unknown";
1182                 break;
1183         }
1184
1185         ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
1186                  desc, ioc_status, request_hdr, func_str);
1187
1188         _debug_dump_mf(request_hdr, frame_sz/4);
1189 }
1190
1191 /**
1192  * _base_display_event_data - verbose translation of firmware asyn events
1193  * @ioc: per adapter object
1194  * @mpi_reply: reply mf payload returned from firmware
1195  */
1196 static void
1197 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
1198         Mpi2EventNotificationReply_t *mpi_reply)
1199 {
1200         char *desc = NULL;
1201         u16 event;
1202
1203         if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
1204                 return;
1205
1206         event = le16_to_cpu(mpi_reply->Event);
1207
1208         switch (event) {
1209         case MPI2_EVENT_LOG_DATA:
1210                 desc = "Log Data";
1211                 break;
1212         case MPI2_EVENT_STATE_CHANGE:
1213                 desc = "Status Change";
1214                 break;
1215         case MPI2_EVENT_HARD_RESET_RECEIVED:
1216                 desc = "Hard Reset Received";
1217                 break;
1218         case MPI2_EVENT_EVENT_CHANGE:
1219                 desc = "Event Change";
1220                 break;
1221         case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
1222                 desc = "Device Status Change";
1223                 break;
1224         case MPI2_EVENT_IR_OPERATION_STATUS:
1225                 if (!ioc->hide_ir_msg)
1226                         desc = "IR Operation Status";
1227                 break;
1228         case MPI2_EVENT_SAS_DISCOVERY:
1229         {
1230                 Mpi2EventDataSasDiscovery_t *event_data =
1231                     (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
1232                 ioc_info(ioc, "Discovery: (%s)",
1233                          event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ?
1234                          "start" : "stop");
1235                 if (event_data->DiscoveryStatus)
1236                         pr_cont(" discovery_status(0x%08x)",
1237                             le32_to_cpu(event_data->DiscoveryStatus));
1238                 pr_cont("\n");
1239                 return;
1240         }
1241         case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
1242                 desc = "SAS Broadcast Primitive";
1243                 break;
1244         case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
1245                 desc = "SAS Init Device Status Change";
1246                 break;
1247         case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
1248                 desc = "SAS Init Table Overflow";
1249                 break;
1250         case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
1251                 desc = "SAS Topology Change List";
1252                 break;
1253         case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
1254                 desc = "SAS Enclosure Device Status Change";
1255                 break;
1256         case MPI2_EVENT_IR_VOLUME:
1257                 if (!ioc->hide_ir_msg)
1258                         desc = "IR Volume";
1259                 break;
1260         case MPI2_EVENT_IR_PHYSICAL_DISK:
1261                 if (!ioc->hide_ir_msg)
1262                         desc = "IR Physical Disk";
1263                 break;
1264         case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
1265                 if (!ioc->hide_ir_msg)
1266                         desc = "IR Configuration Change List";
1267                 break;
1268         case MPI2_EVENT_LOG_ENTRY_ADDED:
1269                 if (!ioc->hide_ir_msg)
1270                         desc = "Log Entry Added";
1271                 break;
1272         case MPI2_EVENT_TEMP_THRESHOLD:
1273                 desc = "Temperature Threshold";
1274                 break;
1275         case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
1276                 desc = "Cable Event";
1277                 break;
1278         case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
1279                 desc = "SAS Device Discovery Error";
1280                 break;
1281         case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE:
1282                 desc = "PCIE Device Status Change";
1283                 break;
1284         case MPI2_EVENT_PCIE_ENUMERATION:
1285         {
1286                 Mpi26EventDataPCIeEnumeration_t *event_data =
1287                         (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData;
1288                 ioc_info(ioc, "PCIE Enumeration: (%s)",
1289                          event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ?
1290                          "start" : "stop");
1291                 if (event_data->EnumerationStatus)
1292                         pr_cont("enumeration_status(0x%08x)",
1293                                 le32_to_cpu(event_data->EnumerationStatus));
1294                 pr_cont("\n");
1295                 return;
1296         }
1297         case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
1298                 desc = "PCIE Topology Change List";
1299                 break;
1300         }
1301
1302         if (!desc)
1303                 return;
1304
1305         ioc_info(ioc, "%s\n", desc);
1306 }
1307
1308 /**
1309  * _base_sas_log_info - verbose translation of firmware log info
1310  * @ioc: per adapter object
1311  * @log_info: log info
1312  */
1313 static void
1314 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
1315 {
1316         union loginfo_type {
1317                 u32     loginfo;
1318                 struct {
1319                         u32     subcode:16;
1320                         u32     code:8;
1321                         u32     originator:4;
1322                         u32     bus_type:4;
1323                 } dw;
1324         };
1325         union loginfo_type sas_loginfo;
1326         char *originator_str = NULL;
1327
1328         sas_loginfo.loginfo = log_info;
1329         if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
1330                 return;
1331
1332         /* each nexus loss loginfo */
1333         if (log_info == 0x31170000)
1334                 return;
1335
1336         /* eat the loginfos associated with task aborts */
1337         if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
1338             0x31140000 || log_info == 0x31130000))
1339                 return;
1340
1341         switch (sas_loginfo.dw.originator) {
1342         case 0:
1343                 originator_str = "IOP";
1344                 break;
1345         case 1:
1346                 originator_str = "PL";
1347                 break;
1348         case 2:
1349                 if (!ioc->hide_ir_msg)
1350                         originator_str = "IR";
1351                 else
1352                         originator_str = "WarpDrive";
1353                 break;
1354         }
1355
1356         ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
1357                  log_info,
1358                  originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode);
1359 }
1360
1361 /**
1362  * _base_display_reply_info -
1363  * @ioc: per adapter object
1364  * @smid: system request message index
1365  * @msix_index: MSIX table index supplied by the OS
1366  * @reply: reply message frame(lower 32bit addr)
1367  */
1368 static void
1369 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1370         u32 reply)
1371 {
1372         MPI2DefaultReply_t *mpi_reply;
1373         u16 ioc_status;
1374         u32 loginfo = 0;
1375
1376         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1377         if (unlikely(!mpi_reply)) {
1378                 ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n",
1379                         __FILE__, __LINE__, __func__);
1380                 return;
1381         }
1382         ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
1383
1384         if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
1385             (ioc->logging_level & MPT_DEBUG_REPLY)) {
1386                 _base_sas_ioc_info(ioc , mpi_reply,
1387                    mpt3sas_base_get_msg_frame(ioc, smid));
1388         }
1389
1390         if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
1391                 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
1392                 _base_sas_log_info(ioc, loginfo);
1393         }
1394
1395         if (ioc_status || loginfo) {
1396                 ioc_status &= MPI2_IOCSTATUS_MASK;
1397                 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
1398         }
1399 }
1400
1401 /**
1402  * mpt3sas_base_done - base internal command completion routine
1403  * @ioc: per adapter object
1404  * @smid: system request message index
1405  * @msix_index: MSIX table index supplied by the OS
1406  * @reply: reply message frame(lower 32bit addr)
1407  *
1408  * Return:
1409  * 1 meaning mf should be freed from _base_interrupt
1410  * 0 means the mf is freed from this function.
1411  */
1412 u8
1413 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1414         u32 reply)
1415 {
1416         MPI2DefaultReply_t *mpi_reply;
1417
1418         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1419         if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
1420                 return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
1421
1422         if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
1423                 return 1;
1424
1425         ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
1426         if (mpi_reply) {
1427                 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
1428                 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
1429         }
1430         ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
1431
1432         complete(&ioc->base_cmds.done);
1433         return 1;
1434 }
1435
1436 /**
1437  * _base_async_event - main callback handler for firmware asyn events
1438  * @ioc: per adapter object
1439  * @msix_index: MSIX table index supplied by the OS
1440  * @reply: reply message frame(lower 32bit addr)
1441  *
1442  * Return:
1443  * 1 meaning mf should be freed from _base_interrupt
1444  * 0 means the mf is freed from this function.
1445  */
1446 static u8
1447 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
1448 {
1449         Mpi2EventNotificationReply_t *mpi_reply;
1450         Mpi2EventAckRequest_t *ack_request;
1451         u16 smid;
1452         struct _event_ack_list *delayed_event_ack;
1453
1454         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1455         if (!mpi_reply)
1456                 return 1;
1457         if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
1458                 return 1;
1459
1460         _base_display_event_data(ioc, mpi_reply);
1461
1462         if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
1463                 goto out;
1464         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
1465         if (!smid) {
1466                 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
1467                                         GFP_ATOMIC);
1468                 if (!delayed_event_ack)
1469                         goto out;
1470                 INIT_LIST_HEAD(&delayed_event_ack->list);
1471                 delayed_event_ack->Event = mpi_reply->Event;
1472                 delayed_event_ack->EventContext = mpi_reply->EventContext;
1473                 list_add_tail(&delayed_event_ack->list,
1474                                 &ioc->delayed_event_ack_list);
1475                 dewtprintk(ioc,
1476                            ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n",
1477                                     le16_to_cpu(mpi_reply->Event)));
1478                 goto out;
1479         }
1480
1481         ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
1482         memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
1483         ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
1484         ack_request->Event = mpi_reply->Event;
1485         ack_request->EventContext = mpi_reply->EventContext;
1486         ack_request->VF_ID = 0;  /* TODO */
1487         ack_request->VP_ID = 0;
1488         ioc->put_smid_default(ioc, smid);
1489
1490  out:
1491
1492         /* scsih callback handler */
1493         mpt3sas_scsih_event_callback(ioc, msix_index, reply);
1494
1495         /* ctl callback handler */
1496         mpt3sas_ctl_event_callback(ioc, msix_index, reply);
1497
1498         return 1;
1499 }
1500
1501 static struct scsiio_tracker *
1502 _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1503 {
1504         struct scsi_cmnd *cmd;
1505
1506         if (WARN_ON(!smid) ||
1507             WARN_ON(smid >= ioc->hi_priority_smid))
1508                 return NULL;
1509
1510         cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
1511         if (cmd)
1512                 return scsi_cmd_priv(cmd);
1513
1514         return NULL;
1515 }
1516
1517 /**
1518  * _base_get_cb_idx - obtain the callback index
1519  * @ioc: per adapter object
1520  * @smid: system request message index
1521  *
1522  * Return: callback index.
1523  */
1524 static u8
1525 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1526 {
1527         int i;
1528         u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1;
1529         u8 cb_idx = 0xFF;
1530
1531         if (smid < ioc->hi_priority_smid) {
1532                 struct scsiio_tracker *st;
1533
1534                 if (smid < ctl_smid) {
1535                         st = _get_st_from_smid(ioc, smid);
1536                         if (st)
1537                                 cb_idx = st->cb_idx;
1538                 } else if (smid == ctl_smid)
1539                         cb_idx = ioc->ctl_cb_idx;
1540         } else if (smid < ioc->internal_smid) {
1541                 i = smid - ioc->hi_priority_smid;
1542                 cb_idx = ioc->hpr_lookup[i].cb_idx;
1543         } else if (smid <= ioc->hba_queue_depth) {
1544                 i = smid - ioc->internal_smid;
1545                 cb_idx = ioc->internal_lookup[i].cb_idx;
1546         }
1547         return cb_idx;
1548 }
1549
1550 /**
1551  * mpt3sas_base_mask_interrupts - disable interrupts
1552  * @ioc: per adapter object
1553  *
1554  * Disabling ResetIRQ, Reply and Doorbell Interrupts
1555  */
1556 void
1557 mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1558 {
1559         u32 him_register;
1560
1561         ioc->mask_interrupts = 1;
1562         him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1563         him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
1564         writel(him_register, &ioc->chip->HostInterruptMask);
1565         ioc->base_readl(&ioc->chip->HostInterruptMask);
1566 }
1567
1568 /**
1569  * mpt3sas_base_unmask_interrupts - enable interrupts
1570  * @ioc: per adapter object
1571  *
1572  * Enabling only Reply Interrupts
1573  */
1574 void
1575 mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1576 {
1577         u32 him_register;
1578
1579         him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1580         him_register &= ~MPI2_HIM_RIM;
1581         writel(him_register, &ioc->chip->HostInterruptMask);
1582         ioc->mask_interrupts = 0;
1583 }
1584
1585 union reply_descriptor {
1586         u64 word;
1587         struct {
1588                 u32 low;
1589                 u32 high;
1590         } u;
1591 };
1592
1593 static u32 base_mod64(u64 dividend, u32 divisor)
1594 {
1595         u32 remainder;
1596
1597         if (!divisor)
1598                 pr_err("mpt3sas: DIVISOR is zero, in div fn\n");
1599         remainder = do_div(dividend, divisor);
1600         return remainder;
1601 }
1602
1603 /**
1604  * _base_process_reply_queue - Process reply descriptors from reply
1605  *              descriptor post queue.
1606  * @reply_q: per IRQ's reply queue object.
1607  *
1608  * Return: number of reply descriptors processed from reply
1609  *              descriptor queue.
1610  */
1611 static int
1612 _base_process_reply_queue(struct adapter_reply_queue *reply_q)
1613 {
1614         union reply_descriptor rd;
1615         u64 completed_cmds;
1616         u8 request_descript_type;
1617         u16 smid;
1618         u8 cb_idx;
1619         u32 reply;
1620         u8 msix_index = reply_q->msix_index;
1621         struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1622         Mpi2ReplyDescriptorsUnion_t *rpf;
1623         u8 rc;
1624
1625         completed_cmds = 0;
1626         if (!atomic_add_unless(&reply_q->busy, 1, 1))
1627                 return completed_cmds;
1628
1629         rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
1630         request_descript_type = rpf->Default.ReplyFlags
1631              & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1632         if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
1633                 atomic_dec(&reply_q->busy);
1634                 return completed_cmds;
1635         }
1636
1637         cb_idx = 0xFF;
1638         do {
1639                 rd.word = le64_to_cpu(rpf->Words);
1640                 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
1641                         goto out;
1642                 reply = 0;
1643                 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
1644                 if (request_descript_type ==
1645                     MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
1646                     request_descript_type ==
1647                     MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
1648                     request_descript_type ==
1649                     MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) {
1650                         cb_idx = _base_get_cb_idx(ioc, smid);
1651                         if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1652                             (likely(mpt_callbacks[cb_idx] != NULL))) {
1653                                 rc = mpt_callbacks[cb_idx](ioc, smid,
1654                                     msix_index, 0);
1655                                 if (rc)
1656                                         mpt3sas_base_free_smid(ioc, smid);
1657                         }
1658                 } else if (request_descript_type ==
1659                     MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
1660                         reply = le32_to_cpu(
1661                             rpf->AddressReply.ReplyFrameAddress);
1662                         if (reply > ioc->reply_dma_max_address ||
1663                             reply < ioc->reply_dma_min_address)
1664                                 reply = 0;
1665                         if (smid) {
1666                                 cb_idx = _base_get_cb_idx(ioc, smid);
1667                                 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1668                                     (likely(mpt_callbacks[cb_idx] != NULL))) {
1669                                         rc = mpt_callbacks[cb_idx](ioc, smid,
1670                                             msix_index, reply);
1671                                         if (reply)
1672                                                 _base_display_reply_info(ioc,
1673                                                     smid, msix_index, reply);
1674                                         if (rc)
1675                                                 mpt3sas_base_free_smid(ioc,
1676                                                     smid);
1677                                 }
1678                         } else {
1679                                 _base_async_event(ioc, msix_index, reply);
1680                         }
1681
1682                         /* reply free queue handling */
1683                         if (reply) {
1684                                 ioc->reply_free_host_index =
1685                                     (ioc->reply_free_host_index ==
1686                                     (ioc->reply_free_queue_depth - 1)) ?
1687                                     0 : ioc->reply_free_host_index + 1;
1688                                 ioc->reply_free[ioc->reply_free_host_index] =
1689                                     cpu_to_le32(reply);
1690                                 if (ioc->is_mcpu_endpoint)
1691                                         _base_clone_reply_to_sys_mem(ioc,
1692                                                 reply,
1693                                                 ioc->reply_free_host_index);
1694                                 writel(ioc->reply_free_host_index,
1695                                     &ioc->chip->ReplyFreeHostIndex);
1696                         }
1697                 }
1698
1699                 rpf->Words = cpu_to_le64(ULLONG_MAX);
1700                 reply_q->reply_post_host_index =
1701                     (reply_q->reply_post_host_index ==
1702                     (ioc->reply_post_queue_depth - 1)) ? 0 :
1703                     reply_q->reply_post_host_index + 1;
1704                 request_descript_type =
1705                     reply_q->reply_post_free[reply_q->reply_post_host_index].
1706                     Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1707                 completed_cmds++;
1708                 /* Update the reply post host index after continuously
1709                  * processing the threshold number of Reply Descriptors.
1710                  * So that FW can find enough entries to post the Reply
1711                  * Descriptors in the reply descriptor post queue.
1712                  */
1713                 if (completed_cmds >= ioc->thresh_hold) {
1714                         if (ioc->combined_reply_queue) {
1715                                 writel(reply_q->reply_post_host_index |
1716                                                 ((msix_index  & 7) <<
1717                                                  MPI2_RPHI_MSIX_INDEX_SHIFT),
1718                                     ioc->replyPostRegisterIndex[msix_index/8]);
1719                         } else {
1720                                 writel(reply_q->reply_post_host_index |
1721                                                 (msix_index <<
1722                                                  MPI2_RPHI_MSIX_INDEX_SHIFT),
1723                                                 &ioc->chip->ReplyPostHostIndex);
1724                         }
1725                         if (!reply_q->irq_poll_scheduled) {
1726                                 reply_q->irq_poll_scheduled = true;
1727                                 irq_poll_sched(&reply_q->irqpoll);
1728                         }
1729                         atomic_dec(&reply_q->busy);
1730                         return completed_cmds;
1731                 }
1732                 if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1733                         goto out;
1734                 if (!reply_q->reply_post_host_index)
1735                         rpf = reply_q->reply_post_free;
1736                 else
1737                         rpf++;
1738         } while (1);
1739
1740  out:
1741
1742         if (!completed_cmds) {
1743                 atomic_dec(&reply_q->busy);
1744                 return completed_cmds;
1745         }
1746
1747         if (ioc->is_warpdrive) {
1748                 writel(reply_q->reply_post_host_index,
1749                 ioc->reply_post_host_index[msix_index]);
1750                 atomic_dec(&reply_q->busy);
1751                 return completed_cmds;
1752         }
1753
1754         /* Update Reply Post Host Index.
1755          * For those HBA's which support combined reply queue feature
1756          * 1. Get the correct Supplemental Reply Post Host Index Register.
1757          *    i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1758          *    Index Register address bank i.e replyPostRegisterIndex[],
1759          * 2. Then update this register with new reply host index value
1760          *    in ReplyPostIndex field and the MSIxIndex field with
1761          *    msix_index value reduced to a value between 0 and 7,
1762          *    using a modulo 8 operation. Since each Supplemental Reply Post
1763          *    Host Index Register supports 8 MSI-X vectors.
1764          *
1765          * For other HBA's just update the Reply Post Host Index register with
1766          * new reply host index value in ReplyPostIndex Field and msix_index
1767          * value in MSIxIndex field.
1768          */
1769         if (ioc->combined_reply_queue)
1770                 writel(reply_q->reply_post_host_index | ((msix_index  & 7) <<
1771                         MPI2_RPHI_MSIX_INDEX_SHIFT),
1772                         ioc->replyPostRegisterIndex[msix_index/8]);
1773         else
1774                 writel(reply_q->reply_post_host_index | (msix_index <<
1775                         MPI2_RPHI_MSIX_INDEX_SHIFT),
1776                         &ioc->chip->ReplyPostHostIndex);
1777         atomic_dec(&reply_q->busy);
1778         return completed_cmds;
1779 }
1780
1781 /**
1782  * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
1783  * @irq: irq number (not used)
1784  * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
1785  *
1786  * Return: IRQ_HANDLED if processed, else IRQ_NONE.
1787  */
1788 static irqreturn_t
1789 _base_interrupt(int irq, void *bus_id)
1790 {
1791         struct adapter_reply_queue *reply_q = bus_id;
1792         struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1793
1794         if (ioc->mask_interrupts)
1795                 return IRQ_NONE;
1796         if (reply_q->irq_poll_scheduled)
1797                 return IRQ_HANDLED;
1798         return ((_base_process_reply_queue(reply_q) > 0) ?
1799                         IRQ_HANDLED : IRQ_NONE);
1800 }
1801
1802 /**
1803  * _base_irqpoll - IRQ poll callback handler
1804  * @irqpoll: irq_poll object
1805  * @budget: irq poll weight
1806  *
1807  * returns number of reply descriptors processed
1808  */
1809 static int
1810 _base_irqpoll(struct irq_poll *irqpoll, int budget)
1811 {
1812         struct adapter_reply_queue *reply_q;
1813         int num_entries = 0;
1814
1815         reply_q = container_of(irqpoll, struct adapter_reply_queue,
1816                         irqpoll);
1817         if (reply_q->irq_line_enable) {
1818                 disable_irq_nosync(reply_q->os_irq);
1819                 reply_q->irq_line_enable = false;
1820         }
1821         num_entries = _base_process_reply_queue(reply_q);
1822         if (num_entries < budget) {
1823                 irq_poll_complete(irqpoll);
1824                 reply_q->irq_poll_scheduled = false;
1825                 reply_q->irq_line_enable = true;
1826                 enable_irq(reply_q->os_irq);
1827                 /*
1828                  * Go for one more round of processing the
1829                  * reply descriptor post queue incase if HBA
1830                  * Firmware has posted some reply descriptors
1831                  * while reenabling the IRQ.
1832                  */
1833                 _base_process_reply_queue(reply_q);
1834         }
1835
1836         return num_entries;
1837 }
1838
1839 /**
1840  * _base_init_irqpolls - initliaze IRQ polls
1841  * @ioc: per adapter object
1842  *
1843  * returns nothing
1844  */
1845 static void
1846 _base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc)
1847 {
1848         struct adapter_reply_queue *reply_q, *next;
1849
1850         if (list_empty(&ioc->reply_queue_list))
1851                 return;
1852
1853         list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1854                 irq_poll_init(&reply_q->irqpoll,
1855                         ioc->hba_queue_depth/4, _base_irqpoll);
1856                 reply_q->irq_poll_scheduled = false;
1857                 reply_q->irq_line_enable = true;
1858                 reply_q->os_irq = pci_irq_vector(ioc->pdev,
1859                     reply_q->msix_index);
1860         }
1861 }
1862
1863 /**
1864  * _base_is_controller_msix_enabled - is controller support muli-reply queues
1865  * @ioc: per adapter object
1866  *
1867  * Return: Whether or not MSI/X is enabled.
1868  */
1869 static inline int
1870 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1871 {
1872         return (ioc->facts.IOCCapabilities &
1873             MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1874 }
1875
1876 /**
1877  * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1878  * @ioc: per adapter object
1879  * @poll: poll over reply descriptor pools incase interrupt for
1880  *              timed-out SCSI command got delayed
1881  * Context: non ISR conext
1882  *
1883  * Called when a Task Management request has completed.
1884  */
1885 void
1886 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll)
1887 {
1888         struct adapter_reply_queue *reply_q;
1889
1890         /* If MSIX capability is turned off
1891          * then multi-queues are not enabled
1892          */
1893         if (!_base_is_controller_msix_enabled(ioc))
1894                 return;
1895
1896         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1897                 if (ioc->shost_recovery || ioc->remove_host ||
1898                                 ioc->pci_error_recovery)
1899                         return;
1900                 /* TMs are on msix_index == 0 */
1901                 if (reply_q->msix_index == 0)
1902                         continue;
1903                 synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
1904                 if (reply_q->irq_poll_scheduled) {
1905                         /* Calling irq_poll_disable will wait for any pending
1906                          * callbacks to have completed.
1907                          */
1908                         irq_poll_disable(&reply_q->irqpoll);
1909                         irq_poll_enable(&reply_q->irqpoll);
1910                         /* check how the scheduled poll has ended,
1911                          * clean up only if necessary
1912                          */
1913                         if (reply_q->irq_poll_scheduled) {
1914                                 reply_q->irq_poll_scheduled = false;
1915                                 reply_q->irq_line_enable = true;
1916                                 enable_irq(reply_q->os_irq);
1917                         }
1918                 }
1919         }
1920         if (poll)
1921                 _base_process_reply_queue(reply_q);
1922 }
1923
1924 /**
1925  * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1926  * @cb_idx: callback index
1927  */
1928 void
1929 mpt3sas_base_release_callback_handler(u8 cb_idx)
1930 {
1931         mpt_callbacks[cb_idx] = NULL;
1932 }
1933
1934 /**
1935  * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1936  * @cb_func: callback function
1937  *
1938  * Return: Index of @cb_func.
1939  */
1940 u8
1941 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1942 {
1943         u8 cb_idx;
1944
1945         for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1946                 if (mpt_callbacks[cb_idx] == NULL)
1947                         break;
1948
1949         mpt_callbacks[cb_idx] = cb_func;
1950         return cb_idx;
1951 }
1952
1953 /**
1954  * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1955  */
1956 void
1957 mpt3sas_base_initialize_callback_handler(void)
1958 {
1959         u8 cb_idx;
1960
1961         for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1962                 mpt3sas_base_release_callback_handler(cb_idx);
1963 }
1964
1965
1966 /**
1967  * _base_build_zero_len_sge - build zero length sg entry
1968  * @ioc: per adapter object
1969  * @paddr: virtual address for SGE
1970  *
1971  * Create a zero length scatter gather entry to insure the IOCs hardware has
1972  * something to use if the target device goes brain dead and tries
1973  * to send data even when none is asked for.
1974  */
1975 static void
1976 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1977 {
1978         u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1979             MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1980             MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1981             MPI2_SGE_FLAGS_SHIFT);
1982         ioc->base_add_sg_single(paddr, flags_length, -1);
1983 }
1984
1985 /**
1986  * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1987  * @paddr: virtual address for SGE
1988  * @flags_length: SGE flags and data transfer length
1989  * @dma_addr: Physical address
1990  */
1991 static void
1992 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1993 {
1994         Mpi2SGESimple32_t *sgel = paddr;
1995
1996         flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1997             MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1998         sgel->FlagsLength = cpu_to_le32(flags_length);
1999         sgel->Address = cpu_to_le32(dma_addr);
2000 }
2001
2002
2003 /**
2004  * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
2005  * @paddr: virtual address for SGE
2006  * @flags_length: SGE flags and data transfer length
2007  * @dma_addr: Physical address
2008  */
2009 static void
2010 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
2011 {
2012         Mpi2SGESimple64_t *sgel = paddr;
2013
2014         flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
2015             MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
2016         sgel->FlagsLength = cpu_to_le32(flags_length);
2017         sgel->Address = cpu_to_le64(dma_addr);
2018 }
2019
2020 /**
2021  * _base_get_chain_buffer_tracker - obtain chain tracker
2022  * @ioc: per adapter object
2023  * @scmd: SCSI commands of the IO request
2024  *
2025  * Return: chain tracker from chain_lookup table using key as
2026  * smid and smid's chain_offset.
2027  */
2028 static struct chain_tracker *
2029 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc,
2030                                struct scsi_cmnd *scmd)
2031 {
2032         struct chain_tracker *chain_req;
2033         struct scsiio_tracker *st = scsi_cmd_priv(scmd);
2034         u16 smid = st->smid;
2035         u8 chain_offset =
2036            atomic_read(&ioc->chain_lookup[smid - 1].chain_offset);
2037
2038         if (chain_offset == ioc->chains_needed_per_io)
2039                 return NULL;
2040
2041         chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset];
2042         atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset);
2043         return chain_req;
2044 }
2045
2046
2047 /**
2048  * _base_build_sg - build generic sg
2049  * @ioc: per adapter object
2050  * @psge: virtual address for SGE
2051  * @data_out_dma: physical address for WRITES
2052  * @data_out_sz: data xfer size for WRITES
2053  * @data_in_dma: physical address for READS
2054  * @data_in_sz: data xfer size for READS
2055  */
2056 static void
2057 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
2058         dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2059         size_t data_in_sz)
2060 {
2061         u32 sgl_flags;
2062
2063         if (!data_out_sz && !data_in_sz) {
2064                 _base_build_zero_len_sge(ioc, psge);
2065                 return;
2066         }
2067
2068         if (data_out_sz && data_in_sz) {
2069                 /* WRITE sgel first */
2070                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2071                     MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
2072                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2073                 ioc->base_add_sg_single(psge, sgl_flags |
2074                     data_out_sz, data_out_dma);
2075
2076                 /* incr sgel */
2077                 psge += ioc->sge_size;
2078
2079                 /* READ sgel last */
2080                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2081                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2082                     MPI2_SGE_FLAGS_END_OF_LIST);
2083                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2084                 ioc->base_add_sg_single(psge, sgl_flags |
2085                     data_in_sz, data_in_dma);
2086         } else if (data_out_sz) /* WRITE */ {
2087                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2088                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2089                     MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
2090                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2091                 ioc->base_add_sg_single(psge, sgl_flags |
2092                     data_out_sz, data_out_dma);
2093         } else if (data_in_sz) /* READ */ {
2094                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2095                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2096                     MPI2_SGE_FLAGS_END_OF_LIST);
2097                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2098                 ioc->base_add_sg_single(psge, sgl_flags |
2099                     data_in_sz, data_in_dma);
2100         }
2101 }
2102
2103 /* IEEE format sgls */
2104
2105 /**
2106  * _base_build_nvme_prp - This function is called for NVMe end devices to build
2107  * a native SGL (NVMe PRP). The native SGL is built starting in the first PRP
2108  * entry of the NVMe message (PRP1).  If the data buffer is small enough to be
2109  * described entirely using PRP1, then PRP2 is not used.  If needed, PRP2 is
2110  * used to describe a larger data buffer.  If the data buffer is too large to
2111  * describe using the two PRP entriess inside the NVMe message, then PRP1
2112  * describes the first data memory segment, and PRP2 contains a pointer to a PRP
2113  * list located elsewhere in memory to describe the remaining data memory
2114  * segments.  The PRP list will be contiguous.
2115  *
2116  * The native SGL for NVMe devices is a Physical Region Page (PRP).  A PRP
2117  * consists of a list of PRP entries to describe a number of noncontigous
2118  * physical memory segments as a single memory buffer, just as a SGL does.  Note
2119  * however, that this function is only used by the IOCTL call, so the memory
2120  * given will be guaranteed to be contiguous.  There is no need to translate
2121  * non-contiguous SGL into a PRP in this case.  All PRPs will describe
2122  * contiguous space that is one page size each.
2123  *
2124  * Each NVMe message contains two PRP entries.  The first (PRP1) either contains
2125  * a PRP list pointer or a PRP element, depending upon the command.  PRP2
2126  * contains the second PRP element if the memory being described fits within 2
2127  * PRP entries, or a PRP list pointer if the PRP spans more than two entries.
2128  *
2129  * A PRP list pointer contains the address of a PRP list, structured as a linear
2130  * array of PRP entries.  Each PRP entry in this list describes a segment of
2131  * physical memory.
2132  *
2133  * Each 64-bit PRP entry comprises an address and an offset field.  The address
2134  * always points at the beginning of a 4KB physical memory page, and the offset
2135  * describes where within that 4KB page the memory segment begins.  Only the
2136  * first element in a PRP list may contain a non-zero offest, implying that all
2137  * memory segments following the first begin at the start of a 4KB page.
2138  *
2139  * Each PRP element normally describes 4KB of physical memory, with exceptions
2140  * for the first and last elements in the list.  If the memory being described
2141  * by the list begins at a non-zero offset within the first 4KB page, then the
2142  * first PRP element will contain a non-zero offset indicating where the region
2143  * begins within the 4KB page.  The last memory segment may end before the end
2144  * of the 4KB segment, depending upon the overall size of the memory being
2145  * described by the PRP list.
2146  *
2147  * Since PRP entries lack any indication of size, the overall data buffer length
2148  * is used to determine where the end of the data memory buffer is located, and
2149  * how many PRP entries are required to describe it.
2150  *
2151  * @ioc: per adapter object
2152  * @smid: system request message index for getting asscociated SGL
2153  * @nvme_encap_request: the NVMe request msg frame pointer
2154  * @data_out_dma: physical address for WRITES
2155  * @data_out_sz: data xfer size for WRITES
2156  * @data_in_dma: physical address for READS
2157  * @data_in_sz: data xfer size for READS
2158  */
2159 static void
2160 _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2161         Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request,
2162         dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2163         size_t data_in_sz)
2164 {
2165         int             prp_size = NVME_PRP_SIZE;
2166         __le64          *prp_entry, *prp1_entry, *prp2_entry;
2167         __le64          *prp_page;
2168         dma_addr_t      prp_entry_dma, prp_page_dma, dma_addr;
2169         u32             offset, entry_len;
2170         u32             page_mask_result, page_mask;
2171         size_t          length;
2172         struct mpt3sas_nvme_cmd *nvme_cmd =
2173                 (void *)nvme_encap_request->NVMe_Command;
2174
2175         /*
2176          * Not all commands require a data transfer. If no data, just return
2177          * without constructing any PRP.
2178          */
2179         if (!data_in_sz && !data_out_sz)
2180                 return;
2181         prp1_entry = &nvme_cmd->prp1;
2182         prp2_entry = &nvme_cmd->prp2;
2183         prp_entry = prp1_entry;
2184         /*
2185          * For the PRP entries, use the specially allocated buffer of
2186          * contiguous memory.
2187          */
2188         prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid);
2189         prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2190
2191         /*
2192          * Check if we are within 1 entry of a page boundary we don't
2193          * want our first entry to be a PRP List entry.
2194          */
2195         page_mask = ioc->page_size - 1;
2196         page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask;
2197         if (!page_mask_result) {
2198                 /* Bump up to next page boundary. */
2199                 prp_page = (__le64 *)((u8 *)prp_page + prp_size);
2200                 prp_page_dma = prp_page_dma + prp_size;
2201         }
2202
2203         /*
2204          * Set PRP physical pointer, which initially points to the current PRP
2205          * DMA memory page.
2206          */
2207         prp_entry_dma = prp_page_dma;
2208
2209         /* Get physical address and length of the data buffer. */
2210         if (data_in_sz) {
2211                 dma_addr = data_in_dma;
2212                 length = data_in_sz;
2213         } else {
2214                 dma_addr = data_out_dma;
2215                 length = data_out_sz;
2216         }
2217
2218         /* Loop while the length is not zero. */
2219         while (length) {
2220                 /*
2221                  * Check if we need to put a list pointer here if we are at
2222                  * page boundary - prp_size (8 bytes).
2223                  */
2224                 page_mask_result = (prp_entry_dma + prp_size) & page_mask;
2225                 if (!page_mask_result) {
2226                         /*
2227                          * This is the last entry in a PRP List, so we need to
2228                          * put a PRP list pointer here.  What this does is:
2229                          *   - bump the current memory pointer to the next
2230                          *     address, which will be the next full page.
2231                          *   - set the PRP Entry to point to that page.  This
2232                          *     is now the PRP List pointer.
2233                          *   - bump the PRP Entry pointer the start of the
2234                          *     next page.  Since all of this PRP memory is
2235                          *     contiguous, no need to get a new page - it's
2236                          *     just the next address.
2237                          */
2238                         prp_entry_dma++;
2239                         *prp_entry = cpu_to_le64(prp_entry_dma);
2240                         prp_entry++;
2241                 }
2242
2243                 /* Need to handle if entry will be part of a page. */
2244                 offset = dma_addr & page_mask;
2245                 entry_len = ioc->page_size - offset;
2246
2247                 if (prp_entry == prp1_entry) {
2248                         /*
2249                          * Must fill in the first PRP pointer (PRP1) before
2250                          * moving on.
2251                          */
2252                         *prp1_entry = cpu_to_le64(dma_addr);
2253
2254                         /*
2255                          * Now point to the second PRP entry within the
2256                          * command (PRP2).
2257                          */
2258                         prp_entry = prp2_entry;
2259                 } else if (prp_entry == prp2_entry) {
2260                         /*
2261                          * Should the PRP2 entry be a PRP List pointer or just
2262                          * a regular PRP pointer?  If there is more than one
2263                          * more page of data, must use a PRP List pointer.
2264                          */
2265                         if (length > ioc->page_size) {
2266                                 /*
2267                                  * PRP2 will contain a PRP List pointer because
2268                                  * more PRP's are needed with this command. The
2269                                  * list will start at the beginning of the
2270                                  * contiguous buffer.
2271                                  */
2272                                 *prp2_entry = cpu_to_le64(prp_entry_dma);
2273
2274                                 /*
2275                                  * The next PRP Entry will be the start of the
2276                                  * first PRP List.
2277                                  */
2278                                 prp_entry = prp_page;
2279                         } else {
2280                                 /*
2281                                  * After this, the PRP Entries are complete.
2282                                  * This command uses 2 PRP's and no PRP list.
2283                                  */
2284                                 *prp2_entry = cpu_to_le64(dma_addr);
2285                         }
2286                 } else {
2287                         /*
2288                          * Put entry in list and bump the addresses.
2289                          *
2290                          * After PRP1 and PRP2 are filled in, this will fill in
2291                          * all remaining PRP entries in a PRP List, one per
2292                          * each time through the loop.
2293                          */
2294                         *prp_entry = cpu_to_le64(dma_addr);
2295                         prp_entry++;
2296                         prp_entry_dma++;
2297                 }
2298
2299                 /*
2300                  * Bump the phys address of the command's data buffer by the
2301                  * entry_len.
2302                  */
2303                 dma_addr += entry_len;
2304
2305                 /* Decrement length accounting for last partial page. */
2306                 if (entry_len > length)
2307                         length = 0;
2308                 else
2309                         length -= entry_len;
2310         }
2311 }
2312
2313 /**
2314  * base_make_prp_nvme -
2315  * Prepare PRPs(Physical Region Page)- SGLs specific to NVMe drives only
2316  *
2317  * @ioc:                per adapter object
2318  * @scmd:               SCSI command from the mid-layer
2319  * @mpi_request:        mpi request
2320  * @smid:               msg Index
2321  * @sge_count:          scatter gather element count.
2322  *
2323  * Return:              true: PRPs are built
2324  *                      false: IEEE SGLs needs to be built
2325  */
2326 static void
2327 base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc,
2328                 struct scsi_cmnd *scmd,
2329                 Mpi25SCSIIORequest_t *mpi_request,
2330                 u16 smid, int sge_count)
2331 {
2332         int sge_len, num_prp_in_chain = 0;
2333         Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl;
2334         __le64 *curr_buff;
2335         dma_addr_t msg_dma, sge_addr, offset;
2336         u32 page_mask, page_mask_result;
2337         struct scatterlist *sg_scmd;
2338         u32 first_prp_len;
2339         int data_len = scsi_bufflen(scmd);
2340         u32 nvme_pg_size;
2341
2342         nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE);
2343         /*
2344          * Nvme has a very convoluted prp format.  One prp is required
2345          * for each page or partial page. Driver need to split up OS sg_list
2346          * entries if it is longer than one page or cross a page
2347          * boundary.  Driver also have to insert a PRP list pointer entry as
2348          * the last entry in each physical page of the PRP list.
2349          *
2350          * NOTE: The first PRP "entry" is actually placed in the first
2351          * SGL entry in the main message as IEEE 64 format.  The 2nd
2352          * entry in the main message is the chain element, and the rest
2353          * of the PRP entries are built in the contiguous pcie buffer.
2354          */
2355         page_mask = nvme_pg_size - 1;
2356
2357         /*
2358          * Native SGL is needed.
2359          * Put a chain element in main message frame that points to the first
2360          * chain buffer.
2361          *
2362          * NOTE:  The ChainOffset field must be 0 when using a chain pointer to
2363          *        a native SGL.
2364          */
2365
2366         /* Set main message chain element pointer */
2367         main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2368         /*
2369          * For NVMe the chain element needs to be the 2nd SG entry in the main
2370          * message.
2371          */
2372         main_chain_element = (Mpi25IeeeSgeChain64_t *)
2373                 ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
2374
2375         /*
2376          * For the PRP entries, use the specially allocated buffer of
2377          * contiguous memory.  Normal chain buffers can't be used
2378          * because each chain buffer would need to be the size of an OS
2379          * page (4k).
2380          */
2381         curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid);
2382         msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2383
2384         main_chain_element->Address = cpu_to_le64(msg_dma);
2385         main_chain_element->NextChainOffset = 0;
2386         main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2387                         MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2388                         MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
2389
2390         /* Build first prp, sge need not to be page aligned*/
2391         ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2392         sg_scmd = scsi_sglist(scmd);
2393         sge_addr = sg_dma_address(sg_scmd);
2394         sge_len = sg_dma_len(sg_scmd);
2395
2396         offset = sge_addr & page_mask;
2397         first_prp_len = nvme_pg_size - offset;
2398
2399         ptr_first_sgl->Address = cpu_to_le64(sge_addr);
2400         ptr_first_sgl->Length = cpu_to_le32(first_prp_len);
2401
2402         data_len -= first_prp_len;
2403
2404         if (sge_len > first_prp_len) {
2405                 sge_addr += first_prp_len;
2406                 sge_len -= first_prp_len;
2407         } else if (data_len && (sge_len == first_prp_len)) {
2408                 sg_scmd = sg_next(sg_scmd);
2409                 sge_addr = sg_dma_address(sg_scmd);
2410                 sge_len = sg_dma_len(sg_scmd);
2411         }
2412
2413         for (;;) {
2414                 offset = sge_addr & page_mask;
2415
2416                 /* Put PRP pointer due to page boundary*/
2417                 page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask;
2418                 if (unlikely(!page_mask_result)) {
2419                         scmd_printk(KERN_NOTICE,
2420                                 scmd, "page boundary curr_buff: 0x%p\n",
2421                                 curr_buff);
2422                         msg_dma += 8;
2423                         *curr_buff = cpu_to_le64(msg_dma);
2424                         curr_buff++;
2425                         num_prp_in_chain++;
2426                 }
2427
2428                 *curr_buff = cpu_to_le64(sge_addr);
2429                 curr_buff++;
2430                 msg_dma += 8;
2431                 num_prp_in_chain++;
2432
2433                 sge_addr += nvme_pg_size;
2434                 sge_len -= nvme_pg_size;
2435                 data_len -= nvme_pg_size;
2436
2437                 if (data_len <= 0)
2438                         break;
2439
2440                 if (sge_len > 0)
2441                         continue;
2442
2443                 sg_scmd = sg_next(sg_scmd);
2444                 sge_addr = sg_dma_address(sg_scmd);
2445                 sge_len = sg_dma_len(sg_scmd);
2446         }
2447
2448         main_chain_element->Length =
2449                 cpu_to_le32(num_prp_in_chain * sizeof(u64));
2450         return;
2451 }
2452
2453 static bool
2454 base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc,
2455         struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count)
2456 {
2457         u32 data_length = 0;
2458         bool build_prp = true;
2459
2460         data_length = scsi_bufflen(scmd);
2461         if (pcie_device &&
2462             (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) {
2463                 build_prp = false;
2464                 return build_prp;
2465         }
2466
2467         /* If Datalenth is <= 16K and number of SGE’s entries are <= 2
2468          * we built IEEE SGL
2469          */
2470         if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2))
2471                 build_prp = false;
2472
2473         return build_prp;
2474 }
2475
2476 /**
2477  * _base_check_pcie_native_sgl - This function is called for PCIe end devices to
2478  * determine if the driver needs to build a native SGL.  If so, that native
2479  * SGL is built in the special contiguous buffers allocated especially for
2480  * PCIe SGL creation.  If the driver will not build a native SGL, return
2481  * TRUE and a normal IEEE SGL will be built.  Currently this routine
2482  * supports NVMe.
2483  * @ioc: per adapter object
2484  * @mpi_request: mf request pointer
2485  * @smid: system request message index
2486  * @scmd: scsi command
2487  * @pcie_device: points to the PCIe device's info
2488  *
2489  * Return: 0 if native SGL was built, 1 if no SGL was built
2490  */
2491 static int
2492 _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc,
2493         Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd,
2494         struct _pcie_device *pcie_device)
2495 {
2496         int sges_left;
2497
2498         /* Get the SG list pointer and info. */
2499         sges_left = scsi_dma_map(scmd);
2500         if (sges_left < 0) {
2501                 sdev_printk(KERN_ERR, scmd->device,
2502                         "scsi_dma_map failed: request for %d bytes!\n",
2503                         scsi_bufflen(scmd));
2504                 return 1;
2505         }
2506
2507         /* Check if we need to build a native SG list. */
2508         if (base_is_prp_possible(ioc, pcie_device,
2509                                 scmd, sges_left) == 0) {
2510                 /* We built a native SG list, just return. */
2511                 goto out;
2512         }
2513
2514         /*
2515          * Build native NVMe PRP.
2516          */
2517         base_make_prp_nvme(ioc, scmd, mpi_request,
2518                         smid, sges_left);
2519
2520         return 0;
2521 out:
2522         scsi_dma_unmap(scmd);
2523         return 1;
2524 }
2525
2526 /**
2527  * _base_add_sg_single_ieee - add sg element for IEEE format
2528  * @paddr: virtual address for SGE
2529  * @flags: SGE flags
2530  * @chain_offset: number of 128 byte elements from start of segment
2531  * @length: data transfer length
2532  * @dma_addr: Physical address
2533  */
2534 static void
2535 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
2536         dma_addr_t dma_addr)
2537 {
2538         Mpi25IeeeSgeChain64_t *sgel = paddr;
2539
2540         sgel->Flags = flags;
2541         sgel->NextChainOffset = chain_offset;
2542         sgel->Length = cpu_to_le32(length);
2543         sgel->Address = cpu_to_le64(dma_addr);
2544 }
2545
2546 /**
2547  * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
2548  * @ioc: per adapter object
2549  * @paddr: virtual address for SGE
2550  *
2551  * Create a zero length scatter gather entry to insure the IOCs hardware has
2552  * something to use if the target device goes brain dead and tries
2553  * to send data even when none is asked for.
2554  */
2555 static void
2556 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
2557 {
2558         u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2559                 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2560                 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
2561
2562         _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
2563 }
2564
2565 /**
2566  * _base_build_sg_scmd - main sg creation routine
2567  *              pcie_device is unused here!
2568  * @ioc: per adapter object
2569  * @scmd: scsi command
2570  * @smid: system request message index
2571  * @unused: unused pcie_device pointer
2572  * Context: none.
2573  *
2574  * The main routine that builds scatter gather table from a given
2575  * scsi request sent via the .queuecommand main handler.
2576  *
2577  * Return: 0 success, anything else error
2578  */
2579 static int
2580 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
2581         struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused)
2582 {
2583         Mpi2SCSIIORequest_t *mpi_request;
2584         dma_addr_t chain_dma;
2585         struct scatterlist *sg_scmd;
2586         void *sg_local, *chain;
2587         u32 chain_offset;
2588         u32 chain_length;
2589         u32 chain_flags;
2590         int sges_left;
2591         u32 sges_in_segment;
2592         u32 sgl_flags;
2593         u32 sgl_flags_last_element;
2594         u32 sgl_flags_end_buffer;
2595         struct chain_tracker *chain_req;
2596
2597         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2598
2599         /* init scatter gather flags */
2600         sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
2601         if (scmd->sc_data_direction == DMA_TO_DEVICE)
2602                 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
2603         sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
2604             << MPI2_SGE_FLAGS_SHIFT;
2605         sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
2606             MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
2607             << MPI2_SGE_FLAGS_SHIFT;
2608         sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2609
2610         sg_scmd = scsi_sglist(scmd);
2611         sges_left = scsi_dma_map(scmd);
2612         if (sges_left < 0) {
2613                 sdev_printk(KERN_ERR, scmd->device,
2614                  "scsi_dma_map failed: request for %d bytes!\n",
2615                  scsi_bufflen(scmd));
2616                 return -ENOMEM;
2617         }
2618
2619         sg_local = &mpi_request->SGL;
2620         sges_in_segment = ioc->max_sges_in_main_message;
2621         if (sges_left <= sges_in_segment)
2622                 goto fill_in_last_segment;
2623
2624         mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
2625             (sges_in_segment * ioc->sge_size))/4;
2626
2627         /* fill in main message segment when there is a chain following */
2628         while (sges_in_segment) {
2629                 if (sges_in_segment == 1)
2630                         ioc->base_add_sg_single(sg_local,
2631                             sgl_flags_last_element | sg_dma_len(sg_scmd),
2632                             sg_dma_address(sg_scmd));
2633                 else
2634                         ioc->base_add_sg_single(sg_local, sgl_flags |
2635                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2636                 sg_scmd = sg_next(sg_scmd);
2637                 sg_local += ioc->sge_size;
2638                 sges_left--;
2639                 sges_in_segment--;
2640         }
2641
2642         /* initializing the chain flags and pointers */
2643         chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
2644         chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2645         if (!chain_req)
2646                 return -1;
2647         chain = chain_req->chain_buffer;
2648         chain_dma = chain_req->chain_buffer_dma;
2649         do {
2650                 sges_in_segment = (sges_left <=
2651                     ioc->max_sges_in_chain_message) ? sges_left :
2652                     ioc->max_sges_in_chain_message;
2653                 chain_offset = (sges_left == sges_in_segment) ?
2654                     0 : (sges_in_segment * ioc->sge_size)/4;
2655                 chain_length = sges_in_segment * ioc->sge_size;
2656                 if (chain_offset) {
2657                         chain_offset = chain_offset <<
2658                             MPI2_SGE_CHAIN_OFFSET_SHIFT;
2659                         chain_length += ioc->sge_size;
2660                 }
2661                 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
2662                     chain_length, chain_dma);
2663                 sg_local = chain;
2664                 if (!chain_offset)
2665                         goto fill_in_last_segment;
2666
2667                 /* fill in chain segments */
2668                 while (sges_in_segment) {
2669                         if (sges_in_segment == 1)
2670                                 ioc->base_add_sg_single(sg_local,
2671                                     sgl_flags_last_element |
2672                                     sg_dma_len(sg_scmd),
2673                                     sg_dma_address(sg_scmd));
2674                         else
2675                                 ioc->base_add_sg_single(sg_local, sgl_flags |
2676                                     sg_dma_len(sg_scmd),
2677                                     sg_dma_address(sg_scmd));
2678                         sg_scmd = sg_next(sg_scmd);
2679                         sg_local += ioc->sge_size;
2680                         sges_left--;
2681                         sges_in_segment--;
2682                 }
2683
2684                 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2685                 if (!chain_req)
2686                         return -1;
2687                 chain = chain_req->chain_buffer;
2688                 chain_dma = chain_req->chain_buffer_dma;
2689         } while (1);
2690
2691
2692  fill_in_last_segment:
2693
2694         /* fill the last segment */
2695         while (sges_left) {
2696                 if (sges_left == 1)
2697                         ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
2698                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2699                 else
2700                         ioc->base_add_sg_single(sg_local, sgl_flags |
2701                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2702                 sg_scmd = sg_next(sg_scmd);
2703                 sg_local += ioc->sge_size;
2704                 sges_left--;
2705         }
2706
2707         return 0;
2708 }
2709
2710 /**
2711  * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
2712  * @ioc: per adapter object
2713  * @scmd: scsi command
2714  * @smid: system request message index
2715  * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be
2716  * constructed on need.
2717  * Context: none.
2718  *
2719  * The main routine that builds scatter gather table from a given
2720  * scsi request sent via the .queuecommand main handler.
2721  *
2722  * Return: 0 success, anything else error
2723  */
2724 static int
2725 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
2726         struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device)
2727 {
2728         Mpi25SCSIIORequest_t *mpi_request;
2729         dma_addr_t chain_dma;
2730         struct scatterlist *sg_scmd;
2731         void *sg_local, *chain;
2732         u32 chain_offset;
2733         u32 chain_length;
2734         int sges_left;
2735         u32 sges_in_segment;
2736         u8 simple_sgl_flags;
2737         u8 simple_sgl_flags_last;
2738         u8 chain_sgl_flags;
2739         struct chain_tracker *chain_req;
2740
2741         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2742
2743         /* init scatter gather flags */
2744         simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2745             MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2746         simple_sgl_flags_last = simple_sgl_flags |
2747             MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2748         chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2749             MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2750
2751         /* Check if we need to build a native SG list. */
2752         if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request,
2753                         smid, scmd, pcie_device) == 0)) {
2754                 /* We built a native SG list, just return. */
2755                 return 0;
2756         }
2757
2758         sg_scmd = scsi_sglist(scmd);
2759         sges_left = scsi_dma_map(scmd);
2760         if (sges_left < 0) {
2761                 sdev_printk(KERN_ERR, scmd->device,
2762                         "scsi_dma_map failed: request for %d bytes!\n",
2763                         scsi_bufflen(scmd));
2764                 return -ENOMEM;
2765         }
2766
2767         sg_local = &mpi_request->SGL;
2768         sges_in_segment = (ioc->request_sz -
2769                    offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
2770         if (sges_left <= sges_in_segment)
2771                 goto fill_in_last_segment;
2772
2773         mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
2774             (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
2775
2776         /* fill in main message segment when there is a chain following */
2777         while (sges_in_segment > 1) {
2778                 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2779                     sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2780                 sg_scmd = sg_next(sg_scmd);
2781                 sg_local += ioc->sge_size_ieee;
2782                 sges_left--;
2783                 sges_in_segment--;
2784         }
2785
2786         /* initializing the pointers */
2787         chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2788         if (!chain_req)
2789                 return -1;
2790         chain = chain_req->chain_buffer;
2791         chain_dma = chain_req->chain_buffer_dma;
2792         do {
2793                 sges_in_segment = (sges_left <=
2794                     ioc->max_sges_in_chain_message) ? sges_left :
2795                     ioc->max_sges_in_chain_message;
2796                 chain_offset = (sges_left == sges_in_segment) ?
2797                     0 : sges_in_segment;
2798                 chain_length = sges_in_segment * ioc->sge_size_ieee;
2799                 if (chain_offset)
2800                         chain_length += ioc->sge_size_ieee;
2801                 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
2802                     chain_offset, chain_length, chain_dma);
2803
2804                 sg_local = chain;
2805                 if (!chain_offset)
2806                         goto fill_in_last_segment;
2807
2808                 /* fill in chain segments */
2809                 while (sges_in_segment) {
2810                         _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2811                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2812                         sg_scmd = sg_next(sg_scmd);
2813                         sg_local += ioc->sge_size_ieee;
2814                         sges_left--;
2815                         sges_in_segment--;
2816                 }
2817
2818                 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2819                 if (!chain_req)
2820                         return -1;
2821                 chain = chain_req->chain_buffer;
2822                 chain_dma = chain_req->chain_buffer_dma;
2823         } while (1);
2824
2825
2826  fill_in_last_segment:
2827
2828         /* fill the last segment */
2829         while (sges_left > 0) {
2830                 if (sges_left == 1)
2831                         _base_add_sg_single_ieee(sg_local,
2832                             simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
2833                             sg_dma_address(sg_scmd));
2834                 else
2835                         _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2836                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2837                 sg_scmd = sg_next(sg_scmd);
2838                 sg_local += ioc->sge_size_ieee;
2839                 sges_left--;
2840         }
2841
2842         return 0;
2843 }
2844
2845 /**
2846  * _base_build_sg_ieee - build generic sg for IEEE format
2847  * @ioc: per adapter object
2848  * @psge: virtual address for SGE
2849  * @data_out_dma: physical address for WRITES
2850  * @data_out_sz: data xfer size for WRITES
2851  * @data_in_dma: physical address for READS
2852  * @data_in_sz: data xfer size for READS
2853  */
2854 static void
2855 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
2856         dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2857         size_t data_in_sz)
2858 {
2859         u8 sgl_flags;
2860
2861         if (!data_out_sz && !data_in_sz) {
2862                 _base_build_zero_len_sge_ieee(ioc, psge);
2863                 return;
2864         }
2865
2866         if (data_out_sz && data_in_sz) {
2867                 /* WRITE sgel first */
2868                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2869                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2870                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2871                     data_out_dma);
2872
2873                 /* incr sgel */
2874                 psge += ioc->sge_size_ieee;
2875
2876                 /* READ sgel last */
2877                 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2878                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2879                     data_in_dma);
2880         } else if (data_out_sz) /* WRITE */ {
2881                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2882                     MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2883                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2884                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2885                     data_out_dma);
2886         } else if (data_in_sz) /* READ */ {
2887                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2888                     MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2889                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2890                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2891                     data_in_dma);
2892         }
2893 }
2894
2895 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
2896
2897 /**
2898  * _base_config_dma_addressing - set dma addressing
2899  * @ioc: per adapter object
2900  * @pdev: PCI device struct
2901  *
2902  * Return: 0 for success, non-zero for failure.
2903  */
2904 static int
2905 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
2906 {
2907         struct sysinfo s;
2908         int dma_mask;
2909
2910         if (ioc->is_mcpu_endpoint ||
2911             sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma ||
2912             dma_get_required_mask(&pdev->dev) <= 32)
2913                 dma_mask = 32;
2914         /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
2915         else if (ioc->hba_mpi_version_belonged > MPI2_VERSION)
2916                 dma_mask = 63;
2917         else
2918                 dma_mask = 64;
2919
2920         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)) ||
2921             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)))
2922                 return -ENODEV;
2923
2924         if (dma_mask > 32) {
2925                 ioc->base_add_sg_single = &_base_add_sg_single_64;
2926                 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
2927         } else {
2928                 ioc->base_add_sg_single = &_base_add_sg_single_32;
2929                 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
2930         }
2931
2932         si_meminfo(&s);
2933         ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
2934                 dma_mask, convert_to_kb(s.totalram));
2935
2936         return 0;
2937 }
2938
2939 /**
2940  * _base_check_enable_msix - checks MSIX capabable.
2941  * @ioc: per adapter object
2942  *
2943  * Check to see if card is capable of MSIX, and set number
2944  * of available msix vectors
2945  */
2946 static int
2947 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
2948 {
2949         int base;
2950         u16 message_control;
2951
2952         /* Check whether controller SAS2008 B0 controller,
2953          * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
2954          */
2955         if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
2956             ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
2957                 return -EINVAL;
2958         }
2959
2960         base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
2961         if (!base) {
2962                 dfailprintk(ioc, ioc_info(ioc, "msix not supported\n"));
2963                 return -EINVAL;
2964         }
2965
2966         /* get msix vector count */
2967         /* NUMA_IO not supported for older controllers */
2968         if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
2969             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
2970             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
2971             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
2972             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
2973             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
2974             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
2975                 ioc->msix_vector_count = 1;
2976         else {
2977                 pci_read_config_word(ioc->pdev, base + 2, &message_control);
2978                 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
2979         }
2980         dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n",
2981                                   ioc->msix_vector_count));
2982         return 0;
2983 }
2984
2985 /**
2986  * _base_free_irq - free irq
2987  * @ioc: per adapter object
2988  *
2989  * Freeing respective reply_queue from the list.
2990  */
2991 static void
2992 _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
2993 {
2994         struct adapter_reply_queue *reply_q, *next;
2995
2996         if (list_empty(&ioc->reply_queue_list))
2997                 return;
2998
2999         list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
3000                 list_del(&reply_q->list);
3001                 if (ioc->smp_affinity_enable)
3002                         irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
3003                             reply_q->msix_index), NULL);
3004                 free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
3005                          reply_q);
3006                 kfree(reply_q);
3007         }
3008 }
3009
3010 /**
3011  * _base_request_irq - request irq
3012  * @ioc: per adapter object
3013  * @index: msix index into vector table
3014  *
3015  * Inserting respective reply_queue into the list.
3016  */
3017 static int
3018 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index)
3019 {
3020         struct pci_dev *pdev = ioc->pdev;
3021         struct adapter_reply_queue *reply_q;
3022         int r;
3023
3024         reply_q =  kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
3025         if (!reply_q) {
3026                 ioc_err(ioc, "unable to allocate memory %zu!\n",
3027                         sizeof(struct adapter_reply_queue));
3028                 return -ENOMEM;
3029         }
3030         reply_q->ioc = ioc;
3031         reply_q->msix_index = index;
3032
3033         atomic_set(&reply_q->busy, 0);
3034         if (ioc->msix_enable)
3035                 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
3036                     ioc->driver_name, ioc->id, index);
3037         else
3038                 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
3039                     ioc->driver_name, ioc->id);
3040         r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
3041                         IRQF_SHARED, reply_q->name, reply_q);
3042         if (r) {
3043                 pr_err("%s: unable to allocate interrupt %d!\n",
3044                        reply_q->name, pci_irq_vector(pdev, index));
3045                 kfree(reply_q);
3046                 return -EBUSY;
3047         }
3048
3049         INIT_LIST_HEAD(&reply_q->list);
3050         list_add_tail(&reply_q->list, &ioc->reply_queue_list);
3051         return 0;
3052 }
3053
3054 /**
3055  * _base_assign_reply_queues - assigning msix index for each cpu
3056  * @ioc: per adapter object
3057  *
3058  * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
3059  *
3060  * It would nice if we could call irq_set_affinity, however it is not
3061  * an exported symbol
3062  */
3063 static void
3064 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
3065 {
3066         unsigned int cpu, nr_cpus, nr_msix, index = 0;
3067         struct adapter_reply_queue *reply_q;
3068         int local_numa_node;
3069
3070         if (!_base_is_controller_msix_enabled(ioc))
3071                 return;
3072
3073         if (ioc->msix_load_balance)
3074                 return;
3075
3076         memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
3077
3078         nr_cpus = num_online_cpus();
3079         nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
3080                                                ioc->facts.MaxMSIxVectors);
3081         if (!nr_msix)
3082                 return;
3083
3084         if (ioc->smp_affinity_enable) {
3085
3086                 /*
3087                  * set irq affinity to local numa node for those irqs
3088                  * corresponding to high iops queues.
3089                  */
3090                 if (ioc->high_iops_queues) {
3091                         local_numa_node = dev_to_node(&ioc->pdev->dev);
3092                         for (index = 0; index < ioc->high_iops_queues;
3093                             index++) {
3094                                 irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
3095                                     index), cpumask_of_node(local_numa_node));
3096                         }
3097                 }
3098
3099                 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3100                         const cpumask_t *mask;
3101
3102                         if (reply_q->msix_index < ioc->high_iops_queues)
3103                                 continue;
3104
3105                         mask = pci_irq_get_affinity(ioc->pdev,
3106                             reply_q->msix_index);
3107                         if (!mask) {
3108                                 ioc_warn(ioc, "no affinity for msi %x\n",
3109                                          reply_q->msix_index);
3110                                 goto fall_back;
3111                         }
3112
3113                         for_each_cpu_and(cpu, mask, cpu_online_mask) {
3114                                 if (cpu >= ioc->cpu_msix_table_sz)
3115                                         break;
3116                                 ioc->cpu_msix_table[cpu] = reply_q->msix_index;
3117                         }
3118                 }
3119                 return;
3120         }
3121
3122 fall_back:
3123         cpu = cpumask_first(cpu_online_mask);
3124         nr_msix -= ioc->high_iops_queues;
3125         index = 0;
3126
3127         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3128                 unsigned int i, group = nr_cpus / nr_msix;
3129
3130                 if (reply_q->msix_index < ioc->high_iops_queues)
3131                         continue;
3132
3133                 if (cpu >= nr_cpus)
3134                         break;
3135
3136                 if (index < nr_cpus % nr_msix)
3137                         group++;
3138
3139                 for (i = 0 ; i < group ; i++) {
3140                         ioc->cpu_msix_table[cpu] = reply_q->msix_index;
3141                         cpu = cpumask_next(cpu, cpu_online_mask);
3142                 }
3143                 index++;
3144         }
3145 }
3146
3147 /**
3148  * _base_check_and_enable_high_iops_queues - enable high iops mode
3149  * @ioc: per adapter object
3150  * @hba_msix_vector_count: msix vectors supported by HBA
3151  *
3152  * Enable high iops queues only if
3153  *  - HBA is a SEA/AERO controller and
3154  *  - MSI-Xs vector supported by the HBA is 128 and
3155  *  - total CPU count in the system >=16 and
3156  *  - loaded driver with default max_msix_vectors module parameter and
3157  *  - system booted in non kdump mode
3158  *
3159  * returns nothing.
3160  */
3161 static void
3162 _base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc,
3163                 int hba_msix_vector_count)
3164 {
3165         u16 lnksta, speed;
3166
3167         if (perf_mode == MPT_PERF_MODE_IOPS ||
3168             perf_mode == MPT_PERF_MODE_LATENCY) {
3169                 ioc->high_iops_queues = 0;
3170                 return;
3171         }
3172
3173         if (perf_mode == MPT_PERF_MODE_DEFAULT) {
3174
3175                 pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta);
3176                 speed = lnksta & PCI_EXP_LNKSTA_CLS;
3177
3178                 if (speed < 0x4) {
3179                         ioc->high_iops_queues = 0;
3180                         return;
3181                 }
3182         }
3183
3184         if (!reset_devices && ioc->is_aero_ioc &&
3185             hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES &&
3186             num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES &&
3187             max_msix_vectors == -1)
3188                 ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES;
3189         else
3190                 ioc->high_iops_queues = 0;
3191 }
3192
3193 /**
3194  * _base_disable_msix - disables msix
3195  * @ioc: per adapter object
3196  *
3197  */
3198 static void
3199 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
3200 {
3201         if (!ioc->msix_enable)
3202                 return;
3203         pci_free_irq_vectors(ioc->pdev);
3204         ioc->msix_enable = 0;
3205 }
3206
3207 /**
3208  * _base_alloc_irq_vectors - allocate msix vectors
3209  * @ioc: per adapter object
3210  *
3211  */
3212 static int
3213 _base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc)
3214 {
3215         int i, irq_flags = PCI_IRQ_MSIX;
3216         struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues };
3217         struct irq_affinity *descp = &desc;
3218
3219         if (ioc->smp_affinity_enable)
3220                 irq_flags |= PCI_IRQ_AFFINITY;
3221         else
3222                 descp = NULL;
3223
3224         ioc_info(ioc, " %d %d\n", ioc->high_iops_queues,
3225             ioc->reply_queue_count);
3226
3227         i = pci_alloc_irq_vectors_affinity(ioc->pdev,
3228             ioc->high_iops_queues,
3229             ioc->reply_queue_count, irq_flags, descp);
3230
3231         return i;
3232 }
3233
3234 /**
3235  * _base_enable_msix - enables msix, failback to io_apic
3236  * @ioc: per adapter object
3237  *
3238  */
3239 static int
3240 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
3241 {
3242         int r;
3243         int i, local_max_msix_vectors;
3244         u8 try_msix = 0;
3245
3246         ioc->msix_load_balance = false;
3247
3248         if (msix_disable == -1 || msix_disable == 0)
3249                 try_msix = 1;
3250
3251         if (!try_msix)
3252                 goto try_ioapic;
3253
3254         if (_base_check_enable_msix(ioc) != 0)
3255                 goto try_ioapic;
3256
3257         ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count);
3258         pr_info("\t no of cores: %d, max_msix_vectors: %d\n",
3259                 ioc->cpu_count, max_msix_vectors);
3260         if (ioc->is_aero_ioc)
3261                 _base_check_and_enable_high_iops_queues(ioc,
3262                         ioc->msix_vector_count);
3263         ioc->reply_queue_count =
3264                 min_t(int, ioc->cpu_count + ioc->high_iops_queues,
3265                 ioc->msix_vector_count);
3266
3267         if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
3268                 local_max_msix_vectors = (reset_devices) ? 1 : 8;
3269         else
3270                 local_max_msix_vectors = max_msix_vectors;
3271
3272         if (local_max_msix_vectors > 0)
3273                 ioc->reply_queue_count = min_t(int, local_max_msix_vectors,
3274                         ioc->reply_queue_count);
3275         else if (local_max_msix_vectors == 0)
3276                 goto try_ioapic;
3277
3278         /*
3279          * Enable msix_load_balance only if combined reply queue mode is
3280          * disabled on SAS3 & above generation HBA devices.
3281          */
3282         if (!ioc->combined_reply_queue &&
3283             ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3284                 ioc_info(ioc,
3285                     "combined ReplyQueue is off, Enabling msix load balance\n");
3286                 ioc->msix_load_balance = true;
3287         }
3288
3289         /*
3290          * smp affinity setting is not need when msix load balance
3291          * is enabled.
3292          */
3293         if (ioc->msix_load_balance)
3294                 ioc->smp_affinity_enable = 0;
3295
3296         r = _base_alloc_irq_vectors(ioc);
3297         if (r < 0) {
3298                 ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r);
3299                 goto try_ioapic;
3300         }
3301
3302         ioc->msix_enable = 1;
3303         ioc->reply_queue_count = r;
3304         for (i = 0; i < ioc->reply_queue_count; i++) {
3305                 r = _base_request_irq(ioc, i);
3306                 if (r) {
3307                         _base_free_irq(ioc);
3308                         _base_disable_msix(ioc);
3309                         goto try_ioapic;
3310                 }
3311         }
3312
3313         ioc_info(ioc, "High IOPs queues : %s\n",
3314                         ioc->high_iops_queues ? "enabled" : "disabled");
3315
3316         return 0;
3317
3318 /* failback to io_apic interrupt routing */
3319  try_ioapic:
3320         ioc->high_iops_queues = 0;
3321         ioc_info(ioc, "High IOPs queues : disabled\n");
3322         ioc->reply_queue_count = 1;
3323         r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
3324         if (r < 0) {
3325                 dfailprintk(ioc,
3326                             ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
3327                                      r));
3328         } else
3329                 r = _base_request_irq(ioc, 0);
3330
3331         return r;
3332 }
3333
3334 /**
3335  * mpt3sas_base_unmap_resources - free controller resources
3336  * @ioc: per adapter object
3337  */
3338 static void
3339 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
3340 {
3341         struct pci_dev *pdev = ioc->pdev;
3342
3343         dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3344
3345         _base_free_irq(ioc);
3346         _base_disable_msix(ioc);
3347
3348         kfree(ioc->replyPostRegisterIndex);
3349         ioc->replyPostRegisterIndex = NULL;
3350
3351
3352         if (ioc->chip_phys) {
3353                 iounmap(ioc->chip);
3354                 ioc->chip_phys = 0;
3355         }
3356
3357         if (pci_is_enabled(pdev)) {
3358                 pci_release_selected_regions(ioc->pdev, ioc->bars);
3359                 pci_disable_pcie_error_reporting(pdev);
3360                 pci_disable_device(pdev);
3361         }
3362 }
3363
3364 static int
3365 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
3366
3367 /**
3368  * _base_check_for_fault_and_issue_reset - check if IOC is in fault state
3369  *     and if it is in fault state then issue diag reset.
3370  * @ioc: per adapter object
3371  *
3372  * Returns: 0 for success, non-zero for failure.
3373  */
3374 static int
3375 _base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc)
3376 {
3377         u32 ioc_state;
3378         int rc = -EFAULT;
3379
3380         dinitprintk(ioc, pr_info("%s\n", __func__));
3381         if (ioc->pci_error_recovery)
3382                 return 0;
3383         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
3384         dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state));
3385
3386         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
3387                 mpt3sas_print_fault_code(ioc, ioc_state &
3388                     MPI2_DOORBELL_DATA_MASK);
3389                 rc = _base_diag_reset(ioc);
3390         } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
3391             MPI2_IOC_STATE_COREDUMP) {
3392                 mpt3sas_print_coredump_info(ioc, ioc_state &
3393                      MPI2_DOORBELL_DATA_MASK);
3394                 mpt3sas_base_wait_for_coredump_completion(ioc, __func__);
3395                 rc = _base_diag_reset(ioc);
3396         }
3397
3398         return rc;
3399 }
3400
3401 /**
3402  * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
3403  * @ioc: per adapter object
3404  *
3405  * Return: 0 for success, non-zero for failure.
3406  */
3407 int
3408 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
3409 {
3410         struct pci_dev *pdev = ioc->pdev;
3411         u32 memap_sz;
3412         u32 pio_sz;
3413         int i, r = 0, rc;
3414         u64 pio_chip = 0;
3415         phys_addr_t chip_phys = 0;
3416         struct adapter_reply_queue *reply_q;
3417
3418         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3419
3420         ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3421         if (pci_enable_device_mem(pdev)) {
3422                 ioc_warn(ioc, "pci_enable_device_mem: failed\n");
3423                 ioc->bars = 0;
3424                 return -ENODEV;
3425         }
3426
3427
3428         if (pci_request_selected_regions(pdev, ioc->bars,
3429             ioc->driver_name)) {
3430                 ioc_warn(ioc, "pci_request_selected_regions: failed\n");
3431                 ioc->bars = 0;
3432                 r = -ENODEV;
3433                 goto out_fail;
3434         }
3435
3436 /* AER (Advanced Error Reporting) hooks */
3437         pci_enable_pcie_error_reporting(pdev);
3438
3439         pci_set_master(pdev);
3440
3441
3442         if (_base_config_dma_addressing(ioc, pdev) != 0) {
3443                 ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev));
3444                 r = -ENODEV;
3445                 goto out_fail;
3446         }
3447
3448         for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
3449              (!memap_sz || !pio_sz); i++) {
3450                 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
3451                         if (pio_sz)
3452                                 continue;
3453                         pio_chip = (u64)pci_resource_start(pdev, i);
3454                         pio_sz = pci_resource_len(pdev, i);
3455                 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3456                         if (memap_sz)
3457                                 continue;
3458                         ioc->chip_phys = pci_resource_start(pdev, i);
3459                         chip_phys = ioc->chip_phys;
3460                         memap_sz = pci_resource_len(pdev, i);
3461                         ioc->chip = ioremap(ioc->chip_phys, memap_sz);
3462                 }
3463         }
3464
3465         if (ioc->chip == NULL) {
3466                 ioc_err(ioc,
3467                     "unable to map adapter memory! or resource not found\n");
3468                 r = -EINVAL;
3469                 goto out_fail;
3470         }
3471
3472         mpt3sas_base_mask_interrupts(ioc);
3473
3474         r = _base_get_ioc_facts(ioc);
3475         if (r) {
3476                 rc = _base_check_for_fault_and_issue_reset(ioc);
3477                 if (rc || (_base_get_ioc_facts(ioc)))
3478                         goto out_fail;
3479         }
3480
3481         if (!ioc->rdpq_array_enable_assigned) {
3482                 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
3483                 ioc->rdpq_array_enable_assigned = 1;
3484         }
3485
3486         r = _base_enable_msix(ioc);
3487         if (r)
3488                 goto out_fail;
3489
3490         if (!ioc->is_driver_loading)
3491                 _base_init_irqpolls(ioc);
3492         /* Use the Combined reply queue feature only for SAS3 C0 & higher
3493          * revision HBAs and also only when reply queue count is greater than 8
3494          */
3495         if (ioc->combined_reply_queue) {
3496                 /* Determine the Supplemental Reply Post Host Index Registers
3497                  * Addresse. Supplemental Reply Post Host Index Registers
3498                  * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
3499                  * each register is at offset bytes of
3500                  * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
3501                  */
3502                 ioc->replyPostRegisterIndex = kcalloc(
3503                      ioc->combined_reply_index_count,
3504                      sizeof(resource_size_t *), GFP_KERNEL);
3505                 if (!ioc->replyPostRegisterIndex) {
3506                         ioc_err(ioc,
3507                             "allocation for replyPostRegisterIndex failed!\n");
3508                         r = -ENOMEM;
3509                         goto out_fail;
3510                 }
3511
3512                 for (i = 0; i < ioc->combined_reply_index_count; i++) {
3513                         ioc->replyPostRegisterIndex[i] = (resource_size_t *)
3514                              ((u8 __force *)&ioc->chip->Doorbell +
3515                              MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
3516                              (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
3517                 }
3518         }
3519
3520         if (ioc->is_warpdrive) {
3521                 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
3522                     &ioc->chip->ReplyPostHostIndex;
3523
3524                 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
3525                         ioc->reply_post_host_index[i] =
3526                         (resource_size_t __iomem *)
3527                         ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
3528                         * 4)));
3529         }
3530
3531         list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
3532                 pr_info("%s: %s enabled: IRQ %d\n",
3533                         reply_q->name,
3534                         ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC",
3535                         pci_irq_vector(ioc->pdev, reply_q->msix_index));
3536
3537         ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n",
3538                  &chip_phys, ioc->chip, memap_sz);
3539         ioc_info(ioc, "ioport(0x%016llx), size(%d)\n",
3540                  (unsigned long long)pio_chip, pio_sz);
3541
3542         /* Save PCI configuration state for recovery from PCI AER/EEH errors */
3543         pci_save_state(pdev);
3544         return 0;
3545
3546  out_fail:
3547         mpt3sas_base_unmap_resources(ioc);
3548         return r;
3549 }
3550
3551 /**
3552  * mpt3sas_base_get_msg_frame - obtain request mf pointer
3553  * @ioc: per adapter object
3554  * @smid: system request message index(smid zero is invalid)
3555  *
3556  * Return: virt pointer to message frame.
3557  */
3558 void *
3559 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3560 {
3561         return (void *)(ioc->request + (smid * ioc->request_sz));
3562 }
3563
3564 /**
3565  * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
3566  * @ioc: per adapter object
3567  * @smid: system request message index
3568  *
3569  * Return: virt pointer to sense buffer.
3570  */
3571 void *
3572 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3573 {
3574         return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
3575 }
3576
3577 /**
3578  * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
3579  * @ioc: per adapter object
3580  * @smid: system request message index
3581  *
3582  * Return: phys pointer to the low 32bit address of the sense buffer.
3583  */
3584 __le32
3585 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3586 {
3587         return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
3588             SCSI_SENSE_BUFFERSIZE));
3589 }
3590
3591 /**
3592  * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr
3593  * @ioc: per adapter object
3594  * @smid: system request message index
3595  *
3596  * Return: virt pointer to a PCIe SGL.
3597  */
3598 void *
3599 mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3600 {
3601         return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl);
3602 }
3603
3604 /**
3605  * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr
3606  * @ioc: per adapter object
3607  * @smid: system request message index
3608  *
3609  * Return: phys pointer to the address of the PCIe buffer.
3610  */
3611 dma_addr_t
3612 mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3613 {
3614         return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma;
3615 }
3616
3617 /**
3618  * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
3619  * @ioc: per adapter object
3620  * @phys_addr: lower 32 physical addr of the reply
3621  *
3622  * Converts 32bit lower physical addr into a virt address.
3623  */
3624 void *
3625 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
3626 {
3627         if (!phys_addr)
3628                 return NULL;
3629         return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
3630 }
3631
3632 /**
3633  * _base_get_msix_index - get the msix index
3634  * @ioc: per adapter object
3635  * @scmd: scsi_cmnd object
3636  *
3637  * returns msix index of general reply queues,
3638  * i.e. reply queue on which IO request's reply
3639  * should be posted by the HBA firmware.
3640  */
3641 static inline u8
3642 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc,
3643         struct scsi_cmnd *scmd)
3644 {
3645         /* Enables reply_queue load balancing */
3646         if (ioc->msix_load_balance)
3647                 return ioc->reply_queue_count ?
3648                     base_mod64(atomic64_add_return(1,
3649                     &ioc->total_io_cnt), ioc->reply_queue_count) : 0;
3650
3651         return ioc->cpu_msix_table[raw_smp_processor_id()];
3652 }
3653
3654 /**
3655  * _base_sdev_nr_inflight_request -get number of inflight requests
3656  *                                 of a request queue.
3657  * @q: request_queue object
3658  *
3659  * returns number of inflight request of a request queue.
3660  */
3661 inline unsigned long
3662 _base_sdev_nr_inflight_request(struct request_queue *q)
3663 {
3664         struct blk_mq_hw_ctx *hctx = q->queue_hw_ctx[0];
3665
3666         return atomic_read(&hctx->nr_active);
3667 }
3668
3669
3670 /**
3671  * _base_get_high_iops_msix_index - get the msix index of
3672  *                              high iops queues
3673  * @ioc: per adapter object
3674  * @scmd: scsi_cmnd object
3675  *
3676  * Returns: msix index of high iops reply queues.
3677  * i.e. high iops reply queue on which IO request's
3678  * reply should be posted by the HBA firmware.
3679  */
3680 static inline u8
3681 _base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc,
3682         struct scsi_cmnd *scmd)
3683 {
3684         /**
3685          * Round robin the IO interrupts among the high iops
3686          * reply queues in terms of batch count 16 when outstanding
3687          * IOs on the target device is >=8.
3688          */
3689         if (_base_sdev_nr_inflight_request(scmd->device->request_queue) >
3690             MPT3SAS_DEVICE_HIGH_IOPS_DEPTH)
3691                 return base_mod64((
3692                     atomic64_add_return(1, &ioc->high_iops_outstanding) /
3693                     MPT3SAS_HIGH_IOPS_BATCH_COUNT),
3694                     MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
3695
3696         return _base_get_msix_index(ioc, scmd);
3697 }
3698
3699 /**
3700  * mpt3sas_base_get_smid - obtain a free smid from internal queue
3701  * @ioc: per adapter object
3702  * @cb_idx: callback index
3703  *
3704  * Return: smid (zero is invalid)
3705  */
3706 u16
3707 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3708 {
3709         unsigned long flags;
3710         struct request_tracker *request;
3711         u16 smid;
3712
3713         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3714         if (list_empty(&ioc->internal_free_list)) {
3715                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3716                 ioc_err(ioc, "%s: smid not available\n", __func__);
3717                 return 0;
3718         }
3719
3720         request = list_entry(ioc->internal_free_list.next,
3721             struct request_tracker, tracker_list);
3722         request->cb_idx = cb_idx;
3723         smid = request->smid;
3724         list_del(&request->tracker_list);
3725         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3726         return smid;
3727 }
3728
3729 /**
3730  * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
3731  * @ioc: per adapter object
3732  * @cb_idx: callback index
3733  * @scmd: pointer to scsi command object
3734  *
3735  * Return: smid (zero is invalid)
3736  */
3737 u16
3738 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
3739         struct scsi_cmnd *scmd)
3740 {
3741         struct scsiio_tracker *request = scsi_cmd_priv(scmd);
3742         unsigned int tag = scmd->request->tag;
3743         u16 smid;
3744
3745         smid = tag + 1;
3746         request->cb_idx = cb_idx;
3747         request->smid = smid;
3748         request->scmd = scmd;
3749         INIT_LIST_HEAD(&request->chain_list);
3750         return smid;
3751 }
3752
3753 /**
3754  * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
3755  * @ioc: per adapter object
3756  * @cb_idx: callback index
3757  *
3758  * Return: smid (zero is invalid)
3759  */
3760 u16
3761 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3762 {
3763         unsigned long flags;
3764         struct request_tracker *request;
3765         u16 smid;
3766
3767         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3768         if (list_empty(&ioc->hpr_free_list)) {
3769                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3770                 return 0;
3771         }
3772
3773         request = list_entry(ioc->hpr_free_list.next,
3774             struct request_tracker, tracker_list);
3775         request->cb_idx = cb_idx;
3776         smid = request->smid;
3777         list_del(&request->tracker_list);
3778         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3779         return smid;
3780 }
3781
3782 static void
3783 _base_recovery_check(struct MPT3SAS_ADAPTER *ioc)
3784 {
3785         /*
3786          * See _wait_for_commands_to_complete() call with regards to this code.
3787          */
3788         if (ioc->shost_recovery && ioc->pending_io_count) {
3789                 ioc->pending_io_count = scsi_host_busy(ioc->shost);
3790                 if (ioc->pending_io_count == 0)
3791                         wake_up(&ioc->reset_wq);
3792         }
3793 }
3794
3795 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc,
3796                            struct scsiio_tracker *st)
3797 {
3798         if (WARN_ON(st->smid == 0))
3799                 return;
3800         st->cb_idx = 0xFF;
3801         st->direct_io = 0;
3802         st->scmd = NULL;
3803         atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0);
3804         st->smid = 0;
3805 }
3806
3807 /**
3808  * mpt3sas_base_free_smid - put smid back on free_list
3809  * @ioc: per adapter object
3810  * @smid: system request message index
3811  */
3812 void
3813 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3814 {
3815         unsigned long flags;
3816         int i;
3817
3818         if (smid < ioc->hi_priority_smid) {
3819                 struct scsiio_tracker *st;
3820                 void *request;
3821
3822                 st = _get_st_from_smid(ioc, smid);
3823                 if (!st) {
3824                         _base_recovery_check(ioc);
3825                         return;
3826                 }
3827
3828                 /* Clear MPI request frame */
3829                 request = mpt3sas_base_get_msg_frame(ioc, smid);
3830                 memset(request, 0, ioc->request_sz);
3831
3832                 mpt3sas_base_clear_st(ioc, st);
3833                 _base_recovery_check(ioc);
3834                 return;
3835         }
3836
3837         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3838         if (smid < ioc->internal_smid) {
3839                 /* hi-priority */
3840                 i = smid - ioc->hi_priority_smid;
3841                 ioc->hpr_lookup[i].cb_idx = 0xFF;
3842                 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
3843         } else if (smid <= ioc->hba_queue_depth) {
3844                 /* internal queue */
3845                 i = smid - ioc->internal_smid;
3846                 ioc->internal_lookup[i].cb_idx = 0xFF;
3847                 list_add(&ioc->internal_lookup[i].tracker_list,
3848                     &ioc->internal_free_list);
3849         }
3850         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3851 }
3852
3853 /**
3854  * _base_mpi_ep_writeq - 32 bit write to MMIO
3855  * @b: data payload
3856  * @addr: address in MMIO space
3857  * @writeq_lock: spin lock
3858  *
3859  * This special handling for MPI EP to take care of 32 bit
3860  * environment where its not quarenteed to send the entire word
3861  * in one transfer.
3862  */
3863 static inline void
3864 _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr,
3865                                         spinlock_t *writeq_lock)
3866 {
3867         unsigned long flags;
3868
3869         spin_lock_irqsave(writeq_lock, flags);
3870         __raw_writel((u32)(b), addr);
3871         __raw_writel((u32)(b >> 32), (addr + 4));
3872         spin_unlock_irqrestore(writeq_lock, flags);
3873 }
3874
3875 /**
3876  * _base_writeq - 64 bit write to MMIO
3877  * @b: data payload
3878  * @addr: address in MMIO space
3879  * @writeq_lock: spin lock
3880  *
3881  * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
3882  * care of 32 bit environment where its not quarenteed to send the entire word
3883  * in one transfer.
3884  */
3885 #if defined(writeq) && defined(CONFIG_64BIT)
3886 static inline void
3887 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
3888 {
3889         wmb();
3890         __raw_writeq(b, addr);
3891         barrier();
3892 }
3893 #else
3894 static inline void
3895 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
3896 {
3897         _base_mpi_ep_writeq(b, addr, writeq_lock);
3898 }
3899 #endif
3900
3901 /**
3902  * _base_set_and_get_msix_index - get the msix index and assign to msix_io
3903  *                                variable of scsi tracker
3904  * @ioc: per adapter object
3905  * @smid: system request message index
3906  *
3907  * returns msix index.
3908  */
3909 static u8
3910 _base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3911 {
3912         struct scsiio_tracker *st = NULL;
3913
3914         if (smid < ioc->hi_priority_smid)
3915                 st = _get_st_from_smid(ioc, smid);
3916
3917         if (st == NULL)
3918                 return  _base_get_msix_index(ioc, NULL);
3919
3920         st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd);
3921         return st->msix_io;
3922 }
3923
3924 /**
3925  * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware
3926  * @ioc: per adapter object
3927  * @smid: system request message index
3928  * @handle: device handle
3929  */
3930 static void
3931 _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc,
3932         u16 smid, u16 handle)
3933 {
3934         Mpi2RequestDescriptorUnion_t descriptor;
3935         u64 *request = (u64 *)&descriptor;
3936         void *mpi_req_iomem;
3937         __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
3938
3939         _clone_sg_entries(ioc, (void *) mfp, smid);
3940         mpi_req_iomem = (void __force *)ioc->chip +
3941                         MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
3942         _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
3943                                         ioc->request_sz);
3944         descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3945         descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3946         descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3947         descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3948         descriptor.SCSIIO.LMID = 0;
3949         _base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3950             &ioc->scsi_lookup_lock);
3951 }
3952
3953 /**
3954  * _base_put_smid_scsi_io - send SCSI_IO request to firmware
3955  * @ioc: per adapter object
3956  * @smid: system request message index
3957  * @handle: device handle
3958  */
3959 static void
3960 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
3961 {
3962         Mpi2RequestDescriptorUnion_t descriptor;
3963         u64 *request = (u64 *)&descriptor;
3964
3965
3966         descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3967         descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3968         descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3969         descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3970         descriptor.SCSIIO.LMID = 0;
3971         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3972             &ioc->scsi_lookup_lock);
3973 }
3974
3975 /**
3976  * _base_put_smid_fast_path - send fast path request to firmware
3977  * @ioc: per adapter object
3978  * @smid: system request message index
3979  * @handle: device handle
3980  */
3981 static void
3982 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3983         u16 handle)
3984 {
3985         Mpi2RequestDescriptorUnion_t descriptor;
3986         u64 *request = (u64 *)&descriptor;
3987
3988         descriptor.SCSIIO.RequestFlags =
3989             MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
3990         descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3991         descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3992         descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3993         descriptor.SCSIIO.LMID = 0;
3994         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3995             &ioc->scsi_lookup_lock);
3996 }
3997
3998 /**
3999  * _base_put_smid_hi_priority - send Task Management request to firmware
4000  * @ioc: per adapter object
4001  * @smid: system request message index
4002  * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
4003  */
4004 static void
4005 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4006         u16 msix_task)
4007 {
4008         Mpi2RequestDescriptorUnion_t descriptor;
4009         void *mpi_req_iomem;
4010         u64 *request;
4011
4012         if (ioc->is_mcpu_endpoint) {
4013                 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4014
4015                 /* TBD 256 is offset within sys register. */
4016                 mpi_req_iomem = (void __force *)ioc->chip
4017                                         + MPI_FRAME_START_OFFSET
4018                                         + (smid * ioc->request_sz);
4019                 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4020                                                         ioc->request_sz);
4021         }
4022
4023         request = (u64 *)&descriptor;
4024
4025         descriptor.HighPriority.RequestFlags =
4026             MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
4027         descriptor.HighPriority.MSIxIndex =  msix_task;
4028         descriptor.HighPriority.SMID = cpu_to_le16(smid);
4029         descriptor.HighPriority.LMID = 0;
4030         descriptor.HighPriority.Reserved1 = 0;
4031         if (ioc->is_mcpu_endpoint)
4032                 _base_mpi_ep_writeq(*request,
4033                                 &ioc->chip->RequestDescriptorPostLow,
4034                                 &ioc->scsi_lookup_lock);
4035         else
4036                 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4037                     &ioc->scsi_lookup_lock);
4038 }
4039
4040 /**
4041  * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to
4042  *  firmware
4043  * @ioc: per adapter object
4044  * @smid: system request message index
4045  */
4046 void
4047 mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4048 {
4049         Mpi2RequestDescriptorUnion_t descriptor;
4050         u64 *request = (u64 *)&descriptor;
4051
4052         descriptor.Default.RequestFlags =
4053                 MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
4054         descriptor.Default.MSIxIndex =  _base_set_and_get_msix_index(ioc, smid);
4055         descriptor.Default.SMID = cpu_to_le16(smid);
4056         descriptor.Default.LMID = 0;
4057         descriptor.Default.DescriptorTypeDependent = 0;
4058         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4059             &ioc->scsi_lookup_lock);
4060 }
4061
4062 /**
4063  * _base_put_smid_default - Default, primarily used for config pages
4064  * @ioc: per adapter object
4065  * @smid: system request message index
4066  */
4067 static void
4068 _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4069 {
4070         Mpi2RequestDescriptorUnion_t descriptor;
4071         void *mpi_req_iomem;
4072         u64 *request;
4073
4074         if (ioc->is_mcpu_endpoint) {
4075                 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4076
4077                 _clone_sg_entries(ioc, (void *) mfp, smid);
4078                 /* TBD 256 is offset within sys register */
4079                 mpi_req_iomem = (void __force *)ioc->chip +
4080                         MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
4081                 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4082                                                         ioc->request_sz);
4083         }
4084         request = (u64 *)&descriptor;
4085         descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
4086         descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4087         descriptor.Default.SMID = cpu_to_le16(smid);
4088         descriptor.Default.LMID = 0;
4089         descriptor.Default.DescriptorTypeDependent = 0;
4090         if (ioc->is_mcpu_endpoint)
4091                 _base_mpi_ep_writeq(*request,
4092                                 &ioc->chip->RequestDescriptorPostLow,
4093                                 &ioc->scsi_lookup_lock);
4094         else
4095                 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4096                                 &ioc->scsi_lookup_lock);
4097 }
4098
4099 /**
4100  * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
4101  *   Atomic Request Descriptor
4102  * @ioc: per adapter object
4103  * @smid: system request message index
4104  * @handle: device handle, unused in this function, for function type match
4105  *
4106  * Return nothing.
4107  */
4108 static void
4109 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4110         u16 handle)
4111 {
4112         Mpi26AtomicRequestDescriptor_t descriptor;
4113         u32 *request = (u32 *)&descriptor;
4114
4115         descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4116         descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4117         descriptor.SMID = cpu_to_le16(smid);
4118
4119         writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4120 }
4121
4122 /**
4123  * _base_put_smid_fast_path_atomic - send fast path request to firmware
4124  * using Atomic Request Descriptor
4125  * @ioc: per adapter object
4126  * @smid: system request message index
4127  * @handle: device handle, unused in this function, for function type match
4128  * Return nothing
4129  */
4130 static void
4131 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4132         u16 handle)
4133 {
4134         Mpi26AtomicRequestDescriptor_t descriptor;
4135         u32 *request = (u32 *)&descriptor;
4136
4137         descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
4138         descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4139         descriptor.SMID = cpu_to_le16(smid);
4140
4141         writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4142 }
4143
4144 /**
4145  * _base_put_smid_hi_priority_atomic - send Task Management request to
4146  * firmware using Atomic Request Descriptor
4147  * @ioc: per adapter object
4148  * @smid: system request message index
4149  * @msix_task: msix_task will be same as msix of IO incase of task abort else 0
4150  *
4151  * Return nothing.
4152  */
4153 static void
4154 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4155         u16 msix_task)
4156 {
4157         Mpi26AtomicRequestDescriptor_t descriptor;
4158         u32 *request = (u32 *)&descriptor;
4159
4160         descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
4161         descriptor.MSIxIndex = msix_task;
4162         descriptor.SMID = cpu_to_le16(smid);
4163
4164         writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4165 }
4166
4167 /**
4168  * _base_put_smid_default - Default, primarily used for config pages
4169  * use Atomic Request Descriptor
4170  * @ioc: per adapter object
4171  * @smid: system request message index
4172  *
4173  * Return nothing.
4174  */
4175 static void
4176 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4177 {
4178         Mpi26AtomicRequestDescriptor_t descriptor;
4179         u32 *request = (u32 *)&descriptor;
4180
4181         descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
4182         descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4183         descriptor.SMID = cpu_to_le16(smid);
4184
4185         writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4186 }
4187
4188 /**
4189  * _base_display_OEMs_branding - Display branding string
4190  * @ioc: per adapter object
4191  */
4192 static void
4193 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
4194 {
4195         if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
4196                 return;
4197
4198         switch (ioc->pdev->subsystem_vendor) {
4199         case PCI_VENDOR_ID_INTEL:
4200                 switch (ioc->pdev->device) {
4201                 case MPI2_MFGPAGE_DEVID_SAS2008:
4202                         switch (ioc->pdev->subsystem_device) {
4203                         case MPT2SAS_INTEL_RMS2LL080_SSDID:
4204                                 ioc_info(ioc, "%s\n",
4205                                          MPT2SAS_INTEL_RMS2LL080_BRANDING);
4206                                 break;
4207                         case MPT2SAS_INTEL_RMS2LL040_SSDID:
4208                                 ioc_info(ioc, "%s\n",
4209                                          MPT2SAS_INTEL_RMS2LL040_BRANDING);
4210                                 break;
4211                         case MPT2SAS_INTEL_SSD910_SSDID:
4212                                 ioc_info(ioc, "%s\n",
4213                                          MPT2SAS_INTEL_SSD910_BRANDING);
4214                                 break;
4215                         default:
4216                                 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4217                                          ioc->pdev->subsystem_device);
4218                                 break;
4219                         }
4220                         break;
4221                 case MPI2_MFGPAGE_DEVID_SAS2308_2:
4222                         switch (ioc->pdev->subsystem_device) {
4223                         case MPT2SAS_INTEL_RS25GB008_SSDID:
4224                                 ioc_info(ioc, "%s\n",
4225                                          MPT2SAS_INTEL_RS25GB008_BRANDING);
4226                                 break;
4227                         case MPT2SAS_INTEL_RMS25JB080_SSDID:
4228                                 ioc_info(ioc, "%s\n",
4229                                          MPT2SAS_INTEL_RMS25JB080_BRANDING);
4230                                 break;
4231                         case MPT2SAS_INTEL_RMS25JB040_SSDID:
4232                                 ioc_info(ioc, "%s\n",
4233                                          MPT2SAS_INTEL_RMS25JB040_BRANDING);
4234                                 break;
4235                         case MPT2SAS_INTEL_RMS25KB080_SSDID:
4236                                 ioc_info(ioc, "%s\n",
4237                                          MPT2SAS_INTEL_RMS25KB080_BRANDING);
4238                                 break;
4239                         case MPT2SAS_INTEL_RMS25KB040_SSDID:
4240                                 ioc_info(ioc, "%s\n",
4241                                          MPT2SAS_INTEL_RMS25KB040_BRANDING);
4242                                 break;
4243                         case MPT2SAS_INTEL_RMS25LB040_SSDID:
4244                                 ioc_info(ioc, "%s\n",
4245                                          MPT2SAS_INTEL_RMS25LB040_BRANDING);
4246                                 break;
4247                         case MPT2SAS_INTEL_RMS25LB080_SSDID:
4248                                 ioc_info(ioc, "%s\n",
4249                                          MPT2SAS_INTEL_RMS25LB080_BRANDING);
4250                                 break;
4251                         default:
4252                                 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4253                                          ioc->pdev->subsystem_device);
4254                                 break;
4255                         }
4256                         break;
4257                 case MPI25_MFGPAGE_DEVID_SAS3008:
4258                         switch (ioc->pdev->subsystem_device) {
4259                         case MPT3SAS_INTEL_RMS3JC080_SSDID:
4260                                 ioc_info(ioc, "%s\n",
4261                                          MPT3SAS_INTEL_RMS3JC080_BRANDING);
4262                                 break;
4263
4264                         case MPT3SAS_INTEL_RS3GC008_SSDID:
4265                                 ioc_info(ioc, "%s\n",
4266                                          MPT3SAS_INTEL_RS3GC008_BRANDING);
4267                                 break;
4268                         case MPT3SAS_INTEL_RS3FC044_SSDID:
4269                                 ioc_info(ioc, "%s\n",
4270                                          MPT3SAS_INTEL_RS3FC044_BRANDING);
4271                                 break;
4272                         case MPT3SAS_INTEL_RS3UC080_SSDID:
4273                                 ioc_info(ioc, "%s\n",
4274                                          MPT3SAS_INTEL_RS3UC080_BRANDING);
4275                                 break;
4276                         default:
4277                                 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4278                                          ioc->pdev->subsystem_device);
4279                                 break;
4280                         }
4281                         break;
4282                 default:
4283                         ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4284                                  ioc->pdev->subsystem_device);
4285                         break;
4286                 }
4287                 break;
4288         case PCI_VENDOR_ID_DELL:
4289                 switch (ioc->pdev->device) {
4290                 case MPI2_MFGPAGE_DEVID_SAS2008:
4291                         switch (ioc->pdev->subsystem_device) {
4292                         case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
4293                                 ioc_info(ioc, "%s\n",
4294                                          MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
4295                                 break;
4296                         case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
4297                                 ioc_info(ioc, "%s\n",
4298                                          MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
4299                                 break;
4300                         case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
4301                                 ioc_info(ioc, "%s\n",
4302                                          MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
4303                                 break;
4304                         case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
4305                                 ioc_info(ioc, "%s\n",
4306                                          MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
4307                                 break;
4308                         case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
4309                                 ioc_info(ioc, "%s\n",
4310                                          MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
4311                                 break;
4312                         case MPT2SAS_DELL_PERC_H200_SSDID:
4313                                 ioc_info(ioc, "%s\n",
4314                                          MPT2SAS_DELL_PERC_H200_BRANDING);
4315                                 break;
4316                         case MPT2SAS_DELL_6GBPS_SAS_SSDID:
4317                                 ioc_info(ioc, "%s\n",
4318                                          MPT2SAS_DELL_6GBPS_SAS_BRANDING);
4319                                 break;
4320                         default:
4321                                 ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
4322                                          ioc->pdev->subsystem_device);
4323                                 break;
4324                         }
4325                         break;
4326                 case MPI25_MFGPAGE_DEVID_SAS3008:
4327                         switch (ioc->pdev->subsystem_device) {
4328                         case MPT3SAS_DELL_12G_HBA_SSDID:
4329                                 ioc_info(ioc, "%s\n",
4330                                          MPT3SAS_DELL_12G_HBA_BRANDING);
4331                                 break;
4332                         default:
4333                                 ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
4334                                          ioc->pdev->subsystem_device);
4335                                 break;
4336                         }
4337                         break;
4338                 default:
4339                         ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n",
4340                                  ioc->pdev->subsystem_device);
4341                         break;
4342                 }
4343                 break;
4344         case PCI_VENDOR_ID_CISCO:
4345                 switch (ioc->pdev->device) {
4346                 case MPI25_MFGPAGE_DEVID_SAS3008:
4347                         switch (ioc->pdev->subsystem_device) {
4348                         case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
4349                                 ioc_info(ioc, "%s\n",
4350                                          MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
4351                                 break;
4352                         case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
4353                                 ioc_info(ioc, "%s\n",
4354                                          MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
4355                                 break;
4356                         case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
4357                                 ioc_info(ioc, "%s\n",
4358                                          MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
4359                                 break;
4360                         default:
4361                                 ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
4362                                          ioc->pdev->subsystem_device);
4363                                 break;
4364                         }
4365                         break;
4366                 case MPI25_MFGPAGE_DEVID_SAS3108_1:
4367                         switch (ioc->pdev->subsystem_device) {
4368                         case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
4369                                 ioc_info(ioc, "%s\n",
4370                                          MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
4371                                 break;
4372                         case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
4373                                 ioc_info(ioc, "%s\n",
4374                                          MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING);
4375                                 break;
4376                         default:
4377                                 ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
4378                                          ioc->pdev->subsystem_device);
4379                                 break;
4380                         }
4381                         break;
4382                 default:
4383                         ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n",
4384                                  ioc->pdev->subsystem_device);
4385                         break;
4386                 }
4387                 break;
4388         case MPT2SAS_HP_3PAR_SSVID:
4389                 switch (ioc->pdev->device) {
4390                 case MPI2_MFGPAGE_DEVID_SAS2004:
4391                         switch (ioc->pdev->subsystem_device) {
4392                         case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
4393                                 ioc_info(ioc, "%s\n",
4394                                          MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
4395                                 break;
4396                         default:
4397                                 ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
4398                                          ioc->pdev->subsystem_device);
4399                                 break;
4400                         }
4401                         break;
4402                 case MPI2_MFGPAGE_DEVID_SAS2308_2:
4403                         switch (ioc->pdev->subsystem_device) {
4404                         case MPT2SAS_HP_2_4_INTERNAL_SSDID:
4405                                 ioc_info(ioc, "%s\n",
4406                                          MPT2SAS_HP_2_4_INTERNAL_BRANDING);
4407                                 break;
4408                         case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
4409                                 ioc_info(ioc, "%s\n",
4410                                          MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
4411                                 break;
4412                         case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
4413                                 ioc_info(ioc, "%s\n",
4414                                          MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
4415                                 break;
4416                         case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
4417                                 ioc_info(ioc, "%s\n",
4418                                          MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
4419                                 break;
4420                         default:
4421                                 ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
4422                                          ioc->pdev->subsystem_device);
4423                                 break;
4424                         }
4425                         break;
4426                 default:
4427                         ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n",
4428                                  ioc->pdev->subsystem_device);
4429                         break;
4430                 }
4431         default:
4432                 break;
4433         }
4434 }
4435
4436 /**
4437  * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg
4438  *                              version from FW Image Header.
4439  * @ioc: per adapter object
4440  *
4441  * Return: 0 for success, non-zero for failure.
4442  */
4443         static int
4444 _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc)
4445 {
4446         Mpi2FWImageHeader_t *fw_img_hdr;
4447         Mpi26ComponentImageHeader_t *cmp_img_hdr;
4448         Mpi25FWUploadRequest_t *mpi_request;
4449         Mpi2FWUploadReply_t mpi_reply;
4450         int r = 0;
4451         u32  package_version = 0;
4452         void *fwpkg_data = NULL;
4453         dma_addr_t fwpkg_data_dma;
4454         u16 smid, ioc_status;
4455         size_t data_length;
4456
4457         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
4458
4459         if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4460                 ioc_err(ioc, "%s: internal command already in use\n", __func__);
4461                 return -EAGAIN;
4462         }
4463
4464         data_length = sizeof(Mpi2FWImageHeader_t);
4465         fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length,
4466                         &fwpkg_data_dma, GFP_KERNEL);
4467         if (!fwpkg_data) {
4468                 ioc_err(ioc,
4469                     "Memory allocation for fwpkg data failed at %s:%d/%s()!\n",
4470                         __FILE__, __LINE__, __func__);
4471                 return -ENOMEM;
4472         }
4473
4474         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4475         if (!smid) {
4476                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
4477                 r = -EAGAIN;
4478                 goto out;
4479         }
4480
4481         ioc->base_cmds.status = MPT3_CMD_PENDING;
4482         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4483         ioc->base_cmds.smid = smid;
4484         memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t));
4485         mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD;
4486         mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH;
4487         mpi_request->ImageSize = cpu_to_le32(data_length);
4488         ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma,
4489                         data_length);
4490         init_completion(&ioc->base_cmds.done);
4491         ioc->put_smid_default(ioc, smid);
4492         /* Wait for 15 seconds */
4493         wait_for_completion_timeout(&ioc->base_cmds.done,
4494                         FW_IMG_HDR_READ_TIMEOUT*HZ);
4495         ioc_info(ioc, "%s: complete\n", __func__);
4496         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4497                 ioc_err(ioc, "%s: timeout\n", __func__);
4498                 _debug_dump_mf(mpi_request,
4499                                 sizeof(Mpi25FWUploadRequest_t)/4);
4500                 r = -ETIME;
4501         } else {
4502                 memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t));
4503                 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) {
4504                         memcpy(&mpi_reply, ioc->base_cmds.reply,
4505                                         sizeof(Mpi2FWUploadReply_t));
4506                         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4507                                                 MPI2_IOCSTATUS_MASK;
4508                         if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4509                                 fw_img_hdr = (Mpi2FWImageHeader_t *)fwpkg_data;
4510                                 if (le32_to_cpu(fw_img_hdr->Signature) ==
4511                                     MPI26_IMAGE_HEADER_SIGNATURE0_MPI26) {
4512                                         cmp_img_hdr =
4513                                             (Mpi26ComponentImageHeader_t *)
4514                                             (fwpkg_data);
4515                                         package_version =
4516                                             le32_to_cpu(
4517                                             cmp_img_hdr->ApplicationSpecific);
4518                                 } else
4519                                         package_version =
4520                                             le32_to_cpu(
4521                                             fw_img_hdr->PackageVersion.Word);
4522                                 if (package_version)
4523                                         ioc_info(ioc,
4524                                         "FW Package Ver(%02d.%02d.%02d.%02d)\n",
4525                                         ((package_version) & 0xFF000000) >> 24,
4526                                         ((package_version) & 0x00FF0000) >> 16,
4527                                         ((package_version) & 0x0000FF00) >> 8,
4528                                         (package_version) & 0x000000FF);
4529                         } else {
4530                                 _debug_dump_mf(&mpi_reply,
4531                                                 sizeof(Mpi2FWUploadReply_t)/4);
4532                         }
4533                 }
4534         }
4535         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4536 out:
4537         if (fwpkg_data)
4538                 dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data,
4539                                 fwpkg_data_dma);
4540         return r;
4541 }
4542
4543 /**
4544  * _base_display_ioc_capabilities - Disply IOC's capabilities.
4545  * @ioc: per adapter object
4546  */
4547 static void
4548 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
4549 {
4550         int i = 0;
4551         char desc[16];
4552         u32 iounit_pg1_flags;
4553         u32 bios_version;
4554
4555         bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
4556         strncpy(desc, ioc->manu_pg0.ChipName, 16);
4557         ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
4558                  desc,
4559                  (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
4560                  (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
4561                  (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
4562                  ioc->facts.FWVersion.Word & 0x000000FF,
4563                  ioc->pdev->revision,
4564                  (bios_version & 0xFF000000) >> 24,
4565                  (bios_version & 0x00FF0000) >> 16,
4566                  (bios_version & 0x0000FF00) >> 8,
4567                  bios_version & 0x000000FF);
4568
4569         _base_display_OEMs_branding(ioc);
4570
4571         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
4572                 pr_info("%sNVMe", i ? "," : "");
4573                 i++;
4574         }
4575
4576         ioc_info(ioc, "Protocol=(");
4577
4578         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
4579                 pr_cont("Initiator");
4580                 i++;
4581         }
4582
4583         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
4584                 pr_cont("%sTarget", i ? "," : "");
4585                 i++;
4586         }
4587
4588         i = 0;
4589         pr_cont("), Capabilities=(");
4590
4591         if (!ioc->hide_ir_msg) {
4592                 if (ioc->facts.IOCCapabilities &
4593                     MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
4594                         pr_cont("Raid");
4595                         i++;
4596                 }
4597         }
4598
4599         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
4600                 pr_cont("%sTLR", i ? "," : "");
4601                 i++;
4602         }
4603
4604         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
4605                 pr_cont("%sMulticast", i ? "," : "");
4606                 i++;
4607         }
4608
4609         if (ioc->facts.IOCCapabilities &
4610             MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
4611                 pr_cont("%sBIDI Target", i ? "," : "");
4612                 i++;
4613         }
4614
4615         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
4616                 pr_cont("%sEEDP", i ? "," : "");
4617                 i++;
4618         }
4619
4620         if (ioc->facts.IOCCapabilities &
4621             MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
4622                 pr_cont("%sSnapshot Buffer", i ? "," : "");
4623                 i++;
4624         }
4625
4626         if (ioc->facts.IOCCapabilities &
4627             MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
4628                 pr_cont("%sDiag Trace Buffer", i ? "," : "");
4629                 i++;
4630         }
4631
4632         if (ioc->facts.IOCCapabilities &
4633             MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
4634                 pr_cont("%sDiag Extended Buffer", i ? "," : "");
4635                 i++;
4636         }
4637
4638         if (ioc->facts.IOCCapabilities &
4639             MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
4640                 pr_cont("%sTask Set Full", i ? "," : "");
4641                 i++;
4642         }
4643
4644         iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
4645         if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
4646                 pr_cont("%sNCQ", i ? "," : "");
4647                 i++;
4648         }
4649
4650         pr_cont(")\n");
4651 }
4652
4653 /**
4654  * mpt3sas_base_update_missing_delay - change the missing delay timers
4655  * @ioc: per adapter object
4656  * @device_missing_delay: amount of time till device is reported missing
4657  * @io_missing_delay: interval IO is returned when there is a missing device
4658  *
4659  * Passed on the command line, this function will modify the device missing
4660  * delay, as well as the io missing delay. This should be called at driver
4661  * load time.
4662  */
4663 void
4664 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
4665         u16 device_missing_delay, u8 io_missing_delay)
4666 {
4667         u16 dmd, dmd_new, dmd_orignal;
4668         u8 io_missing_delay_original;
4669         u16 sz;
4670         Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
4671         Mpi2ConfigReply_t mpi_reply;
4672         u8 num_phys = 0;
4673         u16 ioc_status;
4674
4675         mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
4676         if (!num_phys)
4677                 return;
4678
4679         sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
4680             sizeof(Mpi2SasIOUnit1PhyData_t));
4681         sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
4682         if (!sas_iounit_pg1) {
4683                 ioc_err(ioc, "failure at %s:%d/%s()!\n",
4684                         __FILE__, __LINE__, __func__);
4685                 goto out;
4686         }
4687         if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
4688             sas_iounit_pg1, sz))) {
4689                 ioc_err(ioc, "failure at %s:%d/%s()!\n",
4690                         __FILE__, __LINE__, __func__);
4691                 goto out;
4692         }
4693         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4694             MPI2_IOCSTATUS_MASK;
4695         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4696                 ioc_err(ioc, "failure at %s:%d/%s()!\n",
4697                         __FILE__, __LINE__, __func__);
4698                 goto out;
4699         }
4700
4701         /* device missing delay */
4702         dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
4703         if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
4704                 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
4705         else
4706                 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4707         dmd_orignal = dmd;
4708         if (device_missing_delay > 0x7F) {
4709                 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
4710                     device_missing_delay;
4711                 dmd = dmd / 16;
4712                 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
4713         } else
4714                 dmd = device_missing_delay;
4715         sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
4716
4717         /* io missing delay */
4718         io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
4719         sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
4720
4721         if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
4722             sz)) {
4723                 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
4724                         dmd_new = (dmd &
4725                             MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
4726                 else
4727                         dmd_new =
4728                     dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4729                 ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n",
4730                          dmd_orignal, dmd_new);
4731                 ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n",
4732                          io_missing_delay_original,
4733                          io_missing_delay);
4734                 ioc->device_missing_delay = dmd_new;
4735                 ioc->io_missing_delay = io_missing_delay;
4736         }
4737
4738 out:
4739         kfree(sas_iounit_pg1);
4740 }
4741
4742 /**
4743  * _base_update_ioc_page1_inlinewith_perf_mode - Update IOC Page1 fields
4744  *    according to performance mode.
4745  * @ioc : per adapter object
4746  *
4747  * Return nothing.
4748  */
4749 static void
4750 _base_update_ioc_page1_inlinewith_perf_mode(struct MPT3SAS_ADAPTER *ioc)
4751 {
4752         Mpi2IOCPage1_t ioc_pg1;
4753         Mpi2ConfigReply_t mpi_reply;
4754
4755         mpt3sas_config_get_ioc_pg1(ioc, &mpi_reply, &ioc->ioc_pg1_copy);
4756         memcpy(&ioc_pg1, &ioc->ioc_pg1_copy, sizeof(Mpi2IOCPage1_t));
4757
4758         switch (perf_mode) {
4759         case MPT_PERF_MODE_DEFAULT:
4760         case MPT_PERF_MODE_BALANCED:
4761                 if (ioc->high_iops_queues) {
4762                         ioc_info(ioc,
4763                                 "Enable interrupt coalescing only for first\t"
4764                                 "%d reply queues\n",
4765                                 MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
4766                         /*
4767                          * If 31st bit is zero then interrupt coalescing is
4768                          * enabled for all reply descriptor post queues.
4769                          * If 31st bit is set to one then user can
4770                          * enable/disable interrupt coalescing on per reply
4771                          * descriptor post queue group(8) basis. So to enable
4772                          * interrupt coalescing only on first reply descriptor
4773                          * post queue group 31st bit and zero th bit is enabled.
4774                          */
4775                         ioc_pg1.ProductSpecific = cpu_to_le32(0x80000000 |
4776                             ((1 << MPT3SAS_HIGH_IOPS_REPLY_QUEUES/8) - 1));
4777                         mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
4778                         ioc_info(ioc, "performance mode: balanced\n");
4779                         return;
4780                 }
4781                 fallthrough;
4782         case MPT_PERF_MODE_LATENCY:
4783                 /*
4784                  * Enable interrupt coalescing on all reply queues
4785                  * with timeout value 0xA
4786                  */
4787                 ioc_pg1.CoalescingTimeout = cpu_to_le32(0xa);
4788                 ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
4789                 ioc_pg1.ProductSpecific = 0;
4790                 mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
4791                 ioc_info(ioc, "performance mode: latency\n");
4792                 break;
4793         case MPT_PERF_MODE_IOPS:
4794                 /*
4795                  * Enable interrupt coalescing on all reply queues.
4796                  */
4797                 ioc_info(ioc,
4798                     "performance mode: iops with coalescing timeout: 0x%x\n",
4799                     le32_to_cpu(ioc_pg1.CoalescingTimeout));
4800                 ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
4801                 ioc_pg1.ProductSpecific = 0;
4802                 mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
4803                 break;
4804         }
4805 }
4806
4807 /**
4808  * _base_get_event_diag_triggers - get event diag trigger values from
4809  *                              persistent pages
4810  * @ioc : per adapter object
4811  *
4812  * Return nothing.
4813  */
4814 static void
4815 _base_get_event_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
4816 {
4817         Mpi26DriverTriggerPage2_t trigger_pg2;
4818         struct SL_WH_EVENT_TRIGGER_T *event_tg;
4819         MPI26_DRIVER_MPI_EVENT_TIGGER_ENTRY *mpi_event_tg;
4820         Mpi2ConfigReply_t mpi_reply;
4821         int r = 0, i = 0;
4822         u16 count = 0;
4823         u16 ioc_status;
4824
4825         r = mpt3sas_config_get_driver_trigger_pg2(ioc, &mpi_reply,
4826             &trigger_pg2);
4827         if (r)
4828                 return;
4829
4830         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4831             MPI2_IOCSTATUS_MASK;
4832         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4833                 dinitprintk(ioc,
4834                     ioc_err(ioc,
4835                     "%s: Failed to get trigger pg2, ioc_status(0x%04x)\n",
4836                    __func__, ioc_status));
4837                 return;
4838         }
4839
4840         if (le16_to_cpu(trigger_pg2.NumMPIEventTrigger)) {
4841                 count = le16_to_cpu(trigger_pg2.NumMPIEventTrigger);
4842                 count = min_t(u16, NUM_VALID_ENTRIES, count);
4843                 ioc->diag_trigger_event.ValidEntries = count;
4844
4845                 event_tg = &ioc->diag_trigger_event.EventTriggerEntry[0];
4846                 mpi_event_tg = &trigger_pg2.MPIEventTriggers[0];
4847                 for (i = 0; i < count; i++) {
4848                         event_tg->EventValue = le16_to_cpu(
4849                             mpi_event_tg->MPIEventCode);
4850                         event_tg->LogEntryQualifier = le16_to_cpu(
4851                             mpi_event_tg->MPIEventCodeSpecific);
4852                         event_tg++;
4853                         mpi_event_tg++;
4854                 }
4855         }
4856 }
4857
4858 /**
4859  * _base_get_scsi_diag_triggers - get scsi diag trigger values from
4860  *                              persistent pages
4861  * @ioc : per adapter object
4862  *
4863  * Return nothing.
4864  */
4865 static void
4866 _base_get_scsi_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
4867 {
4868         Mpi26DriverTriggerPage3_t trigger_pg3;
4869         struct SL_WH_SCSI_TRIGGER_T *scsi_tg;
4870         MPI26_DRIVER_SCSI_SENSE_TIGGER_ENTRY *mpi_scsi_tg;
4871         Mpi2ConfigReply_t mpi_reply;
4872         int r = 0, i = 0;
4873         u16 count = 0;
4874         u16 ioc_status;
4875
4876         r = mpt3sas_config_get_driver_trigger_pg3(ioc, &mpi_reply,
4877             &trigger_pg3);
4878         if (r)
4879                 return;
4880
4881         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4882             MPI2_IOCSTATUS_MASK;
4883         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4884                 dinitprintk(ioc,
4885                     ioc_err(ioc,
4886                     "%s: Failed to get trigger pg3, ioc_status(0x%04x)\n",
4887                     __func__, ioc_status));
4888                 return;
4889         }
4890
4891         if (le16_to_cpu(trigger_pg3.NumSCSISenseTrigger)) {
4892                 count = le16_to_cpu(trigger_pg3.NumSCSISenseTrigger);
4893                 count = min_t(u16, NUM_VALID_ENTRIES, count);
4894                 ioc->diag_trigger_scsi.ValidEntries = count;
4895
4896                 scsi_tg = &ioc->diag_trigger_scsi.SCSITriggerEntry[0];
4897                 mpi_scsi_tg = &trigger_pg3.SCSISenseTriggers[0];
4898                 for (i = 0; i < count; i++) {
4899                         scsi_tg->ASCQ = mpi_scsi_tg->ASCQ;
4900                         scsi_tg->ASC = mpi_scsi_tg->ASC;
4901                         scsi_tg->SenseKey = mpi_scsi_tg->SenseKey;
4902
4903                         scsi_tg++;
4904                         mpi_scsi_tg++;
4905                 }
4906         }
4907 }
4908
4909 /**
4910  * _base_get_mpi_diag_triggers - get mpi diag trigger values from
4911  *                              persistent pages
4912  * @ioc : per adapter object
4913  *
4914  * Return nothing.
4915  */
4916 static void
4917 _base_get_mpi_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
4918 {
4919         Mpi26DriverTriggerPage4_t trigger_pg4;
4920         struct SL_WH_MPI_TRIGGER_T *status_tg;
4921         MPI26_DRIVER_IOCSTATUS_LOGINFO_TIGGER_ENTRY *mpi_status_tg;
4922         Mpi2ConfigReply_t mpi_reply;
4923         int r = 0, i = 0;
4924         u16 count = 0;
4925         u16 ioc_status;
4926
4927         r = mpt3sas_config_get_driver_trigger_pg4(ioc, &mpi_reply,
4928             &trigger_pg4);
4929         if (r)
4930                 return;
4931
4932         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4933             MPI2_IOCSTATUS_MASK;
4934         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4935                 dinitprintk(ioc,
4936                     ioc_err(ioc,
4937                     "%s: Failed to get trigger pg4, ioc_status(0x%04x)\n",
4938                     __func__, ioc_status));
4939                 return;
4940         }
4941
4942         if (le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger)) {
4943                 count = le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger);
4944                 count = min_t(u16, NUM_VALID_ENTRIES, count);
4945                 ioc->diag_trigger_mpi.ValidEntries = count;
4946
4947                 status_tg = &ioc->diag_trigger_mpi.MPITriggerEntry[0];
4948                 mpi_status_tg = &trigger_pg4.IOCStatusLoginfoTriggers[0];
4949
4950                 for (i = 0; i < count; i++) {
4951                         status_tg->IOCStatus = le16_to_cpu(
4952                             mpi_status_tg->IOCStatus);
4953                         status_tg->IocLogInfo = le32_to_cpu(
4954                             mpi_status_tg->LogInfo);
4955
4956                         status_tg++;
4957                         mpi_status_tg++;
4958                 }
4959         }
4960 }
4961
4962 /**
4963  * _base_get_master_diag_triggers - get master diag trigger values from
4964  *                              persistent pages
4965  * @ioc : per adapter object
4966  *
4967  * Return nothing.
4968  */
4969 static void
4970 _base_get_master_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
4971 {
4972         Mpi26DriverTriggerPage1_t trigger_pg1;
4973         Mpi2ConfigReply_t mpi_reply;
4974         int r;
4975         u16 ioc_status;
4976
4977         r = mpt3sas_config_get_driver_trigger_pg1(ioc, &mpi_reply,
4978             &trigger_pg1);
4979         if (r)
4980                 return;
4981
4982         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4983             MPI2_IOCSTATUS_MASK;
4984         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4985                 dinitprintk(ioc,
4986                     ioc_err(ioc,
4987                     "%s: Failed to get trigger pg1, ioc_status(0x%04x)\n",
4988                    __func__, ioc_status));
4989                 return;
4990         }
4991
4992         if (le16_to_cpu(trigger_pg1.NumMasterTrigger))
4993                 ioc->diag_trigger_master.MasterData |=
4994                     le32_to_cpu(
4995                     trigger_pg1.MasterTriggers[0].MasterTriggerFlags);
4996 }
4997
4998 /**
4999  * _base_check_for_trigger_pages_support - checks whether HBA FW supports
5000  *                                      driver trigger pages or not
5001  * @ioc : per adapter object
5002  *
5003  * Returns trigger flags mask if HBA FW supports driver trigger pages,
5004  * otherwise returns EFAULT.
5005  */
5006 static int
5007 _base_check_for_trigger_pages_support(struct MPT3SAS_ADAPTER *ioc)
5008 {
5009         Mpi26DriverTriggerPage0_t trigger_pg0;
5010         int r = 0;
5011         Mpi2ConfigReply_t mpi_reply;
5012         u16 ioc_status;
5013
5014         r = mpt3sas_config_get_driver_trigger_pg0(ioc, &mpi_reply,
5015             &trigger_pg0);
5016         if (r)
5017                 return -EFAULT;
5018
5019         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5020             MPI2_IOCSTATUS_MASK;
5021         if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
5022                 return -EFAULT;
5023
5024         return le16_to_cpu(trigger_pg0.TriggerFlags);
5025 }
5026
5027 /**
5028  * _base_get_diag_triggers - Retrieve diag trigger values from
5029  *                              persistent pages.
5030  * @ioc : per adapter object
5031  *
5032  * Return nothing.
5033  */
5034 static void
5035 _base_get_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5036 {
5037         int trigger_flags;
5038
5039         /*
5040          * Default setting of master trigger.
5041          */
5042         ioc->diag_trigger_master.MasterData =
5043             (MASTER_TRIGGER_FW_FAULT + MASTER_TRIGGER_ADAPTER_RESET);
5044
5045         trigger_flags = _base_check_for_trigger_pages_support(ioc);
5046         if (trigger_flags < 0)
5047                 return;
5048
5049         ioc->supports_trigger_pages = 1;
5050
5051         /*
5052          * Retrieve master diag trigger values from driver trigger pg1
5053          * if master trigger bit enabled in TriggerFlags.
5054          */
5055         if ((u16)trigger_flags &
5056             MPI26_DRIVER_TRIGGER0_FLAG_MASTER_TRIGGER_VALID)
5057                 _base_get_master_diag_triggers(ioc);
5058
5059         /*
5060          * Retrieve event diag trigger values from driver trigger pg2
5061          * if event trigger bit enabled in TriggerFlags.
5062          */
5063         if ((u16)trigger_flags &
5064             MPI26_DRIVER_TRIGGER0_FLAG_MPI_EVENT_TRIGGER_VALID)
5065                 _base_get_event_diag_triggers(ioc);
5066
5067         /*
5068          * Retrieve scsi diag trigger values from driver trigger pg3
5069          * if scsi trigger bit enabled in TriggerFlags.
5070          */
5071         if ((u16)trigger_flags &
5072             MPI26_DRIVER_TRIGGER0_FLAG_SCSI_SENSE_TRIGGER_VALID)
5073                 _base_get_scsi_diag_triggers(ioc);
5074         /*
5075          * Retrieve mpi error diag trigger values from driver trigger pg4
5076          * if loginfo trigger bit enabled in TriggerFlags.
5077          */
5078         if ((u16)trigger_flags &
5079             MPI26_DRIVER_TRIGGER0_FLAG_LOGINFO_TRIGGER_VALID)
5080                 _base_get_mpi_diag_triggers(ioc);
5081 }
5082
5083 /**
5084  * _base_update_diag_trigger_pages - Update the driver trigger pages after
5085  *                      online FW update, incase updated FW supports driver
5086  *                      trigger pages.
5087  * @ioc : per adapter object
5088  *
5089  * Return nothing.
5090  */
5091 static void
5092 _base_update_diag_trigger_pages(struct MPT3SAS_ADAPTER *ioc)
5093 {
5094
5095         if (ioc->diag_trigger_master.MasterData)
5096                 mpt3sas_config_update_driver_trigger_pg1(ioc,
5097                     &ioc->diag_trigger_master, 1);
5098
5099         if (ioc->diag_trigger_event.ValidEntries)
5100                 mpt3sas_config_update_driver_trigger_pg2(ioc,
5101                     &ioc->diag_trigger_event, 1);
5102
5103         if (ioc->diag_trigger_scsi.ValidEntries)
5104                 mpt3sas_config_update_driver_trigger_pg3(ioc,
5105                     &ioc->diag_trigger_scsi, 1);
5106
5107         if (ioc->diag_trigger_mpi.ValidEntries)
5108                 mpt3sas_config_update_driver_trigger_pg4(ioc,
5109                     &ioc->diag_trigger_mpi, 1);
5110 }
5111
5112 /**
5113  * _base_static_config_pages - static start of day config pages
5114  * @ioc: per adapter object
5115  */
5116 static void
5117 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
5118 {
5119         Mpi2ConfigReply_t mpi_reply;
5120         u32 iounit_pg1_flags;
5121         int tg_flags = 0;
5122         ioc->nvme_abort_timeout = 30;
5123         mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
5124         if (ioc->ir_firmware)
5125                 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
5126                     &ioc->manu_pg10);
5127
5128         /*
5129          * Ensure correct T10 PI operation if vendor left EEDPTagMode
5130          * flag unset in NVDATA.
5131          */
5132         mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
5133         if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) {
5134                 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
5135                     ioc->name);
5136                 ioc->manu_pg11.EEDPTagMode &= ~0x3;
5137                 ioc->manu_pg11.EEDPTagMode |= 0x1;
5138                 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
5139                     &ioc->manu_pg11);
5140         }
5141         if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK)
5142                 ioc->tm_custom_handling = 1;
5143         else {
5144                 ioc->tm_custom_handling = 0;
5145                 if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT)
5146                         ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT;
5147                 else if (ioc->manu_pg11.NVMeAbortTO >
5148                                         NVME_TASK_ABORT_MAX_TIMEOUT)
5149                         ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT;
5150                 else
5151                         ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO;
5152         }
5153         ioc->time_sync_interval =
5154             ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_MASK;
5155         if (ioc->time_sync_interval) {
5156                 if (ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_UNIT_MASK)
5157                         ioc->time_sync_interval =
5158                             ioc->time_sync_interval * SECONDS_PER_HOUR;
5159                 else
5160                         ioc->time_sync_interval =
5161                             ioc->time_sync_interval * SECONDS_PER_MIN;
5162                 dinitprintk(ioc, ioc_info(ioc,
5163                     "Driver-FW TimeSync interval is %d seconds. ManuPg11 TimeSync Unit is in %s\n",
5164                     ioc->time_sync_interval, (ioc->manu_pg11.TimeSyncInterval &
5165                     MPT3SAS_TIMESYNC_UNIT_MASK) ? "Hour" : "Minute"));
5166         } else {
5167                 if (ioc->is_gen35_ioc)
5168                         ioc_warn(ioc,
5169                             "TimeSync Interval in Manuf page-11 is not enabled. Periodic Time-Sync will be disabled\n");
5170         }
5171         mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
5172         mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
5173         mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
5174         mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
5175         mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
5176         mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
5177         _base_display_ioc_capabilities(ioc);
5178
5179         /*
5180          * Enable task_set_full handling in iounit_pg1 when the
5181          * facts capabilities indicate that its supported.
5182          */
5183         iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
5184         if ((ioc->facts.IOCCapabilities &
5185             MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
5186                 iounit_pg1_flags &=
5187                     ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
5188         else
5189                 iounit_pg1_flags |=
5190                     MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
5191         ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
5192         mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
5193
5194         if (ioc->iounit_pg8.NumSensors)
5195                 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
5196         if (ioc->is_aero_ioc)
5197                 _base_update_ioc_page1_inlinewith_perf_mode(ioc);
5198         if (ioc->is_gen35_ioc) {
5199                 if (ioc->is_driver_loading)
5200                         _base_get_diag_triggers(ioc);
5201                 else {
5202                         /*
5203                          * In case of online HBA FW update operation,
5204                          * check whether updated FW supports the driver trigger
5205                          * pages or not.
5206                          * - If previous FW has not supported driver trigger
5207                          *   pages and newer FW supports them then update these
5208                          *   pages with current diag trigger values.
5209                          * - If previous FW has supported driver trigger pages
5210                          *   and new FW doesn't support them then disable
5211                          *   support_trigger_pages flag.
5212                          */
5213                         tg_flags = _base_check_for_trigger_pages_support(ioc);
5214                         if (!ioc->supports_trigger_pages && tg_flags != -EFAULT)
5215                                 _base_update_diag_trigger_pages(ioc);
5216                         else if (ioc->supports_trigger_pages &&
5217                             tg_flags == -EFAULT)
5218                                 ioc->supports_trigger_pages = 0;
5219                 }
5220         }
5221 }
5222
5223 /**
5224  * mpt3sas_free_enclosure_list - release memory
5225  * @ioc: per adapter object
5226  *
5227  * Free memory allocated during encloure add.
5228  */
5229 void
5230 mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc)
5231 {
5232         struct _enclosure_node *enclosure_dev, *enclosure_dev_next;
5233
5234         /* Free enclosure list */
5235         list_for_each_entry_safe(enclosure_dev,
5236                         enclosure_dev_next, &ioc->enclosure_list, list) {
5237                 list_del(&enclosure_dev->list);
5238                 kfree(enclosure_dev);
5239         }
5240 }
5241
5242 /**
5243  * _base_release_memory_pools - release memory
5244  * @ioc: per adapter object
5245  *
5246  * Free memory allocated from _base_allocate_memory_pools.
5247  */
5248 static void
5249 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
5250 {
5251         int i = 0;
5252         int j = 0;
5253         int dma_alloc_count = 0;
5254         struct chain_tracker *ct;
5255         int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
5256
5257         dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5258
5259         if (ioc->request) {
5260                 dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz,
5261                     ioc->request,  ioc->request_dma);
5262                 dexitprintk(ioc,
5263                             ioc_info(ioc, "request_pool(0x%p): free\n",
5264                                      ioc->request));
5265                 ioc->request = NULL;
5266         }
5267
5268         if (ioc->sense) {
5269                 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
5270                 dma_pool_destroy(ioc->sense_dma_pool);
5271                 dexitprintk(ioc,
5272                             ioc_info(ioc, "sense_pool(0x%p): free\n",
5273                                      ioc->sense));
5274                 ioc->sense = NULL;
5275         }
5276
5277         if (ioc->reply) {
5278                 dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
5279                 dma_pool_destroy(ioc->reply_dma_pool);
5280                 dexitprintk(ioc,
5281                             ioc_info(ioc, "reply_pool(0x%p): free\n",
5282                                      ioc->reply));
5283                 ioc->reply = NULL;
5284         }
5285
5286         if (ioc->reply_free) {
5287                 dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
5288                     ioc->reply_free_dma);
5289                 dma_pool_destroy(ioc->reply_free_dma_pool);
5290                 dexitprintk(ioc,
5291                             ioc_info(ioc, "reply_free_pool(0x%p): free\n",
5292                                      ioc->reply_free));
5293                 ioc->reply_free = NULL;
5294         }
5295
5296         if (ioc->reply_post) {
5297                 dma_alloc_count = DIV_ROUND_UP(count,
5298                                 RDPQ_MAX_INDEX_IN_ONE_CHUNK);
5299                 for (i = 0; i < count; i++) {
5300                         if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
5301                             && dma_alloc_count) {
5302                                 if (ioc->reply_post[i].reply_post_free) {
5303                                         dma_pool_free(
5304                                             ioc->reply_post_free_dma_pool,
5305                                             ioc->reply_post[i].reply_post_free,
5306                                         ioc->reply_post[i].reply_post_free_dma);
5307                                         dexitprintk(ioc, ioc_info(ioc,
5308                                            "reply_post_free_pool(0x%p): free\n",
5309                                            ioc->reply_post[i].reply_post_free));
5310                                         ioc->reply_post[i].reply_post_free =
5311                                                                         NULL;
5312                                 }
5313                                 --dma_alloc_count;
5314                         }
5315                 }
5316                 dma_pool_destroy(ioc->reply_post_free_dma_pool);
5317                 if (ioc->reply_post_free_array &&
5318                         ioc->rdpq_array_enable) {
5319                         dma_pool_free(ioc->reply_post_free_array_dma_pool,
5320                             ioc->reply_post_free_array,
5321                             ioc->reply_post_free_array_dma);
5322                         ioc->reply_post_free_array = NULL;
5323                 }
5324                 dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
5325                 kfree(ioc->reply_post);
5326         }
5327
5328         if (ioc->pcie_sgl_dma_pool) {
5329                 for (i = 0; i < ioc->scsiio_depth; i++) {
5330                         dma_pool_free(ioc->pcie_sgl_dma_pool,
5331                                         ioc->pcie_sg_lookup[i].pcie_sgl,
5332                                         ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5333                 }
5334                 dma_pool_destroy(ioc->pcie_sgl_dma_pool);
5335         }
5336
5337         if (ioc->config_page) {
5338                 dexitprintk(ioc,
5339                             ioc_info(ioc, "config_page(0x%p): free\n",
5340                                      ioc->config_page));
5341                 dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz,
5342                     ioc->config_page, ioc->config_page_dma);
5343         }
5344
5345         kfree(ioc->hpr_lookup);
5346         ioc->hpr_lookup = NULL;
5347         kfree(ioc->internal_lookup);
5348         ioc->internal_lookup = NULL;
5349         if (ioc->chain_lookup) {
5350                 for (i = 0; i < ioc->scsiio_depth; i++) {
5351                         for (j = ioc->chains_per_prp_buffer;
5352                             j < ioc->chains_needed_per_io; j++) {
5353                                 ct = &ioc->chain_lookup[i].chains_per_smid[j];
5354                                 if (ct && ct->chain_buffer)
5355                                         dma_pool_free(ioc->chain_dma_pool,
5356                                                 ct->chain_buffer,
5357                                                 ct->chain_buffer_dma);
5358                         }
5359                         kfree(ioc->chain_lookup[i].chains_per_smid);
5360                 }
5361                 dma_pool_destroy(ioc->chain_dma_pool);
5362                 kfree(ioc->chain_lookup);
5363                 ioc->chain_lookup = NULL;
5364         }
5365 }
5366
5367 /**
5368  * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are
5369  *      having same upper 32bits in their base memory address.
5370  * @reply_pool_start_address: Base address of a reply queue set
5371  * @pool_sz: Size of single Reply Descriptor Post Queues pool size
5372  *
5373  * Return: 1 if reply queues in a set have a same upper 32bits in their base
5374  * memory address, else 0.
5375  */
5376
5377 static int
5378 mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
5379 {
5380         long reply_pool_end_address;
5381
5382         reply_pool_end_address = reply_pool_start_address + pool_sz;
5383
5384         if (upper_32_bits(reply_pool_start_address) ==
5385                 upper_32_bits(reply_pool_end_address))
5386                 return 1;
5387         else
5388                 return 0;
5389 }
5390
5391 /**
5392  * base_alloc_rdpq_dma_pool - Allocating DMA'able memory
5393  *                     for reply queues.
5394  * @ioc: per adapter object
5395  * @sz: DMA Pool size
5396  * Return: 0 for success, non-zero for failure.
5397  */
5398 static int
5399 base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
5400 {
5401         int i = 0;
5402         u32 dma_alloc_count = 0;
5403         int reply_post_free_sz = ioc->reply_post_queue_depth *
5404                 sizeof(Mpi2DefaultReplyDescriptor_t);
5405         int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
5406
5407         ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
5408                         GFP_KERNEL);
5409         if (!ioc->reply_post)
5410                 return -ENOMEM;
5411         /*
5412          *  For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
5413          *  VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
5414          *  be within 4GB boundary i.e reply queues in a set must have same
5415          *  upper 32-bits in their memory address. so here driver is allocating
5416          *  the DMA'able memory for reply queues according.
5417          *  Driver uses limitation of
5418          *  VENTURA_SERIES to manage INVADER_SERIES as well.
5419          */
5420         dma_alloc_count = DIV_ROUND_UP(count,
5421                                 RDPQ_MAX_INDEX_IN_ONE_CHUNK);
5422         ioc->reply_post_free_dma_pool =
5423                 dma_pool_create("reply_post_free pool",
5424                     &ioc->pdev->dev, sz, 16, 0);
5425         if (!ioc->reply_post_free_dma_pool)
5426                 return -ENOMEM;
5427         for (i = 0; i < count; i++) {
5428                 if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
5429                         ioc->reply_post[i].reply_post_free =
5430                             dma_pool_zalloc(ioc->reply_post_free_dma_pool,
5431                                 GFP_KERNEL,
5432                                 &ioc->reply_post[i].reply_post_free_dma);
5433                         if (!ioc->reply_post[i].reply_post_free)
5434                                 return -ENOMEM;
5435                         /*
5436                          * Each set of RDPQ pool must satisfy 4gb boundary
5437                          * restriction.
5438                          * 1) Check if allocated resources for RDPQ pool are in
5439                          *      the same 4GB range.
5440                          * 2) If #1 is true, continue with 64 bit DMA.
5441                          * 3) If #1 is false, return 1. which means free all the
5442                          * resources and set DMA mask to 32 and allocate.
5443                          */
5444                         if (!mpt3sas_check_same_4gb_region(
5445                                 (long)ioc->reply_post[i].reply_post_free, sz)) {
5446                                 dinitprintk(ioc,
5447                                     ioc_err(ioc, "bad Replypost free pool(0x%p)"
5448                                     "reply_post_free_dma = (0x%llx)\n",
5449                                     ioc->reply_post[i].reply_post_free,
5450                                     (unsigned long long)
5451                                     ioc->reply_post[i].reply_post_free_dma));
5452                                 return -EAGAIN;
5453                         }
5454                         dma_alloc_count--;
5455
5456                 } else {
5457                         ioc->reply_post[i].reply_post_free =
5458                             (Mpi2ReplyDescriptorsUnion_t *)
5459                             ((long)ioc->reply_post[i-1].reply_post_free
5460                             + reply_post_free_sz);
5461                         ioc->reply_post[i].reply_post_free_dma =
5462                             (dma_addr_t)
5463                             (ioc->reply_post[i-1].reply_post_free_dma +
5464                             reply_post_free_sz);
5465                 }
5466         }
5467         return 0;
5468 }
5469
5470 /**
5471  * _base_allocate_memory_pools - allocate start of day memory pools
5472  * @ioc: per adapter object
5473  *
5474  * Return: 0 success, anything else error.
5475  */
5476 static int
5477 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
5478 {
5479         struct mpt3sas_facts *facts;
5480         u16 max_sge_elements;
5481         u16 chains_needed_per_io;
5482         u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
5483         u32 retry_sz;
5484         u32 rdpq_sz = 0;
5485         u16 max_request_credit, nvme_blocks_needed;
5486         unsigned short sg_tablesize;
5487         u16 sge_size;
5488         int i, j;
5489         int ret = 0;
5490         struct chain_tracker *ct;
5491
5492         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5493
5494
5495         retry_sz = 0;
5496         facts = &ioc->facts;
5497
5498         /* command line tunables for max sgl entries */
5499         if (max_sgl_entries != -1)
5500                 sg_tablesize = max_sgl_entries;
5501         else {
5502                 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
5503                         sg_tablesize = MPT2SAS_SG_DEPTH;
5504                 else
5505                         sg_tablesize = MPT3SAS_SG_DEPTH;
5506         }
5507
5508         /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */
5509         if (reset_devices)
5510                 sg_tablesize = min_t(unsigned short, sg_tablesize,
5511                    MPT_KDUMP_MIN_PHYS_SEGMENTS);
5512
5513         if (ioc->is_mcpu_endpoint)
5514                 ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
5515         else {
5516                 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
5517                         sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
5518                 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
5519                         sg_tablesize = min_t(unsigned short, sg_tablesize,
5520                                         SG_MAX_SEGMENTS);
5521                         ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n",
5522                                  sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
5523                 }
5524                 ioc->shost->sg_tablesize = sg_tablesize;
5525         }
5526
5527         ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
5528                 (facts->RequestCredit / 4));
5529         if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
5530                 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
5531                                 INTERNAL_SCSIIO_CMDS_COUNT)) {
5532                         ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n",
5533                                 facts->RequestCredit);
5534                         return -ENOMEM;
5535                 }
5536                 ioc->internal_depth = 10;
5537         }
5538
5539         ioc->hi_priority_depth = ioc->internal_depth - (5);
5540         /* command line tunables  for max controller queue depth */
5541         if (max_queue_depth != -1 && max_queue_depth != 0) {
5542                 max_request_credit = min_t(u16, max_queue_depth +
5543                         ioc->internal_depth, facts->RequestCredit);
5544                 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
5545                         max_request_credit =  MAX_HBA_QUEUE_DEPTH;
5546         } else if (reset_devices)
5547                 max_request_credit = min_t(u16, facts->RequestCredit,
5548                     (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth));
5549         else
5550                 max_request_credit = min_t(u16, facts->RequestCredit,
5551                     MAX_HBA_QUEUE_DEPTH);
5552
5553         /* Firmware maintains additional facts->HighPriorityCredit number of
5554          * credits for HiPriprity Request messages, so hba queue depth will be
5555          * sum of max_request_credit and high priority queue depth.
5556          */
5557         ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
5558
5559         /* request frame size */
5560         ioc->request_sz = facts->IOCRequestFrameSize * 4;
5561
5562         /* reply frame size */
5563         ioc->reply_sz = facts->ReplyFrameSize * 4;
5564
5565         /* chain segment size */
5566         if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
5567                 if (facts->IOCMaxChainSegmentSize)
5568                         ioc->chain_segment_sz =
5569                                         facts->IOCMaxChainSegmentSize *
5570                                         MAX_CHAIN_ELEMT_SZ;
5571                 else
5572                 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
5573                         ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
5574                                                     MAX_CHAIN_ELEMT_SZ;
5575         } else
5576                 ioc->chain_segment_sz = ioc->request_sz;
5577
5578         /* calculate the max scatter element size */
5579         sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
5580
5581  retry_allocation:
5582         total_sz = 0;
5583         /* calculate number of sg elements left over in the 1st frame */
5584         max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
5585             sizeof(Mpi2SGEIOUnion_t)) + sge_size);
5586         ioc->max_sges_in_main_message = max_sge_elements/sge_size;
5587
5588         /* now do the same for a chain buffer */
5589         max_sge_elements = ioc->chain_segment_sz - sge_size;
5590         ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
5591
5592         /*
5593          *  MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
5594          */
5595         chains_needed_per_io = ((ioc->shost->sg_tablesize -
5596            ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
5597             + 1;
5598         if (chains_needed_per_io > facts->MaxChainDepth) {
5599                 chains_needed_per_io = facts->MaxChainDepth;
5600                 ioc->shost->sg_tablesize = min_t(u16,
5601                 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
5602                 * chains_needed_per_io), ioc->shost->sg_tablesize);
5603         }
5604         ioc->chains_needed_per_io = chains_needed_per_io;
5605
5606         /* reply free queue sizing - taking into account for 64 FW events */
5607         ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
5608
5609         /* mCPU manage single counters for simplicity */
5610         if (ioc->is_mcpu_endpoint)
5611                 ioc->reply_post_queue_depth = ioc->reply_free_queue_depth;
5612         else {
5613                 /* calculate reply descriptor post queue depth */
5614                 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
5615                         ioc->reply_free_queue_depth +  1;
5616                 /* align the reply post queue on the next 16 count boundary */
5617                 if (ioc->reply_post_queue_depth % 16)
5618                         ioc->reply_post_queue_depth += 16 -
5619                                 (ioc->reply_post_queue_depth % 16);
5620         }
5621
5622         if (ioc->reply_post_queue_depth >
5623             facts->MaxReplyDescriptorPostQueueDepth) {
5624                 ioc->reply_post_queue_depth =
5625                                 facts->MaxReplyDescriptorPostQueueDepth -
5626                     (facts->MaxReplyDescriptorPostQueueDepth % 16);
5627                 ioc->hba_queue_depth =
5628                                 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
5629                 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
5630         }
5631
5632         ioc_info(ioc,
5633             "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), "
5634             "sge_per_io(%d), chains_per_io(%d)\n",
5635             ioc->max_sges_in_main_message,
5636             ioc->max_sges_in_chain_message,
5637             ioc->shost->sg_tablesize,
5638             ioc->chains_needed_per_io);
5639
5640         /* reply post queue, 16 byte align */
5641         reply_post_free_sz = ioc->reply_post_queue_depth *
5642             sizeof(Mpi2DefaultReplyDescriptor_t);
5643         rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
5644         if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
5645                 rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
5646         ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
5647         if (ret == -EAGAIN) {
5648                 /*
5649                  * Free allocated bad RDPQ memory pools.
5650                  * Change dma coherent mask to 32 bit and reallocate RDPQ
5651                  */
5652                 _base_release_memory_pools(ioc);
5653                 ioc->use_32bit_dma = true;
5654                 if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
5655                         ioc_err(ioc,
5656                             "32 DMA mask failed %s\n", pci_name(ioc->pdev));
5657                         return -ENODEV;
5658                 }
5659                 if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
5660                         return -ENOMEM;
5661         } else if (ret == -ENOMEM)
5662                 return -ENOMEM;
5663         total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
5664             DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
5665         ioc->scsiio_depth = ioc->hba_queue_depth -
5666             ioc->hi_priority_depth - ioc->internal_depth;
5667
5668         /* set the scsi host can_queue depth
5669          * with some internal commands that could be outstanding
5670          */
5671         ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
5672         dinitprintk(ioc,
5673                     ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
5674                              ioc->shost->can_queue));
5675
5676         /* contiguous pool for request and chains, 16 byte align, one extra "
5677          * "frame for smid=0
5678          */
5679         ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
5680         sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
5681
5682         /* hi-priority queue */
5683         sz += (ioc->hi_priority_depth * ioc->request_sz);
5684
5685         /* internal queue */
5686         sz += (ioc->internal_depth * ioc->request_sz);
5687
5688         ioc->request_dma_sz = sz;
5689         ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz,
5690                         &ioc->request_dma, GFP_KERNEL);
5691         if (!ioc->request) {
5692                 ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n",
5693                         ioc->hba_queue_depth, ioc->chains_needed_per_io,
5694                         ioc->request_sz, sz / 1024);
5695                 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
5696                         goto out;
5697                 retry_sz = 64;
5698                 ioc->hba_queue_depth -= retry_sz;
5699                 _base_release_memory_pools(ioc);
5700                 goto retry_allocation;
5701         }
5702
5703         if (retry_sz)
5704                 ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n",
5705                         ioc->hba_queue_depth, ioc->chains_needed_per_io,
5706                         ioc->request_sz, sz / 1024);
5707
5708         /* hi-priority queue */
5709         ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
5710             ioc->request_sz);
5711         ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
5712             ioc->request_sz);
5713
5714         /* internal queue */
5715         ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
5716             ioc->request_sz);
5717         ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
5718             ioc->request_sz);
5719
5720         ioc_info(ioc,
5721             "request pool(0x%p) - dma(0x%llx): "
5722             "depth(%d), frame_size(%d), pool_size(%d kB)\n",
5723             ioc->request, (unsigned long long) ioc->request_dma,
5724             ioc->hba_queue_depth, ioc->request_sz,
5725             (ioc->hba_queue_depth * ioc->request_sz) / 1024);
5726
5727         total_sz += sz;
5728
5729         dinitprintk(ioc,
5730                     ioc_info(ioc, "scsiio(0x%p): depth(%d)\n",
5731                              ioc->request, ioc->scsiio_depth));
5732
5733         ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
5734         sz = ioc->scsiio_depth * sizeof(struct chain_lookup);
5735         ioc->chain_lookup = kzalloc(sz, GFP_KERNEL);
5736         if (!ioc->chain_lookup) {
5737                 ioc_err(ioc, "chain_lookup: __get_free_pages failed\n");
5738                 goto out;
5739         }
5740
5741         sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker);
5742         for (i = 0; i < ioc->scsiio_depth; i++) {
5743                 ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL);
5744                 if (!ioc->chain_lookup[i].chains_per_smid) {
5745                         ioc_err(ioc, "chain_lookup: kzalloc failed\n");
5746                         goto out;
5747                 }
5748         }
5749
5750         /* initialize hi-priority queue smid's */
5751         ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
5752             sizeof(struct request_tracker), GFP_KERNEL);
5753         if (!ioc->hpr_lookup) {
5754                 ioc_err(ioc, "hpr_lookup: kcalloc failed\n");
5755                 goto out;
5756         }
5757         ioc->hi_priority_smid = ioc->scsiio_depth + 1;
5758         dinitprintk(ioc,
5759                     ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n",
5760                              ioc->hi_priority,
5761                              ioc->hi_priority_depth, ioc->hi_priority_smid));
5762
5763         /* initialize internal queue smid's */
5764         ioc->internal_lookup = kcalloc(ioc->internal_depth,
5765             sizeof(struct request_tracker), GFP_KERNEL);
5766         if (!ioc->internal_lookup) {
5767                 ioc_err(ioc, "internal_lookup: kcalloc failed\n");
5768                 goto out;
5769         }
5770         ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
5771         dinitprintk(ioc,
5772                     ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n",
5773                              ioc->internal,
5774                              ioc->internal_depth, ioc->internal_smid));
5775         /*
5776          * The number of NVMe page sized blocks needed is:
5777          *     (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
5778          * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry
5779          * that is placed in the main message frame.  8 is the size of each PRP
5780          * entry or PRP list pointer entry.  8 is subtracted from page_size
5781          * because of the PRP list pointer entry at the end of a page, so this
5782          * is not counted as a PRP entry.  The 1 added page is a round up.
5783          *
5784          * To avoid allocation failures due to the amount of memory that could
5785          * be required for NVMe PRP's, only each set of NVMe blocks will be
5786          * contiguous, so a new set is allocated for each possible I/O.
5787          */
5788         ioc->chains_per_prp_buffer = 0;
5789         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
5790                 nvme_blocks_needed =
5791                         (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1;
5792                 nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE);
5793                 nvme_blocks_needed++;
5794
5795                 sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth;
5796                 ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL);
5797                 if (!ioc->pcie_sg_lookup) {
5798                         ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n");
5799                         goto out;
5800                 }
5801                 sz = nvme_blocks_needed * ioc->page_size;
5802                 ioc->pcie_sgl_dma_pool =
5803                         dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 16, 0);
5804                 if (!ioc->pcie_sgl_dma_pool) {
5805                         ioc_info(ioc, "PCIe SGL pool: dma_pool_create failed\n");
5806                         goto out;
5807                 }
5808
5809                 ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
5810                 ioc->chains_per_prp_buffer = min(ioc->chains_per_prp_buffer,
5811                                                 ioc->chains_needed_per_io);
5812
5813                 for (i = 0; i < ioc->scsiio_depth; i++) {
5814                         ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc(
5815                                 ioc->pcie_sgl_dma_pool, GFP_KERNEL,
5816                                 &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5817                         if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
5818                                 ioc_info(ioc, "PCIe SGL pool: dma_pool_alloc failed\n");
5819                                 goto out;
5820                         }
5821                         for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
5822                                 ct = &ioc->chain_lookup[i].chains_per_smid[j];
5823                                 ct->chain_buffer =
5824                                     ioc->pcie_sg_lookup[i].pcie_sgl +
5825                                     (j * ioc->chain_segment_sz);
5826                                 ct->chain_buffer_dma =
5827                                     ioc->pcie_sg_lookup[i].pcie_sgl_dma +
5828                                     (j * ioc->chain_segment_sz);
5829                         }
5830                 }
5831
5832                 dinitprintk(ioc,
5833                             ioc_info(ioc, "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n",
5834                                      ioc->scsiio_depth, sz,
5835                                      (sz * ioc->scsiio_depth) / 1024));
5836                 dinitprintk(ioc,
5837                             ioc_info(ioc, "Number of chains can fit in a PRP page(%d)\n",
5838                                      ioc->chains_per_prp_buffer));
5839                 total_sz += sz * ioc->scsiio_depth;
5840         }
5841
5842         ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev,
5843             ioc->chain_segment_sz, 16, 0);
5844         if (!ioc->chain_dma_pool) {
5845                 ioc_err(ioc, "chain_dma_pool: dma_pool_create failed\n");
5846                 goto out;
5847         }
5848         for (i = 0; i < ioc->scsiio_depth; i++) {
5849                 for (j = ioc->chains_per_prp_buffer;
5850                                 j < ioc->chains_needed_per_io; j++) {
5851                         ct = &ioc->chain_lookup[i].chains_per_smid[j];
5852                         ct->chain_buffer = dma_pool_alloc(
5853                                         ioc->chain_dma_pool, GFP_KERNEL,
5854                                         &ct->chain_buffer_dma);
5855                         if (!ct->chain_buffer) {
5856                                 ioc_err(ioc, "chain_lookup: pci_pool_alloc failed\n");
5857                                 goto out;
5858                         }
5859                 }
5860                 total_sz += ioc->chain_segment_sz;
5861         }
5862
5863         dinitprintk(ioc,
5864                     ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
5865                              ioc->chain_depth, ioc->chain_segment_sz,
5866                              (ioc->chain_depth * ioc->chain_segment_sz) / 1024));
5867
5868         /* sense buffers, 4 byte align */
5869         sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
5870         ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz,
5871                                               4, 0);
5872         if (!ioc->sense_dma_pool) {
5873                 ioc_err(ioc, "sense pool: dma_pool_create failed\n");
5874                 goto out;
5875         }
5876         ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
5877             &ioc->sense_dma);
5878         if (!ioc->sense) {
5879                 ioc_err(ioc, "sense pool: dma_pool_alloc failed\n");
5880                 goto out;
5881         }
5882         /* sense buffer requires to be in same 4 gb region.
5883          * Below function will check the same.
5884          * In case of failure, new pci pool will be created with updated
5885          * alignment. Older allocation and pool will be destroyed.
5886          * Alignment will be used such a way that next allocation if
5887          * success, will always meet same 4gb region requirement.
5888          * Actual requirement is not alignment, but we need start and end of
5889          * DMA address must have same upper 32 bit address.
5890          */
5891         if (!mpt3sas_check_same_4gb_region((long)ioc->sense, sz)) {
5892                 //Release Sense pool & Reallocate
5893                 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
5894                 dma_pool_destroy(ioc->sense_dma_pool);
5895                 ioc->sense = NULL;
5896
5897                 ioc->sense_dma_pool =
5898                         dma_pool_create("sense pool", &ioc->pdev->dev, sz,
5899                                                 roundup_pow_of_two(sz), 0);
5900                 if (!ioc->sense_dma_pool) {
5901                         ioc_err(ioc, "sense pool: pci_pool_create failed\n");
5902                         goto out;
5903                 }
5904                 ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
5905                                 &ioc->sense_dma);
5906                 if (!ioc->sense) {
5907                         ioc_err(ioc, "sense pool: pci_pool_alloc failed\n");
5908                         goto out;
5909                 }
5910         }
5911         ioc_info(ioc,
5912             "sense pool(0x%p)- dma(0x%llx): depth(%d),"
5913             "element_size(%d), pool_size(%d kB)\n",
5914             ioc->sense, (unsigned long long)ioc->sense_dma, ioc->scsiio_depth,
5915             SCSI_SENSE_BUFFERSIZE, sz / 1024);
5916
5917         total_sz += sz;
5918
5919         /* reply pool, 4 byte align */
5920         sz = ioc->reply_free_queue_depth * ioc->reply_sz;
5921         ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz,
5922                                               4, 0);
5923         if (!ioc->reply_dma_pool) {
5924                 ioc_err(ioc, "reply pool: dma_pool_create failed\n");
5925                 goto out;
5926         }
5927         ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
5928             &ioc->reply_dma);
5929         if (!ioc->reply) {
5930                 ioc_err(ioc, "reply pool: dma_pool_alloc failed\n");
5931                 goto out;
5932         }
5933         ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
5934         ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
5935         dinitprintk(ioc,
5936                     ioc_info(ioc, "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
5937                              ioc->reply, ioc->reply_free_queue_depth,
5938                              ioc->reply_sz, sz / 1024));
5939         dinitprintk(ioc,
5940                     ioc_info(ioc, "reply_dma(0x%llx)\n",
5941                              (unsigned long long)ioc->reply_dma));
5942         total_sz += sz;
5943
5944         /* reply free queue, 16 byte align */
5945         sz = ioc->reply_free_queue_depth * 4;
5946         ioc->reply_free_dma_pool = dma_pool_create("reply_free pool",
5947             &ioc->pdev->dev, sz, 16, 0);
5948         if (!ioc->reply_free_dma_pool) {
5949                 ioc_err(ioc, "reply_free pool: dma_pool_create failed\n");
5950                 goto out;
5951         }
5952         ioc->reply_free = dma_pool_zalloc(ioc->reply_free_dma_pool, GFP_KERNEL,
5953             &ioc->reply_free_dma);
5954         if (!ioc->reply_free) {
5955                 ioc_err(ioc, "reply_free pool: dma_pool_alloc failed\n");
5956                 goto out;
5957         }
5958         dinitprintk(ioc,
5959                     ioc_info(ioc, "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
5960                              ioc->reply_free, ioc->reply_free_queue_depth,
5961                              4, sz / 1024));
5962         dinitprintk(ioc,
5963                     ioc_info(ioc, "reply_free_dma (0x%llx)\n",
5964                              (unsigned long long)ioc->reply_free_dma));
5965         total_sz += sz;
5966
5967         if (ioc->rdpq_array_enable) {
5968                 reply_post_free_array_sz = ioc->reply_queue_count *
5969                     sizeof(Mpi2IOCInitRDPQArrayEntry);
5970                 ioc->reply_post_free_array_dma_pool =
5971                     dma_pool_create("reply_post_free_array pool",
5972                     &ioc->pdev->dev, reply_post_free_array_sz, 16, 0);
5973                 if (!ioc->reply_post_free_array_dma_pool) {
5974                         dinitprintk(ioc,
5975                                     ioc_info(ioc, "reply_post_free_array pool: dma_pool_create failed\n"));
5976                         goto out;
5977                 }
5978                 ioc->reply_post_free_array =
5979                     dma_pool_alloc(ioc->reply_post_free_array_dma_pool,
5980                     GFP_KERNEL, &ioc->reply_post_free_array_dma);
5981                 if (!ioc->reply_post_free_array) {
5982                         dinitprintk(ioc,
5983                                     ioc_info(ioc, "reply_post_free_array pool: dma_pool_alloc failed\n"));
5984                         goto out;
5985                 }
5986         }
5987         ioc->config_page_sz = 512;
5988         ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev,
5989                         ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL);
5990         if (!ioc->config_page) {
5991                 ioc_err(ioc, "config page: dma_pool_alloc failed\n");
5992                 goto out;
5993         }
5994
5995         ioc_info(ioc, "config page(0x%p) - dma(0x%llx): size(%d)\n",
5996             ioc->config_page, (unsigned long long)ioc->config_page_dma,
5997             ioc->config_page_sz);
5998         total_sz += ioc->config_page_sz;
5999
6000         ioc_info(ioc, "Allocated physical memory: size(%d kB)\n",
6001                  total_sz / 1024);
6002         ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
6003                  ioc->shost->can_queue, facts->RequestCredit);
6004         ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n",
6005                  ioc->shost->sg_tablesize);
6006         return 0;
6007
6008  out:
6009         return -ENOMEM;
6010 }
6011
6012 /**
6013  * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
6014  * @ioc: Pointer to MPT_ADAPTER structure
6015  * @cooked: Request raw or cooked IOC state
6016  *
6017  * Return: all IOC Doorbell register bits if cooked==0, else just the
6018  * Doorbell bits in MPI_IOC_STATE_MASK.
6019  */
6020 u32
6021 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
6022 {
6023         u32 s, sc;
6024
6025         s = ioc->base_readl(&ioc->chip->Doorbell);
6026         sc = s & MPI2_IOC_STATE_MASK;
6027         return cooked ? sc : s;
6028 }
6029
6030 /**
6031  * _base_wait_on_iocstate - waiting on a particular ioc state
6032  * @ioc: ?
6033  * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
6034  * @timeout: timeout in second
6035  *
6036  * Return: 0 for success, non-zero for failure.
6037  */
6038 static int
6039 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
6040 {
6041         u32 count, cntdn;
6042         u32 current_state;
6043
6044         count = 0;
6045         cntdn = 1000 * timeout;
6046         do {
6047                 current_state = mpt3sas_base_get_iocstate(ioc, 1);
6048                 if (current_state == ioc_state)
6049                         return 0;
6050                 if (count && current_state == MPI2_IOC_STATE_FAULT)
6051                         break;
6052                 if (count && current_state == MPI2_IOC_STATE_COREDUMP)
6053                         break;
6054
6055                 usleep_range(1000, 1500);
6056                 count++;
6057         } while (--cntdn);
6058
6059         return current_state;
6060 }
6061
6062 /**
6063  * _base_dump_reg_set - This function will print hexdump of register set.
6064  * @ioc: per adapter object
6065  *
6066  * Returns nothing.
6067  */
6068 static inline void
6069 _base_dump_reg_set(struct MPT3SAS_ADAPTER *ioc)
6070 {
6071         unsigned int i, sz = 256;
6072         u32 __iomem *reg = (u32 __iomem *)ioc->chip;
6073
6074         ioc_info(ioc, "System Register set:\n");
6075         for (i = 0; i < (sz / sizeof(u32)); i++)
6076                 pr_info("%08x: %08x\n", (i * 4), readl(&reg[i]));
6077 }
6078
6079 /**
6080  * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
6081  * a write to the doorbell)
6082  * @ioc: per adapter object
6083  * @timeout: timeout in seconds
6084  *
6085  * Return: 0 for success, non-zero for failure.
6086  *
6087  * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
6088  */
6089
6090 static int
6091 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
6092 {
6093         u32 cntdn, count;
6094         u32 int_status;
6095
6096         count = 0;
6097         cntdn = 1000 * timeout;
6098         do {
6099                 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6100                 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6101                         dhsprintk(ioc,
6102                                   ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6103                                            __func__, count, timeout));
6104                         return 0;
6105                 }
6106
6107                 usleep_range(1000, 1500);
6108                 count++;
6109         } while (--cntdn);
6110
6111         ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6112                 __func__, count, int_status);
6113         return -EFAULT;
6114 }
6115
6116 static int
6117 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
6118 {
6119         u32 cntdn, count;
6120         u32 int_status;
6121
6122         count = 0;
6123         cntdn = 2000 * timeout;
6124         do {
6125                 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6126                 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6127                         dhsprintk(ioc,
6128                                   ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6129                                            __func__, count, timeout));
6130                         return 0;
6131                 }
6132
6133                 udelay(500);
6134                 count++;
6135         } while (--cntdn);
6136
6137         ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6138                 __func__, count, int_status);
6139         return -EFAULT;
6140
6141 }
6142
6143 /**
6144  * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
6145  * @ioc: per adapter object
6146  * @timeout: timeout in second
6147  *
6148  * Return: 0 for success, non-zero for failure.
6149  *
6150  * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
6151  * doorbell.
6152  */
6153 static int
6154 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
6155 {
6156         u32 cntdn, count;
6157         u32 int_status;
6158         u32 doorbell;
6159
6160         count = 0;
6161         cntdn = 1000 * timeout;
6162         do {
6163                 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6164                 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
6165                         dhsprintk(ioc,
6166                                   ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6167                                            __func__, count, timeout));
6168                         return 0;
6169                 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6170                         doorbell = ioc->base_readl(&ioc->chip->Doorbell);
6171                         if ((doorbell & MPI2_IOC_STATE_MASK) ==
6172                             MPI2_IOC_STATE_FAULT) {
6173                                 mpt3sas_print_fault_code(ioc, doorbell);
6174                                 return -EFAULT;
6175                         }
6176                         if ((doorbell & MPI2_IOC_STATE_MASK) ==
6177                             MPI2_IOC_STATE_COREDUMP) {
6178                                 mpt3sas_print_coredump_info(ioc, doorbell);
6179                                 return -EFAULT;
6180                         }
6181                 } else if (int_status == 0xFFFFFFFF)
6182                         goto out;
6183
6184                 usleep_range(1000, 1500);
6185                 count++;
6186         } while (--cntdn);
6187
6188  out:
6189         ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6190                 __func__, count, int_status);
6191         return -EFAULT;
6192 }
6193
6194 /**
6195  * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
6196  * @ioc: per adapter object
6197  * @timeout: timeout in second
6198  *
6199  * Return: 0 for success, non-zero for failure.
6200  */
6201 static int
6202 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
6203 {
6204         u32 cntdn, count;
6205         u32 doorbell_reg;
6206
6207         count = 0;
6208         cntdn = 1000 * timeout;
6209         do {
6210                 doorbell_reg = ioc->base_readl(&ioc->chip->Doorbell);
6211                 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
6212                         dhsprintk(ioc,
6213                                   ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6214                                            __func__, count, timeout));
6215                         return 0;
6216                 }
6217
6218                 usleep_range(1000, 1500);
6219                 count++;
6220         } while (--cntdn);
6221
6222         ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
6223                 __func__, count, doorbell_reg);
6224         return -EFAULT;
6225 }
6226
6227 /**
6228  * _base_send_ioc_reset - send doorbell reset
6229  * @ioc: per adapter object
6230  * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
6231  * @timeout: timeout in second
6232  *
6233  * Return: 0 for success, non-zero for failure.
6234  */
6235 static int
6236 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
6237 {
6238         u32 ioc_state;
6239         int r = 0;
6240         unsigned long flags;
6241
6242         if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
6243                 ioc_err(ioc, "%s: unknown reset_type\n", __func__);
6244                 return -EFAULT;
6245         }
6246
6247         if (!(ioc->facts.IOCCapabilities &
6248            MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
6249                 return -EFAULT;
6250
6251         ioc_info(ioc, "sending message unit reset !!\n");
6252
6253         writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
6254             &ioc->chip->Doorbell);
6255         if ((_base_wait_for_doorbell_ack(ioc, 15))) {
6256                 r = -EFAULT;
6257                 goto out;
6258         }
6259
6260         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
6261         if (ioc_state) {
6262                 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
6263                         __func__, ioc_state);
6264                 r = -EFAULT;
6265                 goto out;
6266         }
6267  out:
6268         if (r != 0) {
6269                 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6270                 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
6271                 /*
6272                  * Wait for IOC state CoreDump to clear only during
6273                  * HBA initialization & release time.
6274                  */
6275                 if ((ioc_state & MPI2_IOC_STATE_MASK) ==
6276                     MPI2_IOC_STATE_COREDUMP && (ioc->is_driver_loading == 1 ||
6277                     ioc->fault_reset_work_q == NULL)) {
6278                         spin_unlock_irqrestore(
6279                             &ioc->ioc_reset_in_progress_lock, flags);
6280                         mpt3sas_print_coredump_info(ioc, ioc_state);
6281                         mpt3sas_base_wait_for_coredump_completion(ioc,
6282                             __func__);
6283                         spin_lock_irqsave(
6284                             &ioc->ioc_reset_in_progress_lock, flags);
6285                 }
6286                 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
6287         }
6288         ioc_info(ioc, "message unit reset: %s\n",
6289                  r == 0 ? "SUCCESS" : "FAILED");
6290         return r;
6291 }
6292
6293 /**
6294  * mpt3sas_wait_for_ioc - IOC's operational state is checked here.
6295  * @ioc: per adapter object
6296  * @timeout: timeout in seconds
6297  *
6298  * Return: Waits up to timeout seconds for the IOC to
6299  * become operational. Returns 0 if IOC is present
6300  * and operational; otherwise returns -EFAULT.
6301  */
6302
6303 int
6304 mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout)
6305 {
6306         int wait_state_count = 0;
6307         u32 ioc_state;
6308
6309         do {
6310                 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
6311                 if (ioc_state == MPI2_IOC_STATE_OPERATIONAL)
6312                         break;
6313                 ssleep(1);
6314                 ioc_info(ioc, "%s: waiting for operational state(count=%d)\n",
6315                                 __func__, ++wait_state_count);
6316         } while (--timeout);
6317         if (!timeout) {
6318                 ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__);
6319                 return -EFAULT;
6320         }
6321         if (wait_state_count)
6322                 ioc_info(ioc, "ioc is operational\n");
6323         return 0;
6324 }
6325
6326 /**
6327  * _base_handshake_req_reply_wait - send request thru doorbell interface
6328  * @ioc: per adapter object
6329  * @request_bytes: request length
6330  * @request: pointer having request payload
6331  * @reply_bytes: reply length
6332  * @reply: pointer to reply payload
6333  * @timeout: timeout in second
6334  *
6335  * Return: 0 for success, non-zero for failure.
6336  */
6337 static int
6338 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
6339         u32 *request, int reply_bytes, u16 *reply, int timeout)
6340 {
6341         MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
6342         int i;
6343         u8 failed;
6344         __le32 *mfp;
6345
6346         /* make sure doorbell is not in use */
6347         if ((ioc->base_readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
6348                 ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__);
6349                 return -EFAULT;
6350         }
6351
6352         /* clear pending doorbell interrupts from previous state changes */
6353         if (ioc->base_readl(&ioc->chip->HostInterruptStatus) &
6354             MPI2_HIS_IOC2SYS_DB_STATUS)
6355                 writel(0, &ioc->chip->HostInterruptStatus);
6356
6357         /* send message to ioc */
6358         writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
6359             ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
6360             &ioc->chip->Doorbell);
6361
6362         if ((_base_spin_on_doorbell_int(ioc, 5))) {
6363                 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6364                         __LINE__);
6365                 return -EFAULT;
6366         }
6367         writel(0, &ioc->chip->HostInterruptStatus);
6368
6369         if ((_base_wait_for_doorbell_ack(ioc, 5))) {
6370                 ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n",
6371                         __LINE__);
6372                 return -EFAULT;
6373         }
6374
6375         /* send message 32-bits at a time */
6376         for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
6377                 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
6378                 if ((_base_wait_for_doorbell_ack(ioc, 5)))
6379                         failed = 1;
6380         }
6381
6382         if (failed) {
6383                 ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n",
6384                         __LINE__);
6385                 return -EFAULT;
6386         }
6387
6388         /* now wait for the reply */
6389         if ((_base_wait_for_doorbell_int(ioc, timeout))) {
6390                 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6391                         __LINE__);
6392                 return -EFAULT;
6393         }
6394
6395         /* read the first two 16-bits, it gives the total length of the reply */
6396         reply[0] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
6397             & MPI2_DOORBELL_DATA_MASK);
6398         writel(0, &ioc->chip->HostInterruptStatus);
6399         if ((_base_wait_for_doorbell_int(ioc, 5))) {
6400                 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6401                         __LINE__);
6402                 return -EFAULT;
6403         }
6404         reply[1] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
6405             & MPI2_DOORBELL_DATA_MASK);
6406         writel(0, &ioc->chip->HostInterruptStatus);
6407
6408         for (i = 2; i < default_reply->MsgLength * 2; i++)  {
6409                 if ((_base_wait_for_doorbell_int(ioc, 5))) {
6410                         ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6411                                 __LINE__);
6412                         return -EFAULT;
6413                 }
6414                 if (i >=  reply_bytes/2) /* overflow case */
6415                         ioc->base_readl(&ioc->chip->Doorbell);
6416                 else
6417                         reply[i] = le16_to_cpu(
6418                             ioc->base_readl(&ioc->chip->Doorbell)
6419                             & MPI2_DOORBELL_DATA_MASK);
6420                 writel(0, &ioc->chip->HostInterruptStatus);
6421         }
6422
6423         _base_wait_for_doorbell_int(ioc, 5);
6424         if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
6425                 dhsprintk(ioc,
6426                           ioc_info(ioc, "doorbell is in use (line=%d)\n",
6427                                    __LINE__));
6428         }
6429         writel(0, &ioc->chip->HostInterruptStatus);
6430
6431         if (ioc->logging_level & MPT_DEBUG_INIT) {
6432                 mfp = (__le32 *)reply;
6433                 pr_info("\toffset:data\n");
6434                 for (i = 0; i < reply_bytes/4; i++)
6435                         ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
6436                             le32_to_cpu(mfp[i]));
6437         }
6438         return 0;
6439 }
6440
6441 /**
6442  * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
6443  * @ioc: per adapter object
6444  * @mpi_reply: the reply payload from FW
6445  * @mpi_request: the request payload sent to FW
6446  *
6447  * The SAS IO Unit Control Request message allows the host to perform low-level
6448  * operations, such as resets on the PHYs of the IO Unit, also allows the host
6449  * to obtain the IOC assigned device handles for a device if it has other
6450  * identifying information about the device, in addition allows the host to
6451  * remove IOC resources associated with the device.
6452  *
6453  * Return: 0 for success, non-zero for failure.
6454  */
6455 int
6456 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
6457         Mpi2SasIoUnitControlReply_t *mpi_reply,
6458         Mpi2SasIoUnitControlRequest_t *mpi_request)
6459 {
6460         u16 smid;
6461         u8 issue_reset = 0;
6462         int rc;
6463         void *request;
6464
6465         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6466
6467         mutex_lock(&ioc->base_cmds.mutex);
6468
6469         if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
6470                 ioc_err(ioc, "%s: base_cmd in use\n", __func__);
6471                 rc = -EAGAIN;
6472                 goto out;
6473         }
6474
6475         rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
6476         if (rc)
6477                 goto out;
6478
6479         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
6480         if (!smid) {
6481                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
6482                 rc = -EAGAIN;
6483                 goto out;
6484         }
6485
6486         rc = 0;
6487         ioc->base_cmds.status = MPT3_CMD_PENDING;
6488         request = mpt3sas_base_get_msg_frame(ioc, smid);
6489         ioc->base_cmds.smid = smid;
6490         memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
6491         if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
6492             mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
6493                 ioc->ioc_link_reset_in_progress = 1;
6494         init_completion(&ioc->base_cmds.done);
6495         ioc->put_smid_default(ioc, smid);
6496         wait_for_completion_timeout(&ioc->base_cmds.done,
6497             msecs_to_jiffies(10000));
6498         if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
6499             mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
6500             ioc->ioc_link_reset_in_progress)
6501                 ioc->ioc_link_reset_in_progress = 0;
6502         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
6503                 mpt3sas_check_cmd_timeout(ioc, ioc->base_cmds.status,
6504                     mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)/4,
6505                     issue_reset);
6506                 goto issue_host_reset;
6507         }
6508         if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
6509                 memcpy(mpi_reply, ioc->base_cmds.reply,
6510                     sizeof(Mpi2SasIoUnitControlReply_t));
6511         else
6512                 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
6513         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
6514         goto out;
6515
6516  issue_host_reset:
6517         if (issue_reset)
6518                 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
6519         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
6520         rc = -EFAULT;
6521  out:
6522         mutex_unlock(&ioc->base_cmds.mutex);
6523         return rc;
6524 }
6525
6526 /**
6527  * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
6528  * @ioc: per adapter object
6529  * @mpi_reply: the reply payload from FW
6530  * @mpi_request: the request payload sent to FW
6531  *
6532  * The SCSI Enclosure Processor request message causes the IOC to
6533  * communicate with SES devices to control LED status signals.
6534  *
6535  * Return: 0 for success, non-zero for failure.
6536  */
6537 int
6538 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
6539         Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
6540 {
6541         u16 smid;
6542         u8 issue_reset = 0;
6543         int rc;
6544         void *request;
6545
6546         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6547
6548         mutex_lock(&ioc->base_cmds.mutex);
6549
6550         if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
6551                 ioc_err(ioc, "%s: base_cmd in use\n", __func__);
6552                 rc = -EAGAIN;
6553                 goto out;
6554         }
6555
6556         rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
6557         if (rc)
6558                 goto out;
6559
6560         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
6561         if (!smid) {
6562                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
6563                 rc = -EAGAIN;
6564                 goto out;
6565         }
6566
6567         rc = 0;
6568         ioc->base_cmds.status = MPT3_CMD_PENDING;
6569         request = mpt3sas_base_get_msg_frame(ioc, smid);
6570         ioc->base_cmds.smid = smid;
6571         memset(request, 0, ioc->request_sz);
6572         memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
6573         init_completion(&ioc->base_cmds.done);
6574         ioc->put_smid_default(ioc, smid);
6575         wait_for_completion_timeout(&ioc->base_cmds.done,
6576             msecs_to_jiffies(10000));
6577         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
6578                 mpt3sas_check_cmd_timeout(ioc,
6579                     ioc->base_cmds.status, mpi_request,
6580                     sizeof(Mpi2SepRequest_t)/4, issue_reset);
6581                 goto issue_host_reset;
6582         }
6583         if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
6584                 memcpy(mpi_reply, ioc->base_cmds.reply,
6585                     sizeof(Mpi2SepReply_t));
6586         else
6587                 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
6588         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
6589         goto out;
6590
6591  issue_host_reset:
6592         if (issue_reset)
6593                 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
6594         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
6595         rc = -EFAULT;
6596  out:
6597         mutex_unlock(&ioc->base_cmds.mutex);
6598         return rc;
6599 }
6600
6601 /**
6602  * _base_get_port_facts - obtain port facts reply and save in ioc
6603  * @ioc: per adapter object
6604  * @port: ?
6605  *
6606  * Return: 0 for success, non-zero for failure.
6607  */
6608 static int
6609 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
6610 {
6611         Mpi2PortFactsRequest_t mpi_request;
6612         Mpi2PortFactsReply_t mpi_reply;
6613         struct mpt3sas_port_facts *pfacts;
6614         int mpi_reply_sz, mpi_request_sz, r;
6615
6616         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6617
6618         mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
6619         mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
6620         memset(&mpi_request, 0, mpi_request_sz);
6621         mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
6622         mpi_request.PortNumber = port;
6623         r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
6624             (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
6625
6626         if (r != 0) {
6627                 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
6628                 return r;
6629         }
6630
6631         pfacts = &ioc->pfacts[port];
6632         memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
6633         pfacts->PortNumber = mpi_reply.PortNumber;
6634         pfacts->VP_ID = mpi_reply.VP_ID;
6635         pfacts->VF_ID = mpi_reply.VF_ID;
6636         pfacts->MaxPostedCmdBuffers =
6637             le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
6638
6639         return 0;
6640 }
6641
6642 /**
6643  * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
6644  * @ioc: per adapter object
6645  * @timeout:
6646  *
6647  * Return: 0 for success, non-zero for failure.
6648  */
6649 static int
6650 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
6651 {
6652         u32 ioc_state;
6653         int rc;
6654
6655         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6656
6657         if (ioc->pci_error_recovery) {
6658                 dfailprintk(ioc,
6659                             ioc_info(ioc, "%s: host in pci error recovery\n",
6660                                      __func__));
6661                 return -EFAULT;
6662         }
6663
6664         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6665         dhsprintk(ioc,
6666                   ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
6667                            __func__, ioc_state));
6668
6669         if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
6670             (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
6671                 return 0;
6672
6673         if (ioc_state & MPI2_DOORBELL_USED) {
6674                 dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n"));
6675                 goto issue_diag_reset;
6676         }
6677
6678         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
6679                 mpt3sas_print_fault_code(ioc, ioc_state &
6680                     MPI2_DOORBELL_DATA_MASK);
6681                 goto issue_diag_reset;
6682         } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
6683             MPI2_IOC_STATE_COREDUMP) {
6684                 ioc_info(ioc,
6685                     "%s: Skipping the diag reset here. (ioc_state=0x%x)\n",
6686                     __func__, ioc_state);
6687                 return -EFAULT;
6688         }
6689
6690         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
6691         if (ioc_state) {
6692                 dfailprintk(ioc,
6693                             ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
6694                                      __func__, ioc_state));
6695                 return -EFAULT;
6696         }
6697
6698  issue_diag_reset:
6699         rc = _base_diag_reset(ioc);
6700         return rc;
6701 }
6702
6703 /**
6704  * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
6705  * @ioc: per adapter object
6706  *
6707  * Return: 0 for success, non-zero for failure.
6708  */
6709 static int
6710 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
6711 {
6712         Mpi2IOCFactsRequest_t mpi_request;
6713         Mpi2IOCFactsReply_t mpi_reply;
6714         struct mpt3sas_facts *facts;
6715         int mpi_reply_sz, mpi_request_sz, r;
6716
6717         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6718
6719         r = _base_wait_for_iocstate(ioc, 10);
6720         if (r) {
6721                 dfailprintk(ioc,
6722                             ioc_info(ioc, "%s: failed getting to correct state\n",
6723                                      __func__));
6724                 return r;
6725         }
6726         mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
6727         mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
6728         memset(&mpi_request, 0, mpi_request_sz);
6729         mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
6730         r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
6731             (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
6732
6733         if (r != 0) {
6734                 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
6735                 return r;
6736         }
6737
6738         facts = &ioc->facts;
6739         memset(facts, 0, sizeof(struct mpt3sas_facts));
6740         facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
6741         facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
6742         facts->VP_ID = mpi_reply.VP_ID;
6743         facts->VF_ID = mpi_reply.VF_ID;
6744         facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
6745         facts->MaxChainDepth = mpi_reply.MaxChainDepth;
6746         facts->WhoInit = mpi_reply.WhoInit;
6747         facts->NumberOfPorts = mpi_reply.NumberOfPorts;
6748         facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
6749         if (ioc->msix_enable && (facts->MaxMSIxVectors <=
6750             MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc)))
6751                 ioc->combined_reply_queue = 0;
6752         facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
6753         facts->MaxReplyDescriptorPostQueueDepth =
6754             le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
6755         facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
6756         facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
6757         if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
6758                 ioc->ir_firmware = 1;
6759         if ((facts->IOCCapabilities &
6760               MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices))
6761                 ioc->rdpq_array_capable = 1;
6762         if ((facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ)
6763             && ioc->is_aero_ioc)
6764                 ioc->atomic_desc_capable = 1;
6765         facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
6766         facts->IOCRequestFrameSize =
6767             le16_to_cpu(mpi_reply.IOCRequestFrameSize);
6768         if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
6769                 facts->IOCMaxChainSegmentSize =
6770                         le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
6771         }
6772         facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
6773         facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
6774         ioc->shost->max_id = -1;
6775         facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
6776         facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
6777         facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
6778         facts->HighPriorityCredit =
6779             le16_to_cpu(mpi_reply.HighPriorityCredit);
6780         facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
6781         facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
6782         facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize;
6783
6784         /*
6785          * Get the Page Size from IOC Facts. If it's 0, default to 4k.
6786          */
6787         ioc->page_size = 1 << facts->CurrentHostPageSize;
6788         if (ioc->page_size == 1) {
6789                 ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n");
6790                 ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K;
6791         }
6792         dinitprintk(ioc,
6793                     ioc_info(ioc, "CurrentHostPageSize(%d)\n",
6794                              facts->CurrentHostPageSize));
6795
6796         dinitprintk(ioc,
6797                     ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n",
6798                              facts->RequestCredit, facts->MaxChainDepth));
6799         dinitprintk(ioc,
6800                     ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n",
6801                              facts->IOCRequestFrameSize * 4,
6802                              facts->ReplyFrameSize * 4));
6803         return 0;
6804 }
6805
6806 /**
6807  * _base_send_ioc_init - send ioc_init to firmware
6808  * @ioc: per adapter object
6809  *
6810  * Return: 0 for success, non-zero for failure.
6811  */
6812 static int
6813 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
6814 {
6815         Mpi2IOCInitRequest_t mpi_request;
6816         Mpi2IOCInitReply_t mpi_reply;
6817         int i, r = 0;
6818         ktime_t current_time;
6819         u16 ioc_status;
6820         u32 reply_post_free_array_sz = 0;
6821
6822         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6823
6824         memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
6825         mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
6826         mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
6827         mpi_request.VF_ID = 0; /* TODO */
6828         mpi_request.VP_ID = 0;
6829         mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
6830         mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
6831         mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K;
6832
6833         if (_base_is_controller_msix_enabled(ioc))
6834                 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
6835         mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
6836         mpi_request.ReplyDescriptorPostQueueDepth =
6837             cpu_to_le16(ioc->reply_post_queue_depth);
6838         mpi_request.ReplyFreeQueueDepth =
6839             cpu_to_le16(ioc->reply_free_queue_depth);
6840
6841         mpi_request.SenseBufferAddressHigh =
6842             cpu_to_le32((u64)ioc->sense_dma >> 32);
6843         mpi_request.SystemReplyAddressHigh =
6844             cpu_to_le32((u64)ioc->reply_dma >> 32);
6845         mpi_request.SystemRequestFrameBaseAddress =
6846             cpu_to_le64((u64)ioc->request_dma);
6847         mpi_request.ReplyFreeQueueAddress =
6848             cpu_to_le64((u64)ioc->reply_free_dma);
6849
6850         if (ioc->rdpq_array_enable) {
6851                 reply_post_free_array_sz = ioc->reply_queue_count *
6852                     sizeof(Mpi2IOCInitRDPQArrayEntry);
6853                 memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz);
6854                 for (i = 0; i < ioc->reply_queue_count; i++)
6855                         ioc->reply_post_free_array[i].RDPQBaseAddress =
6856                             cpu_to_le64(
6857                                 (u64)ioc->reply_post[i].reply_post_free_dma);
6858                 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
6859                 mpi_request.ReplyDescriptorPostQueueAddress =
6860                     cpu_to_le64((u64)ioc->reply_post_free_array_dma);
6861         } else {
6862                 mpi_request.ReplyDescriptorPostQueueAddress =
6863                     cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
6864         }
6865
6866         /*
6867          * Set the flag to enable CoreDump state feature in IOC firmware.
6868          */
6869         mpi_request.ConfigurationFlags |=
6870             cpu_to_le16(MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE);
6871
6872         /* This time stamp specifies number of milliseconds
6873          * since epoch ~ midnight January 1, 1970.
6874          */
6875         current_time = ktime_get_real();
6876         mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
6877
6878         if (ioc->logging_level & MPT_DEBUG_INIT) {
6879                 __le32 *mfp;
6880                 int i;
6881
6882                 mfp = (__le32 *)&mpi_request;
6883                 ioc_info(ioc, "\toffset:data\n");
6884                 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
6885                         ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
6886                             le32_to_cpu(mfp[i]));
6887         }
6888
6889         r = _base_handshake_req_reply_wait(ioc,
6890             sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
6891             sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30);
6892
6893         if (r != 0) {
6894                 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
6895                 return r;
6896         }
6897
6898         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
6899         if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
6900             mpi_reply.IOCLogInfo) {
6901                 ioc_err(ioc, "%s: failed\n", __func__);
6902                 r = -EIO;
6903         }
6904
6905         /* Reset TimeSync Counter*/
6906         ioc->timestamp_update_count = 0;
6907         return r;
6908 }
6909
6910 /**
6911  * mpt3sas_port_enable_done - command completion routine for port enable
6912  * @ioc: per adapter object
6913  * @smid: system request message index
6914  * @msix_index: MSIX table index supplied by the OS
6915  * @reply: reply message frame(lower 32bit addr)
6916  *
6917  * Return: 1 meaning mf should be freed from _base_interrupt
6918  *          0 means the mf is freed from this function.
6919  */
6920 u8
6921 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
6922         u32 reply)
6923 {
6924         MPI2DefaultReply_t *mpi_reply;
6925         u16 ioc_status;
6926
6927         if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
6928                 return 1;
6929
6930         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
6931         if (!mpi_reply)
6932                 return 1;
6933
6934         if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
6935                 return 1;
6936
6937         ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
6938         ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
6939         ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
6940         memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
6941         ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
6942         if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
6943                 ioc->port_enable_failed = 1;
6944
6945         if (ioc->is_driver_loading) {
6946                 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
6947                         mpt3sas_port_enable_complete(ioc);
6948                         return 1;
6949                 } else {
6950                         ioc->start_scan_failed = ioc_status;
6951                         ioc->start_scan = 0;
6952                         return 1;
6953                 }
6954         }
6955         complete(&ioc->port_enable_cmds.done);
6956         return 1;
6957 }
6958
6959 /**
6960  * _base_send_port_enable - send port_enable(discovery stuff) to firmware
6961  * @ioc: per adapter object
6962  *
6963  * Return: 0 for success, non-zero for failure.
6964  */
6965 static int
6966 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
6967 {
6968         Mpi2PortEnableRequest_t *mpi_request;
6969         Mpi2PortEnableReply_t *mpi_reply;
6970         int r = 0;
6971         u16 smid;
6972         u16 ioc_status;
6973
6974         ioc_info(ioc, "sending port enable !!\n");
6975
6976         if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
6977                 ioc_err(ioc, "%s: internal command already in use\n", __func__);
6978                 return -EAGAIN;
6979         }
6980
6981         smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
6982         if (!smid) {
6983                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
6984                 return -EAGAIN;
6985         }
6986
6987         ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
6988         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
6989         ioc->port_enable_cmds.smid = smid;
6990         memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
6991         mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
6992
6993         init_completion(&ioc->port_enable_cmds.done);
6994         ioc->put_smid_default(ioc, smid);
6995         wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
6996         if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
6997                 ioc_err(ioc, "%s: timeout\n", __func__);
6998                 _debug_dump_mf(mpi_request,
6999                     sizeof(Mpi2PortEnableRequest_t)/4);
7000                 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
7001                         r = -EFAULT;
7002                 else
7003                         r = -ETIME;
7004                 goto out;
7005         }
7006
7007         mpi_reply = ioc->port_enable_cmds.reply;
7008         ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
7009         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
7010                 ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n",
7011                         __func__, ioc_status);
7012                 r = -EFAULT;
7013                 goto out;
7014         }
7015
7016  out:
7017         ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
7018         ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED");
7019         return r;
7020 }
7021
7022 /**
7023  * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
7024  * @ioc: per adapter object
7025  *
7026  * Return: 0 for success, non-zero for failure.
7027  */
7028 int
7029 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
7030 {
7031         Mpi2PortEnableRequest_t *mpi_request;
7032         u16 smid;
7033
7034         ioc_info(ioc, "sending port enable !!\n");
7035
7036         if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
7037                 ioc_err(ioc, "%s: internal command already in use\n", __func__);
7038                 return -EAGAIN;
7039         }
7040
7041         smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
7042         if (!smid) {
7043                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7044                 return -EAGAIN;
7045         }
7046
7047         ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
7048         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7049         ioc->port_enable_cmds.smid = smid;
7050         memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
7051         mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
7052
7053         ioc->put_smid_default(ioc, smid);
7054         return 0;
7055 }
7056
7057 /**
7058  * _base_determine_wait_on_discovery - desposition
7059  * @ioc: per adapter object
7060  *
7061  * Decide whether to wait on discovery to complete. Used to either
7062  * locate boot device, or report volumes ahead of physical devices.
7063  *
7064  * Return: 1 for wait, 0 for don't wait.
7065  */
7066 static int
7067 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
7068 {
7069         /* We wait for discovery to complete if IR firmware is loaded.
7070          * The sas topology events arrive before PD events, so we need time to
7071          * turn on the bit in ioc->pd_handles to indicate PD
7072          * Also, it maybe required to report Volumes ahead of physical
7073          * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
7074          */
7075         if (ioc->ir_firmware)
7076                 return 1;
7077
7078         /* if no Bios, then we don't need to wait */
7079         if (!ioc->bios_pg3.BiosVersion)
7080                 return 0;
7081
7082         /* Bios is present, then we drop down here.
7083          *
7084          * If there any entries in the Bios Page 2, then we wait
7085          * for discovery to complete.
7086          */
7087
7088         /* Current Boot Device */
7089         if ((ioc->bios_pg2.CurrentBootDeviceForm &
7090             MPI2_BIOSPAGE2_FORM_MASK) ==
7091             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
7092         /* Request Boot Device */
7093            (ioc->bios_pg2.ReqBootDeviceForm &
7094             MPI2_BIOSPAGE2_FORM_MASK) ==
7095             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
7096         /* Alternate Request Boot Device */
7097            (ioc->bios_pg2.ReqAltBootDeviceForm &
7098             MPI2_BIOSPAGE2_FORM_MASK) ==
7099             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
7100                 return 0;
7101
7102         return 1;
7103 }
7104
7105 /**
7106  * _base_unmask_events - turn on notification for this event
7107  * @ioc: per adapter object
7108  * @event: firmware event
7109  *
7110  * The mask is stored in ioc->event_masks.
7111  */
7112 static void
7113 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
7114 {
7115         u32 desired_event;
7116
7117         if (event >= 128)
7118                 return;
7119
7120         desired_event = (1 << (event % 32));
7121
7122         if (event < 32)
7123                 ioc->event_masks[0] &= ~desired_event;
7124         else if (event < 64)
7125                 ioc->event_masks[1] &= ~desired_event;
7126         else if (event < 96)
7127                 ioc->event_masks[2] &= ~desired_event;
7128         else if (event < 128)
7129                 ioc->event_masks[3] &= ~desired_event;
7130 }
7131
7132 /**
7133  * _base_event_notification - send event notification
7134  * @ioc: per adapter object
7135  *
7136  * Return: 0 for success, non-zero for failure.
7137  */
7138 static int
7139 _base_event_notification(struct MPT3SAS_ADAPTER *ioc)
7140 {
7141         Mpi2EventNotificationRequest_t *mpi_request;
7142         u16 smid;
7143         int r = 0;
7144         int i;
7145
7146         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7147
7148         if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
7149                 ioc_err(ioc, "%s: internal command already in use\n", __func__);
7150                 return -EAGAIN;
7151         }
7152
7153         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
7154         if (!smid) {
7155                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7156                 return -EAGAIN;
7157         }
7158         ioc->base_cmds.status = MPT3_CMD_PENDING;
7159         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7160         ioc->base_cmds.smid = smid;
7161         memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
7162         mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
7163         mpi_request->VF_ID = 0; /* TODO */
7164         mpi_request->VP_ID = 0;
7165         for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
7166                 mpi_request->EventMasks[i] =
7167                     cpu_to_le32(ioc->event_masks[i]);
7168         init_completion(&ioc->base_cmds.done);
7169         ioc->put_smid_default(ioc, smid);
7170         wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
7171         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
7172                 ioc_err(ioc, "%s: timeout\n", __func__);
7173                 _debug_dump_mf(mpi_request,
7174                     sizeof(Mpi2EventNotificationRequest_t)/4);
7175                 if (ioc->base_cmds.status & MPT3_CMD_RESET)
7176                         r = -EFAULT;
7177                 else
7178                         r = -ETIME;
7179         } else
7180                 dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__));
7181         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7182         return r;
7183 }
7184
7185 /**
7186  * mpt3sas_base_validate_event_type - validating event types
7187  * @ioc: per adapter object
7188  * @event_type: firmware event
7189  *
7190  * This will turn on firmware event notification when application
7191  * ask for that event. We don't mask events that are already enabled.
7192  */
7193 void
7194 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
7195 {
7196         int i, j;
7197         u32 event_mask, desired_event;
7198         u8 send_update_to_fw;
7199
7200         for (i = 0, send_update_to_fw = 0; i <
7201             MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
7202                 event_mask = ~event_type[i];
7203                 desired_event = 1;
7204                 for (j = 0; j < 32; j++) {
7205                         if (!(event_mask & desired_event) &&
7206                             (ioc->event_masks[i] & desired_event)) {
7207                                 ioc->event_masks[i] &= ~desired_event;
7208                                 send_update_to_fw = 1;
7209                         }
7210                         desired_event = (desired_event << 1);
7211                 }
7212         }
7213
7214         if (!send_update_to_fw)
7215                 return;
7216
7217         mutex_lock(&ioc->base_cmds.mutex);
7218         _base_event_notification(ioc);
7219         mutex_unlock(&ioc->base_cmds.mutex);
7220 }
7221
7222 /**
7223  * _base_diag_reset - the "big hammer" start of day reset
7224  * @ioc: per adapter object
7225  *
7226  * Return: 0 for success, non-zero for failure.
7227  */
7228 static int
7229 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
7230 {
7231         u32 host_diagnostic;
7232         u32 ioc_state;
7233         u32 count;
7234         u32 hcb_size;
7235
7236         ioc_info(ioc, "sending diag reset !!\n");
7237
7238         drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
7239
7240         count = 0;
7241         do {
7242                 /* Write magic sequence to WriteSequence register
7243                  * Loop until in diagnostic mode
7244                  */
7245                 drsprintk(ioc, ioc_info(ioc, "write magic sequence\n"));
7246                 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
7247                 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
7248                 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
7249                 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
7250                 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
7251                 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
7252                 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
7253
7254                 /* wait 100 msec */
7255                 msleep(100);
7256
7257                 if (count++ > 20) {
7258                         ioc_info(ioc,
7259                             "Stop writing magic sequence after 20 retries\n");
7260                         _base_dump_reg_set(ioc);
7261                         goto out;
7262                 }
7263
7264                 host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
7265                 drsprintk(ioc,
7266                           ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
7267                                    count, host_diagnostic));
7268
7269         } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
7270
7271         hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
7272
7273         drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
7274         writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
7275              &ioc->chip->HostDiagnostic);
7276
7277         /*This delay allows the chip PCIe hardware time to finish reset tasks*/
7278         msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
7279
7280         /* Approximately 300 second max wait */
7281         for (count = 0; count < (300000000 /
7282                 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
7283
7284                 host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
7285
7286                 if (host_diagnostic == 0xFFFFFFFF) {
7287                         ioc_info(ioc,
7288                             "Invalid host diagnostic register value\n");
7289                         _base_dump_reg_set(ioc);
7290                         goto out;
7291                 }
7292                 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
7293                         break;
7294
7295                 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
7296         }
7297
7298         if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
7299
7300                 drsprintk(ioc,
7301                           ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n"));
7302                 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
7303                 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
7304                 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
7305
7306                 drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n"));
7307                 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
7308                     &ioc->chip->HCBSize);
7309         }
7310
7311         drsprintk(ioc, ioc_info(ioc, "restart the adapter\n"));
7312         writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
7313             &ioc->chip->HostDiagnostic);
7314
7315         drsprintk(ioc,
7316                   ioc_info(ioc, "disable writes to the diagnostic register\n"));
7317         writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
7318
7319         drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
7320         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
7321         if (ioc_state) {
7322                 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
7323                         __func__, ioc_state);
7324                 _base_dump_reg_set(ioc);
7325                 goto out;
7326         }
7327
7328         ioc_info(ioc, "diag reset: SUCCESS\n");
7329         return 0;
7330
7331  out:
7332         ioc_err(ioc, "diag reset: FAILED\n");
7333         return -EFAULT;
7334 }
7335
7336 /**
7337  * _base_make_ioc_ready - put controller in READY state
7338  * @ioc: per adapter object
7339  * @type: FORCE_BIG_HAMMER or SOFT_RESET
7340  *
7341  * Return: 0 for success, non-zero for failure.
7342  */
7343 static int
7344 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
7345 {
7346         u32 ioc_state;
7347         int rc;
7348         int count;
7349
7350         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7351
7352         if (ioc->pci_error_recovery)
7353                 return 0;
7354
7355         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
7356         dhsprintk(ioc,
7357                   ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
7358                            __func__, ioc_state));
7359
7360         /* if in RESET state, it should move to READY state shortly */
7361         count = 0;
7362         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
7363                 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
7364                     MPI2_IOC_STATE_READY) {
7365                         if (count++ == 10) {
7366                                 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
7367                                         __func__, ioc_state);
7368                                 return -EFAULT;
7369                         }
7370                         ssleep(1);
7371                         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
7372                 }
7373         }
7374
7375         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
7376                 return 0;
7377
7378         if (ioc_state & MPI2_DOORBELL_USED) {
7379                 ioc_info(ioc, "unexpected doorbell active!\n");
7380                 goto issue_diag_reset;
7381         }
7382
7383         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
7384                 mpt3sas_print_fault_code(ioc, ioc_state &
7385                     MPI2_DOORBELL_DATA_MASK);
7386                 goto issue_diag_reset;
7387         }
7388
7389         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
7390                 /*
7391                  * if host reset is invoked while watch dog thread is waiting
7392                  * for IOC state to be changed to Fault state then driver has
7393                  * to wait here for CoreDump state to clear otherwise reset
7394                  * will be issued to the FW and FW move the IOC state to
7395                  * reset state without copying the FW logs to coredump region.
7396                  */
7397                 if (ioc->ioc_coredump_loop != MPT3SAS_COREDUMP_LOOP_DONE) {
7398                         mpt3sas_print_coredump_info(ioc, ioc_state &
7399                             MPI2_DOORBELL_DATA_MASK);
7400                         mpt3sas_base_wait_for_coredump_completion(ioc,
7401                             __func__);
7402                 }
7403                 goto issue_diag_reset;
7404         }
7405
7406         if (type == FORCE_BIG_HAMMER)
7407                 goto issue_diag_reset;
7408
7409         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
7410                 if (!(_base_send_ioc_reset(ioc,
7411                     MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
7412                         return 0;
7413         }
7414
7415  issue_diag_reset:
7416         rc = _base_diag_reset(ioc);
7417         return rc;
7418 }
7419
7420 /**
7421  * _base_make_ioc_operational - put controller in OPERATIONAL state
7422  * @ioc: per adapter object
7423  *
7424  * Return: 0 for success, non-zero for failure.
7425  */
7426 static int
7427 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
7428 {
7429         int r, i, index, rc;
7430         unsigned long   flags;
7431         u32 reply_address;
7432         u16 smid;
7433         struct _tr_list *delayed_tr, *delayed_tr_next;
7434         struct _sc_list *delayed_sc, *delayed_sc_next;
7435         struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
7436         u8 hide_flag;
7437         struct adapter_reply_queue *reply_q;
7438         Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
7439
7440         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7441
7442         /* clean the delayed target reset list */
7443         list_for_each_entry_safe(delayed_tr, delayed_tr_next,
7444             &ioc->delayed_tr_list, list) {
7445                 list_del(&delayed_tr->list);
7446                 kfree(delayed_tr);
7447         }
7448
7449
7450         list_for_each_entry_safe(delayed_tr, delayed_tr_next,
7451             &ioc->delayed_tr_volume_list, list) {
7452                 list_del(&delayed_tr->list);
7453                 kfree(delayed_tr);
7454         }
7455
7456         list_for_each_entry_safe(delayed_sc, delayed_sc_next,
7457             &ioc->delayed_sc_list, list) {
7458                 list_del(&delayed_sc->list);
7459                 kfree(delayed_sc);
7460         }
7461
7462         list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
7463             &ioc->delayed_event_ack_list, list) {
7464                 list_del(&delayed_event_ack->list);
7465                 kfree(delayed_event_ack);
7466         }
7467
7468         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
7469
7470         /* hi-priority queue */
7471         INIT_LIST_HEAD(&ioc->hpr_free_list);
7472         smid = ioc->hi_priority_smid;
7473         for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
7474                 ioc->hpr_lookup[i].cb_idx = 0xFF;
7475                 ioc->hpr_lookup[i].smid = smid;
7476                 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
7477                     &ioc->hpr_free_list);
7478         }
7479
7480         /* internal queue */
7481         INIT_LIST_HEAD(&ioc->internal_free_list);
7482         smid = ioc->internal_smid;
7483         for (i = 0; i < ioc->internal_depth; i++, smid++) {
7484                 ioc->internal_lookup[i].cb_idx = 0xFF;
7485                 ioc->internal_lookup[i].smid = smid;
7486                 list_add_tail(&ioc->internal_lookup[i].tracker_list,
7487                     &ioc->internal_free_list);
7488         }
7489
7490         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
7491
7492         /* initialize Reply Free Queue */
7493         for (i = 0, reply_address = (u32)ioc->reply_dma ;
7494             i < ioc->reply_free_queue_depth ; i++, reply_address +=
7495             ioc->reply_sz) {
7496                 ioc->reply_free[i] = cpu_to_le32(reply_address);
7497                 if (ioc->is_mcpu_endpoint)
7498                         _base_clone_reply_to_sys_mem(ioc,
7499                                         reply_address, i);
7500         }
7501
7502         /* initialize reply queues */
7503         if (ioc->is_driver_loading)
7504                 _base_assign_reply_queues(ioc);
7505
7506         /* initialize Reply Post Free Queue */
7507         index = 0;
7508         reply_post_free_contig = ioc->reply_post[0].reply_post_free;
7509         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
7510                 /*
7511                  * If RDPQ is enabled, switch to the next allocation.
7512                  * Otherwise advance within the contiguous region.
7513                  */
7514                 if (ioc->rdpq_array_enable) {
7515                         reply_q->reply_post_free =
7516                                 ioc->reply_post[index++].reply_post_free;
7517                 } else {
7518                         reply_q->reply_post_free = reply_post_free_contig;
7519                         reply_post_free_contig += ioc->reply_post_queue_depth;
7520                 }
7521
7522                 reply_q->reply_post_host_index = 0;
7523                 for (i = 0; i < ioc->reply_post_queue_depth; i++)
7524                         reply_q->reply_post_free[i].Words =
7525                             cpu_to_le64(ULLONG_MAX);
7526                 if (!_base_is_controller_msix_enabled(ioc))
7527                         goto skip_init_reply_post_free_queue;
7528         }
7529  skip_init_reply_post_free_queue:
7530
7531         r = _base_send_ioc_init(ioc);
7532         if (r) {
7533                 /*
7534                  * No need to check IOC state for fault state & issue
7535                  * diag reset during host reset. This check is need
7536                  * only during driver load time.
7537                  */
7538                 if (!ioc->is_driver_loading)
7539                         return r;
7540
7541                 rc = _base_check_for_fault_and_issue_reset(ioc);
7542                 if (rc || (_base_send_ioc_init(ioc)))
7543                         return r;
7544         }
7545
7546         /* initialize reply free host index */
7547         ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
7548         writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
7549
7550         /* initialize reply post host index */
7551         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
7552                 if (ioc->combined_reply_queue)
7553                         writel((reply_q->msix_index & 7)<<
7554                            MPI2_RPHI_MSIX_INDEX_SHIFT,
7555                            ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
7556                 else
7557                         writel(reply_q->msix_index <<
7558                                 MPI2_RPHI_MSIX_INDEX_SHIFT,
7559                                 &ioc->chip->ReplyPostHostIndex);
7560
7561                 if (!_base_is_controller_msix_enabled(ioc))
7562                         goto skip_init_reply_post_host_index;
7563         }
7564
7565  skip_init_reply_post_host_index:
7566
7567         mpt3sas_base_unmask_interrupts(ioc);
7568
7569         if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
7570                 r = _base_display_fwpkg_version(ioc);
7571                 if (r)
7572                         return r;
7573         }
7574
7575         _base_static_config_pages(ioc);
7576         r = _base_event_notification(ioc);
7577         if (r)
7578                 return r;
7579
7580         if (ioc->is_driver_loading) {
7581
7582                 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
7583                     == 0x80) {
7584                         hide_flag = (u8) (
7585                             le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
7586                             MFG_PAGE10_HIDE_SSDS_MASK);
7587                         if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
7588                                 ioc->mfg_pg10_hide_flag = hide_flag;
7589                 }
7590
7591                 ioc->wait_for_discovery_to_complete =
7592                     _base_determine_wait_on_discovery(ioc);
7593
7594                 return r; /* scan_start and scan_finished support */
7595         }
7596
7597         r = _base_send_port_enable(ioc);
7598         if (r)
7599                 return r;
7600
7601         return r;
7602 }
7603
7604 /**
7605  * mpt3sas_base_free_resources - free resources controller resources
7606  * @ioc: per adapter object
7607  */
7608 void
7609 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
7610 {
7611         dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7612
7613         /* synchronizing freeing resource with pci_access_mutex lock */
7614         mutex_lock(&ioc->pci_access_mutex);
7615         if (ioc->chip_phys && ioc->chip) {
7616                 mpt3sas_base_mask_interrupts(ioc);
7617                 ioc->shost_recovery = 1;
7618                 _base_make_ioc_ready(ioc, SOFT_RESET);
7619                 ioc->shost_recovery = 0;
7620         }
7621
7622         mpt3sas_base_unmap_resources(ioc);
7623         mutex_unlock(&ioc->pci_access_mutex);
7624         return;
7625 }
7626
7627 /**
7628  * mpt3sas_base_attach - attach controller instance
7629  * @ioc: per adapter object
7630  *
7631  * Return: 0 for success, non-zero for failure.
7632  */
7633 int
7634 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
7635 {
7636         int r, i, rc;
7637         int cpu_id, last_cpu_id = 0;
7638
7639         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7640
7641         /* setup cpu_msix_table */
7642         ioc->cpu_count = num_online_cpus();
7643         for_each_online_cpu(cpu_id)
7644                 last_cpu_id = cpu_id;
7645         ioc->cpu_msix_table_sz = last_cpu_id + 1;
7646         ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
7647         ioc->reply_queue_count = 1;
7648         if (!ioc->cpu_msix_table) {
7649                 ioc_info(ioc, "Allocation for cpu_msix_table failed!!!\n");
7650                 r = -ENOMEM;
7651                 goto out_free_resources;
7652         }
7653
7654         if (ioc->is_warpdrive) {
7655                 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
7656                     sizeof(resource_size_t *), GFP_KERNEL);
7657                 if (!ioc->reply_post_host_index) {
7658                         ioc_info(ioc, "Allocation for reply_post_host_index failed!!!\n");
7659                         r = -ENOMEM;
7660                         goto out_free_resources;
7661                 }
7662         }
7663
7664         ioc->smp_affinity_enable = smp_affinity_enable;
7665
7666         ioc->rdpq_array_enable_assigned = 0;
7667         ioc->use_32bit_dma = false;
7668         if (ioc->is_aero_ioc)
7669                 ioc->base_readl = &_base_readl_aero;
7670         else
7671                 ioc->base_readl = &_base_readl;
7672         r = mpt3sas_base_map_resources(ioc);
7673         if (r)
7674                 goto out_free_resources;
7675
7676         pci_set_drvdata(ioc->pdev, ioc->shost);
7677         r = _base_get_ioc_facts(ioc);
7678         if (r) {
7679                 rc = _base_check_for_fault_and_issue_reset(ioc);
7680                 if (rc || (_base_get_ioc_facts(ioc)))
7681                         goto out_free_resources;
7682         }
7683
7684         switch (ioc->hba_mpi_version_belonged) {
7685         case MPI2_VERSION:
7686                 ioc->build_sg_scmd = &_base_build_sg_scmd;
7687                 ioc->build_sg = &_base_build_sg;
7688                 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
7689                 ioc->get_msix_index_for_smlio = &_base_get_msix_index;
7690                 break;
7691         case MPI25_VERSION:
7692         case MPI26_VERSION:
7693                 /*
7694                  * In SAS3.0,
7695                  * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
7696                  * Target Status - all require the IEEE formated scatter gather
7697                  * elements.
7698                  */
7699                 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
7700                 ioc->build_sg = &_base_build_sg_ieee;
7701                 ioc->build_nvme_prp = &_base_build_nvme_prp;
7702                 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
7703                 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
7704                 if (ioc->high_iops_queues)
7705                         ioc->get_msix_index_for_smlio =
7706                                         &_base_get_high_iops_msix_index;
7707                 else
7708                         ioc->get_msix_index_for_smlio = &_base_get_msix_index;
7709                 break;
7710         }
7711         if (ioc->atomic_desc_capable) {
7712                 ioc->put_smid_default = &_base_put_smid_default_atomic;
7713                 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic;
7714                 ioc->put_smid_fast_path =
7715                                 &_base_put_smid_fast_path_atomic;
7716                 ioc->put_smid_hi_priority =
7717                                 &_base_put_smid_hi_priority_atomic;
7718         } else {
7719                 ioc->put_smid_default = &_base_put_smid_default;
7720                 ioc->put_smid_fast_path = &_base_put_smid_fast_path;
7721                 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority;
7722                 if (ioc->is_mcpu_endpoint)
7723                         ioc->put_smid_scsi_io =
7724                                 &_base_put_smid_mpi_ep_scsi_io;
7725                 else
7726                         ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
7727         }
7728         /*
7729          * These function pointers for other requests that don't
7730          * the require IEEE scatter gather elements.
7731          *
7732          * For example Configuration Pages and SAS IOUNIT Control don't.
7733          */
7734         ioc->build_sg_mpi = &_base_build_sg;
7735         ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
7736
7737         r = _base_make_ioc_ready(ioc, SOFT_RESET);
7738         if (r)
7739                 goto out_free_resources;
7740
7741         ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
7742             sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
7743         if (!ioc->pfacts) {
7744                 r = -ENOMEM;
7745                 goto out_free_resources;
7746         }
7747
7748         for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
7749                 r = _base_get_port_facts(ioc, i);
7750                 if (r) {
7751                         rc = _base_check_for_fault_and_issue_reset(ioc);
7752                         if (rc || (_base_get_port_facts(ioc, i)))
7753                                 goto out_free_resources;
7754                 }
7755         }
7756
7757         r = _base_allocate_memory_pools(ioc);
7758         if (r)
7759                 goto out_free_resources;
7760
7761         if (irqpoll_weight > 0)
7762                 ioc->thresh_hold = irqpoll_weight;
7763         else
7764                 ioc->thresh_hold = ioc->hba_queue_depth/4;
7765
7766         _base_init_irqpolls(ioc);
7767         init_waitqueue_head(&ioc->reset_wq);
7768
7769         /* allocate memory pd handle bitmask list */
7770         ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
7771         if (ioc->facts.MaxDevHandle % 8)
7772                 ioc->pd_handles_sz++;
7773         ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
7774             GFP_KERNEL);
7775         if (!ioc->pd_handles) {
7776                 r = -ENOMEM;
7777                 goto out_free_resources;
7778         }
7779         ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
7780             GFP_KERNEL);
7781         if (!ioc->blocking_handles) {
7782                 r = -ENOMEM;
7783                 goto out_free_resources;
7784         }
7785
7786         /* allocate memory for pending OS device add list */
7787         ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8);
7788         if (ioc->facts.MaxDevHandle % 8)
7789                 ioc->pend_os_device_add_sz++;
7790         ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz,
7791             GFP_KERNEL);
7792         if (!ioc->pend_os_device_add)
7793                 goto out_free_resources;
7794
7795         ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz;
7796         ioc->device_remove_in_progress =
7797                 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL);
7798         if (!ioc->device_remove_in_progress)
7799                 goto out_free_resources;
7800
7801         ioc->fwfault_debug = mpt3sas_fwfault_debug;
7802
7803         /* base internal command bits */
7804         mutex_init(&ioc->base_cmds.mutex);
7805         ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
7806         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7807
7808         /* port_enable command bits */
7809         ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
7810         ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
7811
7812         /* transport internal command bits */
7813         ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
7814         ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
7815         mutex_init(&ioc->transport_cmds.mutex);
7816
7817         /* scsih internal command bits */
7818         ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
7819         ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
7820         mutex_init(&ioc->scsih_cmds.mutex);
7821
7822         /* task management internal command bits */
7823         ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
7824         ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
7825         mutex_init(&ioc->tm_cmds.mutex);
7826
7827         /* config page internal command bits */
7828         ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
7829         ioc->config_cmds.status = MPT3_CMD_NOT_USED;
7830         mutex_init(&ioc->config_cmds.mutex);
7831
7832         /* ctl module internal command bits */
7833         ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
7834         ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
7835         ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
7836         mutex_init(&ioc->ctl_cmds.mutex);
7837
7838         if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply ||
7839             !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply ||
7840             !ioc->tm_cmds.reply || !ioc->config_cmds.reply ||
7841             !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) {
7842                 r = -ENOMEM;
7843                 goto out_free_resources;
7844         }
7845
7846         for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
7847                 ioc->event_masks[i] = -1;
7848
7849         /* here we enable the events we care about */
7850         _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
7851         _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
7852         _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
7853         _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
7854         _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
7855         _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
7856         _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
7857         _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
7858         _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
7859         _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
7860         _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
7861         _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
7862         _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
7863         if (ioc->hba_mpi_version_belonged == MPI26_VERSION) {
7864                 if (ioc->is_gen35_ioc) {
7865                         _base_unmask_events(ioc,
7866                                 MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE);
7867                         _base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION);
7868                         _base_unmask_events(ioc,
7869                                 MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
7870                 }
7871         }
7872         r = _base_make_ioc_operational(ioc);
7873         if (r)
7874                 goto out_free_resources;
7875
7876         /*
7877          * Copy current copy of IOCFacts in prev_fw_facts
7878          * and it will be used during online firmware upgrade.
7879          */
7880         memcpy(&ioc->prev_fw_facts, &ioc->facts,
7881             sizeof(struct mpt3sas_facts));
7882
7883         ioc->non_operational_loop = 0;
7884         ioc->ioc_coredump_loop = 0;
7885         ioc->got_task_abort_from_ioctl = 0;
7886         return 0;
7887
7888  out_free_resources:
7889
7890         ioc->remove_host = 1;
7891
7892         mpt3sas_base_free_resources(ioc);
7893         _base_release_memory_pools(ioc);
7894         pci_set_drvdata(ioc->pdev, NULL);
7895         kfree(ioc->cpu_msix_table);
7896         if (ioc->is_warpdrive)
7897                 kfree(ioc->reply_post_host_index);
7898         kfree(ioc->pd_handles);
7899         kfree(ioc->blocking_handles);
7900         kfree(ioc->device_remove_in_progress);
7901         kfree(ioc->pend_os_device_add);
7902         kfree(ioc->tm_cmds.reply);
7903         kfree(ioc->transport_cmds.reply);
7904         kfree(ioc->scsih_cmds.reply);
7905         kfree(ioc->config_cmds.reply);
7906         kfree(ioc->base_cmds.reply);
7907         kfree(ioc->port_enable_cmds.reply);
7908         kfree(ioc->ctl_cmds.reply);
7909         kfree(ioc->ctl_cmds.sense);
7910         kfree(ioc->pfacts);
7911         ioc->ctl_cmds.reply = NULL;
7912         ioc->base_cmds.reply = NULL;
7913         ioc->tm_cmds.reply = NULL;
7914         ioc->scsih_cmds.reply = NULL;
7915         ioc->transport_cmds.reply = NULL;
7916         ioc->config_cmds.reply = NULL;
7917         ioc->pfacts = NULL;
7918         return r;
7919 }
7920
7921
7922 /**
7923  * mpt3sas_base_detach - remove controller instance
7924  * @ioc: per adapter object
7925  */
7926 void
7927 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
7928 {
7929         dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7930
7931         mpt3sas_base_stop_watchdog(ioc);
7932         mpt3sas_base_free_resources(ioc);
7933         _base_release_memory_pools(ioc);
7934         mpt3sas_free_enclosure_list(ioc);
7935         pci_set_drvdata(ioc->pdev, NULL);
7936         kfree(ioc->cpu_msix_table);
7937         if (ioc->is_warpdrive)
7938                 kfree(ioc->reply_post_host_index);
7939         kfree(ioc->pd_handles);
7940         kfree(ioc->blocking_handles);
7941         kfree(ioc->device_remove_in_progress);
7942         kfree(ioc->pend_os_device_add);
7943         kfree(ioc->pfacts);
7944         kfree(ioc->ctl_cmds.reply);
7945         kfree(ioc->ctl_cmds.sense);
7946         kfree(ioc->base_cmds.reply);
7947         kfree(ioc->port_enable_cmds.reply);
7948         kfree(ioc->tm_cmds.reply);
7949         kfree(ioc->transport_cmds.reply);
7950         kfree(ioc->scsih_cmds.reply);
7951         kfree(ioc->config_cmds.reply);
7952 }
7953
7954 /**
7955  * _base_pre_reset_handler - pre reset handler
7956  * @ioc: per adapter object
7957  */
7958 static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc)
7959 {
7960         mpt3sas_scsih_pre_reset_handler(ioc);
7961         mpt3sas_ctl_pre_reset_handler(ioc);
7962         dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__));
7963 }
7964
7965 /**
7966  * _base_clear_outstanding_mpt_commands - clears outstanding mpt commands
7967  * @ioc: per adapter object
7968  */
7969 static void
7970 _base_clear_outstanding_mpt_commands(struct MPT3SAS_ADAPTER *ioc)
7971 {
7972         dtmprintk(ioc,
7973             ioc_info(ioc, "%s: clear outstanding mpt cmds\n", __func__));
7974         if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
7975                 ioc->transport_cmds.status |= MPT3_CMD_RESET;
7976                 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
7977                 complete(&ioc->transport_cmds.done);
7978         }
7979         if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
7980                 ioc->base_cmds.status |= MPT3_CMD_RESET;
7981                 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
7982                 complete(&ioc->base_cmds.done);
7983         }
7984         if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
7985                 ioc->port_enable_failed = 1;
7986                 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
7987                 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
7988                 if (ioc->is_driver_loading) {
7989                         ioc->start_scan_failed =
7990                                 MPI2_IOCSTATUS_INTERNAL_ERROR;
7991                         ioc->start_scan = 0;
7992                         ioc->port_enable_cmds.status =
7993                                 MPT3_CMD_NOT_USED;
7994                 } else {
7995                         complete(&ioc->port_enable_cmds.done);
7996                 }
7997         }
7998         if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
7999                 ioc->config_cmds.status |= MPT3_CMD_RESET;
8000                 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
8001                 ioc->config_cmds.smid = USHRT_MAX;
8002                 complete(&ioc->config_cmds.done);
8003         }
8004 }
8005
8006 /**
8007  * _base_clear_outstanding_commands - clear all outstanding commands
8008  * @ioc: per adapter object
8009  */
8010 static void _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc)
8011 {
8012         mpt3sas_scsih_clear_outstanding_scsi_tm_commands(ioc);
8013         mpt3sas_ctl_clear_outstanding_ioctls(ioc);
8014         _base_clear_outstanding_mpt_commands(ioc);
8015 }
8016
8017 /**
8018  * _base_reset_done_handler - reset done handler
8019  * @ioc: per adapter object
8020  */
8021 static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc)
8022 {
8023         mpt3sas_scsih_reset_done_handler(ioc);
8024         mpt3sas_ctl_reset_done_handler(ioc);
8025         dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__));
8026 }
8027
8028 /**
8029  * mpt3sas_wait_for_commands_to_complete - reset controller
8030  * @ioc: Pointer to MPT_ADAPTER structure
8031  *
8032  * This function is waiting 10s for all pending commands to complete
8033  * prior to putting controller in reset.
8034  */
8035 void
8036 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
8037 {
8038         u32 ioc_state;
8039
8040         ioc->pending_io_count = 0;
8041
8042         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
8043         if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
8044                 return;
8045
8046         /* pending command count */
8047         ioc->pending_io_count = scsi_host_busy(ioc->shost);
8048
8049         if (!ioc->pending_io_count)
8050                 return;
8051
8052         /* wait for pending commands to complete */
8053         wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
8054 }
8055
8056 /**
8057  * _base_check_ioc_facts_changes - Look for increase/decrease of IOCFacts
8058  *     attributes during online firmware upgrade and update the corresponding
8059  *     IOC variables accordingly.
8060  *
8061  * @ioc: Pointer to MPT_ADAPTER structure
8062  */
8063 static int
8064 _base_check_ioc_facts_changes(struct MPT3SAS_ADAPTER *ioc)
8065 {
8066         u16 pd_handles_sz;
8067         void *pd_handles = NULL, *blocking_handles = NULL;
8068         void *pend_os_device_add = NULL, *device_remove_in_progress = NULL;
8069         struct mpt3sas_facts *old_facts = &ioc->prev_fw_facts;
8070
8071         if (ioc->facts.MaxDevHandle > old_facts->MaxDevHandle) {
8072                 pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
8073                 if (ioc->facts.MaxDevHandle % 8)
8074                         pd_handles_sz++;
8075
8076                 pd_handles = krealloc(ioc->pd_handles, pd_handles_sz,
8077                     GFP_KERNEL);
8078                 if (!pd_handles) {
8079                         ioc_info(ioc,
8080                             "Unable to allocate the memory for pd_handles of sz: %d\n",
8081                             pd_handles_sz);
8082                         return -ENOMEM;
8083                 }
8084                 memset(pd_handles + ioc->pd_handles_sz, 0,
8085                     (pd_handles_sz - ioc->pd_handles_sz));
8086                 ioc->pd_handles = pd_handles;
8087
8088                 blocking_handles = krealloc(ioc->blocking_handles,
8089                     pd_handles_sz, GFP_KERNEL);
8090                 if (!blocking_handles) {
8091                         ioc_info(ioc,
8092                             "Unable to allocate the memory for "
8093                             "blocking_handles of sz: %d\n",
8094                             pd_handles_sz);
8095                         return -ENOMEM;
8096                 }
8097                 memset(blocking_handles + ioc->pd_handles_sz, 0,
8098                     (pd_handles_sz - ioc->pd_handles_sz));
8099                 ioc->blocking_handles = blocking_handles;
8100                 ioc->pd_handles_sz = pd_handles_sz;
8101
8102                 pend_os_device_add = krealloc(ioc->pend_os_device_add,
8103                     pd_handles_sz, GFP_KERNEL);
8104                 if (!pend_os_device_add) {
8105                         ioc_info(ioc,
8106                             "Unable to allocate the memory for pend_os_device_add of sz: %d\n",
8107                             pd_handles_sz);
8108                         return -ENOMEM;
8109                 }
8110                 memset(pend_os_device_add + ioc->pend_os_device_add_sz, 0,
8111                     (pd_handles_sz - ioc->pend_os_device_add_sz));
8112                 ioc->pend_os_device_add = pend_os_device_add;
8113                 ioc->pend_os_device_add_sz = pd_handles_sz;
8114
8115                 device_remove_in_progress = krealloc(
8116                     ioc->device_remove_in_progress, pd_handles_sz, GFP_KERNEL);
8117                 if (!device_remove_in_progress) {
8118                         ioc_info(ioc,
8119                             "Unable to allocate the memory for "
8120                             "device_remove_in_progress of sz: %d\n "
8121                             , pd_handles_sz);
8122                         return -ENOMEM;
8123                 }
8124                 memset(device_remove_in_progress +
8125                     ioc->device_remove_in_progress_sz, 0,
8126                     (pd_handles_sz - ioc->device_remove_in_progress_sz));
8127                 ioc->device_remove_in_progress = device_remove_in_progress;
8128                 ioc->device_remove_in_progress_sz = pd_handles_sz;
8129         }
8130
8131         memcpy(&ioc->prev_fw_facts, &ioc->facts, sizeof(struct mpt3sas_facts));
8132         return 0;
8133 }
8134
8135 /**
8136  * mpt3sas_base_hard_reset_handler - reset controller
8137  * @ioc: Pointer to MPT_ADAPTER structure
8138  * @type: FORCE_BIG_HAMMER or SOFT_RESET
8139  *
8140  * Return: 0 for success, non-zero for failure.
8141  */
8142 int
8143 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
8144         enum reset_type type)
8145 {
8146         int r;
8147         unsigned long flags;
8148         u32 ioc_state;
8149         u8 is_fault = 0, is_trigger = 0;
8150
8151         dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__));
8152
8153         if (ioc->pci_error_recovery) {
8154                 ioc_err(ioc, "%s: pci error recovery reset\n", __func__);
8155                 r = 0;
8156                 goto out_unlocked;
8157         }
8158
8159         if (mpt3sas_fwfault_debug)
8160                 mpt3sas_halt_firmware(ioc);
8161
8162         /* wait for an active reset in progress to complete */
8163         mutex_lock(&ioc->reset_in_progress_mutex);
8164
8165         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
8166         ioc->shost_recovery = 1;
8167         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
8168
8169         if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
8170             MPT3_DIAG_BUFFER_IS_REGISTERED) &&
8171             (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
8172             MPT3_DIAG_BUFFER_IS_RELEASED))) {
8173                 is_trigger = 1;
8174                 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
8175                 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT ||
8176                     (ioc_state & MPI2_IOC_STATE_MASK) ==
8177                     MPI2_IOC_STATE_COREDUMP)
8178                         is_fault = 1;
8179         }
8180         _base_pre_reset_handler(ioc);
8181         mpt3sas_wait_for_commands_to_complete(ioc);
8182         mpt3sas_base_mask_interrupts(ioc);
8183         r = _base_make_ioc_ready(ioc, type);
8184         if (r)
8185                 goto out;
8186         _base_clear_outstanding_commands(ioc);
8187
8188         /* If this hard reset is called while port enable is active, then
8189          * there is no reason to call make_ioc_operational
8190          */
8191         if (ioc->is_driver_loading && ioc->port_enable_failed) {
8192                 ioc->remove_host = 1;
8193                 r = -EFAULT;
8194                 goto out;
8195         }
8196         r = _base_get_ioc_facts(ioc);
8197         if (r)
8198                 goto out;
8199
8200         r = _base_check_ioc_facts_changes(ioc);
8201         if (r) {
8202                 ioc_info(ioc,
8203                     "Some of the parameters got changed in this new firmware"
8204                     " image and it requires system reboot\n");
8205                 goto out;
8206         }
8207         if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
8208                 panic("%s: Issue occurred with flashing controller firmware."
8209                       "Please reboot the system and ensure that the correct"
8210                       " firmware version is running\n", ioc->name);
8211
8212         r = _base_make_ioc_operational(ioc);
8213         if (!r)
8214                 _base_reset_done_handler(ioc);
8215
8216  out:
8217         ioc_info(ioc, "%s: %s\n", __func__, r == 0 ? "SUCCESS" : "FAILED");
8218
8219         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
8220         ioc->shost_recovery = 0;
8221         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
8222         ioc->ioc_reset_count++;
8223         mutex_unlock(&ioc->reset_in_progress_mutex);
8224
8225  out_unlocked:
8226         if ((r == 0) && is_trigger) {
8227                 if (is_fault)
8228                         mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
8229                 else
8230                         mpt3sas_trigger_master(ioc,
8231                             MASTER_TRIGGER_ADAPTER_RESET);
8232         }
8233         dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__));
8234         return r;
8235 }