drivers/scsi/megaraid/megaraid_sas.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  Linux MegaRAID driver for SAS based RAID controllers
   4  *
   5  *  Copyright (c) 2003-2013  LSI Corporation
   6  *  Copyright (c) 2013-2016  Avago Technologies
   7  *  Copyright (c) 2016-2018  Broadcom Inc.
   8  *
   9  *  FILE: megaraid_sas.h
  10  *
  11  *  Authors: Broadcom Inc.
  12  *           Kashyap Desai <kashyap.desai@broadcom.com>
  13  *           Sumit Saxena <sumit.saxena@broadcom.com>
  14  *
  15  *  Send feedback to: megaraidlinux.pdl@broadcom.com
  16  */
  17
  18 #ifndef LSI_MEGARAID_SAS_H
  19 #define LSI_MEGARAID_SAS_H
  20
  21 /*
  22  * MegaRAID SAS Driver meta data
  23  */
  24 #define MEGASAS_VERSION                         "07.710.50.00-rc1"
  25 #define MEGASAS_RELDATE                         "June 28, 2019"
  26
  27 /*
  28  * Device IDs
  29  */
  30 #define PCI_DEVICE_ID_LSI_SAS1078R              0x0060
  31 #define PCI_DEVICE_ID_LSI_SAS1078DE             0x007C
  32 #define PCI_DEVICE_ID_LSI_VERDE_ZCR             0x0413
  33 #define PCI_DEVICE_ID_LSI_SAS1078GEN2           0x0078
  34 #define PCI_DEVICE_ID_LSI_SAS0079GEN2           0x0079
  35 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY         0x0073
  36 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY         0x0071
  37 #define PCI_DEVICE_ID_LSI_FUSION                0x005b
  38 #define PCI_DEVICE_ID_LSI_PLASMA                0x002f
  39 #define PCI_DEVICE_ID_LSI_INVADER               0x005d
  40 #define PCI_DEVICE_ID_LSI_FURY                  0x005f
  41 #define PCI_DEVICE_ID_LSI_INTRUDER              0x00ce
  42 #define PCI_DEVICE_ID_LSI_INTRUDER_24           0x00cf
  43 #define PCI_DEVICE_ID_LSI_CUTLASS_52            0x0052
  44 #define PCI_DEVICE_ID_LSI_CUTLASS_53            0x0053
  45 #define PCI_DEVICE_ID_LSI_VENTURA                   0x0014
  46 #define PCI_DEVICE_ID_LSI_CRUSADER                  0x0015
  47 #define PCI_DEVICE_ID_LSI_HARPOON                   0x0016
  48 #define PCI_DEVICE_ID_LSI_TOMCAT                    0x0017
  49 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT         0x001B
  50 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT        0x001C
  51 #define PCI_DEVICE_ID_LSI_AERO_10E1             0x10e1
  52 #define PCI_DEVICE_ID_LSI_AERO_10E2             0x10e2
  53 #define PCI_DEVICE_ID_LSI_AERO_10E5             0x10e5
  54 #define PCI_DEVICE_ID_LSI_AERO_10E6             0x10e6
  55 #define PCI_DEVICE_ID_LSI_AERO_10E0             0x10e0
  56 #define PCI_DEVICE_ID_LSI_AERO_10E3             0x10e3
  57 #define PCI_DEVICE_ID_LSI_AERO_10E4             0x10e4
  58 #define PCI_DEVICE_ID_LSI_AERO_10E7             0x10e7
  59
  60 /*
  61  * Intel HBA SSDIDs
  62  */
  63 #define MEGARAID_INTEL_RS3DC080_SSDID           0x9360
  64 #define MEGARAID_INTEL_RS3DC040_SSDID           0x9362
  65 #define MEGARAID_INTEL_RS3SC008_SSDID           0x9380
  66 #define MEGARAID_INTEL_RS3MC044_SSDID           0x9381
  67 #define MEGARAID_INTEL_RS3WC080_SSDID           0x9341
  68 #define MEGARAID_INTEL_RS3WC040_SSDID           0x9343
  69 #define MEGARAID_INTEL_RMS3BC160_SSDID          0x352B
  70
  71 /*
  72  * Intruder HBA SSDIDs
  73  */
  74 #define MEGARAID_INTRUDER_SSDID1                0x9371
  75 #define MEGARAID_INTRUDER_SSDID2                0x9390
  76 #define MEGARAID_INTRUDER_SSDID3                0x9370
  77
  78 /*
  79  * Intel HBA branding
  80  */
  81 #define MEGARAID_INTEL_RS3DC080_BRANDING        \
  82         "Intel(R) RAID Controller RS3DC080"
  83 #define MEGARAID_INTEL_RS3DC040_BRANDING        \
  84         "Intel(R) RAID Controller RS3DC040"
  85 #define MEGARAID_INTEL_RS3SC008_BRANDING        \
  86         "Intel(R) RAID Controller RS3SC008"
  87 #define MEGARAID_INTEL_RS3MC044_BRANDING        \
  88         "Intel(R) RAID Controller RS3MC044"
  89 #define MEGARAID_INTEL_RS3WC080_BRANDING        \
  90         "Intel(R) RAID Controller RS3WC080"
  91 #define MEGARAID_INTEL_RS3WC040_BRANDING        \
  92         "Intel(R) RAID Controller RS3WC040"
  93 #define MEGARAID_INTEL_RMS3BC160_BRANDING       \
  94         "Intel(R) Integrated RAID Module RMS3BC160"
  95
  96 /*
  97  * =====================================
  98  * MegaRAID SAS MFI firmware definitions
  99  * =====================================
 100  */
 101
 102 /*
 103  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
 104  * protocol between the software and firmware. Commands are issued using
 105  * "message frames"
 106  */
 107
 108 /*
 109  * FW posts its state in upper 4 bits of outbound_msg_0 register
 110  */
 111 #define MFI_STATE_MASK                          0xF0000000
 112 #define MFI_STATE_UNDEFINED                     0x00000000
 113 #define MFI_STATE_BB_INIT                       0x10000000
 114 #define MFI_STATE_FW_INIT                       0x40000000
 115 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
 116 #define MFI_STATE_FW_INIT_2                     0x70000000
 117 #define MFI_STATE_DEVICE_SCAN                   0x80000000
 118 #define MFI_STATE_BOOT_MESSAGE_PENDING          0x90000000
 119 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
 120 #define MFI_STATE_READY                         0xB0000000
 121 #define MFI_STATE_OPERATIONAL                   0xC0000000
 122 #define MFI_STATE_FAULT                         0xF0000000
 123 #define MFI_STATE_FORCE_OCR                     0x00000080
 124 #define MFI_STATE_DMADONE                       0x00000008
 125 #define MFI_STATE_CRASH_DUMP_DONE               0x00000004
 126 #define MFI_RESET_REQUIRED                      0x00000001
 127 #define MFI_RESET_ADAPTER                       0x00000002
 128 #define MEGAMFI_FRAME_SIZE                      64
 129
 130 #define MFI_STATE_FAULT_CODE                    0x0FFF0000
 131 #define MFI_STATE_FAULT_SUBCODE                 0x0000FF00
 132 /*
 133  * During FW init, clear pending cmds & reset state using inbound_msg_0
 134  *
 135  * ABORT        : Abort all pending cmds
 136  * READY        : Move from OPERATIONAL to READY state; discard queue info
 137  * MFIMODE      : Discard (possible) low MFA posted in 64-bit mode (??)
 138  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
 139  * HOTPLUG      : Resume from Hotplug
 140  * MFI_STOP_ADP : Send signal to FW to stop processing
 141  * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump
 142  */
 143 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC) /* I20 */
 144 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)  /* I20 */
 145 #define DIAG_WRITE_ENABLE                       (0x00000080)
 146 #define DIAG_RESET_ADAPTER                      (0x00000004)
 147
 148 #define MFI_ADP_RESET                           0x00000040
 149 #define MFI_INIT_ABORT                          0x00000001
 150 #define MFI_INIT_READY                          0x00000002
 151 #define MFI_INIT_MFIMODE                        0x00000004
 152 #define MFI_INIT_CLEAR_HANDSHAKE                0x00000008
 153 #define MFI_INIT_HOTPLUG                        0x00000010
 154 #define MFI_STOP_ADP                            0x00000020
 155 #define MFI_RESET_FLAGS                         MFI_INIT_READY| \
 156                                                 MFI_INIT_MFIMODE| \
 157                                                 MFI_INIT_ABORT
 158 #define MFI_ADP_TRIGGER_SNAP_DUMP               0x00000100
 159 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
 160
 161 /*
 162  * MFI frame flags
 163  */
 164 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
 165 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
 166 #define MFI_FRAME_SGL32                         0x0000
 167 #define MFI_FRAME_SGL64                         0x0002
 168 #define MFI_FRAME_SENSE32                       0x0000
 169 #define MFI_FRAME_SENSE64                       0x0004
 170 #define MFI_FRAME_DIR_NONE                      0x0000
 171 #define MFI_FRAME_DIR_WRITE                     0x0008
 172 #define MFI_FRAME_DIR_READ                      0x0010
 173 #define MFI_FRAME_DIR_BOTH                      0x0018
 174 #define MFI_FRAME_IEEE                          0x0020
 175
 176 /* Driver internal */
 177 #define DRV_DCMD_POLLED_MODE            0x1
 178 #define DRV_DCMD_SKIP_REFIRE            0x2
 179
 180 /*
 181  * Definition for cmd_status
 182  */
 183 #define MFI_CMD_STATUS_POLL_MODE                0xFF
 184
 185 /*
 186  * MFI command opcodes
 187  */
 188 enum MFI_CMD_OP {
 189         MFI_CMD_INIT            = 0x0,
 190         MFI_CMD_LD_READ         = 0x1,
 191         MFI_CMD_LD_WRITE        = 0x2,
 192         MFI_CMD_LD_SCSI_IO      = 0x3,
 193         MFI_CMD_PD_SCSI_IO      = 0x4,
 194         MFI_CMD_DCMD            = 0x5,
 195         MFI_CMD_ABORT           = 0x6,
 196         MFI_CMD_SMP             = 0x7,
 197         MFI_CMD_STP             = 0x8,
 198         MFI_CMD_NVME            = 0x9,
 199         MFI_CMD_TOOLBOX         = 0xa,
 200         MFI_CMD_OP_COUNT,
 201         MFI_CMD_INVALID         = 0xff
 202 };
 203
 204 #define MR_DCMD_CTRL_GET_INFO                   0x01010000
 205 #define MR_DCMD_LD_GET_LIST                     0x03010000
 206 #define MR_DCMD_LD_LIST_QUERY                   0x03010100
 207
 208 #define MR_DCMD_CTRL_CACHE_FLUSH                0x01101000
 209 #define MR_FLUSH_CTRL_CACHE                     0x01
 210 #define MR_FLUSH_DISK_CACHE                     0x02
 211
 212 #define MR_DCMD_CTRL_SHUTDOWN                   0x01050000
 213 #define MR_DCMD_HIBERNATE_SHUTDOWN              0x01060000
 214 #define MR_ENABLE_DRIVE_SPINDOWN                0x01
 215
 216 #define MR_DCMD_CTRL_EVENT_GET_INFO             0x01040100
 217 #define MR_DCMD_CTRL_EVENT_GET                  0x01040300
 218 #define MR_DCMD_CTRL_EVENT_WAIT                 0x01040500
 219 #define MR_DCMD_LD_GET_PROPERTIES               0x03030000
 220
 221 #define MR_DCMD_CLUSTER                         0x08000000
 222 #define MR_DCMD_CLUSTER_RESET_ALL               0x08010100
 223 #define MR_DCMD_CLUSTER_RESET_LD                0x08010200
 224 #define MR_DCMD_PD_LIST_QUERY                   0x02010100
 225
 226 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS      0x01190100
 227 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE        (0xF0010000 | 0x0600)
 228 #define MR_DCMD_PD_GET_INFO                     0x02020000
 229
 230 /*
 231  * Global functions
 232  */
 233 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id);
 234
 235
 236 /*
 237  * MFI command completion codes
 238  */
 239 enum MFI_STAT {
 240         MFI_STAT_OK = 0x00,
 241         MFI_STAT_INVALID_CMD = 0x01,
 242         MFI_STAT_INVALID_DCMD = 0x02,
 243         MFI_STAT_INVALID_PARAMETER = 0x03,
 244         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
 245         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
 246         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
 247         MFI_STAT_APP_IN_USE = 0x07,
 248         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
 249         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
 250         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
 251         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
 252         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
 253         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
 254         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
 255         MFI_STAT_FLASH_BUSY = 0x0f,
 256         MFI_STAT_FLASH_ERROR = 0x10,
 257         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
 258         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
 259         MFI_STAT_FLASH_NOT_OPEN = 0x13,
 260         MFI_STAT_FLASH_NOT_STARTED = 0x14,
 261         MFI_STAT_FLUSH_FAILED = 0x15,
 262         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
 263         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
 264         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
 265         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
 266         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
 267         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
 268         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
 269         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
 270         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
 271         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
 272         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
 273         MFI_STAT_MFC_HW_ERROR = 0x21,
 274         MFI_STAT_NO_HW_PRESENT = 0x22,
 275         MFI_STAT_NOT_FOUND = 0x23,
 276         MFI_STAT_NOT_IN_ENCL = 0x24,
 277         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
 278         MFI_STAT_PD_TYPE_WRONG = 0x26,
 279         MFI_STAT_PR_DISABLED = 0x27,
 280         MFI_STAT_ROW_INDEX_INVALID = 0x28,
 281         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
 282         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
 283         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
 284         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
 285         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
 286         MFI_STAT_SCSI_IO_FAILED = 0x2e,
 287         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
 288         MFI_STAT_SHUTDOWN_FAILED = 0x30,
 289         MFI_STAT_TIME_NOT_SET = 0x31,
 290         MFI_STAT_WRONG_STATE = 0x32,
 291         MFI_STAT_LD_OFFLINE = 0x33,
 292         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
 293         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
 294         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
 295         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
 296         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
 297         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
 298
 299         MFI_STAT_INVALID_STATUS = 0xFF
 300 };
 301
 302 enum mfi_evt_class {
 303         MFI_EVT_CLASS_DEBUG =           -2,
 304         MFI_EVT_CLASS_PROGRESS =        -1,
 305         MFI_EVT_CLASS_INFO =            0,
 306         MFI_EVT_CLASS_WARNING =         1,
 307         MFI_EVT_CLASS_CRITICAL =        2,
 308         MFI_EVT_CLASS_FATAL =           3,
 309         MFI_EVT_CLASS_DEAD =            4
 310 };
 311
 312 /*
 313  * Crash dump related defines
 314  */
 315 #define MAX_CRASH_DUMP_SIZE 512
 316 #define CRASH_DMA_BUF_SIZE  (1024 * 1024)
 317
 318 enum MR_FW_CRASH_DUMP_STATE {
 319         UNAVAILABLE = 0,
 320         AVAILABLE = 1,
 321         COPYING = 2,
 322         COPIED = 3,
 323         COPY_ERROR = 4,
 324 };
 325
 326 enum _MR_CRASH_BUF_STATUS {
 327         MR_CRASH_BUF_TURN_OFF = 0,
 328         MR_CRASH_BUF_TURN_ON = 1,
 329 };
 330
 331 /*
 332  * Number of mailbox bytes in DCMD message frame
 333  */
 334 #define MFI_MBOX_SIZE                           12
 335
 336 enum MR_EVT_CLASS {
 337
 338         MR_EVT_CLASS_DEBUG = -2,
 339         MR_EVT_CLASS_PROGRESS = -1,
 340         MR_EVT_CLASS_INFO = 0,
 341         MR_EVT_CLASS_WARNING = 1,
 342         MR_EVT_CLASS_CRITICAL = 2,
 343         MR_EVT_CLASS_FATAL = 3,
 344         MR_EVT_CLASS_DEAD = 4,
 345
 346 };
 347
 348 enum MR_EVT_LOCALE {
 349
 350         MR_EVT_LOCALE_LD = 0x0001,
 351         MR_EVT_LOCALE_PD = 0x0002,
 352         MR_EVT_LOCALE_ENCL = 0x0004,
 353         MR_EVT_LOCALE_BBU = 0x0008,
 354         MR_EVT_LOCALE_SAS = 0x0010,
 355         MR_EVT_LOCALE_CTRL = 0x0020,
 356         MR_EVT_LOCALE_CONFIG = 0x0040,
 357         MR_EVT_LOCALE_CLUSTER = 0x0080,
 358         MR_EVT_LOCALE_ALL = 0xffff,
 359
 360 };
 361
 362 enum MR_EVT_ARGS {
 363
 364         MR_EVT_ARGS_NONE,
 365         MR_EVT_ARGS_CDB_SENSE,
 366         MR_EVT_ARGS_LD,
 367         MR_EVT_ARGS_LD_COUNT,
 368         MR_EVT_ARGS_LD_LBA,
 369         MR_EVT_ARGS_LD_OWNER,
 370         MR_EVT_ARGS_LD_LBA_PD_LBA,
 371         MR_EVT_ARGS_LD_PROG,
 372         MR_EVT_ARGS_LD_STATE,
 373         MR_EVT_ARGS_LD_STRIP,
 374         MR_EVT_ARGS_PD,
 375         MR_EVT_ARGS_PD_ERR,
 376         MR_EVT_ARGS_PD_LBA,
 377         MR_EVT_ARGS_PD_LBA_LD,
 378         MR_EVT_ARGS_PD_PROG,
 379         MR_EVT_ARGS_PD_STATE,
 380         MR_EVT_ARGS_PCI,
 381         MR_EVT_ARGS_RATE,
 382         MR_EVT_ARGS_STR,
 383         MR_EVT_ARGS_TIME,
 384         MR_EVT_ARGS_ECC,
 385         MR_EVT_ARGS_LD_PROP,
 386         MR_EVT_ARGS_PD_SPARE,
 387         MR_EVT_ARGS_PD_INDEX,
 388         MR_EVT_ARGS_DIAG_PASS,
 389         MR_EVT_ARGS_DIAG_FAIL,
 390         MR_EVT_ARGS_PD_LBA_LBA,
 391         MR_EVT_ARGS_PORT_PHY,
 392         MR_EVT_ARGS_PD_MISSING,
 393         MR_EVT_ARGS_PD_ADDRESS,
 394         MR_EVT_ARGS_BITMAP,
 395         MR_EVT_ARGS_CONNECTOR,
 396         MR_EVT_ARGS_PD_PD,
 397         MR_EVT_ARGS_PD_FRU,
 398         MR_EVT_ARGS_PD_PATHINFO,
 399         MR_EVT_ARGS_PD_POWER_STATE,
 400         MR_EVT_ARGS_GENERIC,
 401 };
 402
 403
 404 #define SGE_BUFFER_SIZE 4096
 405 #define MEGASAS_CLUSTER_ID_SIZE 16
 406 /*
 407  * define constants for device list query options
 408  */
 409 enum MR_PD_QUERY_TYPE {
 410         MR_PD_QUERY_TYPE_ALL                = 0,
 411         MR_PD_QUERY_TYPE_STATE              = 1,
 412         MR_PD_QUERY_TYPE_POWER_STATE        = 2,
 413         MR_PD_QUERY_TYPE_MEDIA_TYPE         = 3,
 414         MR_PD_QUERY_TYPE_SPEED              = 4,
 415         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST    = 5,
 416 };
 417
 418 enum MR_LD_QUERY_TYPE {
 419         MR_LD_QUERY_TYPE_ALL             = 0,
 420         MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
 421         MR_LD_QUERY_TYPE_USED_TGT_IDS    = 2,
 422         MR_LD_QUERY_TYPE_CLUSTER_ACCESS  = 3,
 423         MR_LD_QUERY_TYPE_CLUSTER_LOCALE  = 4,
 424 };
 425
 426
 427 #define MR_EVT_CFG_CLEARED                              0x0004
 428 #define MR_EVT_LD_STATE_CHANGE                          0x0051
 429 #define MR_EVT_PD_INSERTED                              0x005b
 430 #define MR_EVT_PD_REMOVED                               0x0070
 431 #define MR_EVT_LD_CREATED                               0x008a
 432 #define MR_EVT_LD_DELETED                               0x008b
 433 #define MR_EVT_FOREIGN_CFG_IMPORTED                     0x00db
 434 #define MR_EVT_LD_OFFLINE                               0x00fc
 435 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
 436 #define MR_EVT_CTRL_PROP_CHANGED                        0x012f
 437
 438 enum MR_PD_STATE {
 439         MR_PD_STATE_UNCONFIGURED_GOOD   = 0x00,
 440         MR_PD_STATE_UNCONFIGURED_BAD    = 0x01,
 441         MR_PD_STATE_HOT_SPARE           = 0x02,
 442         MR_PD_STATE_OFFLINE             = 0x10,
 443         MR_PD_STATE_FAILED              = 0x11,
 444         MR_PD_STATE_REBUILD             = 0x14,
 445         MR_PD_STATE_ONLINE              = 0x18,
 446         MR_PD_STATE_COPYBACK            = 0x20,
 447         MR_PD_STATE_SYSTEM              = 0x40,
 448  };
 449
 450 union MR_PD_REF {
 451         struct {
 452                 u16      deviceId;
 453                 u16      seqNum;
 454         } mrPdRef;
 455         u32      ref;
 456 };
 457
 458 /*
 459  * define the DDF Type bit structure
 460  */
 461 union MR_PD_DDF_TYPE {
 462          struct {
 463                 union {
 464                         struct {
 465 #ifndef __BIG_ENDIAN_BITFIELD
 466                                  u16     forcedPDGUID:1;
 467                                  u16     inVD:1;
 468                                  u16     isGlobalSpare:1;
 469                                  u16     isSpare:1;
 470                                  u16     isForeign:1;
 471                                  u16     reserved:7;
 472                                  u16     intf:4;
 473 #else
 474                                  u16     intf:4;
 475                                  u16     reserved:7;
 476                                  u16     isForeign:1;
 477                                  u16     isSpare:1;
 478                                  u16     isGlobalSpare:1;
 479                                  u16     inVD:1;
 480                                  u16     forcedPDGUID:1;
 481 #endif
 482                          } pdType;
 483                          u16     type;
 484                  };
 485                  u16     reserved;
 486          } ddf;
 487          struct {
 488                  u32    reserved;
 489          } nonDisk;
 490          u32     type;
 491 } __packed;
 492
 493 /*
 494  * defines the progress structure
 495  */
 496 union MR_PROGRESS {
 497         struct  {
 498                 u16 progress;
 499                 union {
 500                         u16 elapsedSecs;
 501                         u16 elapsedSecsForLastPercent;
 502                 };
 503         } mrProgress;
 504         u32 w;
 505 } __packed;
 506
 507 /*
 508  * defines the physical drive progress structure
 509  */
 510 struct MR_PD_PROGRESS {
 511         struct {
 512 #ifndef MFI_BIG_ENDIAN
 513                 u32     rbld:1;
 514                 u32     patrol:1;
 515                 u32     clear:1;
 516                 u32     copyBack:1;
 517                 u32     erase:1;
 518                 u32     locate:1;
 519                 u32     reserved:26;
 520 #else
 521                 u32     reserved:26;
 522                 u32     locate:1;
 523                 u32     erase:1;
 524                 u32     copyBack:1;
 525                 u32     clear:1;
 526                 u32     patrol:1;
 527                 u32     rbld:1;
 528 #endif
 529         } active;
 530         union MR_PROGRESS     rbld;
 531         union MR_PROGRESS     patrol;
 532         union {
 533                 union MR_PROGRESS     clear;
 534                 union MR_PROGRESS     erase;
 535         };
 536
 537         struct {
 538 #ifndef MFI_BIG_ENDIAN
 539                 u32     rbld:1;
 540                 u32     patrol:1;
 541                 u32     clear:1;
 542                 u32     copyBack:1;
 543                 u32     erase:1;
 544                 u32     reserved:27;
 545 #else
 546                 u32     reserved:27;
 547                 u32     erase:1;
 548                 u32     copyBack:1;
 549                 u32     clear:1;
 550                 u32     patrol:1;
 551                 u32     rbld:1;
 552 #endif
 553         } pause;
 554
 555         union MR_PROGRESS     reserved[3];
 556 } __packed;
 557
 558 struct  MR_PD_INFO {
 559         union MR_PD_REF ref;
 560         u8 inquiryData[96];
 561         u8 vpdPage83[64];
 562         u8 notSupported;
 563         u8 scsiDevType;
 564
 565         union {
 566                 u8 connectedPortBitmap;
 567                 u8 connectedPortNumbers;
 568         };
 569
 570         u8 deviceSpeed;
 571         u32 mediaErrCount;
 572         u32 otherErrCount;
 573         u32 predFailCount;
 574         u32 lastPredFailEventSeqNum;
 575
 576         u16 fwState;
 577         u8 disabledForRemoval;
 578         u8 linkSpeed;
 579         union MR_PD_DDF_TYPE state;
 580
 581         struct {
 582                 u8 count;
 583 #ifndef __BIG_ENDIAN_BITFIELD
 584                 u8 isPathBroken:4;
 585                 u8 reserved3:3;
 586                 u8 widePortCapable:1;
 587 #else
 588                 u8 widePortCapable:1;
 589                 u8 reserved3:3;
 590                 u8 isPathBroken:4;
 591 #endif
 592
 593                 u8 connectorIndex[2];
 594                 u8 reserved[4];
 595                 u64 sasAddr[2];
 596                 u8 reserved2[16];
 597         } pathInfo;
 598
 599         u64 rawSize;
 600         u64 nonCoercedSize;
 601         u64 coercedSize;
 602         u16 enclDeviceId;
 603         u8 enclIndex;
 604
 605         union {
 606                 u8 slotNumber;
 607                 u8 enclConnectorIndex;
 608         };
 609
 610         struct MR_PD_PROGRESS progInfo;
 611         u8 badBlockTableFull;
 612         u8 unusableInCurrentConfig;
 613         u8 vpdPage83Ext[64];
 614         u8 powerState;
 615         u8 enclPosition;
 616         u32 allowedOps;
 617         u16 copyBackPartnerId;
 618         u16 enclPartnerDeviceId;
 619         struct {
 620 #ifndef __BIG_ENDIAN_BITFIELD
 621                 u16 fdeCapable:1;
 622                 u16 fdeEnabled:1;
 623                 u16 secured:1;
 624                 u16 locked:1;
 625                 u16 foreign:1;
 626                 u16 needsEKM:1;
 627                 u16 reserved:10;
 628 #else
 629                 u16 reserved:10;
 630                 u16 needsEKM:1;
 631                 u16 foreign:1;
 632                 u16 locked:1;
 633                 u16 secured:1;
 634                 u16 fdeEnabled:1;
 635                 u16 fdeCapable:1;
 636 #endif
 637         } security;
 638         u8 mediaType;
 639         u8 notCertified;
 640         u8 bridgeVendor[8];
 641         u8 bridgeProductIdentification[16];
 642         u8 bridgeProductRevisionLevel[4];
 643         u8 satBridgeExists;
 644
 645         u8 interfaceType;
 646         u8 temperature;
 647         u8 emulatedBlockSize;
 648         u16 userDataBlockSize;
 649         u16 reserved2;
 650
 651         struct {
 652 #ifndef __BIG_ENDIAN_BITFIELD
 653                 u32 piType:3;
 654                 u32 piFormatted:1;
 655                 u32 piEligible:1;
 656                 u32 NCQ:1;
 657                 u32 WCE:1;
 658                 u32 commissionedSpare:1;
 659                 u32 emergencySpare:1;
 660                 u32 ineligibleForSSCD:1;
 661                 u32 ineligibleForLd:1;
 662                 u32 useSSEraseType:1;
 663                 u32 wceUnchanged:1;
 664                 u32 supportScsiUnmap:1;
 665                 u32 reserved:18;
 666 #else
 667                 u32 reserved:18;
 668                 u32 supportScsiUnmap:1;
 669                 u32 wceUnchanged:1;
 670                 u32 useSSEraseType:1;
 671                 u32 ineligibleForLd:1;
 672                 u32 ineligibleForSSCD:1;
 673                 u32 emergencySpare:1;
 674                 u32 commissionedSpare:1;
 675                 u32 WCE:1;
 676                 u32 NCQ:1;
 677                 u32 piEligible:1;
 678                 u32 piFormatted:1;
 679                 u32 piType:3;
 680 #endif
 681         } properties;
 682
 683         u64 shieldDiagCompletionTime;
 684         u8 shieldCounter;
 685
 686         u8 linkSpeedOther;
 687         u8 reserved4[2];
 688
 689         struct {
 690 #ifndef __BIG_ENDIAN_BITFIELD
 691                 u32 bbmErrCountSupported:1;
 692                 u32 bbmErrCount:31;
 693 #else
 694                 u32 bbmErrCount:31;
 695                 u32 bbmErrCountSupported:1;
 696 #endif
 697         } bbmErr;
 698
 699         u8 reserved1[512-428];
 700 } __packed;
 701
 702 /*
 703  * Definition of structure used to expose attributes of VD or JBOD
 704  * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
 705  * is fired by driver)
 706  */
 707 struct MR_TARGET_PROPERTIES {
 708         u32    max_io_size_kb;
 709         u32    device_qdepth;
 710         u32    sector_size;
 711         u8     reset_tmo;
 712         u8     reserved[499];
 713 } __packed;
 714
 715  /*
 716  * defines the physical drive address structure
 717  */
 718 struct MR_PD_ADDRESS {
 719         __le16  deviceId;
 720         u16     enclDeviceId;
 721
 722         union {
 723                 struct {
 724                         u8  enclIndex;
 725                         u8  slotNumber;
 726                 } mrPdAddress;
 727                 struct {
 728                         u8  enclPosition;
 729                         u8  enclConnectorIndex;
 730                 } mrEnclAddress;
 731         };
 732         u8      scsiDevType;
 733         union {
 734                 u8      connectedPortBitmap;
 735                 u8      connectedPortNumbers;
 736         };
 737         u64     sasAddr[2];
 738 } __packed;
 739
 740 /*
 741  * defines the physical drive list structure
 742  */
 743 struct MR_PD_LIST {
 744         __le32          size;
 745         __le32          count;
 746         struct MR_PD_ADDRESS   addr[1];
 747 } __packed;
 748
 749 struct megasas_pd_list {
 750         u16             tid;
 751         u8             driveType;
 752         u8             driveState;
 753 } __packed;
 754
 755  /*
 756  * defines the logical drive reference structure
 757  */
 758 union  MR_LD_REF {
 759         struct {
 760                 u8      targetId;
 761                 u8      reserved;
 762                 __le16     seqNum;
 763         };
 764         __le32     ref;
 765 } __packed;
 766
 767 /*
 768  * defines the logical drive list structure
 769  */
 770 struct MR_LD_LIST {
 771         __le32     ldCount;
 772         __le32     reserved;
 773         struct {
 774                 union MR_LD_REF   ref;
 775                 u8          state;
 776                 u8          reserved[3];
 777                 __le64          size;
 778         } ldList[MAX_LOGICAL_DRIVES_EXT];
 779 } __packed;
 780
 781 struct MR_LD_TARGETID_LIST {
 782         __le32  size;
 783         __le32  count;
 784         u8      pad[3];
 785         u8      targetId[MAX_LOGICAL_DRIVES_EXT];
 786 };
 787
 788 struct MR_HOST_DEVICE_LIST_ENTRY {
 789         struct {
 790                 union {
 791                         struct {
 792 #if defined(__BIG_ENDIAN_BITFIELD)
 793                                 u8 reserved:7;
 794                                 u8 is_sys_pd:1;
 795 #else
 796                                 u8 is_sys_pd:1;
 797                                 u8 reserved:7;
 798 #endif
 799                         } bits;
 800                         u8 byte;
 801                 } u;
 802         } flags;
 803         u8 scsi_type;
 804         __le16 target_id;
 805         u8 reserved[4];
 806         __le64 sas_addr[2];
 807 } __packed;
 808
 809 struct MR_HOST_DEVICE_LIST {
 810         __le32                  size;
 811         __le32                  count;
 812         __le32                  reserved[2];
 813         struct MR_HOST_DEVICE_LIST_ENTRY        host_device_list[1];
 814 } __packed;
 815
 816 #define HOST_DEVICE_LIST_SZ (sizeof(struct MR_HOST_DEVICE_LIST) +              \
 817                               (sizeof(struct MR_HOST_DEVICE_LIST_ENTRY) *      \
 818                               (MEGASAS_MAX_PD + MAX_LOGICAL_DRIVES_EXT - 1)))
 819
 820
 821 /*
 822  * SAS controller properties
 823  */
 824 struct megasas_ctrl_prop {
 825
 826         u16 seq_num;
 827         u16 pred_fail_poll_interval;
 828         u16 intr_throttle_count;
 829         u16 intr_throttle_timeouts;
 830         u8 rebuild_rate;
 831         u8 patrol_read_rate;
 832         u8 bgi_rate;
 833         u8 cc_rate;
 834         u8 recon_rate;
 835         u8 cache_flush_interval;
 836         u8 spinup_drv_count;
 837         u8 spinup_delay;
 838         u8 cluster_enable;
 839         u8 coercion_mode;
 840         u8 alarm_enable;
 841         u8 disable_auto_rebuild;
 842         u8 disable_battery_warn;
 843         u8 ecc_bucket_size;
 844         u16 ecc_bucket_leak_rate;
 845         u8 restore_hotspare_on_insertion;
 846         u8 expose_encl_devices;
 847         u8 maintainPdFailHistory;
 848         u8 disallowHostRequestReordering;
 849         u8 abortCCOnError;
 850         u8 loadBalanceMode;
 851         u8 disableAutoDetectBackplane;
 852
 853         u8 snapVDSpace;
 854
 855         /*
 856         * Add properties that can be controlled by
 857         * a bit in the following structure.
 858         */
 859         struct {
 860 #if   defined(__BIG_ENDIAN_BITFIELD)
 861                 u32     reserved:18;
 862                 u32     enableJBOD:1;
 863                 u32     disableSpinDownHS:1;
 864                 u32     allowBootWithPinnedCache:1;
 865                 u32     disableOnlineCtrlReset:1;
 866                 u32     enableSecretKeyControl:1;
 867                 u32     autoEnhancedImport:1;
 868                 u32     enableSpinDownUnconfigured:1;
 869                 u32     SSDPatrolReadEnabled:1;
 870                 u32     SSDSMARTerEnabled:1;
 871                 u32     disableNCQ:1;
 872                 u32     useFdeOnly:1;
 873                 u32     prCorrectUnconfiguredAreas:1;
 874                 u32     SMARTerEnabled:1;
 875                 u32     copyBackDisabled:1;
 876 #else
 877                 u32     copyBackDisabled:1;
 878                 u32     SMARTerEnabled:1;
 879                 u32     prCorrectUnconfiguredAreas:1;
 880                 u32     useFdeOnly:1;
 881                 u32     disableNCQ:1;
 882                 u32     SSDSMARTerEnabled:1;
 883                 u32     SSDPatrolReadEnabled:1;
 884                 u32     enableSpinDownUnconfigured:1;
 885                 u32     autoEnhancedImport:1;
 886                 u32     enableSecretKeyControl:1;
 887                 u32     disableOnlineCtrlReset:1;
 888                 u32     allowBootWithPinnedCache:1;
 889                 u32     disableSpinDownHS:1;
 890                 u32     enableJBOD:1;
 891                 u32     reserved:18;
 892 #endif
 893         } OnOffProperties;
 894
 895         union {
 896                 u8 autoSnapVDSpace;
 897                 u8 viewSpace;
 898                 struct {
 899 #if   defined(__BIG_ENDIAN_BITFIELD)
 900                         u16 reserved3:9;
 901                         u16 enable_fw_dev_list:1;
 902                         u16 reserved2:1;
 903                         u16 enable_snap_dump:1;
 904                         u16 reserved1:4;
 905 #else
 906                         u16 reserved1:4;
 907                         u16 enable_snap_dump:1;
 908                         u16 reserved2:1;
 909                         u16 enable_fw_dev_list:1;
 910                         u16 reserved3:9;
 911 #endif
 912                 } on_off_properties2;
 913         };
 914         __le16 spinDownTime;
 915         u8  reserved[24];
 916 } __packed;
 917
 918 /*
 919  * SAS controller information
 920  */
 921 struct megasas_ctrl_info {
 922
 923         /*
 924          * PCI device information
 925          */
 926         struct {
 927
 928                 __le16 vendor_id;
 929                 __le16 device_id;
 930                 __le16 sub_vendor_id;
 931                 __le16 sub_device_id;
 932                 u8 reserved[24];
 933
 934         } __attribute__ ((packed)) pci;
 935
 936         /*
 937          * Host interface information
 938          */
 939         struct {
 940
 941                 u8 PCIX:1;
 942                 u8 PCIE:1;
 943                 u8 iSCSI:1;
 944                 u8 SAS_3G:1;
 945                 u8 SRIOV:1;
 946                 u8 reserved_0:3;
 947                 u8 reserved_1[6];
 948                 u8 port_count;
 949                 u64 port_addr[8];
 950
 951         } __attribute__ ((packed)) host_interface;
 952
 953         /*
 954          * Device (backend) interface information
 955          */
 956         struct {
 957
 958                 u8 SPI:1;
 959                 u8 SAS_3G:1;
 960                 u8 SATA_1_5G:1;
 961                 u8 SATA_3G:1;
 962                 u8 reserved_0:4;
 963                 u8 reserved_1[6];
 964                 u8 port_count;
 965                 u64 port_addr[8];
 966
 967         } __attribute__ ((packed)) device_interface;
 968
 969         /*
 970          * List of components residing in flash. All str are null terminated
 971          */
 972         __le32 image_check_word;
 973         __le32 image_component_count;
 974
 975         struct {
 976
 977                 char name[8];
 978                 char version[32];
 979                 char build_date[16];
 980                 char built_time[16];
 981
 982         } __attribute__ ((packed)) image_component[8];
 983
 984         /*
 985          * List of flash components that have been flashed on the card, but
 986          * are not in use, pending reset of the adapter. This list will be
 987          * empty if a flash operation has not occurred. All stings are null
 988          * terminated
 989          */
 990         __le32 pending_image_component_count;
 991
 992         struct {
 993
 994                 char name[8];
 995                 char version[32];
 996                 char build_date[16];
 997                 char build_time[16];
 998
 999         } __attribute__ ((packed)) pending_image_component[8];
1000
1001         u8 max_arms;
1002         u8 max_spans;
1003         u8 max_arrays;
1004         u8 max_lds;
1005
1006         char product_name[80];
1007         char serial_no[32];
1008
1009         /*
1010          * Other physical/controller/operation information. Indicates the
1011          * presence of the hardware
1012          */
1013         struct {
1014
1015                 u32 bbu:1;
1016                 u32 alarm:1;
1017                 u32 nvram:1;
1018                 u32 uart:1;
1019                 u32 reserved:28;
1020
1021         } __attribute__ ((packed)) hw_present;
1022
1023         __le32 current_fw_time;
1024
1025         /*
1026          * Maximum data transfer sizes
1027          */
1028         __le16 max_concurrent_cmds;
1029         __le16 max_sge_count;
1030         __le32 max_request_size;
1031
1032         /*
1033          * Logical and physical device counts
1034          */
1035         __le16 ld_present_count;
1036         __le16 ld_degraded_count;
1037         __le16 ld_offline_count;
1038
1039         __le16 pd_present_count;
1040         __le16 pd_disk_present_count;
1041         __le16 pd_disk_pred_failure_count;
1042         __le16 pd_disk_failed_count;
1043
1044         /*
1045          * Memory size information
1046          */
1047         __le16 nvram_size;
1048         __le16 memory_size;
1049         __le16 flash_size;
1050
1051         /*
1052          * Error counters
1053          */
1054         __le16 mem_correctable_error_count;
1055         __le16 mem_uncorrectable_error_count;
1056
1057         /*
1058          * Cluster information
1059          */
1060         u8 cluster_permitted;
1061         u8 cluster_active;
1062
1063         /*
1064          * Additional max data transfer sizes
1065          */
1066         __le16 max_strips_per_io;
1067
1068         /*
1069          * Controller capabilities structures
1070          */
1071         struct {
1072
1073                 u32 raid_level_0:1;
1074                 u32 raid_level_1:1;
1075                 u32 raid_level_5:1;
1076                 u32 raid_level_1E:1;
1077                 u32 raid_level_6:1;
1078                 u32 reserved:27;
1079
1080         } __attribute__ ((packed)) raid_levels;
1081
1082         struct {
1083
1084                 u32 rbld_rate:1;
1085                 u32 cc_rate:1;
1086                 u32 bgi_rate:1;
1087                 u32 recon_rate:1;
1088                 u32 patrol_rate:1;
1089                 u32 alarm_control:1;
1090                 u32 cluster_supported:1;
1091                 u32 bbu:1;
1092                 u32 spanning_allowed:1;
1093                 u32 dedicated_hotspares:1;
1094                 u32 revertible_hotspares:1;
1095                 u32 foreign_config_import:1;
1096                 u32 self_diagnostic:1;
1097                 u32 mixed_redundancy_arr:1;
1098                 u32 global_hot_spares:1;
1099                 u32 reserved:17;
1100
1101         } __attribute__ ((packed)) adapter_operations;
1102
1103         struct {
1104
1105                 u32 read_policy:1;
1106                 u32 write_policy:1;
1107                 u32 io_policy:1;
1108                 u32 access_policy:1;
1109                 u32 disk_cache_policy:1;
1110                 u32 reserved:27;
1111
1112         } __attribute__ ((packed)) ld_operations;
1113
1114         struct {
1115
1116                 u8 min;
1117                 u8 max;
1118                 u8 reserved[2];
1119
1120         } __attribute__ ((packed)) stripe_sz_ops;
1121
1122         struct {
1123
1124                 u32 force_online:1;
1125                 u32 force_offline:1;
1126                 u32 force_rebuild:1;
1127                 u32 reserved:29;
1128
1129         } __attribute__ ((packed)) pd_operations;
1130
1131         struct {
1132
1133                 u32 ctrl_supports_sas:1;
1134                 u32 ctrl_supports_sata:1;
1135                 u32 allow_mix_in_encl:1;
1136                 u32 allow_mix_in_ld:1;
1137                 u32 allow_sata_in_cluster:1;
1138                 u32 reserved:27;
1139
1140         } __attribute__ ((packed)) pd_mix_support;
1141
1142         /*
1143          * Define ECC single-bit-error bucket information
1144          */
1145         u8 ecc_bucket_count;
1146         u8 reserved_2[11];
1147
1148         /*
1149          * Include the controller properties (changeable items)
1150          */
1151         struct megasas_ctrl_prop properties;
1152
1153         /*
1154          * Define FW pkg version (set in envt v'bles on OEM basis)
1155          */
1156         char package_version[0x60];
1157
1158
1159         /*
1160         * If adapterOperations.supportMoreThan8Phys is set,
1161         * and deviceInterface.portCount is greater than 8,
1162         * SAS Addrs for first 8 ports shall be populated in
1163         * deviceInterface.portAddr, and the rest shall be
1164         * populated in deviceInterfacePortAddr2.
1165         */
1166         __le64      deviceInterfacePortAddr2[8]; /*6a0h */
1167         u8          reserved3[128];              /*6e0h */
1168
1169         struct {                                /*760h */
1170                 u16 minPdRaidLevel_0:4;
1171                 u16 maxPdRaidLevel_0:12;
1172
1173                 u16 minPdRaidLevel_1:4;
1174                 u16 maxPdRaidLevel_1:12;
1175
1176                 u16 minPdRaidLevel_5:4;
1177                 u16 maxPdRaidLevel_5:12;
1178
1179                 u16 minPdRaidLevel_1E:4;
1180                 u16 maxPdRaidLevel_1E:12;
1181
1182                 u16 minPdRaidLevel_6:4;
1183                 u16 maxPdRaidLevel_6:12;
1184
1185                 u16 minPdRaidLevel_10:4;
1186                 u16 maxPdRaidLevel_10:12;
1187
1188                 u16 minPdRaidLevel_50:4;
1189                 u16 maxPdRaidLevel_50:12;
1190
1191                 u16 minPdRaidLevel_60:4;
1192                 u16 maxPdRaidLevel_60:12;
1193
1194                 u16 minPdRaidLevel_1E_RLQ0:4;
1195                 u16 maxPdRaidLevel_1E_RLQ0:12;
1196
1197                 u16 minPdRaidLevel_1E0_RLQ0:4;
1198                 u16 maxPdRaidLevel_1E0_RLQ0:12;
1199
1200                 u16 reserved[6];
1201         } pdsForRaidLevels;
1202
1203         __le16 maxPds;                          /*780h */
1204         __le16 maxDedHSPs;                      /*782h */
1205         __le16 maxGlobalHSP;                    /*784h */
1206         __le16 ddfSize;                         /*786h */
1207         u8  maxLdsPerArray;                     /*788h */
1208         u8  partitionsInDDF;                    /*789h */
1209         u8  lockKeyBinding;                     /*78ah */
1210         u8  maxPITsPerLd;                       /*78bh */
1211         u8  maxViewsPerLd;                      /*78ch */
1212         u8  maxTargetId;                        /*78dh */
1213         __le16 maxBvlVdSize;                    /*78eh */
1214
1215         __le16 maxConfigurableSSCSize;          /*790h */
1216         __le16 currentSSCsize;                  /*792h */
1217
1218         char    expanderFwVersion[12];          /*794h */
1219
1220         __le16 PFKTrialTimeRemaining;           /*7A0h */
1221
1222         __le16 cacheMemorySize;                 /*7A2h */
1223
1224         struct {                                /*7A4h */
1225 #if   defined(__BIG_ENDIAN_BITFIELD)
1226                 u32     reserved:5;
1227                 u32     activePassive:2;
1228                 u32     supportConfigAutoBalance:1;
1229                 u32     mpio:1;
1230                 u32     supportDataLDonSSCArray:1;
1231                 u32     supportPointInTimeProgress:1;
1232                 u32     supportUnevenSpans:1;
1233                 u32     dedicatedHotSparesLimited:1;
1234                 u32     headlessMode:1;
1235                 u32     supportEmulatedDrives:1;
1236                 u32     supportResetNow:1;
1237                 u32     realTimeScheduler:1;
1238                 u32     supportSSDPatrolRead:1;
1239                 u32     supportPerfTuning:1;
1240                 u32     disableOnlinePFKChange:1;
1241                 u32     supportJBOD:1;
1242                 u32     supportBootTimePFKChange:1;
1243                 u32     supportSetLinkSpeed:1;
1244                 u32     supportEmergencySpares:1;
1245                 u32     supportSuspendResumeBGops:1;
1246                 u32     blockSSDWriteCacheChange:1;
1247                 u32     supportShieldState:1;
1248                 u32     supportLdBBMInfo:1;
1249                 u32     supportLdPIType3:1;
1250                 u32     supportLdPIType2:1;
1251                 u32     supportLdPIType1:1;
1252                 u32     supportPIcontroller:1;
1253 #else
1254                 u32     supportPIcontroller:1;
1255                 u32     supportLdPIType1:1;
1256                 u32     supportLdPIType2:1;
1257                 u32     supportLdPIType3:1;
1258                 u32     supportLdBBMInfo:1;
1259                 u32     supportShieldState:1;
1260                 u32     blockSSDWriteCacheChange:1;
1261                 u32     supportSuspendResumeBGops:1;
1262                 u32     supportEmergencySpares:1;
1263                 u32     supportSetLinkSpeed:1;
1264                 u32     supportBootTimePFKChange:1;
1265                 u32     supportJBOD:1;
1266                 u32     disableOnlinePFKChange:1;
1267                 u32     supportPerfTuning:1;
1268                 u32     supportSSDPatrolRead:1;
1269                 u32     realTimeScheduler:1;
1270
1271                 u32     supportResetNow:1;
1272                 u32     supportEmulatedDrives:1;
1273                 u32     headlessMode:1;
1274                 u32     dedicatedHotSparesLimited:1;
1275
1276
1277                 u32     supportUnevenSpans:1;
1278                 u32     supportPointInTimeProgress:1;
1279                 u32     supportDataLDonSSCArray:1;
1280                 u32     mpio:1;
1281                 u32     supportConfigAutoBalance:1;
1282                 u32     activePassive:2;
1283                 u32     reserved:5;
1284 #endif
1285         } adapterOperations2;
1286
1287         u8  driverVersion[32];                  /*7A8h */
1288         u8  maxDAPdCountSpinup60;               /*7C8h */
1289         u8  temperatureROC;                     /*7C9h */
1290         u8  temperatureCtrl;                    /*7CAh */
1291         u8  reserved4;                          /*7CBh */
1292         __le16 maxConfigurablePds;              /*7CCh */
1293
1294
1295         u8  reserved5[2];                       /*0x7CDh */
1296
1297         /*
1298         * HA cluster information
1299         */
1300         struct {
1301 #if defined(__BIG_ENDIAN_BITFIELD)
1302                 u32     reserved:25;
1303                 u32     passive:1;
1304                 u32     premiumFeatureMismatch:1;
1305                 u32     ctrlPropIncompatible:1;
1306                 u32     fwVersionMismatch:1;
1307                 u32     hwIncompatible:1;
1308                 u32     peerIsIncompatible:1;
1309                 u32     peerIsPresent:1;
1310 #else
1311                 u32     peerIsPresent:1;
1312                 u32     peerIsIncompatible:1;
1313                 u32     hwIncompatible:1;
1314                 u32     fwVersionMismatch:1;
1315                 u32     ctrlPropIncompatible:1;
1316                 u32     premiumFeatureMismatch:1;
1317                 u32     passive:1;
1318                 u32     reserved:25;
1319 #endif
1320         } cluster;
1321
1322         char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1323         struct {
1324                 u8  maxVFsSupported;            /*0x7E4*/
1325                 u8  numVFsEnabled;              /*0x7E5*/
1326                 u8  requestorId;                /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1327                 u8  reserved;                   /*0x7E7*/
1328         } iov;
1329
1330         struct {
1331 #if defined(__BIG_ENDIAN_BITFIELD)
1332                 u32     reserved:7;
1333                 u32     useSeqNumJbodFP:1;
1334                 u32     supportExtendedSSCSize:1;
1335                 u32     supportDiskCacheSettingForSysPDs:1;
1336                 u32     supportCPLDUpdate:1;
1337                 u32     supportTTYLogCompression:1;
1338                 u32     discardCacheDuringLDDelete:1;
1339                 u32     supportSecurityonJBOD:1;
1340                 u32     supportCacheBypassModes:1;
1341                 u32     supportDisableSESMonitoring:1;
1342                 u32     supportForceFlash:1;
1343                 u32     supportNVDRAM:1;
1344                 u32     supportDrvActivityLEDSetting:1;
1345                 u32     supportAllowedOpsforDrvRemoval:1;
1346                 u32     supportHOQRebuild:1;
1347                 u32     supportForceTo512e:1;
1348                 u32     supportNVCacheErase:1;
1349                 u32     supportDebugQueue:1;
1350                 u32     supportSwZone:1;
1351                 u32     supportCrashDump:1;
1352                 u32     supportMaxExtLDs:1;
1353                 u32     supportT10RebuildAssist:1;
1354                 u32     supportDisableImmediateIO:1;
1355                 u32     supportThermalPollInterval:1;
1356                 u32     supportPersonalityChange:2;
1357 #else
1358                 u32     supportPersonalityChange:2;
1359                 u32     supportThermalPollInterval:1;
1360                 u32     supportDisableImmediateIO:1;
1361                 u32     supportT10RebuildAssist:1;
1362                 u32     supportMaxExtLDs:1;
1363                 u32     supportCrashDump:1;
1364                 u32     supportSwZone:1;
1365                 u32     supportDebugQueue:1;
1366                 u32     supportNVCacheErase:1;
1367                 u32     supportForceTo512e:1;
1368                 u32     supportHOQRebuild:1;
1369                 u32     supportAllowedOpsforDrvRemoval:1;
1370                 u32     supportDrvActivityLEDSetting:1;
1371                 u32     supportNVDRAM:1;
1372                 u32     supportForceFlash:1;
1373                 u32     supportDisableSESMonitoring:1;
1374                 u32     supportCacheBypassModes:1;
1375                 u32     supportSecurityonJBOD:1;
1376                 u32     discardCacheDuringLDDelete:1;
1377                 u32     supportTTYLogCompression:1;
1378                 u32     supportCPLDUpdate:1;
1379                 u32     supportDiskCacheSettingForSysPDs:1;
1380                 u32     supportExtendedSSCSize:1;
1381                 u32     useSeqNumJbodFP:1;
1382                 u32     reserved:7;
1383 #endif
1384         } adapterOperations3;
1385
1386         struct {
1387 #if defined(__BIG_ENDIAN_BITFIELD)
1388         u8 reserved:7;
1389         /* Indicates whether the CPLD image is part of
1390          *  the package and stored in flash
1391          */
1392         u8 cpld_in_flash:1;
1393 #else
1394         u8 cpld_in_flash:1;
1395         u8 reserved:7;
1396 #endif
1397         u8 reserved1[3];
1398         /* Null terminated string. Has the version
1399          *  information if cpld_in_flash = FALSE
1400          */
1401         u8 userCodeDefinition[12];
1402         } cpld;  /* Valid only if upgradableCPLD is TRUE */
1403
1404         struct {
1405         #if defined(__BIG_ENDIAN_BITFIELD)
1406                 u16 reserved:2;
1407                 u16 support_nvme_passthru:1;
1408                 u16 support_pl_debug_info:1;
1409                 u16 support_flash_comp_info:1;
1410                 u16 support_host_info:1;
1411                 u16 support_dual_fw_update:1;
1412                 u16 support_ssc_rev3:1;
1413                 u16 fw_swaps_bbu_vpd_info:1;
1414                 u16 support_pd_map_target_id:1;
1415                 u16 support_ses_ctrl_in_multipathcfg:1;
1416                 u16 image_upload_supported:1;
1417                 u16 support_encrypted_mfc:1;
1418                 u16 supported_enc_algo:1;
1419                 u16 support_ibutton_less:1;
1420                 u16 ctrl_info_ext_supported:1;
1421         #else
1422
1423                 u16 ctrl_info_ext_supported:1;
1424                 u16 support_ibutton_less:1;
1425                 u16 supported_enc_algo:1;
1426                 u16 support_encrypted_mfc:1;
1427                 u16 image_upload_supported:1;
1428                 /* FW supports LUN based association and target port based */
1429                 u16 support_ses_ctrl_in_multipathcfg:1;
1430                 /* association for the SES device connected in multipath mode */
1431                 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1432                 u16 support_pd_map_target_id:1;
1433                 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1434                  *  provide the data in little endian order
1435                  */
1436                 u16 fw_swaps_bbu_vpd_info:1;
1437                 u16 support_ssc_rev3:1;
1438                 /* FW supports CacheCade 3.0, only one SSCD creation allowed */
1439                 u16 support_dual_fw_update:1;
1440                 /* FW supports dual firmware update feature */
1441                 u16 support_host_info:1;
1442                 /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */
1443                 u16 support_flash_comp_info:1;
1444                 /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */
1445                 u16 support_pl_debug_info:1;
1446                 /* FW supports retrieval of PL debug information through apps */
1447                 u16 support_nvme_passthru:1;
1448                 /* FW supports NVMe passthru commands */
1449                 u16 reserved:2;
1450         #endif
1451                 } adapter_operations4;
1452         u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1453
1454         u32 size;
1455         u32 pad1;
1456
1457         u8 reserved6[64];
1458
1459         struct {
1460         #if defined(__BIG_ENDIAN_BITFIELD)
1461                 u32 reserved:19;
1462                 u32 support_pci_lane_margining: 1;
1463                 u32 support_psoc_update:1;
1464                 u32 support_force_personality_change:1;
1465                 u32 support_fde_type_mix:1;
1466                 u32 support_snap_dump:1;
1467                 u32 support_nvme_tm:1;
1468                 u32 support_oce_only:1;
1469                 u32 support_ext_mfg_vpd:1;
1470                 u32 support_pcie:1;
1471                 u32 support_cvhealth_info:1;
1472                 u32 support_profile_change:2;
1473                 u32 mr_config_ext2_supported:1;
1474         #else
1475                 u32 mr_config_ext2_supported:1;
1476                 u32 support_profile_change:2;
1477                 u32 support_cvhealth_info:1;
1478                 u32 support_pcie:1;
1479                 u32 support_ext_mfg_vpd:1;
1480                 u32 support_oce_only:1;
1481                 u32 support_nvme_tm:1;
1482                 u32 support_snap_dump:1;
1483                 u32 support_fde_type_mix:1;
1484                 u32 support_force_personality_change:1;
1485                 u32 support_psoc_update:1;
1486                 u32 support_pci_lane_margining: 1;
1487                 u32 reserved:19;
1488         #endif
1489         } adapter_operations5;
1490
1491         u32 rsvdForAdptOp[63];
1492
1493         u8 reserved7[3];
1494
1495         u8 TaskAbortTO; /* Timeout value in seconds used by Abort Task TM */
1496         u8 MaxResetTO;  /* Max Supported Reset timeout in seconds. */
1497         u8 reserved8[3];
1498 } __packed;
1499
1500 /*
1501  * ===============================
1502  * MegaRAID SAS driver definitions
1503  * ===============================
1504  */
1505 #define MEGASAS_MAX_PD_CHANNELS                 2
1506 #define MEGASAS_MAX_LD_CHANNELS                 2
1507 #define MEGASAS_MAX_CHANNELS                    (MEGASAS_MAX_PD_CHANNELS + \
1508                                                 MEGASAS_MAX_LD_CHANNELS)
1509 #define MEGASAS_MAX_DEV_PER_CHANNEL             128
1510 #define MEGASAS_DEFAULT_INIT_ID                 -1
1511 #define MEGASAS_MAX_LUN                         8
1512 #define MEGASAS_DEFAULT_CMD_PER_LUN             256
1513 #define MEGASAS_MAX_PD                          (MEGASAS_MAX_PD_CHANNELS * \
1514                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1515 #define MEGASAS_MAX_LD_IDS                      (MEGASAS_MAX_LD_CHANNELS * \
1516                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1517
1518 #define MEGASAS_MAX_SECTORS                    (2*1024)
1519 #define MEGASAS_MAX_SECTORS_IEEE                (2*128)
1520 #define MEGASAS_DBG_LVL                         1
1521
1522 #define MEGASAS_FW_BUSY                         1
1523
1524 /* Driver's internal Logging levels*/
1525 #define OCR_DEBUG    (1 << 0)
1526 #define TM_DEBUG     (1 << 1)
1527 #define LD_PD_DEBUG    (1 << 2)
1528
1529 #define SCAN_PD_CHANNEL 0x1
1530 #define SCAN_VD_CHANNEL 0x2
1531
1532 #define MEGASAS_KDUMP_QUEUE_DEPTH               100
1533 #define MR_LARGE_IO_MIN_SIZE                    (32 * 1024)
1534 #define MR_R1_LDIO_PIGGYBACK_DEFAULT            4
1535
1536 enum MR_SCSI_CMD_TYPE {
1537         READ_WRITE_LDIO = 0,
1538         NON_READ_WRITE_LDIO = 1,
1539         READ_WRITE_SYSPDIO = 2,
1540         NON_READ_WRITE_SYSPDIO = 3,
1541 };
1542
1543 enum DCMD_TIMEOUT_ACTION {
1544         INITIATE_OCR = 0,
1545         KILL_ADAPTER = 1,
1546         IGNORE_TIMEOUT = 2,
1547 };
1548
1549 enum FW_BOOT_CONTEXT {
1550         PROBE_CONTEXT = 0,
1551         OCR_CONTEXT = 1,
1552 };
1553
1554 /* Frame Type */
1555 #define IO_FRAME                                0
1556 #define PTHRU_FRAME                             1
1557
1558 /*
1559  * When SCSI mid-layer calls driver's reset routine, driver waits for
1560  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1561  * that the driver cannot _actually_ abort or reset pending commands. While
1562  * it is waiting for the commands to complete, it prints a diagnostic message
1563  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1564  */
1565 #define MEGASAS_RESET_WAIT_TIME                 180
1566 #define MEGASAS_INTERNAL_CMD_WAIT_TIME          180
1567 #define MEGASAS_RESET_NOTICE_INTERVAL           5
1568 #define MEGASAS_IOCTL_CMD                       0
1569 #define MEGASAS_DEFAULT_CMD_TIMEOUT             90
1570 #define MEGASAS_THROTTLE_QUEUE_DEPTH            16
1571 #define MEGASAS_DEFAULT_TM_TIMEOUT              50
1572 /*
1573  * FW reports the maximum of number of commands that it can accept (maximum
1574  * commands that can be outstanding) at any time. The driver must report a
1575  * lower number to the mid layer because it can issue a few internal commands
1576  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1577  * is shown below
1578  */
1579 #define MEGASAS_INT_CMDS                        32
1580 #define MEGASAS_SKINNY_INT_CMDS                 5
1581 #define MEGASAS_FUSION_INTERNAL_CMDS            8
1582 #define MEGASAS_FUSION_IOCTL_CMDS               3
1583 #define MEGASAS_MFI_IOCTL_CMDS                  27
1584
1585 #define MEGASAS_MAX_MSIX_QUEUES                 128
1586 /*
1587  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1588  * SGLs based on the size of dma_addr_t
1589  */
1590 #define IS_DMA64                                (sizeof(dma_addr_t) == 8)
1591
1592 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT                0x00000001
1593
1594 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
1595 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE             0x00000002
1596 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
1597
1598 #define MFI_OB_INTR_STATUS_MASK                 0x00000002
1599 #define MFI_POLL_TIMEOUT_SECS                   60
1600 #define MFI_IO_TIMEOUT_SECS                     180
1601 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF     (5 * HZ)
1602 #define MEGASAS_OCR_SETTLE_TIME_VF              (1000 * 30)
1603 #define MEGASAS_SRIOV_MAX_RESET_TRIES_VF        1
1604 #define MEGASAS_ROUTINE_WAIT_TIME_VF            300
1605 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
1606 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
1607 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          (0x00000001 | 0x00000004)
1608 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
1609 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
1610
1611 #define MFI_1068_PCSR_OFFSET                    0x84
1612 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
1613 #define MFI_1068_FW_READY                       0xDDDD0000
1614
1615 #define MR_MAX_REPLY_QUEUES_OFFSET              0X0000001F
1616 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET          0X003FC000
1617 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
1618 #define MR_MAX_MSIX_REG_ARRAY                   16
1619 #define MR_RDPQ_MODE_OFFSET                     0X00800000
1620
1621 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT       16
1622 #define MR_MAX_RAID_MAP_SIZE_MASK               0x1FF
1623 #define MR_MIN_MAP_SIZE                         0x10000
1624 /* 64k */
1625
1626 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET         0X01000000
1627
1628 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET     (1 << 24)
1629
1630 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET         (1 << 25)
1631 #define MR_INTR_COALESCING_SUPPORT_OFFSET       (1 << 26)
1632
1633 #define MEGASAS_WATCHDOG_THREAD_INTERVAL        1000
1634 #define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS         20
1635 #define MEGASAS_WATCHDOG_WAIT_COUNT             50
1636
1637 enum MR_ADAPTER_TYPE {
1638         MFI_SERIES = 1,
1639         THUNDERBOLT_SERIES = 2,
1640         INVADER_SERIES = 3,
1641         VENTURA_SERIES = 4,
1642         AERO_SERIES = 5,
1643 };
1644
1645 /*
1646 * register set for both 1068 and 1078 controllers
1647 * structure extended for 1078 registers
1648 */
1649
1650 struct megasas_register_set {
1651         u32     doorbell;                       /*0000h*/
1652         u32     fusion_seq_offset;              /*0004h*/
1653         u32     fusion_host_diag;               /*0008h*/
1654         u32     reserved_01;                    /*000Ch*/
1655
1656         u32     inbound_msg_0;                  /*0010h*/
1657         u32     inbound_msg_1;                  /*0014h*/
1658         u32     outbound_msg_0;                 /*0018h*/
1659         u32     outbound_msg_1;                 /*001Ch*/
1660
1661         u32     inbound_doorbell;               /*0020h*/
1662         u32     inbound_intr_status;            /*0024h*/
1663         u32     inbound_intr_mask;              /*0028h*/
1664
1665         u32     outbound_doorbell;              /*002Ch*/
1666         u32     outbound_intr_status;           /*0030h*/
1667         u32     outbound_intr_mask;             /*0034h*/
1668
1669         u32     reserved_1[2];                  /*0038h*/
1670
1671         u32     inbound_queue_port;             /*0040h*/
1672         u32     outbound_queue_port;            /*0044h*/
1673
1674         u32     reserved_2[9];                  /*0048h*/
1675         u32     reply_post_host_index;          /*006Ch*/
1676         u32     reserved_2_2[12];               /*0070h*/
1677
1678         u32     outbound_doorbell_clear;        /*00A0h*/
1679
1680         u32     reserved_3[3];                  /*00A4h*/
1681
1682         u32     outbound_scratch_pad_0;         /*00B0h*/
1683         u32     outbound_scratch_pad_1;         /*00B4h*/
1684         u32     outbound_scratch_pad_2;         /*00B8h*/
1685         u32     outbound_scratch_pad_3;         /*00BCh*/
1686
1687         u32     inbound_low_queue_port ;        /*00C0h*/
1688
1689         u32     inbound_high_queue_port ;       /*00C4h*/
1690
1691         u32 inbound_single_queue_port;  /*00C8h*/
1692         u32     res_6[11];                      /*CCh*/
1693         u32     host_diag;
1694         u32     seq_offset;
1695         u32     index_registers[807];           /*00CCh*/
1696 } __attribute__ ((packed));
1697
1698 struct megasas_sge32 {
1699
1700         __le32 phys_addr;
1701         __le32 length;
1702
1703 } __attribute__ ((packed));
1704
1705 struct megasas_sge64 {
1706
1707         __le64 phys_addr;
1708         __le32 length;
1709
1710 } __attribute__ ((packed));
1711
1712 struct megasas_sge_skinny {
1713         __le64 phys_addr;
1714         __le32 length;
1715         __le32 flag;
1716 } __packed;
1717
1718 union megasas_sgl {
1719
1720         struct megasas_sge32 sge32[1];
1721         struct megasas_sge64 sge64[1];
1722         struct megasas_sge_skinny sge_skinny[1];
1723
1724 } __attribute__ ((packed));
1725
1726 struct megasas_header {
1727
1728         u8 cmd;                 /*00h */
1729         u8 sense_len;           /*01h */
1730         u8 cmd_status;          /*02h */
1731         u8 scsi_status;         /*03h */
1732
1733         u8 target_id;           /*04h */
1734         u8 lun;                 /*05h */
1735         u8 cdb_len;             /*06h */
1736         u8 sge_count;           /*07h */
1737
1738         __le32 context;         /*08h */
1739         __le32 pad_0;           /*0Ch */
1740
1741         __le16 flags;           /*10h */
1742         __le16 timeout;         /*12h */
1743         __le32 data_xferlen;    /*14h */
1744
1745 } __attribute__ ((packed));
1746
1747 union megasas_sgl_frame {
1748
1749         struct megasas_sge32 sge32[8];
1750         struct megasas_sge64 sge64[5];
1751
1752 } __attribute__ ((packed));
1753
1754 typedef union _MFI_CAPABILITIES {
1755         struct {
1756 #if   defined(__BIG_ENDIAN_BITFIELD)
1757         u32     reserved:16;
1758         u32     support_fw_exposed_dev_list:1;
1759         u32     support_nvme_passthru:1;
1760         u32     support_64bit_mode:1;
1761         u32 support_pd_map_target_id:1;
1762         u32     support_qd_throttling:1;
1763         u32     support_fp_rlbypass:1;
1764         u32     support_vfid_in_ioframe:1;
1765         u32     support_ext_io_size:1;
1766         u32             support_ext_queue_depth:1;
1767         u32     security_protocol_cmds_fw:1;
1768         u32     support_core_affinity:1;
1769         u32     support_ndrive_r1_lb:1;
1770         u32             support_max_255lds:1;
1771         u32             support_fastpath_wb:1;
1772         u32     support_additional_msix:1;
1773         u32     support_fp_remote_lun:1;
1774 #else
1775         u32     support_fp_remote_lun:1;
1776         u32     support_additional_msix:1;
1777         u32             support_fastpath_wb:1;
1778         u32             support_max_255lds:1;
1779         u32     support_ndrive_r1_lb:1;
1780         u32     support_core_affinity:1;
1781         u32     security_protocol_cmds_fw:1;
1782         u32             support_ext_queue_depth:1;
1783         u32     support_ext_io_size:1;
1784         u32     support_vfid_in_ioframe:1;
1785         u32     support_fp_rlbypass:1;
1786         u32     support_qd_throttling:1;
1787         u32     support_pd_map_target_id:1;
1788         u32     support_64bit_mode:1;
1789         u32     support_nvme_passthru:1;
1790         u32     support_fw_exposed_dev_list:1;
1791         u32     reserved:16;
1792 #endif
1793         } mfi_capabilities;
1794         __le32          reg;
1795 } MFI_CAPABILITIES;
1796
1797 struct megasas_init_frame {
1798
1799         u8 cmd;                 /*00h */
1800         u8 reserved_0;          /*01h */
1801         u8 cmd_status;          /*02h */
1802
1803         u8 reserved_1;          /*03h */
1804         MFI_CAPABILITIES driver_operations; /*04h*/
1805
1806         __le32 context;         /*08h */
1807         __le32 pad_0;           /*0Ch */
1808
1809         __le16 flags;           /*10h */
1810         __le16 replyqueue_mask;         /*12h */
1811         __le32 data_xfer_len;   /*14h */
1812
1813         __le32 queue_info_new_phys_addr_lo;     /*18h */
1814         __le32 queue_info_new_phys_addr_hi;     /*1Ch */
1815         __le32 queue_info_old_phys_addr_lo;     /*20h */
1816         __le32 queue_info_old_phys_addr_hi;     /*24h */
1817         __le32 reserved_4[2];   /*28h */
1818         __le32 system_info_lo;      /*30h */
1819         __le32 system_info_hi;      /*34h */
1820         __le32 reserved_5[2];   /*38h */
1821
1822 } __attribute__ ((packed));
1823
1824 struct megasas_init_queue_info {
1825
1826         __le32 init_flags;              /*00h */
1827         __le32 reply_queue_entries;     /*04h */
1828
1829         __le32 reply_queue_start_phys_addr_lo;  /*08h */
1830         __le32 reply_queue_start_phys_addr_hi;  /*0Ch */
1831         __le32 producer_index_phys_addr_lo;     /*10h */
1832         __le32 producer_index_phys_addr_hi;     /*14h */
1833         __le32 consumer_index_phys_addr_lo;     /*18h */
1834         __le32 consumer_index_phys_addr_hi;     /*1Ch */
1835
1836 } __attribute__ ((packed));
1837
1838 struct megasas_io_frame {
1839
1840         u8 cmd;                 /*00h */
1841         u8 sense_len;           /*01h */
1842         u8 cmd_status;          /*02h */
1843         u8 scsi_status;         /*03h */
1844
1845         u8 target_id;           /*04h */
1846         u8 access_byte;         /*05h */
1847         u8 reserved_0;          /*06h */
1848         u8 sge_count;           /*07h */
1849
1850         __le32 context;         /*08h */
1851         __le32 pad_0;           /*0Ch */
1852
1853         __le16 flags;           /*10h */
1854         __le16 timeout;         /*12h */
1855         __le32 lba_count;       /*14h */
1856
1857         __le32 sense_buf_phys_addr_lo;  /*18h */
1858         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1859
1860         __le32 start_lba_lo;    /*20h */
1861         __le32 start_lba_hi;    /*24h */
1862
1863         union megasas_sgl sgl;  /*28h */
1864
1865 } __attribute__ ((packed));
1866
1867 struct megasas_pthru_frame {
1868
1869         u8 cmd;                 /*00h */
1870         u8 sense_len;           /*01h */
1871         u8 cmd_status;          /*02h */
1872         u8 scsi_status;         /*03h */
1873
1874         u8 target_id;           /*04h */
1875         u8 lun;                 /*05h */
1876         u8 cdb_len;             /*06h */
1877         u8 sge_count;           /*07h */
1878
1879         __le32 context;         /*08h */
1880         __le32 pad_0;           /*0Ch */
1881
1882         __le16 flags;           /*10h */
1883         __le16 timeout;         /*12h */
1884         __le32 data_xfer_len;   /*14h */
1885
1886         __le32 sense_buf_phys_addr_lo;  /*18h */
1887         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1888
1889         u8 cdb[16];             /*20h */
1890         union megasas_sgl sgl;  /*30h */
1891
1892 } __attribute__ ((packed));
1893
1894 struct megasas_dcmd_frame {
1895
1896         u8 cmd;                 /*00h */
1897         u8 reserved_0;          /*01h */
1898         u8 cmd_status;          /*02h */
1899         u8 reserved_1[4];       /*03h */
1900         u8 sge_count;           /*07h */
1901
1902         __le32 context;         /*08h */
1903         __le32 pad_0;           /*0Ch */
1904
1905         __le16 flags;           /*10h */
1906         __le16 timeout;         /*12h */
1907
1908         __le32 data_xfer_len;   /*14h */
1909         __le32 opcode;          /*18h */
1910
1911         union {                 /*1Ch */
1912                 u8 b[12];
1913                 __le16 s[6];
1914                 __le32 w[3];
1915         } mbox;
1916
1917         union megasas_sgl sgl;  /*28h */
1918
1919 } __attribute__ ((packed));
1920
1921 struct megasas_abort_frame {
1922
1923         u8 cmd;                 /*00h */
1924         u8 reserved_0;          /*01h */
1925         u8 cmd_status;          /*02h */
1926
1927         u8 reserved_1;          /*03h */
1928         __le32 reserved_2;      /*04h */
1929
1930         __le32 context;         /*08h */
1931         __le32 pad_0;           /*0Ch */
1932
1933         __le16 flags;           /*10h */
1934         __le16 reserved_3;      /*12h */
1935         __le32 reserved_4;      /*14h */
1936
1937         __le32 abort_context;   /*18h */
1938         __le32 pad_1;           /*1Ch */
1939
1940         __le32 abort_mfi_phys_addr_lo;  /*20h */
1941         __le32 abort_mfi_phys_addr_hi;  /*24h */
1942
1943         __le32 reserved_5[6];   /*28h */
1944
1945 } __attribute__ ((packed));
1946
1947 struct megasas_smp_frame {
1948
1949         u8 cmd;                 /*00h */
1950         u8 reserved_1;          /*01h */
1951         u8 cmd_status;          /*02h */
1952         u8 connection_status;   /*03h */
1953
1954         u8 reserved_2[3];       /*04h */
1955         u8 sge_count;           /*07h */
1956
1957         __le32 context;         /*08h */
1958         __le32 pad_0;           /*0Ch */
1959
1960         __le16 flags;           /*10h */
1961         __le16 timeout;         /*12h */
1962
1963         __le32 data_xfer_len;   /*14h */
1964         __le64 sas_addr;        /*18h */
1965
1966         union {
1967                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: req */
1968                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: req */
1969         } sgl;
1970
1971 } __attribute__ ((packed));
1972
1973 struct megasas_stp_frame {
1974
1975         u8 cmd;                 /*00h */
1976         u8 reserved_1;          /*01h */
1977         u8 cmd_status;          /*02h */
1978         u8 reserved_2;          /*03h */
1979
1980         u8 target_id;           /*04h */
1981         u8 reserved_3[2];       /*05h */
1982         u8 sge_count;           /*07h */
1983
1984         __le32 context;         /*08h */
1985         __le32 pad_0;           /*0Ch */
1986
1987         __le16 flags;           /*10h */
1988         __le16 timeout;         /*12h */
1989
1990         __le32 data_xfer_len;   /*14h */
1991
1992         __le16 fis[10];         /*18h */
1993         __le32 stp_flags;
1994
1995         union {
1996                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: data */
1997                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: data */
1998         } sgl;
1999
2000 } __attribute__ ((packed));
2001
2002 union megasas_frame {
2003
2004         struct megasas_header hdr;
2005         struct megasas_init_frame init;
2006         struct megasas_io_frame io;
2007         struct megasas_pthru_frame pthru;
2008         struct megasas_dcmd_frame dcmd;
2009         struct megasas_abort_frame abort;
2010         struct megasas_smp_frame smp;
2011         struct megasas_stp_frame stp;
2012
2013         u8 raw_bytes[64];
2014 };
2015
2016 /**
2017  * struct MR_PRIV_DEVICE - sdev private hostdata
2018  * @is_tm_capable: firmware managed tm_capable flag
2019  * @tm_busy: TM request is in progress
2020  */
2021 struct MR_PRIV_DEVICE {
2022         bool is_tm_capable;
2023         bool tm_busy;
2024         atomic_t r1_ldio_hint;
2025         u8 interface_type;
2026         u8 task_abort_tmo;
2027         u8 target_reset_tmo;
2028 };
2029 struct megasas_cmd;
2030
2031 union megasas_evt_class_locale {
2032
2033         struct {
2034 #ifndef __BIG_ENDIAN_BITFIELD
2035                 u16 locale;
2036                 u8 reserved;
2037                 s8 class;
2038 #else
2039                 s8 class;
2040                 u8 reserved;
2041                 u16 locale;
2042 #endif
2043         } __attribute__ ((packed)) members;
2044
2045         u32 word;
2046
2047 } __attribute__ ((packed));
2048
2049 struct megasas_evt_log_info {
2050         __le32 newest_seq_num;
2051         __le32 oldest_seq_num;
2052         __le32 clear_seq_num;
2053         __le32 shutdown_seq_num;
2054         __le32 boot_seq_num;
2055
2056 } __attribute__ ((packed));
2057
2058 struct megasas_progress {
2059
2060         __le16 progress;
2061         __le16 elapsed_seconds;
2062
2063 } __attribute__ ((packed));
2064
2065 struct megasas_evtarg_ld {
2066
2067         u16 target_id;
2068         u8 ld_index;
2069         u8 reserved;
2070
2071 } __attribute__ ((packed));
2072
2073 struct megasas_evtarg_pd {
2074         u16 device_id;
2075         u8 encl_index;
2076         u8 slot_number;
2077
2078 } __attribute__ ((packed));
2079
2080 struct megasas_evt_detail {
2081
2082         __le32 seq_num;
2083         __le32 time_stamp;
2084         __le32 code;
2085         union megasas_evt_class_locale cl;
2086         u8 arg_type;
2087         u8 reserved1[15];
2088
2089         union {
2090                 struct {
2091                         struct megasas_evtarg_pd pd;
2092                         u8 cdb_length;
2093                         u8 sense_length;
2094                         u8 reserved[2];
2095                         u8 cdb[16];
2096                         u8 sense[64];
2097                 } __attribute__ ((packed)) cdbSense;
2098
2099                 struct megasas_evtarg_ld ld;
2100
2101                 struct {
2102                         struct megasas_evtarg_ld ld;
2103                         __le64 count;
2104                 } __attribute__ ((packed)) ld_count;
2105
2106                 struct {
2107                         __le64 lba;
2108                         struct megasas_evtarg_ld ld;
2109                 } __attribute__ ((packed)) ld_lba;
2110
2111                 struct {
2112                         struct megasas_evtarg_ld ld;
2113                         __le32 prevOwner;
2114                         __le32 newOwner;
2115                 } __attribute__ ((packed)) ld_owner;
2116
2117                 struct {
2118                         u64 ld_lba;
2119                         u64 pd_lba;
2120                         struct megasas_evtarg_ld ld;
2121                         struct megasas_evtarg_pd pd;
2122                 } __attribute__ ((packed)) ld_lba_pd_lba;
2123
2124                 struct {
2125                         struct megasas_evtarg_ld ld;
2126                         struct megasas_progress prog;
2127                 } __attribute__ ((packed)) ld_prog;
2128
2129                 struct {
2130                         struct megasas_evtarg_ld ld;
2131                         u32 prev_state;
2132                         u32 new_state;
2133                 } __attribute__ ((packed)) ld_state;
2134
2135                 struct {
2136                         u64 strip;
2137                         struct megasas_evtarg_ld ld;
2138                 } __attribute__ ((packed)) ld_strip;
2139
2140                 struct megasas_evtarg_pd pd;
2141
2142                 struct {
2143                         struct megasas_evtarg_pd pd;
2144                         u32 err;
2145                 } __attribute__ ((packed)) pd_err;
2146
2147                 struct {
2148                         u64 lba;
2149                         struct megasas_evtarg_pd pd;
2150                 } __attribute__ ((packed)) pd_lba;
2151
2152                 struct {
2153                         u64 lba;
2154                         struct megasas_evtarg_pd pd;
2155                         struct megasas_evtarg_ld ld;
2156                 } __attribute__ ((packed)) pd_lba_ld;
2157
2158                 struct {
2159                         struct megasas_evtarg_pd pd;
2160                         struct megasas_progress prog;
2161                 } __attribute__ ((packed)) pd_prog;
2162
2163                 struct {
2164                         struct megasas_evtarg_pd pd;
2165                         u32 prevState;
2166                         u32 newState;
2167                 } __attribute__ ((packed)) pd_state;
2168
2169                 struct {
2170                         u16 vendorId;
2171                         __le16 deviceId;
2172                         u16 subVendorId;
2173                         u16 subDeviceId;
2174                 } __attribute__ ((packed)) pci;
2175
2176                 u32 rate;
2177                 char str[96];
2178
2179                 struct {
2180                         u32 rtc;
2181                         u32 elapsedSeconds;
2182                 } __attribute__ ((packed)) time;
2183
2184                 struct {
2185                         u32 ecar;
2186                         u32 elog;
2187                         char str[64];
2188                 } __attribute__ ((packed)) ecc;
2189
2190                 u8 b[96];
2191                 __le16 s[48];
2192                 __le32 w[24];
2193                 __le64 d[12];
2194         } args;
2195
2196         char description[128];
2197
2198 } __attribute__ ((packed));
2199
2200 struct megasas_aen_event {
2201         struct delayed_work hotplug_work;
2202         struct megasas_instance *instance;
2203 };
2204
2205 struct megasas_irq_context {
2206         struct megasas_instance *instance;
2207         u32 MSIxIndex;
2208         u32 os_irq;
2209         struct irq_poll irqpoll;
2210         bool irq_poll_scheduled;
2211         bool irq_line_enable;
2212 };
2213
2214 struct MR_DRV_SYSTEM_INFO {
2215         u8      infoVersion;
2216         u8      systemIdLength;
2217         u16     reserved0;
2218         u8      systemId[64];
2219         u8      reserved[1980];
2220 };
2221
2222 enum MR_PD_TYPE {
2223         UNKNOWN_DRIVE = 0,
2224         PARALLEL_SCSI = 1,
2225         SAS_PD = 2,
2226         SATA_PD = 3,
2227         FC_PD = 4,
2228         NVME_PD = 5,
2229 };
2230
2231 /* JBOD Queue depth definitions */
2232 #define MEGASAS_SATA_QD 32
2233 #define MEGASAS_SAS_QD  64
2234 #define MEGASAS_DEFAULT_PD_QD   64
2235 #define MEGASAS_NVME_QD         32
2236
2237 #define MR_DEFAULT_NVME_PAGE_SIZE       4096
2238 #define MR_DEFAULT_NVME_PAGE_SHIFT      12
2239 #define MR_DEFAULT_NVME_MDTS_KB         128
2240 #define MR_NVME_PAGE_SIZE_MASK          0x000000FF
2241
2242 /*Aero performance parameters*/
2243 #define MR_HIGH_IOPS_QUEUE_COUNT        8
2244 #define MR_DEVICE_HIGH_IOPS_DEPTH       8
2245 #define MR_HIGH_IOPS_BATCH_COUNT        16
2246
2247 enum MR_PERF_MODE {
2248         MR_BALANCED_PERF_MODE           = 0,
2249         MR_IOPS_PERF_MODE               = 1,
2250         MR_LATENCY_PERF_MODE            = 2,
2251 };
2252
2253 #define MEGASAS_PERF_MODE_2STR(mode) \
2254                 ((mode) == MR_BALANCED_PERF_MODE ? "Balanced" : \
2255                  (mode) == MR_IOPS_PERF_MODE ? "IOPS" : \
2256                  (mode) == MR_LATENCY_PERF_MODE ? "Latency" : \
2257                  "Unknown")
2258
2259 struct megasas_instance {
2260
2261         unsigned int *reply_map;
2262         __le32 *producer;
2263         dma_addr_t producer_h;
2264         __le32 *consumer;
2265         dma_addr_t consumer_h;
2266         struct MR_DRV_SYSTEM_INFO *system_info_buf;
2267         dma_addr_t system_info_h;
2268         struct MR_LD_VF_AFFILIATION *vf_affiliation;
2269         dma_addr_t vf_affiliation_h;
2270         struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
2271         dma_addr_t vf_affiliation_111_h;
2272         struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
2273         dma_addr_t hb_host_mem_h;
2274         struct MR_PD_INFO *pd_info;
2275         dma_addr_t pd_info_h;
2276         struct MR_TARGET_PROPERTIES *tgt_prop;
2277         dma_addr_t tgt_prop_h;
2278
2279         __le32 *reply_queue;
2280         dma_addr_t reply_queue_h;
2281
2282         u32 *crash_dump_buf;
2283         dma_addr_t crash_dump_h;
2284
2285         struct MR_PD_LIST *pd_list_buf;
2286         dma_addr_t pd_list_buf_h;
2287
2288         struct megasas_ctrl_info *ctrl_info_buf;
2289         dma_addr_t ctrl_info_buf_h;
2290
2291         struct MR_LD_LIST *ld_list_buf;
2292         dma_addr_t ld_list_buf_h;
2293
2294         struct MR_LD_TARGETID_LIST *ld_targetid_list_buf;
2295         dma_addr_t ld_targetid_list_buf_h;
2296
2297         struct MR_HOST_DEVICE_LIST *host_device_list_buf;
2298         dma_addr_t host_device_list_buf_h;
2299
2300         struct MR_SNAPDUMP_PROPERTIES *snapdump_prop;
2301         dma_addr_t snapdump_prop_h;
2302
2303         void *crash_buf[MAX_CRASH_DUMP_SIZE];
2304         unsigned int    fw_crash_buffer_size;
2305         unsigned int    fw_crash_state;
2306         unsigned int    fw_crash_buffer_offset;
2307         u32 drv_buf_index;
2308         u32 drv_buf_alloc;
2309         u32 crash_dump_fw_support;
2310         u32 crash_dump_drv_support;
2311         u32 crash_dump_app_support;
2312         u32 secure_jbod_support;
2313         u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
2314         bool use_seqnum_jbod_fp;   /* Added for PD sequence */
2315         bool smp_affinity_enable;
2316         spinlock_t crashdump_lock;
2317
2318         struct megasas_register_set __iomem *reg_set;
2319         u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
2320         struct megasas_pd_list          pd_list[MEGASAS_MAX_PD];
2321         struct megasas_pd_list          local_pd_list[MEGASAS_MAX_PD];
2322         u8 ld_ids[MEGASAS_MAX_LD_IDS];
2323         s8 init_id;
2324
2325         u16 max_num_sge;
2326         u16 max_fw_cmds;
2327         u16 max_mpt_cmds;
2328         u16 max_mfi_cmds;
2329         u16 max_scsi_cmds;
2330         u16 ldio_threshold;
2331         u16 cur_can_queue;
2332         u32 max_sectors_per_req;
2333         bool msix_load_balance;
2334         struct megasas_aen_event *ev;
2335
2336         struct megasas_cmd **cmd_list;
2337         struct list_head cmd_pool;
2338         /* used to sync fire the cmd to fw */
2339         spinlock_t mfi_pool_lock;
2340         /* used to sync fire the cmd to fw */
2341         spinlock_t hba_lock;
2342         /* used to synch producer, consumer ptrs in dpc */
2343         spinlock_t stream_lock;
2344         spinlock_t completion_lock;
2345         struct dma_pool *frame_dma_pool;
2346         struct dma_pool *sense_dma_pool;
2347
2348         struct megasas_evt_detail *evt_detail;
2349         dma_addr_t evt_detail_h;
2350         struct megasas_cmd *aen_cmd;
2351         struct semaphore ioctl_sem;
2352
2353         struct Scsi_Host *host;
2354
2355         wait_queue_head_t int_cmd_wait_q;
2356         wait_queue_head_t abort_cmd_wait_q;
2357
2358         struct pci_dev *pdev;
2359         u32 unique_id;
2360         u32 fw_support_ieee;
2361         u32 threshold_reply_count;
2362
2363         atomic_t fw_outstanding;
2364         atomic_t ldio_outstanding;
2365         atomic_t fw_reset_no_pci_access;
2366         atomic64_t total_io_count;
2367         atomic64_t high_iops_outstanding;
2368
2369         struct megasas_instance_template *instancet;
2370         struct tasklet_struct isr_tasklet;
2371         struct work_struct work_init;
2372         struct delayed_work fw_fault_work;
2373         struct workqueue_struct *fw_fault_work_q;
2374         char fault_handler_work_q_name[48];
2375
2376         u8 flag;
2377         u8 unload;
2378         u8 flag_ieee;
2379         u8 issuepend_done;
2380         u8 disableOnlineCtrlReset;
2381         u8 UnevenSpanSupport;
2382
2383         u8 supportmax256vd;
2384         u8 pd_list_not_supported;
2385         u16 fw_supported_vd_count;
2386         u16 fw_supported_pd_count;
2387
2388         u16 drv_supported_vd_count;
2389         u16 drv_supported_pd_count;
2390
2391         atomic_t adprecovery;
2392         unsigned long last_time;
2393         u32 mfiStatus;
2394         u32 last_seq_num;
2395
2396         struct list_head internal_reset_pending_q;
2397
2398         /* Ptr to hba specific information */
2399         void *ctrl_context;
2400         unsigned int msix_vectors;
2401         struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
2402         u64 map_id;
2403         u64 pd_seq_map_id;
2404         struct megasas_cmd *map_update_cmd;
2405         struct megasas_cmd *jbod_seq_cmd;
2406         unsigned long bar;
2407         long reset_flags;
2408         struct mutex reset_mutex;
2409         struct timer_list sriov_heartbeat_timer;
2410         char skip_heartbeat_timer_del;
2411         u8 requestorId;
2412         char PlasmaFW111;
2413         char clusterId[MEGASAS_CLUSTER_ID_SIZE];
2414         u8 peerIsPresent;
2415         u8 passive;
2416         u16 throttlequeuedepth;
2417         u8 mask_interrupts;
2418         u16 max_chain_frame_sz;
2419         u8 is_imr;
2420         u8 is_rdpq;
2421         bool dev_handle;
2422         bool fw_sync_cache_support;
2423         u32 mfi_frame_size;
2424         bool msix_combined;
2425         u16 max_raid_mapsize;
2426         /* preffered count to send as LDIO irrspective of FP capable.*/
2427         u8  r1_ldio_hint_default;
2428         u32 nvme_page_size;
2429         u8 adapter_type;
2430         bool consistent_mask_64bit;
2431         bool support_nvme_passthru;
2432         u8 task_abort_tmo;
2433         u8 max_reset_tmo;
2434         u8 snapdump_wait_time;
2435 #ifdef CONFIG_DEBUG_FS
2436         struct dentry *debugfs_root;
2437         struct dentry *raidmap_dump;
2438 #endif
2439         u8 enable_fw_dev_list;
2440         bool atomic_desc_support;
2441         bool support_seqnum_jbod_fp;
2442         bool support_pci_lane_margining;
2443         u8  low_latency_index_start;
2444         int perf_mode;
2445 };
2446
2447 struct MR_LD_VF_MAP {
2448         u32 size;
2449         union MR_LD_REF ref;
2450         u8 ldVfCount;
2451         u8 reserved[6];
2452         u8 policy[1];
2453 };
2454
2455 struct MR_LD_VF_AFFILIATION {
2456         u32 size;
2457         u8 ldCount;
2458         u8 vfCount;
2459         u8 thisVf;
2460         u8 reserved[9];
2461         struct MR_LD_VF_MAP map[1];
2462 };
2463
2464 /* Plasma 1.11 FW backward compatibility structures */
2465 #define IOV_111_OFFSET 0x7CE
2466 #define MAX_VIRTUAL_FUNCTIONS 8
2467 #define MR_LD_ACCESS_HIDDEN 15
2468
2469 struct IOV_111 {
2470         u8 maxVFsSupported;
2471         u8 numVFsEnabled;
2472         u8 requestorId;
2473         u8 reserved[5];
2474 };
2475
2476 struct MR_LD_VF_MAP_111 {
2477         u8 targetId;
2478         u8 reserved[3];
2479         u8 policy[MAX_VIRTUAL_FUNCTIONS];
2480 };
2481
2482 struct MR_LD_VF_AFFILIATION_111 {
2483         u8 vdCount;
2484         u8 vfCount;
2485         u8 thisVf;
2486         u8 reserved[5];
2487         struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
2488 };
2489
2490 struct MR_CTRL_HB_HOST_MEM {
2491         struct {
2492                 u32 fwCounter;  /* Firmware heart beat counter */
2493                 struct {
2494                         u32 debugmode:1; /* 1=Firmware is in debug mode.
2495                                             Heart beat will not be updated. */
2496                         u32 reserved:31;
2497                 } debug;
2498                 u32 reserved_fw[6];
2499                 u32 driverCounter; /* Driver heart beat counter.  0x20 */
2500                 u32 reserved_driver[7];
2501         } HB;
2502         u8 pad[0x400-0x40];
2503 };
2504
2505 enum {
2506         MEGASAS_HBA_OPERATIONAL                 = 0,
2507         MEGASAS_ADPRESET_SM_INFAULT             = 1,
2508         MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS    = 2,
2509         MEGASAS_ADPRESET_SM_OPERATIONAL         = 3,
2510         MEGASAS_HW_CRITICAL_ERROR               = 4,
2511         MEGASAS_ADPRESET_SM_POLLING             = 5,
2512         MEGASAS_ADPRESET_INPROG_SIGN            = 0xDEADDEAD,
2513 };
2514
2515 struct megasas_instance_template {
2516         void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
2517                 u32, struct megasas_register_set __iomem *);
2518
2519         void (*enable_intr)(struct megasas_instance *);
2520         void (*disable_intr)(struct megasas_instance *);
2521
2522         int (*clear_intr)(struct megasas_instance *);
2523
2524         u32 (*read_fw_status_reg)(struct megasas_instance *);
2525         int (*adp_reset)(struct megasas_instance *, \
2526                 struct megasas_register_set __iomem *);
2527         int (*check_reset)(struct megasas_instance *, \
2528                 struct megasas_register_set __iomem *);
2529         irqreturn_t (*service_isr)(int irq, void *devp);
2530         void (*tasklet)(unsigned long);
2531         u32 (*init_adapter)(struct megasas_instance *);
2532         u32 (*build_and_issue_cmd) (struct megasas_instance *,
2533                                     struct scsi_cmnd *);
2534         void (*issue_dcmd)(struct megasas_instance *instance,
2535                             struct megasas_cmd *cmd);
2536 };
2537
2538 #define MEGASAS_IS_LOGICAL(sdev)                                        \
2539         ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2540
2541 #define MEGASAS_DEV_INDEX(scp)                                          \
2542         (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) +   \
2543         scp->device->id)
2544
2545 #define MEGASAS_PD_INDEX(scp)                                           \
2546         ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) +         \
2547         scp->device->id)
2548
2549 struct megasas_cmd {
2550
2551         union megasas_frame *frame;
2552         dma_addr_t frame_phys_addr;
2553         u8 *sense;
2554         dma_addr_t sense_phys_addr;
2555
2556         u32 index;
2557         u8 sync_cmd;
2558         u8 cmd_status_drv;
2559         u8 abort_aen;
2560         u8 retry_for_fw_reset;
2561
2562
2563         struct list_head list;
2564         struct scsi_cmnd *scmd;
2565         u8 flags;
2566
2567         struct megasas_instance *instance;
2568         union {
2569                 struct {
2570                         u16 smid;
2571                         u16 resvd;
2572                 } context;
2573                 u32 frame_count;
2574         };
2575 };
2576
2577 #define MAX_MGMT_ADAPTERS               1024
2578 #define MAX_IOCTL_SGE                   16
2579
2580 struct megasas_iocpacket {
2581
2582         u16 host_no;
2583         u16 __pad1;
2584         u32 sgl_off;
2585         u32 sge_count;
2586         u32 sense_off;
2587         u32 sense_len;
2588         union {
2589                 u8 raw[128];
2590                 struct megasas_header hdr;
2591         } frame;
2592
2593         struct iovec sgl[MAX_IOCTL_SGE];
2594
2595 } __attribute__ ((packed));
2596
2597 struct megasas_aen {
2598         u16 host_no;
2599         u16 __pad1;
2600         u32 seq_num;
2601         u32 class_locale_word;
2602 } __attribute__ ((packed));
2603
2604 #ifdef CONFIG_COMPAT
2605 struct compat_megasas_iocpacket {
2606         u16 host_no;
2607         u16 __pad1;
2608         u32 sgl_off;
2609         u32 sge_count;
2610         u32 sense_off;
2611         u32 sense_len;
2612         union {
2613                 u8 raw[128];
2614                 struct megasas_header hdr;
2615         } frame;
2616         struct compat_iovec sgl[MAX_IOCTL_SGE];
2617 } __attribute__ ((packed));
2618
2619 #define MEGASAS_IOC_FIRMWARE32  _IOWR('M', 1, struct compat_megasas_iocpacket)
2620 #endif
2621
2622 #define MEGASAS_IOC_FIRMWARE    _IOWR('M', 1, struct megasas_iocpacket)
2623 #define MEGASAS_IOC_GET_AEN     _IOW('M', 3, struct megasas_aen)
2624
2625 struct megasas_mgmt_info {
2626
2627         u16 count;
2628         struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2629         int max_index;
2630 };
2631
2632 enum MEGASAS_OCR_CAUSE {
2633         FW_FAULT_OCR                    = 0,
2634         SCSIIO_TIMEOUT_OCR              = 1,
2635         MFI_IO_TIMEOUT_OCR              = 2,
2636 };
2637
2638 enum DCMD_RETURN_STATUS {
2639         DCMD_SUCCESS            = 0,
2640         DCMD_TIMEOUT            = 1,
2641         DCMD_FAILED             = 2,
2642         DCMD_NOT_FIRED          = 3,
2643 };
2644
2645 u8
2646 MR_BuildRaidContext(struct megasas_instance *instance,
2647                     struct IO_REQUEST_INFO *io_info,
2648                     struct RAID_CONTEXT *pRAID_Context,
2649                     struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2650 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2651 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2652 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2653 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
2654 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
2655 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2656
2657 __le16 get_updated_dev_handle(struct megasas_instance *instance,
2658                               struct LD_LOAD_BALANCE_INFO *lbInfo,
2659                               struct IO_REQUEST_INFO *in_info,
2660                               struct MR_DRV_RAID_MAP_ALL *drv_map);
2661 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2662         struct LD_LOAD_BALANCE_INFO *lbInfo);
2663 int megasas_get_ctrl_info(struct megasas_instance *instance);
2664 /* PD sequence */
2665 int
2666 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
2667 void megasas_set_dynamic_target_properties(struct scsi_device *sdev,
2668                                            bool is_target_prop);
2669 int megasas_get_target_prop(struct megasas_instance *instance,
2670                             struct scsi_device *sdev);
2671 void megasas_get_snapdump_properties(struct megasas_instance *instance);
2672
2673 int megasas_set_crash_dump_params(struct megasas_instance *instance,
2674         u8 crash_buf_state);
2675 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2676
2677 void megasas_return_cmd_fusion(struct megasas_instance *instance,
2678         struct megasas_cmd_fusion *cmd);
2679 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2680         struct megasas_cmd *cmd, int timeout);
2681 void __megasas_return_cmd(struct megasas_instance *instance,
2682         struct megasas_cmd *cmd);
2683
2684 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2685         struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2686 int megasas_cmd_type(struct scsi_cmnd *cmd);
2687 void megasas_setup_jbod_map(struct megasas_instance *instance);
2688
2689 void megasas_update_sdev_properties(struct scsi_device *sdev);
2690 int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
2691 int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
2692 int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
2693 u32 mega_mod64(u64 dividend, u32 divisor);
2694 int megasas_alloc_fusion_context(struct megasas_instance *instance);
2695 void megasas_free_fusion_context(struct megasas_instance *instance);
2696 int megasas_fusion_start_watchdog(struct megasas_instance *instance);
2697 void megasas_fusion_stop_watchdog(struct megasas_instance *instance);
2698
2699 void megasas_set_dma_settings(struct megasas_instance *instance,
2700                               struct megasas_dcmd_frame *dcmd,
2701                               dma_addr_t dma_addr, u32 dma_len);
2702 int megasas_adp_reset_wait_for_ready(struct megasas_instance *instance,
2703                                      bool do_adp_reset,
2704                                      int ocr_context);
2705 int megasas_irqpoll(struct irq_poll *irqpoll, int budget);
2706 void megasas_dump_fusion_io(struct scsi_cmnd *scmd);
2707 #endif                          /*LSI_MEGARAID_SAS_H */