drivers/scsi/megaraid/megaraid_sas.h

   1 /*
   2  *  Linux MegaRAID driver for SAS based RAID controllers
   3  *
   4  *  Copyright (c) 2003-2013  LSI Corporation
   5  *  Copyright (c) 2013-2016  Avago Technologies
   6  *  Copyright (c) 2016-2018  Broadcom Inc.
   7  *
   8  *  This program is free software; you can redistribute it and/or
   9  *  modify it under the terms of the GNU General Public License
  10  *  as published by the Free Software Foundation; either version 2
  11  *  of the License, or (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  *
  21  *  FILE: megaraid_sas.h
  22  *
  23  *  Authors: Broadcom Inc.
  24  *           Kashyap Desai <kashyap.desai@broadcom.com>
  25  *           Sumit Saxena <sumit.saxena@broadcom.com>
  26  *
  27  *  Send feedback to: megaraidlinux.pdl@broadcom.com
  28  */
  29
  30 #ifndef LSI_MEGARAID_SAS_H
  31 #define LSI_MEGARAID_SAS_H
  32
  33 /*
  34  * MegaRAID SAS Driver meta data
  35  */
  36 #define MEGASAS_VERSION                         "07.707.51.00-rc1"
  37 #define MEGASAS_RELDATE                         "February 7, 2019"
  38
  39 /*
  40  * Device IDs
  41  */
  42 #define PCI_DEVICE_ID_LSI_SAS1078R              0x0060
  43 #define PCI_DEVICE_ID_LSI_SAS1078DE             0x007C
  44 #define PCI_DEVICE_ID_LSI_VERDE_ZCR             0x0413
  45 #define PCI_DEVICE_ID_LSI_SAS1078GEN2           0x0078
  46 #define PCI_DEVICE_ID_LSI_SAS0079GEN2           0x0079
  47 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY         0x0073
  48 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY         0x0071
  49 #define PCI_DEVICE_ID_LSI_FUSION                0x005b
  50 #define PCI_DEVICE_ID_LSI_PLASMA                0x002f
  51 #define PCI_DEVICE_ID_LSI_INVADER               0x005d
  52 #define PCI_DEVICE_ID_LSI_FURY                  0x005f
  53 #define PCI_DEVICE_ID_LSI_INTRUDER              0x00ce
  54 #define PCI_DEVICE_ID_LSI_INTRUDER_24           0x00cf
  55 #define PCI_DEVICE_ID_LSI_CUTLASS_52            0x0052
  56 #define PCI_DEVICE_ID_LSI_CUTLASS_53            0x0053
  57 #define PCI_DEVICE_ID_LSI_VENTURA                   0x0014
  58 #define PCI_DEVICE_ID_LSI_CRUSADER                  0x0015
  59 #define PCI_DEVICE_ID_LSI_HARPOON                   0x0016
  60 #define PCI_DEVICE_ID_LSI_TOMCAT                    0x0017
  61 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT         0x001B
  62 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT        0x001C
  63 #define PCI_DEVICE_ID_LSI_AERO_10E1             0x10e1
  64 #define PCI_DEVICE_ID_LSI_AERO_10E2             0x10e2
  65 #define PCI_DEVICE_ID_LSI_AERO_10E5             0x10e5
  66 #define PCI_DEVICE_ID_LSI_AERO_10E6             0x10e6
  67
  68 /*
  69  * Intel HBA SSDIDs
  70  */
  71 #define MEGARAID_INTEL_RS3DC080_SSDID           0x9360
  72 #define MEGARAID_INTEL_RS3DC040_SSDID           0x9362
  73 #define MEGARAID_INTEL_RS3SC008_SSDID           0x9380
  74 #define MEGARAID_INTEL_RS3MC044_SSDID           0x9381
  75 #define MEGARAID_INTEL_RS3WC080_SSDID           0x9341
  76 #define MEGARAID_INTEL_RS3WC040_SSDID           0x9343
  77 #define MEGARAID_INTEL_RMS3BC160_SSDID          0x352B
  78
  79 /*
  80  * Intruder HBA SSDIDs
  81  */
  82 #define MEGARAID_INTRUDER_SSDID1                0x9371
  83 #define MEGARAID_INTRUDER_SSDID2                0x9390
  84 #define MEGARAID_INTRUDER_SSDID3                0x9370
  85
  86 /*
  87  * Intel HBA branding
  88  */
  89 #define MEGARAID_INTEL_RS3DC080_BRANDING        \
  90         "Intel(R) RAID Controller RS3DC080"
  91 #define MEGARAID_INTEL_RS3DC040_BRANDING        \
  92         "Intel(R) RAID Controller RS3DC040"
  93 #define MEGARAID_INTEL_RS3SC008_BRANDING        \
  94         "Intel(R) RAID Controller RS3SC008"
  95 #define MEGARAID_INTEL_RS3MC044_BRANDING        \
  96         "Intel(R) RAID Controller RS3MC044"
  97 #define MEGARAID_INTEL_RS3WC080_BRANDING        \
  98         "Intel(R) RAID Controller RS3WC080"
  99 #define MEGARAID_INTEL_RS3WC040_BRANDING        \
 100         "Intel(R) RAID Controller RS3WC040"
 101 #define MEGARAID_INTEL_RMS3BC160_BRANDING       \
 102         "Intel(R) Integrated RAID Module RMS3BC160"
 103
 104 /*
 105  * =====================================
 106  * MegaRAID SAS MFI firmware definitions
 107  * =====================================
 108  */
 109
 110 /*
 111  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
 112  * protocol between the software and firmware. Commands are issued using
 113  * "message frames"
 114  */
 115
 116 /*
 117  * FW posts its state in upper 4 bits of outbound_msg_0 register
 118  */
 119 #define MFI_STATE_MASK                          0xF0000000
 120 #define MFI_STATE_UNDEFINED                     0x00000000
 121 #define MFI_STATE_BB_INIT                       0x10000000
 122 #define MFI_STATE_FW_INIT                       0x40000000
 123 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
 124 #define MFI_STATE_FW_INIT_2                     0x70000000
 125 #define MFI_STATE_DEVICE_SCAN                   0x80000000
 126 #define MFI_STATE_BOOT_MESSAGE_PENDING          0x90000000
 127 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
 128 #define MFI_STATE_READY                         0xB0000000
 129 #define MFI_STATE_OPERATIONAL                   0xC0000000
 130 #define MFI_STATE_FAULT                         0xF0000000
 131 #define MFI_STATE_FORCE_OCR                     0x00000080
 132 #define MFI_STATE_DMADONE                       0x00000008
 133 #define MFI_STATE_CRASH_DUMP_DONE               0x00000004
 134 #define MFI_RESET_REQUIRED                      0x00000001
 135 #define MFI_RESET_ADAPTER                       0x00000002
 136 #define MEGAMFI_FRAME_SIZE                      64
 137
 138 /*
 139  * During FW init, clear pending cmds & reset state using inbound_msg_0
 140  *
 141  * ABORT        : Abort all pending cmds
 142  * READY        : Move from OPERATIONAL to READY state; discard queue info
 143  * MFIMODE      : Discard (possible) low MFA posted in 64-bit mode (??)
 144  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
 145  * HOTPLUG      : Resume from Hotplug
 146  * MFI_STOP_ADP : Send signal to FW to stop processing
 147  * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump
 148  */
 149 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC) /* I20 */
 150 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)  /* I20 */
 151 #define DIAG_WRITE_ENABLE                       (0x00000080)
 152 #define DIAG_RESET_ADAPTER                      (0x00000004)
 153
 154 #define MFI_ADP_RESET                           0x00000040
 155 #define MFI_INIT_ABORT                          0x00000001
 156 #define MFI_INIT_READY                          0x00000002
 157 #define MFI_INIT_MFIMODE                        0x00000004
 158 #define MFI_INIT_CLEAR_HANDSHAKE                0x00000008
 159 #define MFI_INIT_HOTPLUG                        0x00000010
 160 #define MFI_STOP_ADP                            0x00000020
 161 #define MFI_RESET_FLAGS                         MFI_INIT_READY| \
 162                                                 MFI_INIT_MFIMODE| \
 163                                                 MFI_INIT_ABORT
 164 #define MFI_ADP_TRIGGER_SNAP_DUMP               0x00000100
 165 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
 166
 167 /*
 168  * MFI frame flags
 169  */
 170 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
 171 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
 172 #define MFI_FRAME_SGL32                         0x0000
 173 #define MFI_FRAME_SGL64                         0x0002
 174 #define MFI_FRAME_SENSE32                       0x0000
 175 #define MFI_FRAME_SENSE64                       0x0004
 176 #define MFI_FRAME_DIR_NONE                      0x0000
 177 #define MFI_FRAME_DIR_WRITE                     0x0008
 178 #define MFI_FRAME_DIR_READ                      0x0010
 179 #define MFI_FRAME_DIR_BOTH                      0x0018
 180 #define MFI_FRAME_IEEE                          0x0020
 181
 182 /* Driver internal */
 183 #define DRV_DCMD_POLLED_MODE            0x1
 184 #define DRV_DCMD_SKIP_REFIRE            0x2
 185
 186 /*
 187  * Definition for cmd_status
 188  */
 189 #define MFI_CMD_STATUS_POLL_MODE                0xFF
 190
 191 /*
 192  * MFI command opcodes
 193  */
 194 enum MFI_CMD_OP {
 195         MFI_CMD_INIT            = 0x0,
 196         MFI_CMD_LD_READ         = 0x1,
 197         MFI_CMD_LD_WRITE        = 0x2,
 198         MFI_CMD_LD_SCSI_IO      = 0x3,
 199         MFI_CMD_PD_SCSI_IO      = 0x4,
 200         MFI_CMD_DCMD            = 0x5,
 201         MFI_CMD_ABORT           = 0x6,
 202         MFI_CMD_SMP             = 0x7,
 203         MFI_CMD_STP             = 0x8,
 204         MFI_CMD_NVME            = 0x9,
 205         MFI_CMD_OP_COUNT,
 206         MFI_CMD_INVALID         = 0xff
 207 };
 208
 209 #define MR_DCMD_CTRL_GET_INFO                   0x01010000
 210 #define MR_DCMD_LD_GET_LIST                     0x03010000
 211 #define MR_DCMD_LD_LIST_QUERY                   0x03010100
 212
 213 #define MR_DCMD_CTRL_CACHE_FLUSH                0x01101000
 214 #define MR_FLUSH_CTRL_CACHE                     0x01
 215 #define MR_FLUSH_DISK_CACHE                     0x02
 216
 217 #define MR_DCMD_CTRL_SHUTDOWN                   0x01050000
 218 #define MR_DCMD_HIBERNATE_SHUTDOWN              0x01060000
 219 #define MR_ENABLE_DRIVE_SPINDOWN                0x01
 220
 221 #define MR_DCMD_CTRL_EVENT_GET_INFO             0x01040100
 222 #define MR_DCMD_CTRL_EVENT_GET                  0x01040300
 223 #define MR_DCMD_CTRL_EVENT_WAIT                 0x01040500
 224 #define MR_DCMD_LD_GET_PROPERTIES               0x03030000
 225
 226 #define MR_DCMD_CLUSTER                         0x08000000
 227 #define MR_DCMD_CLUSTER_RESET_ALL               0x08010100
 228 #define MR_DCMD_CLUSTER_RESET_LD                0x08010200
 229 #define MR_DCMD_PD_LIST_QUERY                   0x02010100
 230
 231 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS      0x01190100
 232 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE        (0xF0010000 | 0x0600)
 233 #define MR_DCMD_PD_GET_INFO                     0x02020000
 234
 235 /*
 236  * Global functions
 237  */
 238 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id);
 239
 240
 241 /*
 242  * MFI command completion codes
 243  */
 244 enum MFI_STAT {
 245         MFI_STAT_OK = 0x00,
 246         MFI_STAT_INVALID_CMD = 0x01,
 247         MFI_STAT_INVALID_DCMD = 0x02,
 248         MFI_STAT_INVALID_PARAMETER = 0x03,
 249         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
 250         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
 251         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
 252         MFI_STAT_APP_IN_USE = 0x07,
 253         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
 254         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
 255         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
 256         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
 257         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
 258         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
 259         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
 260         MFI_STAT_FLASH_BUSY = 0x0f,
 261         MFI_STAT_FLASH_ERROR = 0x10,
 262         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
 263         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
 264         MFI_STAT_FLASH_NOT_OPEN = 0x13,
 265         MFI_STAT_FLASH_NOT_STARTED = 0x14,
 266         MFI_STAT_FLUSH_FAILED = 0x15,
 267         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
 268         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
 269         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
 270         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
 271         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
 272         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
 273         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
 274         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
 275         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
 276         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
 277         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
 278         MFI_STAT_MFC_HW_ERROR = 0x21,
 279         MFI_STAT_NO_HW_PRESENT = 0x22,
 280         MFI_STAT_NOT_FOUND = 0x23,
 281         MFI_STAT_NOT_IN_ENCL = 0x24,
 282         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
 283         MFI_STAT_PD_TYPE_WRONG = 0x26,
 284         MFI_STAT_PR_DISABLED = 0x27,
 285         MFI_STAT_ROW_INDEX_INVALID = 0x28,
 286         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
 287         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
 288         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
 289         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
 290         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
 291         MFI_STAT_SCSI_IO_FAILED = 0x2e,
 292         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
 293         MFI_STAT_SHUTDOWN_FAILED = 0x30,
 294         MFI_STAT_TIME_NOT_SET = 0x31,
 295         MFI_STAT_WRONG_STATE = 0x32,
 296         MFI_STAT_LD_OFFLINE = 0x33,
 297         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
 298         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
 299         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
 300         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
 301         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
 302         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
 303
 304         MFI_STAT_INVALID_STATUS = 0xFF
 305 };
 306
 307 enum mfi_evt_class {
 308         MFI_EVT_CLASS_DEBUG =           -2,
 309         MFI_EVT_CLASS_PROGRESS =        -1,
 310         MFI_EVT_CLASS_INFO =            0,
 311         MFI_EVT_CLASS_WARNING =         1,
 312         MFI_EVT_CLASS_CRITICAL =        2,
 313         MFI_EVT_CLASS_FATAL =           3,
 314         MFI_EVT_CLASS_DEAD =            4
 315 };
 316
 317 /*
 318  * Crash dump related defines
 319  */
 320 #define MAX_CRASH_DUMP_SIZE 512
 321 #define CRASH_DMA_BUF_SIZE  (1024 * 1024)
 322
 323 enum MR_FW_CRASH_DUMP_STATE {
 324         UNAVAILABLE = 0,
 325         AVAILABLE = 1,
 326         COPYING = 2,
 327         COPIED = 3,
 328         COPY_ERROR = 4,
 329 };
 330
 331 enum _MR_CRASH_BUF_STATUS {
 332         MR_CRASH_BUF_TURN_OFF = 0,
 333         MR_CRASH_BUF_TURN_ON = 1,
 334 };
 335
 336 /*
 337  * Number of mailbox bytes in DCMD message frame
 338  */
 339 #define MFI_MBOX_SIZE                           12
 340
 341 enum MR_EVT_CLASS {
 342
 343         MR_EVT_CLASS_DEBUG = -2,
 344         MR_EVT_CLASS_PROGRESS = -1,
 345         MR_EVT_CLASS_INFO = 0,
 346         MR_EVT_CLASS_WARNING = 1,
 347         MR_EVT_CLASS_CRITICAL = 2,
 348         MR_EVT_CLASS_FATAL = 3,
 349         MR_EVT_CLASS_DEAD = 4,
 350
 351 };
 352
 353 enum MR_EVT_LOCALE {
 354
 355         MR_EVT_LOCALE_LD = 0x0001,
 356         MR_EVT_LOCALE_PD = 0x0002,
 357         MR_EVT_LOCALE_ENCL = 0x0004,
 358         MR_EVT_LOCALE_BBU = 0x0008,
 359         MR_EVT_LOCALE_SAS = 0x0010,
 360         MR_EVT_LOCALE_CTRL = 0x0020,
 361         MR_EVT_LOCALE_CONFIG = 0x0040,
 362         MR_EVT_LOCALE_CLUSTER = 0x0080,
 363         MR_EVT_LOCALE_ALL = 0xffff,
 364
 365 };
 366
 367 enum MR_EVT_ARGS {
 368
 369         MR_EVT_ARGS_NONE,
 370         MR_EVT_ARGS_CDB_SENSE,
 371         MR_EVT_ARGS_LD,
 372         MR_EVT_ARGS_LD_COUNT,
 373         MR_EVT_ARGS_LD_LBA,
 374         MR_EVT_ARGS_LD_OWNER,
 375         MR_EVT_ARGS_LD_LBA_PD_LBA,
 376         MR_EVT_ARGS_LD_PROG,
 377         MR_EVT_ARGS_LD_STATE,
 378         MR_EVT_ARGS_LD_STRIP,
 379         MR_EVT_ARGS_PD,
 380         MR_EVT_ARGS_PD_ERR,
 381         MR_EVT_ARGS_PD_LBA,
 382         MR_EVT_ARGS_PD_LBA_LD,
 383         MR_EVT_ARGS_PD_PROG,
 384         MR_EVT_ARGS_PD_STATE,
 385         MR_EVT_ARGS_PCI,
 386         MR_EVT_ARGS_RATE,
 387         MR_EVT_ARGS_STR,
 388         MR_EVT_ARGS_TIME,
 389         MR_EVT_ARGS_ECC,
 390         MR_EVT_ARGS_LD_PROP,
 391         MR_EVT_ARGS_PD_SPARE,
 392         MR_EVT_ARGS_PD_INDEX,
 393         MR_EVT_ARGS_DIAG_PASS,
 394         MR_EVT_ARGS_DIAG_FAIL,
 395         MR_EVT_ARGS_PD_LBA_LBA,
 396         MR_EVT_ARGS_PORT_PHY,
 397         MR_EVT_ARGS_PD_MISSING,
 398         MR_EVT_ARGS_PD_ADDRESS,
 399         MR_EVT_ARGS_BITMAP,
 400         MR_EVT_ARGS_CONNECTOR,
 401         MR_EVT_ARGS_PD_PD,
 402         MR_EVT_ARGS_PD_FRU,
 403         MR_EVT_ARGS_PD_PATHINFO,
 404         MR_EVT_ARGS_PD_POWER_STATE,
 405         MR_EVT_ARGS_GENERIC,
 406 };
 407
 408
 409 #define SGE_BUFFER_SIZE 4096
 410 #define MEGASAS_CLUSTER_ID_SIZE 16
 411 /*
 412  * define constants for device list query options
 413  */
 414 enum MR_PD_QUERY_TYPE {
 415         MR_PD_QUERY_TYPE_ALL                = 0,
 416         MR_PD_QUERY_TYPE_STATE              = 1,
 417         MR_PD_QUERY_TYPE_POWER_STATE        = 2,
 418         MR_PD_QUERY_TYPE_MEDIA_TYPE         = 3,
 419         MR_PD_QUERY_TYPE_SPEED              = 4,
 420         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST    = 5,
 421 };
 422
 423 enum MR_LD_QUERY_TYPE {
 424         MR_LD_QUERY_TYPE_ALL             = 0,
 425         MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
 426         MR_LD_QUERY_TYPE_USED_TGT_IDS    = 2,
 427         MR_LD_QUERY_TYPE_CLUSTER_ACCESS  = 3,
 428         MR_LD_QUERY_TYPE_CLUSTER_LOCALE  = 4,
 429 };
 430
 431
 432 #define MR_EVT_CFG_CLEARED                              0x0004
 433 #define MR_EVT_LD_STATE_CHANGE                          0x0051
 434 #define MR_EVT_PD_INSERTED                              0x005b
 435 #define MR_EVT_PD_REMOVED                               0x0070
 436 #define MR_EVT_LD_CREATED                               0x008a
 437 #define MR_EVT_LD_DELETED                               0x008b
 438 #define MR_EVT_FOREIGN_CFG_IMPORTED                     0x00db
 439 #define MR_EVT_LD_OFFLINE                               0x00fc
 440 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
 441 #define MR_EVT_CTRL_PROP_CHANGED                        0x012f
 442
 443 enum MR_PD_STATE {
 444         MR_PD_STATE_UNCONFIGURED_GOOD   = 0x00,
 445         MR_PD_STATE_UNCONFIGURED_BAD    = 0x01,
 446         MR_PD_STATE_HOT_SPARE           = 0x02,
 447         MR_PD_STATE_OFFLINE             = 0x10,
 448         MR_PD_STATE_FAILED              = 0x11,
 449         MR_PD_STATE_REBUILD             = 0x14,
 450         MR_PD_STATE_ONLINE              = 0x18,
 451         MR_PD_STATE_COPYBACK            = 0x20,
 452         MR_PD_STATE_SYSTEM              = 0x40,
 453  };
 454
 455 union MR_PD_REF {
 456         struct {
 457                 u16      deviceId;
 458                 u16      seqNum;
 459         } mrPdRef;
 460         u32      ref;
 461 };
 462
 463 /*
 464  * define the DDF Type bit structure
 465  */
 466 union MR_PD_DDF_TYPE {
 467          struct {
 468                 union {
 469                         struct {
 470 #ifndef __BIG_ENDIAN_BITFIELD
 471                                  u16     forcedPDGUID:1;
 472                                  u16     inVD:1;
 473                                  u16     isGlobalSpare:1;
 474                                  u16     isSpare:1;
 475                                  u16     isForeign:1;
 476                                  u16     reserved:7;
 477                                  u16     intf:4;
 478 #else
 479                                  u16     intf:4;
 480                                  u16     reserved:7;
 481                                  u16     isForeign:1;
 482                                  u16     isSpare:1;
 483                                  u16     isGlobalSpare:1;
 484                                  u16     inVD:1;
 485                                  u16     forcedPDGUID:1;
 486 #endif
 487                          } pdType;
 488                          u16     type;
 489                  };
 490                  u16     reserved;
 491          } ddf;
 492          struct {
 493                  u32    reserved;
 494          } nonDisk;
 495          u32     type;
 496 } __packed;
 497
 498 /*
 499  * defines the progress structure
 500  */
 501 union MR_PROGRESS {
 502         struct  {
 503                 u16 progress;
 504                 union {
 505                         u16 elapsedSecs;
 506                         u16 elapsedSecsForLastPercent;
 507                 };
 508         } mrProgress;
 509         u32 w;
 510 } __packed;
 511
 512 /*
 513  * defines the physical drive progress structure
 514  */
 515 struct MR_PD_PROGRESS {
 516         struct {
 517 #ifndef MFI_BIG_ENDIAN
 518                 u32     rbld:1;
 519                 u32     patrol:1;
 520                 u32     clear:1;
 521                 u32     copyBack:1;
 522                 u32     erase:1;
 523                 u32     locate:1;
 524                 u32     reserved:26;
 525 #else
 526                 u32     reserved:26;
 527                 u32     locate:1;
 528                 u32     erase:1;
 529                 u32     copyBack:1;
 530                 u32     clear:1;
 531                 u32     patrol:1;
 532                 u32     rbld:1;
 533 #endif
 534         } active;
 535         union MR_PROGRESS     rbld;
 536         union MR_PROGRESS     patrol;
 537         union {
 538                 union MR_PROGRESS     clear;
 539                 union MR_PROGRESS     erase;
 540         };
 541
 542         struct {
 543 #ifndef MFI_BIG_ENDIAN
 544                 u32     rbld:1;
 545                 u32     patrol:1;
 546                 u32     clear:1;
 547                 u32     copyBack:1;
 548                 u32     erase:1;
 549                 u32     reserved:27;
 550 #else
 551                 u32     reserved:27;
 552                 u32     erase:1;
 553                 u32     copyBack:1;
 554                 u32     clear:1;
 555                 u32     patrol:1;
 556                 u32     rbld:1;
 557 #endif
 558         } pause;
 559
 560         union MR_PROGRESS     reserved[3];
 561 } __packed;
 562
 563 struct  MR_PD_INFO {
 564         union MR_PD_REF ref;
 565         u8 inquiryData[96];
 566         u8 vpdPage83[64];
 567         u8 notSupported;
 568         u8 scsiDevType;
 569
 570         union {
 571                 u8 connectedPortBitmap;
 572                 u8 connectedPortNumbers;
 573         };
 574
 575         u8 deviceSpeed;
 576         u32 mediaErrCount;
 577         u32 otherErrCount;
 578         u32 predFailCount;
 579         u32 lastPredFailEventSeqNum;
 580
 581         u16 fwState;
 582         u8 disabledForRemoval;
 583         u8 linkSpeed;
 584         union MR_PD_DDF_TYPE state;
 585
 586         struct {
 587                 u8 count;
 588 #ifndef __BIG_ENDIAN_BITFIELD
 589                 u8 isPathBroken:4;
 590                 u8 reserved3:3;
 591                 u8 widePortCapable:1;
 592 #else
 593                 u8 widePortCapable:1;
 594                 u8 reserved3:3;
 595                 u8 isPathBroken:4;
 596 #endif
 597
 598                 u8 connectorIndex[2];
 599                 u8 reserved[4];
 600                 u64 sasAddr[2];
 601                 u8 reserved2[16];
 602         } pathInfo;
 603
 604         u64 rawSize;
 605         u64 nonCoercedSize;
 606         u64 coercedSize;
 607         u16 enclDeviceId;
 608         u8 enclIndex;
 609
 610         union {
 611                 u8 slotNumber;
 612                 u8 enclConnectorIndex;
 613         };
 614
 615         struct MR_PD_PROGRESS progInfo;
 616         u8 badBlockTableFull;
 617         u8 unusableInCurrentConfig;
 618         u8 vpdPage83Ext[64];
 619         u8 powerState;
 620         u8 enclPosition;
 621         u32 allowedOps;
 622         u16 copyBackPartnerId;
 623         u16 enclPartnerDeviceId;
 624         struct {
 625 #ifndef __BIG_ENDIAN_BITFIELD
 626                 u16 fdeCapable:1;
 627                 u16 fdeEnabled:1;
 628                 u16 secured:1;
 629                 u16 locked:1;
 630                 u16 foreign:1;
 631                 u16 needsEKM:1;
 632                 u16 reserved:10;
 633 #else
 634                 u16 reserved:10;
 635                 u16 needsEKM:1;
 636                 u16 foreign:1;
 637                 u16 locked:1;
 638                 u16 secured:1;
 639                 u16 fdeEnabled:1;
 640                 u16 fdeCapable:1;
 641 #endif
 642         } security;
 643         u8 mediaType;
 644         u8 notCertified;
 645         u8 bridgeVendor[8];
 646         u8 bridgeProductIdentification[16];
 647         u8 bridgeProductRevisionLevel[4];
 648         u8 satBridgeExists;
 649
 650         u8 interfaceType;
 651         u8 temperature;
 652         u8 emulatedBlockSize;
 653         u16 userDataBlockSize;
 654         u16 reserved2;
 655
 656         struct {
 657 #ifndef __BIG_ENDIAN_BITFIELD
 658                 u32 piType:3;
 659                 u32 piFormatted:1;
 660                 u32 piEligible:1;
 661                 u32 NCQ:1;
 662                 u32 WCE:1;
 663                 u32 commissionedSpare:1;
 664                 u32 emergencySpare:1;
 665                 u32 ineligibleForSSCD:1;
 666                 u32 ineligibleForLd:1;
 667                 u32 useSSEraseType:1;
 668                 u32 wceUnchanged:1;
 669                 u32 supportScsiUnmap:1;
 670                 u32 reserved:18;
 671 #else
 672                 u32 reserved:18;
 673                 u32 supportScsiUnmap:1;
 674                 u32 wceUnchanged:1;
 675                 u32 useSSEraseType:1;
 676                 u32 ineligibleForLd:1;
 677                 u32 ineligibleForSSCD:1;
 678                 u32 emergencySpare:1;
 679                 u32 commissionedSpare:1;
 680                 u32 WCE:1;
 681                 u32 NCQ:1;
 682                 u32 piEligible:1;
 683                 u32 piFormatted:1;
 684                 u32 piType:3;
 685 #endif
 686         } properties;
 687
 688         u64 shieldDiagCompletionTime;
 689         u8 shieldCounter;
 690
 691         u8 linkSpeedOther;
 692         u8 reserved4[2];
 693
 694         struct {
 695 #ifndef __BIG_ENDIAN_BITFIELD
 696                 u32 bbmErrCountSupported:1;
 697                 u32 bbmErrCount:31;
 698 #else
 699                 u32 bbmErrCount:31;
 700                 u32 bbmErrCountSupported:1;
 701 #endif
 702         } bbmErr;
 703
 704         u8 reserved1[512-428];
 705 } __packed;
 706
 707 /*
 708  * Definition of structure used to expose attributes of VD or JBOD
 709  * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
 710  * is fired by driver)
 711  */
 712 struct MR_TARGET_PROPERTIES {
 713         u32    max_io_size_kb;
 714         u32    device_qdepth;
 715         u32    sector_size;
 716         u8     reset_tmo;
 717         u8     reserved[499];
 718 } __packed;
 719
 720  /*
 721  * defines the physical drive address structure
 722  */
 723 struct MR_PD_ADDRESS {
 724         __le16  deviceId;
 725         u16     enclDeviceId;
 726
 727         union {
 728                 struct {
 729                         u8  enclIndex;
 730                         u8  slotNumber;
 731                 } mrPdAddress;
 732                 struct {
 733                         u8  enclPosition;
 734                         u8  enclConnectorIndex;
 735                 } mrEnclAddress;
 736         };
 737         u8      scsiDevType;
 738         union {
 739                 u8      connectedPortBitmap;
 740                 u8      connectedPortNumbers;
 741         };
 742         u64     sasAddr[2];
 743 } __packed;
 744
 745 /*
 746  * defines the physical drive list structure
 747  */
 748 struct MR_PD_LIST {
 749         __le32          size;
 750         __le32          count;
 751         struct MR_PD_ADDRESS   addr[1];
 752 } __packed;
 753
 754 struct megasas_pd_list {
 755         u16             tid;
 756         u8             driveType;
 757         u8             driveState;
 758 } __packed;
 759
 760  /*
 761  * defines the logical drive reference structure
 762  */
 763 union  MR_LD_REF {
 764         struct {
 765                 u8      targetId;
 766                 u8      reserved;
 767                 __le16     seqNum;
 768         };
 769         __le32     ref;
 770 } __packed;
 771
 772 /*
 773  * defines the logical drive list structure
 774  */
 775 struct MR_LD_LIST {
 776         __le32     ldCount;
 777         __le32     reserved;
 778         struct {
 779                 union MR_LD_REF   ref;
 780                 u8          state;
 781                 u8          reserved[3];
 782                 __le64          size;
 783         } ldList[MAX_LOGICAL_DRIVES_EXT];
 784 } __packed;
 785
 786 struct MR_LD_TARGETID_LIST {
 787         __le32  size;
 788         __le32  count;
 789         u8      pad[3];
 790         u8      targetId[MAX_LOGICAL_DRIVES_EXT];
 791 };
 792
 793 struct MR_HOST_DEVICE_LIST_ENTRY {
 794         struct {
 795                 union {
 796                         struct {
 797 #if defined(__BIG_ENDIAN_BITFIELD)
 798                                 u8 reserved:7;
 799                                 u8 is_sys_pd:1;
 800 #else
 801                                 u8 is_sys_pd:1;
 802                                 u8 reserved:7;
 803 #endif
 804                         } bits;
 805                         u8 byte;
 806                 } u;
 807         } flags;
 808         u8 scsi_type;
 809         __le16 target_id;
 810         u8 reserved[4];
 811         __le64 sas_addr[2];
 812 } __packed;
 813
 814 struct MR_HOST_DEVICE_LIST {
 815         __le32                  size;
 816         __le32                  count;
 817         __le32                  reserved[2];
 818         struct MR_HOST_DEVICE_LIST_ENTRY        host_device_list[1];
 819 } __packed;
 820
 821 #define HOST_DEVICE_LIST_SZ (sizeof(struct MR_HOST_DEVICE_LIST) +              \
 822                               (sizeof(struct MR_HOST_DEVICE_LIST_ENTRY) *      \
 823                               (MEGASAS_MAX_PD + MAX_LOGICAL_DRIVES_EXT - 1)))
 824
 825
 826 /*
 827  * SAS controller properties
 828  */
 829 struct megasas_ctrl_prop {
 830
 831         u16 seq_num;
 832         u16 pred_fail_poll_interval;
 833         u16 intr_throttle_count;
 834         u16 intr_throttle_timeouts;
 835         u8 rebuild_rate;
 836         u8 patrol_read_rate;
 837         u8 bgi_rate;
 838         u8 cc_rate;
 839         u8 recon_rate;
 840         u8 cache_flush_interval;
 841         u8 spinup_drv_count;
 842         u8 spinup_delay;
 843         u8 cluster_enable;
 844         u8 coercion_mode;
 845         u8 alarm_enable;
 846         u8 disable_auto_rebuild;
 847         u8 disable_battery_warn;
 848         u8 ecc_bucket_size;
 849         u16 ecc_bucket_leak_rate;
 850         u8 restore_hotspare_on_insertion;
 851         u8 expose_encl_devices;
 852         u8 maintainPdFailHistory;
 853         u8 disallowHostRequestReordering;
 854         u8 abortCCOnError;
 855         u8 loadBalanceMode;
 856         u8 disableAutoDetectBackplane;
 857
 858         u8 snapVDSpace;
 859
 860         /*
 861         * Add properties that can be controlled by
 862         * a bit in the following structure.
 863         */
 864         struct {
 865 #if   defined(__BIG_ENDIAN_BITFIELD)
 866                 u32     reserved:18;
 867                 u32     enableJBOD:1;
 868                 u32     disableSpinDownHS:1;
 869                 u32     allowBootWithPinnedCache:1;
 870                 u32     disableOnlineCtrlReset:1;
 871                 u32     enableSecretKeyControl:1;
 872                 u32     autoEnhancedImport:1;
 873                 u32     enableSpinDownUnconfigured:1;
 874                 u32     SSDPatrolReadEnabled:1;
 875                 u32     SSDSMARTerEnabled:1;
 876                 u32     disableNCQ:1;
 877                 u32     useFdeOnly:1;
 878                 u32     prCorrectUnconfiguredAreas:1;
 879                 u32     SMARTerEnabled:1;
 880                 u32     copyBackDisabled:1;
 881 #else
 882                 u32     copyBackDisabled:1;
 883                 u32     SMARTerEnabled:1;
 884                 u32     prCorrectUnconfiguredAreas:1;
 885                 u32     useFdeOnly:1;
 886                 u32     disableNCQ:1;
 887                 u32     SSDSMARTerEnabled:1;
 888                 u32     SSDPatrolReadEnabled:1;
 889                 u32     enableSpinDownUnconfigured:1;
 890                 u32     autoEnhancedImport:1;
 891                 u32     enableSecretKeyControl:1;
 892                 u32     disableOnlineCtrlReset:1;
 893                 u32     allowBootWithPinnedCache:1;
 894                 u32     disableSpinDownHS:1;
 895                 u32     enableJBOD:1;
 896                 u32     reserved:18;
 897 #endif
 898         } OnOffProperties;
 899
 900         union {
 901                 u8 autoSnapVDSpace;
 902                 u8 viewSpace;
 903                 struct {
 904 #if   defined(__BIG_ENDIAN_BITFIELD)
 905                         u16 reserved3:9;
 906                         u16 enable_fw_dev_list:1;
 907                         u16 reserved2:1;
 908                         u16 enable_snap_dump:1;
 909                         u16 reserved1:4;
 910 #else
 911                         u16 reserved1:4;
 912                         u16 enable_snap_dump:1;
 913                         u16 reserved2:1;
 914                         u16 enable_fw_dev_list:1;
 915                         u16 reserved3:9;
 916 #endif
 917                 } on_off_properties2;
 918         };
 919         __le16 spinDownTime;
 920         u8  reserved[24];
 921 } __packed;
 922
 923 /*
 924  * SAS controller information
 925  */
 926 struct megasas_ctrl_info {
 927
 928         /*
 929          * PCI device information
 930          */
 931         struct {
 932
 933                 __le16 vendor_id;
 934                 __le16 device_id;
 935                 __le16 sub_vendor_id;
 936                 __le16 sub_device_id;
 937                 u8 reserved[24];
 938
 939         } __attribute__ ((packed)) pci;
 940
 941         /*
 942          * Host interface information
 943          */
 944         struct {
 945
 946                 u8 PCIX:1;
 947                 u8 PCIE:1;
 948                 u8 iSCSI:1;
 949                 u8 SAS_3G:1;
 950                 u8 SRIOV:1;
 951                 u8 reserved_0:3;
 952                 u8 reserved_1[6];
 953                 u8 port_count;
 954                 u64 port_addr[8];
 955
 956         } __attribute__ ((packed)) host_interface;
 957
 958         /*
 959          * Device (backend) interface information
 960          */
 961         struct {
 962
 963                 u8 SPI:1;
 964                 u8 SAS_3G:1;
 965                 u8 SATA_1_5G:1;
 966                 u8 SATA_3G:1;
 967                 u8 reserved_0:4;
 968                 u8 reserved_1[6];
 969                 u8 port_count;
 970                 u64 port_addr[8];
 971
 972         } __attribute__ ((packed)) device_interface;
 973
 974         /*
 975          * List of components residing in flash. All str are null terminated
 976          */
 977         __le32 image_check_word;
 978         __le32 image_component_count;
 979
 980         struct {
 981
 982                 char name[8];
 983                 char version[32];
 984                 char build_date[16];
 985                 char built_time[16];
 986
 987         } __attribute__ ((packed)) image_component[8];
 988
 989         /*
 990          * List of flash components that have been flashed on the card, but
 991          * are not in use, pending reset of the adapter. This list will be
 992          * empty if a flash operation has not occurred. All stings are null
 993          * terminated
 994          */
 995         __le32 pending_image_component_count;
 996
 997         struct {
 998
 999                 char name[8];
1000                 char version[32];
1001                 char build_date[16];
1002                 char build_time[16];
1003
1004         } __attribute__ ((packed)) pending_image_component[8];
1005
1006         u8 max_arms;
1007         u8 max_spans;
1008         u8 max_arrays;
1009         u8 max_lds;
1010
1011         char product_name[80];
1012         char serial_no[32];
1013
1014         /*
1015          * Other physical/controller/operation information. Indicates the
1016          * presence of the hardware
1017          */
1018         struct {
1019
1020                 u32 bbu:1;
1021                 u32 alarm:1;
1022                 u32 nvram:1;
1023                 u32 uart:1;
1024                 u32 reserved:28;
1025
1026         } __attribute__ ((packed)) hw_present;
1027
1028         __le32 current_fw_time;
1029
1030         /*
1031          * Maximum data transfer sizes
1032          */
1033         __le16 max_concurrent_cmds;
1034         __le16 max_sge_count;
1035         __le32 max_request_size;
1036
1037         /*
1038          * Logical and physical device counts
1039          */
1040         __le16 ld_present_count;
1041         __le16 ld_degraded_count;
1042         __le16 ld_offline_count;
1043
1044         __le16 pd_present_count;
1045         __le16 pd_disk_present_count;
1046         __le16 pd_disk_pred_failure_count;
1047         __le16 pd_disk_failed_count;
1048
1049         /*
1050          * Memory size information
1051          */
1052         __le16 nvram_size;
1053         __le16 memory_size;
1054         __le16 flash_size;
1055
1056         /*
1057          * Error counters
1058          */
1059         __le16 mem_correctable_error_count;
1060         __le16 mem_uncorrectable_error_count;
1061
1062         /*
1063          * Cluster information
1064          */
1065         u8 cluster_permitted;
1066         u8 cluster_active;
1067
1068         /*
1069          * Additional max data transfer sizes
1070          */
1071         __le16 max_strips_per_io;
1072
1073         /*
1074          * Controller capabilities structures
1075          */
1076         struct {
1077
1078                 u32 raid_level_0:1;
1079                 u32 raid_level_1:1;
1080                 u32 raid_level_5:1;
1081                 u32 raid_level_1E:1;
1082                 u32 raid_level_6:1;
1083                 u32 reserved:27;
1084
1085         } __attribute__ ((packed)) raid_levels;
1086
1087         struct {
1088
1089                 u32 rbld_rate:1;
1090                 u32 cc_rate:1;
1091                 u32 bgi_rate:1;
1092                 u32 recon_rate:1;
1093                 u32 patrol_rate:1;
1094                 u32 alarm_control:1;
1095                 u32 cluster_supported:1;
1096                 u32 bbu:1;
1097                 u32 spanning_allowed:1;
1098                 u32 dedicated_hotspares:1;
1099                 u32 revertible_hotspares:1;
1100                 u32 foreign_config_import:1;
1101                 u32 self_diagnostic:1;
1102                 u32 mixed_redundancy_arr:1;
1103                 u32 global_hot_spares:1;
1104                 u32 reserved:17;
1105
1106         } __attribute__ ((packed)) adapter_operations;
1107
1108         struct {
1109
1110                 u32 read_policy:1;
1111                 u32 write_policy:1;
1112                 u32 io_policy:1;
1113                 u32 access_policy:1;
1114                 u32 disk_cache_policy:1;
1115                 u32 reserved:27;
1116
1117         } __attribute__ ((packed)) ld_operations;
1118
1119         struct {
1120
1121                 u8 min;
1122                 u8 max;
1123                 u8 reserved[2];
1124
1125         } __attribute__ ((packed)) stripe_sz_ops;
1126
1127         struct {
1128
1129                 u32 force_online:1;
1130                 u32 force_offline:1;
1131                 u32 force_rebuild:1;
1132                 u32 reserved:29;
1133
1134         } __attribute__ ((packed)) pd_operations;
1135
1136         struct {
1137
1138                 u32 ctrl_supports_sas:1;
1139                 u32 ctrl_supports_sata:1;
1140                 u32 allow_mix_in_encl:1;
1141                 u32 allow_mix_in_ld:1;
1142                 u32 allow_sata_in_cluster:1;
1143                 u32 reserved:27;
1144
1145         } __attribute__ ((packed)) pd_mix_support;
1146
1147         /*
1148          * Define ECC single-bit-error bucket information
1149          */
1150         u8 ecc_bucket_count;
1151         u8 reserved_2[11];
1152
1153         /*
1154          * Include the controller properties (changeable items)
1155          */
1156         struct megasas_ctrl_prop properties;
1157
1158         /*
1159          * Define FW pkg version (set in envt v'bles on OEM basis)
1160          */
1161         char package_version[0x60];
1162
1163
1164         /*
1165         * If adapterOperations.supportMoreThan8Phys is set,
1166         * and deviceInterface.portCount is greater than 8,
1167         * SAS Addrs for first 8 ports shall be populated in
1168         * deviceInterface.portAddr, and the rest shall be
1169         * populated in deviceInterfacePortAddr2.
1170         */
1171         __le64      deviceInterfacePortAddr2[8]; /*6a0h */
1172         u8          reserved3[128];              /*6e0h */
1173
1174         struct {                                /*760h */
1175                 u16 minPdRaidLevel_0:4;
1176                 u16 maxPdRaidLevel_0:12;
1177
1178                 u16 minPdRaidLevel_1:4;
1179                 u16 maxPdRaidLevel_1:12;
1180
1181                 u16 minPdRaidLevel_5:4;
1182                 u16 maxPdRaidLevel_5:12;
1183
1184                 u16 minPdRaidLevel_1E:4;
1185                 u16 maxPdRaidLevel_1E:12;
1186
1187                 u16 minPdRaidLevel_6:4;
1188                 u16 maxPdRaidLevel_6:12;
1189
1190                 u16 minPdRaidLevel_10:4;
1191                 u16 maxPdRaidLevel_10:12;
1192
1193                 u16 minPdRaidLevel_50:4;
1194                 u16 maxPdRaidLevel_50:12;
1195
1196                 u16 minPdRaidLevel_60:4;
1197                 u16 maxPdRaidLevel_60:12;
1198
1199                 u16 minPdRaidLevel_1E_RLQ0:4;
1200                 u16 maxPdRaidLevel_1E_RLQ0:12;
1201
1202                 u16 minPdRaidLevel_1E0_RLQ0:4;
1203                 u16 maxPdRaidLevel_1E0_RLQ0:12;
1204
1205                 u16 reserved[6];
1206         } pdsForRaidLevels;
1207
1208         __le16 maxPds;                          /*780h */
1209         __le16 maxDedHSPs;                      /*782h */
1210         __le16 maxGlobalHSP;                    /*784h */
1211         __le16 ddfSize;                         /*786h */
1212         u8  maxLdsPerArray;                     /*788h */
1213         u8  partitionsInDDF;                    /*789h */
1214         u8  lockKeyBinding;                     /*78ah */
1215         u8  maxPITsPerLd;                       /*78bh */
1216         u8  maxViewsPerLd;                      /*78ch */
1217         u8  maxTargetId;                        /*78dh */
1218         __le16 maxBvlVdSize;                    /*78eh */
1219
1220         __le16 maxConfigurableSSCSize;          /*790h */
1221         __le16 currentSSCsize;                  /*792h */
1222
1223         char    expanderFwVersion[12];          /*794h */
1224
1225         __le16 PFKTrialTimeRemaining;           /*7A0h */
1226
1227         __le16 cacheMemorySize;                 /*7A2h */
1228
1229         struct {                                /*7A4h */
1230 #if   defined(__BIG_ENDIAN_BITFIELD)
1231                 u32     reserved:5;
1232                 u32     activePassive:2;
1233                 u32     supportConfigAutoBalance:1;
1234                 u32     mpio:1;
1235                 u32     supportDataLDonSSCArray:1;
1236                 u32     supportPointInTimeProgress:1;
1237                 u32     supportUnevenSpans:1;
1238                 u32     dedicatedHotSparesLimited:1;
1239                 u32     headlessMode:1;
1240                 u32     supportEmulatedDrives:1;
1241                 u32     supportResetNow:1;
1242                 u32     realTimeScheduler:1;
1243                 u32     supportSSDPatrolRead:1;
1244                 u32     supportPerfTuning:1;
1245                 u32     disableOnlinePFKChange:1;
1246                 u32     supportJBOD:1;
1247                 u32     supportBootTimePFKChange:1;
1248                 u32     supportSetLinkSpeed:1;
1249                 u32     supportEmergencySpares:1;
1250                 u32     supportSuspendResumeBGops:1;
1251                 u32     blockSSDWriteCacheChange:1;
1252                 u32     supportShieldState:1;
1253                 u32     supportLdBBMInfo:1;
1254                 u32     supportLdPIType3:1;
1255                 u32     supportLdPIType2:1;
1256                 u32     supportLdPIType1:1;
1257                 u32     supportPIcontroller:1;
1258 #else
1259                 u32     supportPIcontroller:1;
1260                 u32     supportLdPIType1:1;
1261                 u32     supportLdPIType2:1;
1262                 u32     supportLdPIType3:1;
1263                 u32     supportLdBBMInfo:1;
1264                 u32     supportShieldState:1;
1265                 u32     blockSSDWriteCacheChange:1;
1266                 u32     supportSuspendResumeBGops:1;
1267                 u32     supportEmergencySpares:1;
1268                 u32     supportSetLinkSpeed:1;
1269                 u32     supportBootTimePFKChange:1;
1270                 u32     supportJBOD:1;
1271                 u32     disableOnlinePFKChange:1;
1272                 u32     supportPerfTuning:1;
1273                 u32     supportSSDPatrolRead:1;
1274                 u32     realTimeScheduler:1;
1275
1276                 u32     supportResetNow:1;
1277                 u32     supportEmulatedDrives:1;
1278                 u32     headlessMode:1;
1279                 u32     dedicatedHotSparesLimited:1;
1280
1281
1282                 u32     supportUnevenSpans:1;
1283                 u32     supportPointInTimeProgress:1;
1284                 u32     supportDataLDonSSCArray:1;
1285                 u32     mpio:1;
1286                 u32     supportConfigAutoBalance:1;
1287                 u32     activePassive:2;
1288                 u32     reserved:5;
1289 #endif
1290         } adapterOperations2;
1291
1292         u8  driverVersion[32];                  /*7A8h */
1293         u8  maxDAPdCountSpinup60;               /*7C8h */
1294         u8  temperatureROC;                     /*7C9h */
1295         u8  temperatureCtrl;                    /*7CAh */
1296         u8  reserved4;                          /*7CBh */
1297         __le16 maxConfigurablePds;              /*7CCh */
1298
1299
1300         u8  reserved5[2];                       /*0x7CDh */
1301
1302         /*
1303         * HA cluster information
1304         */
1305         struct {
1306 #if defined(__BIG_ENDIAN_BITFIELD)
1307                 u32     reserved:25;
1308                 u32     passive:1;
1309                 u32     premiumFeatureMismatch:1;
1310                 u32     ctrlPropIncompatible:1;
1311                 u32     fwVersionMismatch:1;
1312                 u32     hwIncompatible:1;
1313                 u32     peerIsIncompatible:1;
1314                 u32     peerIsPresent:1;
1315 #else
1316                 u32     peerIsPresent:1;
1317                 u32     peerIsIncompatible:1;
1318                 u32     hwIncompatible:1;
1319                 u32     fwVersionMismatch:1;
1320                 u32     ctrlPropIncompatible:1;
1321                 u32     premiumFeatureMismatch:1;
1322                 u32     passive:1;
1323                 u32     reserved:25;
1324 #endif
1325         } cluster;
1326
1327         char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1328         struct {
1329                 u8  maxVFsSupported;            /*0x7E4*/
1330                 u8  numVFsEnabled;              /*0x7E5*/
1331                 u8  requestorId;                /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1332                 u8  reserved;                   /*0x7E7*/
1333         } iov;
1334
1335         struct {
1336 #if defined(__BIG_ENDIAN_BITFIELD)
1337                 u32     reserved:7;
1338                 u32     useSeqNumJbodFP:1;
1339                 u32     supportExtendedSSCSize:1;
1340                 u32     supportDiskCacheSettingForSysPDs:1;
1341                 u32     supportCPLDUpdate:1;
1342                 u32     supportTTYLogCompression:1;
1343                 u32     discardCacheDuringLDDelete:1;
1344                 u32     supportSecurityonJBOD:1;
1345                 u32     supportCacheBypassModes:1;
1346                 u32     supportDisableSESMonitoring:1;
1347                 u32     supportForceFlash:1;
1348                 u32     supportNVDRAM:1;
1349                 u32     supportDrvActivityLEDSetting:1;
1350                 u32     supportAllowedOpsforDrvRemoval:1;
1351                 u32     supportHOQRebuild:1;
1352                 u32     supportForceTo512e:1;
1353                 u32     supportNVCacheErase:1;
1354                 u32     supportDebugQueue:1;
1355                 u32     supportSwZone:1;
1356                 u32     supportCrashDump:1;
1357                 u32     supportMaxExtLDs:1;
1358                 u32     supportT10RebuildAssist:1;
1359                 u32     supportDisableImmediateIO:1;
1360                 u32     supportThermalPollInterval:1;
1361                 u32     supportPersonalityChange:2;
1362 #else
1363                 u32     supportPersonalityChange:2;
1364                 u32     supportThermalPollInterval:1;
1365                 u32     supportDisableImmediateIO:1;
1366                 u32     supportT10RebuildAssist:1;
1367                 u32     supportMaxExtLDs:1;
1368                 u32     supportCrashDump:1;
1369                 u32     supportSwZone:1;
1370                 u32     supportDebugQueue:1;
1371                 u32     supportNVCacheErase:1;
1372                 u32     supportForceTo512e:1;
1373                 u32     supportHOQRebuild:1;
1374                 u32     supportAllowedOpsforDrvRemoval:1;
1375                 u32     supportDrvActivityLEDSetting:1;
1376                 u32     supportNVDRAM:1;
1377                 u32     supportForceFlash:1;
1378                 u32     supportDisableSESMonitoring:1;
1379                 u32     supportCacheBypassModes:1;
1380                 u32     supportSecurityonJBOD:1;
1381                 u32     discardCacheDuringLDDelete:1;
1382                 u32     supportTTYLogCompression:1;
1383                 u32     supportCPLDUpdate:1;
1384                 u32     supportDiskCacheSettingForSysPDs:1;
1385                 u32     supportExtendedSSCSize:1;
1386                 u32     useSeqNumJbodFP:1;
1387                 u32     reserved:7;
1388 #endif
1389         } adapterOperations3;
1390
1391         struct {
1392 #if defined(__BIG_ENDIAN_BITFIELD)
1393         u8 reserved:7;
1394         /* Indicates whether the CPLD image is part of
1395          *  the package and stored in flash
1396          */
1397         u8 cpld_in_flash:1;
1398 #else
1399         u8 cpld_in_flash:1;
1400         u8 reserved:7;
1401 #endif
1402         u8 reserved1[3];
1403         /* Null terminated string. Has the version
1404          *  information if cpld_in_flash = FALSE
1405          */
1406         u8 userCodeDefinition[12];
1407         } cpld;  /* Valid only if upgradableCPLD is TRUE */
1408
1409         struct {
1410         #if defined(__BIG_ENDIAN_BITFIELD)
1411                 u16 reserved:2;
1412                 u16 support_nvme_passthru:1;
1413                 u16 support_pl_debug_info:1;
1414                 u16 support_flash_comp_info:1;
1415                 u16 support_host_info:1;
1416                 u16 support_dual_fw_update:1;
1417                 u16 support_ssc_rev3:1;
1418                 u16 fw_swaps_bbu_vpd_info:1;
1419                 u16 support_pd_map_target_id:1;
1420                 u16 support_ses_ctrl_in_multipathcfg:1;
1421                 u16 image_upload_supported:1;
1422                 u16 support_encrypted_mfc:1;
1423                 u16 supported_enc_algo:1;
1424                 u16 support_ibutton_less:1;
1425                 u16 ctrl_info_ext_supported:1;
1426         #else
1427
1428                 u16 ctrl_info_ext_supported:1;
1429                 u16 support_ibutton_less:1;
1430                 u16 supported_enc_algo:1;
1431                 u16 support_encrypted_mfc:1;
1432                 u16 image_upload_supported:1;
1433                 /* FW supports LUN based association and target port based */
1434                 u16 support_ses_ctrl_in_multipathcfg:1;
1435                 /* association for the SES device connected in multipath mode */
1436                 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1437                 u16 support_pd_map_target_id:1;
1438                 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1439                  *  provide the data in little endian order
1440                  */
1441                 u16 fw_swaps_bbu_vpd_info:1;
1442                 u16 support_ssc_rev3:1;
1443                 /* FW supports CacheCade 3.0, only one SSCD creation allowed */
1444                 u16 support_dual_fw_update:1;
1445                 /* FW supports dual firmware update feature */
1446                 u16 support_host_info:1;
1447                 /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */
1448                 u16 support_flash_comp_info:1;
1449                 /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */
1450                 u16 support_pl_debug_info:1;
1451                 /* FW supports retrieval of PL debug information through apps */
1452                 u16 support_nvme_passthru:1;
1453                 /* FW supports NVMe passthru commands */
1454                 u16 reserved:2;
1455         #endif
1456                 } adapter_operations4;
1457         u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1458
1459         u32 size;
1460         u32 pad1;
1461
1462         u8 reserved6[64];
1463
1464         u32 rsvdForAdptOp[64];
1465
1466         u8 reserved7[3];
1467
1468         u8 TaskAbortTO; /* Timeout value in seconds used by Abort Task TM */
1469         u8 MaxResetTO;  /* Max Supported Reset timeout in seconds. */
1470         u8 reserved8[3];
1471 } __packed;
1472
1473 /*
1474  * ===============================
1475  * MegaRAID SAS driver definitions
1476  * ===============================
1477  */
1478 #define MEGASAS_MAX_PD_CHANNELS                 2
1479 #define MEGASAS_MAX_LD_CHANNELS                 2
1480 #define MEGASAS_MAX_CHANNELS                    (MEGASAS_MAX_PD_CHANNELS + \
1481                                                 MEGASAS_MAX_LD_CHANNELS)
1482 #define MEGASAS_MAX_DEV_PER_CHANNEL             128
1483 #define MEGASAS_DEFAULT_INIT_ID                 -1
1484 #define MEGASAS_MAX_LUN                         8
1485 #define MEGASAS_DEFAULT_CMD_PER_LUN             256
1486 #define MEGASAS_MAX_PD                          (MEGASAS_MAX_PD_CHANNELS * \
1487                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1488 #define MEGASAS_MAX_LD_IDS                      (MEGASAS_MAX_LD_CHANNELS * \
1489                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1490
1491 #define MEGASAS_MAX_SECTORS                    (2*1024)
1492 #define MEGASAS_MAX_SECTORS_IEEE                (2*128)
1493 #define MEGASAS_DBG_LVL                         1
1494
1495 #define MEGASAS_FW_BUSY                         1
1496
1497 /* Driver's internal Logging levels*/
1498 #define OCR_LOGS    (1 << 0)
1499
1500 #define SCAN_PD_CHANNEL 0x1
1501 #define SCAN_VD_CHANNEL 0x2
1502
1503 #define MEGASAS_KDUMP_QUEUE_DEPTH               100
1504 #define MR_LARGE_IO_MIN_SIZE                    (32 * 1024)
1505 #define MR_R1_LDIO_PIGGYBACK_DEFAULT            4
1506
1507 enum MR_SCSI_CMD_TYPE {
1508         READ_WRITE_LDIO = 0,
1509         NON_READ_WRITE_LDIO = 1,
1510         READ_WRITE_SYSPDIO = 2,
1511         NON_READ_WRITE_SYSPDIO = 3,
1512 };
1513
1514 enum DCMD_TIMEOUT_ACTION {
1515         INITIATE_OCR = 0,
1516         KILL_ADAPTER = 1,
1517         IGNORE_TIMEOUT = 2,
1518 };
1519
1520 enum FW_BOOT_CONTEXT {
1521         PROBE_CONTEXT = 0,
1522         OCR_CONTEXT = 1,
1523 };
1524
1525 /* Frame Type */
1526 #define IO_FRAME                                0
1527 #define PTHRU_FRAME                             1
1528
1529 /*
1530  * When SCSI mid-layer calls driver's reset routine, driver waits for
1531  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1532  * that the driver cannot _actually_ abort or reset pending commands. While
1533  * it is waiting for the commands to complete, it prints a diagnostic message
1534  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1535  */
1536 #define MEGASAS_RESET_WAIT_TIME                 180
1537 #define MEGASAS_INTERNAL_CMD_WAIT_TIME          180
1538 #define MEGASAS_RESET_NOTICE_INTERVAL           5
1539 #define MEGASAS_IOCTL_CMD                       0
1540 #define MEGASAS_DEFAULT_CMD_TIMEOUT             90
1541 #define MEGASAS_THROTTLE_QUEUE_DEPTH            16
1542 #define MEGASAS_DEFAULT_TM_TIMEOUT              50
1543 /*
1544  * FW reports the maximum of number of commands that it can accept (maximum
1545  * commands that can be outstanding) at any time. The driver must report a
1546  * lower number to the mid layer because it can issue a few internal commands
1547  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1548  * is shown below
1549  */
1550 #define MEGASAS_INT_CMDS                        32
1551 #define MEGASAS_SKINNY_INT_CMDS                 5
1552 #define MEGASAS_FUSION_INTERNAL_CMDS            8
1553 #define MEGASAS_FUSION_IOCTL_CMDS               3
1554 #define MEGASAS_MFI_IOCTL_CMDS                  27
1555
1556 #define MEGASAS_MAX_MSIX_QUEUES                 128
1557 /*
1558  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1559  * SGLs based on the size of dma_addr_t
1560  */
1561 #define IS_DMA64                                (sizeof(dma_addr_t) == 8)
1562
1563 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT                0x00000001
1564
1565 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
1566 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE             0x00000002
1567 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
1568
1569 #define MFI_OB_INTR_STATUS_MASK                 0x00000002
1570 #define MFI_POLL_TIMEOUT_SECS                   60
1571 #define MFI_IO_TIMEOUT_SECS                     180
1572 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF     (5 * HZ)
1573 #define MEGASAS_OCR_SETTLE_TIME_VF              (1000 * 30)
1574 #define MEGASAS_SRIOV_MAX_RESET_TRIES_VF        1
1575 #define MEGASAS_ROUTINE_WAIT_TIME_VF            300
1576 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
1577 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
1578 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          (0x00000001 | 0x00000004)
1579 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
1580 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
1581
1582 #define MFI_1068_PCSR_OFFSET                    0x84
1583 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
1584 #define MFI_1068_FW_READY                       0xDDDD0000
1585
1586 #define MR_MAX_REPLY_QUEUES_OFFSET              0X0000001F
1587 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET          0X003FC000
1588 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
1589 #define MR_MAX_MSIX_REG_ARRAY                   16
1590 #define MR_RDPQ_MODE_OFFSET                     0X00800000
1591
1592 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT       16
1593 #define MR_MAX_RAID_MAP_SIZE_MASK               0x1FF
1594 #define MR_MIN_MAP_SIZE                         0x10000
1595 /* 64k */
1596
1597 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET         0X01000000
1598
1599 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET         (1 << 25)
1600
1601 #define MEGASAS_WATCHDOG_THREAD_INTERVAL        1000
1602 #define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS         20
1603 #define MEGASAS_WATCHDOG_WAIT_COUNT             50
1604
1605 enum MR_ADAPTER_TYPE {
1606         MFI_SERIES = 1,
1607         THUNDERBOLT_SERIES = 2,
1608         INVADER_SERIES = 3,
1609         VENTURA_SERIES = 4,
1610         AERO_SERIES = 5,
1611 };
1612
1613 /*
1614 * register set for both 1068 and 1078 controllers
1615 * structure extended for 1078 registers
1616 */
1617
1618 struct megasas_register_set {
1619         u32     doorbell;                       /*0000h*/
1620         u32     fusion_seq_offset;              /*0004h*/
1621         u32     fusion_host_diag;               /*0008h*/
1622         u32     reserved_01;                    /*000Ch*/
1623
1624         u32     inbound_msg_0;                  /*0010h*/
1625         u32     inbound_msg_1;                  /*0014h*/
1626         u32     outbound_msg_0;                 /*0018h*/
1627         u32     outbound_msg_1;                 /*001Ch*/
1628
1629         u32     inbound_doorbell;               /*0020h*/
1630         u32     inbound_intr_status;            /*0024h*/
1631         u32     inbound_intr_mask;              /*0028h*/
1632
1633         u32     outbound_doorbell;              /*002Ch*/
1634         u32     outbound_intr_status;           /*0030h*/
1635         u32     outbound_intr_mask;             /*0034h*/
1636
1637         u32     reserved_1[2];                  /*0038h*/
1638
1639         u32     inbound_queue_port;             /*0040h*/
1640         u32     outbound_queue_port;            /*0044h*/
1641
1642         u32     reserved_2[9];                  /*0048h*/
1643         u32     reply_post_host_index;          /*006Ch*/
1644         u32     reserved_2_2[12];               /*0070h*/
1645
1646         u32     outbound_doorbell_clear;        /*00A0h*/
1647
1648         u32     reserved_3[3];                  /*00A4h*/
1649
1650         u32     outbound_scratch_pad_0;         /*00B0h*/
1651         u32     outbound_scratch_pad_1;         /*00B4h*/
1652         u32     outbound_scratch_pad_2;         /*00B8h*/
1653         u32     outbound_scratch_pad_3;         /*00BCh*/
1654
1655         u32     inbound_low_queue_port ;        /*00C0h*/
1656
1657         u32     inbound_high_queue_port ;       /*00C4h*/
1658
1659         u32 inbound_single_queue_port;  /*00C8h*/
1660         u32     res_6[11];                      /*CCh*/
1661         u32     host_diag;
1662         u32     seq_offset;
1663         u32     index_registers[807];           /*00CCh*/
1664 } __attribute__ ((packed));
1665
1666 struct megasas_sge32 {
1667
1668         __le32 phys_addr;
1669         __le32 length;
1670
1671 } __attribute__ ((packed));
1672
1673 struct megasas_sge64 {
1674
1675         __le64 phys_addr;
1676         __le32 length;
1677
1678 } __attribute__ ((packed));
1679
1680 struct megasas_sge_skinny {
1681         __le64 phys_addr;
1682         __le32 length;
1683         __le32 flag;
1684 } __packed;
1685
1686 union megasas_sgl {
1687
1688         struct megasas_sge32 sge32[1];
1689         struct megasas_sge64 sge64[1];
1690         struct megasas_sge_skinny sge_skinny[1];
1691
1692 } __attribute__ ((packed));
1693
1694 struct megasas_header {
1695
1696         u8 cmd;                 /*00h */
1697         u8 sense_len;           /*01h */
1698         u8 cmd_status;          /*02h */
1699         u8 scsi_status;         /*03h */
1700
1701         u8 target_id;           /*04h */
1702         u8 lun;                 /*05h */
1703         u8 cdb_len;             /*06h */
1704         u8 sge_count;           /*07h */
1705
1706         __le32 context;         /*08h */
1707         __le32 pad_0;           /*0Ch */
1708
1709         __le16 flags;           /*10h */
1710         __le16 timeout;         /*12h */
1711         __le32 data_xferlen;    /*14h */
1712
1713 } __attribute__ ((packed));
1714
1715 union megasas_sgl_frame {
1716
1717         struct megasas_sge32 sge32[8];
1718         struct megasas_sge64 sge64[5];
1719
1720 } __attribute__ ((packed));
1721
1722 typedef union _MFI_CAPABILITIES {
1723         struct {
1724 #if   defined(__BIG_ENDIAN_BITFIELD)
1725         u32     reserved:16;
1726         u32     support_fw_exposed_dev_list:1;
1727         u32     support_nvme_passthru:1;
1728         u32     support_64bit_mode:1;
1729         u32 support_pd_map_target_id:1;
1730         u32     support_qd_throttling:1;
1731         u32     support_fp_rlbypass:1;
1732         u32     support_vfid_in_ioframe:1;
1733         u32     support_ext_io_size:1;
1734         u32             support_ext_queue_depth:1;
1735         u32     security_protocol_cmds_fw:1;
1736         u32     support_core_affinity:1;
1737         u32     support_ndrive_r1_lb:1;
1738         u32             support_max_255lds:1;
1739         u32             support_fastpath_wb:1;
1740         u32     support_additional_msix:1;
1741         u32     support_fp_remote_lun:1;
1742 #else
1743         u32     support_fp_remote_lun:1;
1744         u32     support_additional_msix:1;
1745         u32             support_fastpath_wb:1;
1746         u32             support_max_255lds:1;
1747         u32     support_ndrive_r1_lb:1;
1748         u32     support_core_affinity:1;
1749         u32     security_protocol_cmds_fw:1;
1750         u32             support_ext_queue_depth:1;
1751         u32     support_ext_io_size:1;
1752         u32     support_vfid_in_ioframe:1;
1753         u32     support_fp_rlbypass:1;
1754         u32     support_qd_throttling:1;
1755         u32     support_pd_map_target_id:1;
1756         u32     support_64bit_mode:1;
1757         u32     support_nvme_passthru:1;
1758         u32     support_fw_exposed_dev_list:1;
1759         u32     reserved:16;
1760 #endif
1761         } mfi_capabilities;
1762         __le32          reg;
1763 } MFI_CAPABILITIES;
1764
1765 struct megasas_init_frame {
1766
1767         u8 cmd;                 /*00h */
1768         u8 reserved_0;          /*01h */
1769         u8 cmd_status;          /*02h */
1770
1771         u8 reserved_1;          /*03h */
1772         MFI_CAPABILITIES driver_operations; /*04h*/
1773
1774         __le32 context;         /*08h */
1775         __le32 pad_0;           /*0Ch */
1776
1777         __le16 flags;           /*10h */
1778         __le16 reserved_3;              /*12h */
1779         __le32 data_xfer_len;   /*14h */
1780
1781         __le32 queue_info_new_phys_addr_lo;     /*18h */
1782         __le32 queue_info_new_phys_addr_hi;     /*1Ch */
1783         __le32 queue_info_old_phys_addr_lo;     /*20h */
1784         __le32 queue_info_old_phys_addr_hi;     /*24h */
1785         __le32 reserved_4[2];   /*28h */
1786         __le32 system_info_lo;      /*30h */
1787         __le32 system_info_hi;      /*34h */
1788         __le32 reserved_5[2];   /*38h */
1789
1790 } __attribute__ ((packed));
1791
1792 struct megasas_init_queue_info {
1793
1794         __le32 init_flags;              /*00h */
1795         __le32 reply_queue_entries;     /*04h */
1796
1797         __le32 reply_queue_start_phys_addr_lo;  /*08h */
1798         __le32 reply_queue_start_phys_addr_hi;  /*0Ch */
1799         __le32 producer_index_phys_addr_lo;     /*10h */
1800         __le32 producer_index_phys_addr_hi;     /*14h */
1801         __le32 consumer_index_phys_addr_lo;     /*18h */
1802         __le32 consumer_index_phys_addr_hi;     /*1Ch */
1803
1804 } __attribute__ ((packed));
1805
1806 struct megasas_io_frame {
1807
1808         u8 cmd;                 /*00h */
1809         u8 sense_len;           /*01h */
1810         u8 cmd_status;          /*02h */
1811         u8 scsi_status;         /*03h */
1812
1813         u8 target_id;           /*04h */
1814         u8 access_byte;         /*05h */
1815         u8 reserved_0;          /*06h */
1816         u8 sge_count;           /*07h */
1817
1818         __le32 context;         /*08h */
1819         __le32 pad_0;           /*0Ch */
1820
1821         __le16 flags;           /*10h */
1822         __le16 timeout;         /*12h */
1823         __le32 lba_count;       /*14h */
1824
1825         __le32 sense_buf_phys_addr_lo;  /*18h */
1826         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1827
1828         __le32 start_lba_lo;    /*20h */
1829         __le32 start_lba_hi;    /*24h */
1830
1831         union megasas_sgl sgl;  /*28h */
1832
1833 } __attribute__ ((packed));
1834
1835 struct megasas_pthru_frame {
1836
1837         u8 cmd;                 /*00h */
1838         u8 sense_len;           /*01h */
1839         u8 cmd_status;          /*02h */
1840         u8 scsi_status;         /*03h */
1841
1842         u8 target_id;           /*04h */
1843         u8 lun;                 /*05h */
1844         u8 cdb_len;             /*06h */
1845         u8 sge_count;           /*07h */
1846
1847         __le32 context;         /*08h */
1848         __le32 pad_0;           /*0Ch */
1849
1850         __le16 flags;           /*10h */
1851         __le16 timeout;         /*12h */
1852         __le32 data_xfer_len;   /*14h */
1853
1854         __le32 sense_buf_phys_addr_lo;  /*18h */
1855         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1856
1857         u8 cdb[16];             /*20h */
1858         union megasas_sgl sgl;  /*30h */
1859
1860 } __attribute__ ((packed));
1861
1862 struct megasas_dcmd_frame {
1863
1864         u8 cmd;                 /*00h */
1865         u8 reserved_0;          /*01h */
1866         u8 cmd_status;          /*02h */
1867         u8 reserved_1[4];       /*03h */
1868         u8 sge_count;           /*07h */
1869
1870         __le32 context;         /*08h */
1871         __le32 pad_0;           /*0Ch */
1872
1873         __le16 flags;           /*10h */
1874         __le16 timeout;         /*12h */
1875
1876         __le32 data_xfer_len;   /*14h */
1877         __le32 opcode;          /*18h */
1878
1879         union {                 /*1Ch */
1880                 u8 b[12];
1881                 __le16 s[6];
1882                 __le32 w[3];
1883         } mbox;
1884
1885         union megasas_sgl sgl;  /*28h */
1886
1887 } __attribute__ ((packed));
1888
1889 struct megasas_abort_frame {
1890
1891         u8 cmd;                 /*00h */
1892         u8 reserved_0;          /*01h */
1893         u8 cmd_status;          /*02h */
1894
1895         u8 reserved_1;          /*03h */
1896         __le32 reserved_2;      /*04h */
1897
1898         __le32 context;         /*08h */
1899         __le32 pad_0;           /*0Ch */
1900
1901         __le16 flags;           /*10h */
1902         __le16 reserved_3;      /*12h */
1903         __le32 reserved_4;      /*14h */
1904
1905         __le32 abort_context;   /*18h */
1906         __le32 pad_1;           /*1Ch */
1907
1908         __le32 abort_mfi_phys_addr_lo;  /*20h */
1909         __le32 abort_mfi_phys_addr_hi;  /*24h */
1910
1911         __le32 reserved_5[6];   /*28h */
1912
1913 } __attribute__ ((packed));
1914
1915 struct megasas_smp_frame {
1916
1917         u8 cmd;                 /*00h */
1918         u8 reserved_1;          /*01h */
1919         u8 cmd_status;          /*02h */
1920         u8 connection_status;   /*03h */
1921
1922         u8 reserved_2[3];       /*04h */
1923         u8 sge_count;           /*07h */
1924
1925         __le32 context;         /*08h */
1926         __le32 pad_0;           /*0Ch */
1927
1928         __le16 flags;           /*10h */
1929         __le16 timeout;         /*12h */
1930
1931         __le32 data_xfer_len;   /*14h */
1932         __le64 sas_addr;        /*18h */
1933
1934         union {
1935                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: req */
1936                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: req */
1937         } sgl;
1938
1939 } __attribute__ ((packed));
1940
1941 struct megasas_stp_frame {
1942
1943         u8 cmd;                 /*00h */
1944         u8 reserved_1;          /*01h */
1945         u8 cmd_status;          /*02h */
1946         u8 reserved_2;          /*03h */
1947
1948         u8 target_id;           /*04h */
1949         u8 reserved_3[2];       /*05h */
1950         u8 sge_count;           /*07h */
1951
1952         __le32 context;         /*08h */
1953         __le32 pad_0;           /*0Ch */
1954
1955         __le16 flags;           /*10h */
1956         __le16 timeout;         /*12h */
1957
1958         __le32 data_xfer_len;   /*14h */
1959
1960         __le16 fis[10];         /*18h */
1961         __le32 stp_flags;
1962
1963         union {
1964                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: data */
1965                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: data */
1966         } sgl;
1967
1968 } __attribute__ ((packed));
1969
1970 union megasas_frame {
1971
1972         struct megasas_header hdr;
1973         struct megasas_init_frame init;
1974         struct megasas_io_frame io;
1975         struct megasas_pthru_frame pthru;
1976         struct megasas_dcmd_frame dcmd;
1977         struct megasas_abort_frame abort;
1978         struct megasas_smp_frame smp;
1979         struct megasas_stp_frame stp;
1980
1981         u8 raw_bytes[64];
1982 };
1983
1984 /**
1985  * struct MR_PRIV_DEVICE - sdev private hostdata
1986  * @is_tm_capable: firmware managed tm_capable flag
1987  * @tm_busy: TM request is in progress
1988  */
1989 struct MR_PRIV_DEVICE {
1990         bool is_tm_capable;
1991         bool tm_busy;
1992         atomic_t r1_ldio_hint;
1993         u8 interface_type;
1994         u8 task_abort_tmo;
1995         u8 target_reset_tmo;
1996 };
1997 struct megasas_cmd;
1998
1999 union megasas_evt_class_locale {
2000
2001         struct {
2002 #ifndef __BIG_ENDIAN_BITFIELD
2003                 u16 locale;
2004                 u8 reserved;
2005                 s8 class;
2006 #else
2007                 s8 class;
2008                 u8 reserved;
2009                 u16 locale;
2010 #endif
2011         } __attribute__ ((packed)) members;
2012
2013         u32 word;
2014
2015 } __attribute__ ((packed));
2016
2017 struct megasas_evt_log_info {
2018         __le32 newest_seq_num;
2019         __le32 oldest_seq_num;
2020         __le32 clear_seq_num;
2021         __le32 shutdown_seq_num;
2022         __le32 boot_seq_num;
2023
2024 } __attribute__ ((packed));
2025
2026 struct megasas_progress {
2027
2028         __le16 progress;
2029         __le16 elapsed_seconds;
2030
2031 } __attribute__ ((packed));
2032
2033 struct megasas_evtarg_ld {
2034
2035         u16 target_id;
2036         u8 ld_index;
2037         u8 reserved;
2038
2039 } __attribute__ ((packed));
2040
2041 struct megasas_evtarg_pd {
2042         u16 device_id;
2043         u8 encl_index;
2044         u8 slot_number;
2045
2046 } __attribute__ ((packed));
2047
2048 struct megasas_evt_detail {
2049
2050         __le32 seq_num;
2051         __le32 time_stamp;
2052         __le32 code;
2053         union megasas_evt_class_locale cl;
2054         u8 arg_type;
2055         u8 reserved1[15];
2056
2057         union {
2058                 struct {
2059                         struct megasas_evtarg_pd pd;
2060                         u8 cdb_length;
2061                         u8 sense_length;
2062                         u8 reserved[2];
2063                         u8 cdb[16];
2064                         u8 sense[64];
2065                 } __attribute__ ((packed)) cdbSense;
2066
2067                 struct megasas_evtarg_ld ld;
2068
2069                 struct {
2070                         struct megasas_evtarg_ld ld;
2071                         __le64 count;
2072                 } __attribute__ ((packed)) ld_count;
2073
2074                 struct {
2075                         __le64 lba;
2076                         struct megasas_evtarg_ld ld;
2077                 } __attribute__ ((packed)) ld_lba;
2078
2079                 struct {
2080                         struct megasas_evtarg_ld ld;
2081                         __le32 prevOwner;
2082                         __le32 newOwner;
2083                 } __attribute__ ((packed)) ld_owner;
2084
2085                 struct {
2086                         u64 ld_lba;
2087                         u64 pd_lba;
2088                         struct megasas_evtarg_ld ld;
2089                         struct megasas_evtarg_pd pd;
2090                 } __attribute__ ((packed)) ld_lba_pd_lba;
2091
2092                 struct {
2093                         struct megasas_evtarg_ld ld;
2094                         struct megasas_progress prog;
2095                 } __attribute__ ((packed)) ld_prog;
2096
2097                 struct {
2098                         struct megasas_evtarg_ld ld;
2099                         u32 prev_state;
2100                         u32 new_state;
2101                 } __attribute__ ((packed)) ld_state;
2102
2103                 struct {
2104                         u64 strip;
2105                         struct megasas_evtarg_ld ld;
2106                 } __attribute__ ((packed)) ld_strip;
2107
2108                 struct megasas_evtarg_pd pd;
2109
2110                 struct {
2111                         struct megasas_evtarg_pd pd;
2112                         u32 err;
2113                 } __attribute__ ((packed)) pd_err;
2114
2115                 struct {
2116                         u64 lba;
2117                         struct megasas_evtarg_pd pd;
2118                 } __attribute__ ((packed)) pd_lba;
2119
2120                 struct {
2121                         u64 lba;
2122                         struct megasas_evtarg_pd pd;
2123                         struct megasas_evtarg_ld ld;
2124                 } __attribute__ ((packed)) pd_lba_ld;
2125
2126                 struct {
2127                         struct megasas_evtarg_pd pd;
2128                         struct megasas_progress prog;
2129                 } __attribute__ ((packed)) pd_prog;
2130
2131                 struct {
2132                         struct megasas_evtarg_pd pd;
2133                         u32 prevState;
2134                         u32 newState;
2135                 } __attribute__ ((packed)) pd_state;
2136
2137                 struct {
2138                         u16 vendorId;
2139                         __le16 deviceId;
2140                         u16 subVendorId;
2141                         u16 subDeviceId;
2142                 } __attribute__ ((packed)) pci;
2143
2144                 u32 rate;
2145                 char str[96];
2146
2147                 struct {
2148                         u32 rtc;
2149                         u32 elapsedSeconds;
2150                 } __attribute__ ((packed)) time;
2151
2152                 struct {
2153                         u32 ecar;
2154                         u32 elog;
2155                         char str[64];
2156                 } __attribute__ ((packed)) ecc;
2157
2158                 u8 b[96];
2159                 __le16 s[48];
2160                 __le32 w[24];
2161                 __le64 d[12];
2162         } args;
2163
2164         char description[128];
2165
2166 } __attribute__ ((packed));
2167
2168 struct megasas_aen_event {
2169         struct delayed_work hotplug_work;
2170         struct megasas_instance *instance;
2171 };
2172
2173 struct megasas_irq_context {
2174         struct megasas_instance *instance;
2175         u32 MSIxIndex;
2176 };
2177
2178 struct MR_DRV_SYSTEM_INFO {
2179         u8      infoVersion;
2180         u8      systemIdLength;
2181         u16     reserved0;
2182         u8      systemId[64];
2183         u8      reserved[1980];
2184 };
2185
2186 enum MR_PD_TYPE {
2187         UNKNOWN_DRIVE = 0,
2188         PARALLEL_SCSI = 1,
2189         SAS_PD = 2,
2190         SATA_PD = 3,
2191         FC_PD = 4,
2192         NVME_PD = 5,
2193 };
2194
2195 /* JBOD Queue depth definitions */
2196 #define MEGASAS_SATA_QD 32
2197 #define MEGASAS_SAS_QD  64
2198 #define MEGASAS_DEFAULT_PD_QD   64
2199 #define MEGASAS_NVME_QD         32
2200
2201 #define MR_DEFAULT_NVME_PAGE_SIZE       4096
2202 #define MR_DEFAULT_NVME_PAGE_SHIFT      12
2203 #define MR_DEFAULT_NVME_MDTS_KB         128
2204 #define MR_NVME_PAGE_SIZE_MASK          0x000000FF
2205
2206 struct megasas_instance {
2207
2208         unsigned int *reply_map;
2209         __le32 *producer;
2210         dma_addr_t producer_h;
2211         __le32 *consumer;
2212         dma_addr_t consumer_h;
2213         struct MR_DRV_SYSTEM_INFO *system_info_buf;
2214         dma_addr_t system_info_h;
2215         struct MR_LD_VF_AFFILIATION *vf_affiliation;
2216         dma_addr_t vf_affiliation_h;
2217         struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
2218         dma_addr_t vf_affiliation_111_h;
2219         struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
2220         dma_addr_t hb_host_mem_h;
2221         struct MR_PD_INFO *pd_info;
2222         dma_addr_t pd_info_h;
2223         struct MR_TARGET_PROPERTIES *tgt_prop;
2224         dma_addr_t tgt_prop_h;
2225
2226         __le32 *reply_queue;
2227         dma_addr_t reply_queue_h;
2228
2229         u32 *crash_dump_buf;
2230         dma_addr_t crash_dump_h;
2231
2232         struct MR_PD_LIST *pd_list_buf;
2233         dma_addr_t pd_list_buf_h;
2234
2235         struct megasas_ctrl_info *ctrl_info_buf;
2236         dma_addr_t ctrl_info_buf_h;
2237
2238         struct MR_LD_LIST *ld_list_buf;
2239         dma_addr_t ld_list_buf_h;
2240
2241         struct MR_LD_TARGETID_LIST *ld_targetid_list_buf;
2242         dma_addr_t ld_targetid_list_buf_h;
2243
2244         struct MR_HOST_DEVICE_LIST *host_device_list_buf;
2245         dma_addr_t host_device_list_buf_h;
2246
2247         struct MR_SNAPDUMP_PROPERTIES *snapdump_prop;
2248         dma_addr_t snapdump_prop_h;
2249
2250         void *crash_buf[MAX_CRASH_DUMP_SIZE];
2251         unsigned int    fw_crash_buffer_size;
2252         unsigned int    fw_crash_state;
2253         unsigned int    fw_crash_buffer_offset;
2254         u32 drv_buf_index;
2255         u32 drv_buf_alloc;
2256         u32 crash_dump_fw_support;
2257         u32 crash_dump_drv_support;
2258         u32 crash_dump_app_support;
2259         u32 secure_jbod_support;
2260         u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
2261         bool use_seqnum_jbod_fp;   /* Added for PD sequence */
2262         spinlock_t crashdump_lock;
2263
2264         struct megasas_register_set __iomem *reg_set;
2265         u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
2266         struct megasas_pd_list          pd_list[MEGASAS_MAX_PD];
2267         struct megasas_pd_list          local_pd_list[MEGASAS_MAX_PD];
2268         u8 ld_ids[MEGASAS_MAX_LD_IDS];
2269         s8 init_id;
2270
2271         u16 max_num_sge;
2272         u16 max_fw_cmds;
2273         u16 max_mpt_cmds;
2274         u16 max_mfi_cmds;
2275         u16 max_scsi_cmds;
2276         u16 ldio_threshold;
2277         u16 cur_can_queue;
2278         u32 max_sectors_per_req;
2279         struct megasas_aen_event *ev;
2280
2281         struct megasas_cmd **cmd_list;
2282         struct list_head cmd_pool;
2283         /* used to sync fire the cmd to fw */
2284         spinlock_t mfi_pool_lock;
2285         /* used to sync fire the cmd to fw */
2286         spinlock_t hba_lock;
2287         /* used to synch producer, consumer ptrs in dpc */
2288         spinlock_t stream_lock;
2289         spinlock_t completion_lock;
2290         struct dma_pool *frame_dma_pool;
2291         struct dma_pool *sense_dma_pool;
2292
2293         struct megasas_evt_detail *evt_detail;
2294         dma_addr_t evt_detail_h;
2295         struct megasas_cmd *aen_cmd;
2296         struct semaphore ioctl_sem;
2297
2298         struct Scsi_Host *host;
2299
2300         wait_queue_head_t int_cmd_wait_q;
2301         wait_queue_head_t abort_cmd_wait_q;
2302
2303         struct pci_dev *pdev;
2304         u32 unique_id;
2305         u32 fw_support_ieee;
2306
2307         atomic_t fw_outstanding;
2308         atomic_t ldio_outstanding;
2309         atomic_t fw_reset_no_pci_access;
2310         atomic_t ieee_sgl;
2311         atomic_t prp_sgl;
2312         atomic_t sge_holes_type1;
2313         atomic_t sge_holes_type2;
2314         atomic_t sge_holes_type3;
2315
2316         struct megasas_instance_template *instancet;
2317         struct tasklet_struct isr_tasklet;
2318         struct work_struct work_init;
2319         struct delayed_work fw_fault_work;
2320         struct workqueue_struct *fw_fault_work_q;
2321         char fault_handler_work_q_name[48];
2322
2323         u8 flag;
2324         u8 unload;
2325         u8 flag_ieee;
2326         u8 issuepend_done;
2327         u8 disableOnlineCtrlReset;
2328         u8 UnevenSpanSupport;
2329
2330         u8 supportmax256vd;
2331         u8 pd_list_not_supported;
2332         u16 fw_supported_vd_count;
2333         u16 fw_supported_pd_count;
2334
2335         u16 drv_supported_vd_count;
2336         u16 drv_supported_pd_count;
2337
2338         atomic_t adprecovery;
2339         unsigned long last_time;
2340         u32 mfiStatus;
2341         u32 last_seq_num;
2342
2343         struct list_head internal_reset_pending_q;
2344
2345         /* Ptr to hba specific information */
2346         void *ctrl_context;
2347         unsigned int msix_vectors;
2348         struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
2349         u64 map_id;
2350         u64 pd_seq_map_id;
2351         struct megasas_cmd *map_update_cmd;
2352         struct megasas_cmd *jbod_seq_cmd;
2353         unsigned long bar;
2354         long reset_flags;
2355         struct mutex reset_mutex;
2356         struct timer_list sriov_heartbeat_timer;
2357         char skip_heartbeat_timer_del;
2358         u8 requestorId;
2359         char PlasmaFW111;
2360         char clusterId[MEGASAS_CLUSTER_ID_SIZE];
2361         u8 peerIsPresent;
2362         u8 passive;
2363         u16 throttlequeuedepth;
2364         u8 mask_interrupts;
2365         u16 max_chain_frame_sz;
2366         u8 is_imr;
2367         u8 is_rdpq;
2368         bool dev_handle;
2369         bool fw_sync_cache_support;
2370         u32 mfi_frame_size;
2371         bool msix_combined;
2372         u16 max_raid_mapsize;
2373         /* preffered count to send as LDIO irrspective of FP capable.*/
2374         u8  r1_ldio_hint_default;
2375         u32 nvme_page_size;
2376         u8 adapter_type;
2377         bool consistent_mask_64bit;
2378         bool support_nvme_passthru;
2379         u8 task_abort_tmo;
2380         u8 max_reset_tmo;
2381         u8 snapdump_wait_time;
2382         u8 enable_fw_dev_list;
2383 };
2384 struct MR_LD_VF_MAP {
2385         u32 size;
2386         union MR_LD_REF ref;
2387         u8 ldVfCount;
2388         u8 reserved[6];
2389         u8 policy[1];
2390 };
2391
2392 struct MR_LD_VF_AFFILIATION {
2393         u32 size;
2394         u8 ldCount;
2395         u8 vfCount;
2396         u8 thisVf;
2397         u8 reserved[9];
2398         struct MR_LD_VF_MAP map[1];
2399 };
2400
2401 /* Plasma 1.11 FW backward compatibility structures */
2402 #define IOV_111_OFFSET 0x7CE
2403 #define MAX_VIRTUAL_FUNCTIONS 8
2404 #define MR_LD_ACCESS_HIDDEN 15
2405
2406 struct IOV_111 {
2407         u8 maxVFsSupported;
2408         u8 numVFsEnabled;
2409         u8 requestorId;
2410         u8 reserved[5];
2411 };
2412
2413 struct MR_LD_VF_MAP_111 {
2414         u8 targetId;
2415         u8 reserved[3];
2416         u8 policy[MAX_VIRTUAL_FUNCTIONS];
2417 };
2418
2419 struct MR_LD_VF_AFFILIATION_111 {
2420         u8 vdCount;
2421         u8 vfCount;
2422         u8 thisVf;
2423         u8 reserved[5];
2424         struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
2425 };
2426
2427 struct MR_CTRL_HB_HOST_MEM {
2428         struct {
2429                 u32 fwCounter;  /* Firmware heart beat counter */
2430                 struct {
2431                         u32 debugmode:1; /* 1=Firmware is in debug mode.
2432                                             Heart beat will not be updated. */
2433                         u32 reserved:31;
2434                 } debug;
2435                 u32 reserved_fw[6];
2436                 u32 driverCounter; /* Driver heart beat counter.  0x20 */
2437                 u32 reserved_driver[7];
2438         } HB;
2439         u8 pad[0x400-0x40];
2440 };
2441
2442 enum {
2443         MEGASAS_HBA_OPERATIONAL                 = 0,
2444         MEGASAS_ADPRESET_SM_INFAULT             = 1,
2445         MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS    = 2,
2446         MEGASAS_ADPRESET_SM_OPERATIONAL         = 3,
2447         MEGASAS_HW_CRITICAL_ERROR               = 4,
2448         MEGASAS_ADPRESET_SM_POLLING             = 5,
2449         MEGASAS_ADPRESET_INPROG_SIGN            = 0xDEADDEAD,
2450 };
2451
2452 struct megasas_instance_template {
2453         void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
2454                 u32, struct megasas_register_set __iomem *);
2455
2456         void (*enable_intr)(struct megasas_instance *);
2457         void (*disable_intr)(struct megasas_instance *);
2458
2459         int (*clear_intr)(struct megasas_instance *);
2460
2461         u32 (*read_fw_status_reg)(struct megasas_instance *);
2462         int (*adp_reset)(struct megasas_instance *, \
2463                 struct megasas_register_set __iomem *);
2464         int (*check_reset)(struct megasas_instance *, \
2465                 struct megasas_register_set __iomem *);
2466         irqreturn_t (*service_isr)(int irq, void *devp);
2467         void (*tasklet)(unsigned long);
2468         u32 (*init_adapter)(struct megasas_instance *);
2469         u32 (*build_and_issue_cmd) (struct megasas_instance *,
2470                                     struct scsi_cmnd *);
2471         void (*issue_dcmd)(struct megasas_instance *instance,
2472                             struct megasas_cmd *cmd);
2473 };
2474
2475 #define MEGASAS_IS_LOGICAL(sdev)                                        \
2476         ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2477
2478 #define MEGASAS_DEV_INDEX(scp)                                          \
2479         (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) +   \
2480         scp->device->id)
2481
2482 #define MEGASAS_PD_INDEX(scp)                                           \
2483         ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) +         \
2484         scp->device->id)
2485
2486 struct megasas_cmd {
2487
2488         union megasas_frame *frame;
2489         dma_addr_t frame_phys_addr;
2490         u8 *sense;
2491         dma_addr_t sense_phys_addr;
2492
2493         u32 index;
2494         u8 sync_cmd;
2495         u8 cmd_status_drv;
2496         u8 abort_aen;
2497         u8 retry_for_fw_reset;
2498
2499
2500         struct list_head list;
2501         struct scsi_cmnd *scmd;
2502         u8 flags;
2503
2504         struct megasas_instance *instance;
2505         union {
2506                 struct {
2507                         u16 smid;
2508                         u16 resvd;
2509                 } context;
2510                 u32 frame_count;
2511         };
2512 };
2513
2514 #define MAX_MGMT_ADAPTERS               1024
2515 #define MAX_IOCTL_SGE                   16
2516
2517 struct megasas_iocpacket {
2518
2519         u16 host_no;
2520         u16 __pad1;
2521         u32 sgl_off;
2522         u32 sge_count;
2523         u32 sense_off;
2524         u32 sense_len;
2525         union {
2526                 u8 raw[128];
2527                 struct megasas_header hdr;
2528         } frame;
2529
2530         struct iovec sgl[MAX_IOCTL_SGE];
2531
2532 } __attribute__ ((packed));
2533
2534 struct megasas_aen {
2535         u16 host_no;
2536         u16 __pad1;
2537         u32 seq_num;
2538         u32 class_locale_word;
2539 } __attribute__ ((packed));
2540
2541 #ifdef CONFIG_COMPAT
2542 struct compat_megasas_iocpacket {
2543         u16 host_no;
2544         u16 __pad1;
2545         u32 sgl_off;
2546         u32 sge_count;
2547         u32 sense_off;
2548         u32 sense_len;
2549         union {
2550                 u8 raw[128];
2551                 struct megasas_header hdr;
2552         } frame;
2553         struct compat_iovec sgl[MAX_IOCTL_SGE];
2554 } __attribute__ ((packed));
2555
2556 #define MEGASAS_IOC_FIRMWARE32  _IOWR('M', 1, struct compat_megasas_iocpacket)
2557 #endif
2558
2559 #define MEGASAS_IOC_FIRMWARE    _IOWR('M', 1, struct megasas_iocpacket)
2560 #define MEGASAS_IOC_GET_AEN     _IOW('M', 3, struct megasas_aen)
2561
2562 struct megasas_mgmt_info {
2563
2564         u16 count;
2565         struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2566         int max_index;
2567 };
2568
2569 enum MEGASAS_OCR_CAUSE {
2570         FW_FAULT_OCR                    = 0,
2571         SCSIIO_TIMEOUT_OCR              = 1,
2572         MFI_IO_TIMEOUT_OCR              = 2,
2573 };
2574
2575 enum DCMD_RETURN_STATUS {
2576         DCMD_SUCCESS            = 0,
2577         DCMD_TIMEOUT            = 1,
2578         DCMD_FAILED             = 2,
2579         DCMD_NOT_FIRED          = 3,
2580 };
2581
2582 u8
2583 MR_BuildRaidContext(struct megasas_instance *instance,
2584                     struct IO_REQUEST_INFO *io_info,
2585                     struct RAID_CONTEXT *pRAID_Context,
2586                     struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2587 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2588 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2589 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2590 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
2591 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
2592 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2593
2594 __le16 get_updated_dev_handle(struct megasas_instance *instance,
2595                               struct LD_LOAD_BALANCE_INFO *lbInfo,
2596                               struct IO_REQUEST_INFO *in_info,
2597                               struct MR_DRV_RAID_MAP_ALL *drv_map);
2598 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2599         struct LD_LOAD_BALANCE_INFO *lbInfo);
2600 int megasas_get_ctrl_info(struct megasas_instance *instance);
2601 /* PD sequence */
2602 int
2603 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
2604 void megasas_set_dynamic_target_properties(struct scsi_device *sdev,
2605                                            bool is_target_prop);
2606 int megasas_get_target_prop(struct megasas_instance *instance,
2607                             struct scsi_device *sdev);
2608 void megasas_get_snapdump_properties(struct megasas_instance *instance);
2609
2610 int megasas_set_crash_dump_params(struct megasas_instance *instance,
2611         u8 crash_buf_state);
2612 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2613
2614 void megasas_return_cmd_fusion(struct megasas_instance *instance,
2615         struct megasas_cmd_fusion *cmd);
2616 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2617         struct megasas_cmd *cmd, int timeout);
2618 void __megasas_return_cmd(struct megasas_instance *instance,
2619         struct megasas_cmd *cmd);
2620
2621 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2622         struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2623 int megasas_cmd_type(struct scsi_cmnd *cmd);
2624 void megasas_setup_jbod_map(struct megasas_instance *instance);
2625
2626 void megasas_update_sdev_properties(struct scsi_device *sdev);
2627 int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
2628 int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
2629 int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
2630 u32 mega_mod64(u64 dividend, u32 divisor);
2631 int megasas_alloc_fusion_context(struct megasas_instance *instance);
2632 void megasas_free_fusion_context(struct megasas_instance *instance);
2633 int megasas_fusion_start_watchdog(struct megasas_instance *instance);
2634 void megasas_fusion_stop_watchdog(struct megasas_instance *instance);
2635
2636 void megasas_set_dma_settings(struct megasas_instance *instance,
2637                               struct megasas_dcmd_frame *dcmd,
2638                               dma_addr_t dma_addr, u32 dma_len);
2639 #endif                          /*LSI_MEGARAID_SAS_H */