1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2017 Hisilicon Limited.
6 #include <linux/sched/clock.h>
8 #define DRV_NAME "hisi_sas_v3_hw"
10 /* global registers need init */
11 #define DLVRY_QUEUE_ENABLE 0x0
12 #define IOST_BASE_ADDR_LO 0x8
13 #define IOST_BASE_ADDR_HI 0xc
14 #define ITCT_BASE_ADDR_LO 0x10
15 #define ITCT_BASE_ADDR_HI 0x14
16 #define IO_BROKEN_MSG_ADDR_LO 0x18
17 #define IO_BROKEN_MSG_ADDR_HI 0x1c
18 #define PHY_CONTEXT 0x20
19 #define PHY_STATE 0x24
20 #define PHY_PORT_NUM_MA 0x28
21 #define PHY_CONN_RATE 0x30
23 #define ITCT_CLR_EN_OFF 16
24 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
25 #define ITCT_DEV_OFF 0
26 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
27 #define SAS_AXI_USER3 0x50
28 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
29 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
30 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
31 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
32 #define CFG_MAX_TAG 0x68
33 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
34 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
35 #define HGC_GET_ITV_TIME 0x90
36 #define DEVICE_MSG_WORK_MODE 0x94
37 #define OPENA_WT_CONTI_TIME 0x9c
38 #define I_T_NEXUS_LOSS_TIME 0xa0
39 #define MAX_CON_TIME_LIMIT_TIME 0xa4
40 #define BUS_INACTIVE_LIMIT_TIME 0xa8
41 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
42 #define CQ_INT_CONVERGE_EN 0xb0
43 #define CFG_AGING_TIME 0xbc
44 #define HGC_DFX_CFG2 0xc0
45 #define CFG_ABT_SET_QUERY_IPTT 0xd4
46 #define CFG_SET_ABORTED_IPTT_OFF 0
47 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
48 #define CFG_SET_ABORTED_EN_OFF 12
49 #define CFG_ABT_SET_IPTT_DONE 0xd8
50 #define CFG_ABT_SET_IPTT_DONE_OFF 0
51 #define HGC_IOMB_PROC1_STATUS 0x104
52 #define HGC_LM_DFX_STATUS2 0x128
53 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
54 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
55 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
56 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
57 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
58 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
59 #define HGC_CQE_ECC_ADDR 0x13c
60 #define HGC_CQE_ECC_1B_ADDR_OFF 0
61 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
62 #define HGC_CQE_ECC_MB_ADDR_OFF 8
63 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
64 #define HGC_IOST_ECC_ADDR 0x140
65 #define HGC_IOST_ECC_1B_ADDR_OFF 0
66 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
67 #define HGC_IOST_ECC_MB_ADDR_OFF 16
68 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
69 #define HGC_DQE_ECC_ADDR 0x144
70 #define HGC_DQE_ECC_1B_ADDR_OFF 0
71 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
72 #define HGC_DQE_ECC_MB_ADDR_OFF 16
73 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
74 #define CHNL_INT_STATUS 0x148
76 #define HGC_ITCT_ECC_ADDR 0x150
77 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
78 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
79 HGC_ITCT_ECC_1B_ADDR_OFF)
80 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
81 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
82 HGC_ITCT_ECC_MB_ADDR_OFF)
83 #define HGC_AXI_FIFO_ERR_INFO 0x154
84 #define AXI_ERR_INFO_OFF 0
85 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
86 #define FIFO_ERR_INFO_OFF 8
87 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
88 #define TAB_RD_TYPE 0x15c
89 #define INT_COAL_EN 0x19c
90 #define OQ_INT_COAL_TIME 0x1a0
91 #define OQ_INT_COAL_CNT 0x1a4
92 #define ENT_INT_COAL_TIME 0x1a8
93 #define ENT_INT_COAL_CNT 0x1ac
94 #define OQ_INT_SRC 0x1b0
95 #define OQ_INT_SRC_MSK 0x1b4
96 #define ENT_INT_SRC1 0x1b8
97 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
98 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
99 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
100 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
101 #define ENT_INT_SRC2 0x1bc
102 #define ENT_INT_SRC3 0x1c0
103 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
104 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
105 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
106 #define ENT_INT_SRC3_AXI_OFF 11
107 #define ENT_INT_SRC3_FIFO_OFF 12
108 #define ENT_INT_SRC3_LM_OFF 14
109 #define ENT_INT_SRC3_ITC_INT_OFF 15
110 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
111 #define ENT_INT_SRC3_ABT_OFF 16
112 #define ENT_INT_SRC3_DQE_POISON_OFF 18
113 #define ENT_INT_SRC3_IOST_POISON_OFF 19
114 #define ENT_INT_SRC3_ITCT_POISON_OFF 20
115 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21
116 #define ENT_INT_SRC_MSK1 0x1c4
117 #define ENT_INT_SRC_MSK2 0x1c8
118 #define ENT_INT_SRC_MSK3 0x1cc
119 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
120 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
121 #define CHNL_ENT_INT_MSK 0x1d4
122 #define HGC_COM_INT_MSK 0x1d8
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5
131 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6
132 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7
133 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19
145 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20
146 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21
147 #define SAS_ECC_INTR_MSK 0x1ec
148 #define HGC_ERR_STAT_EN 0x238
149 #define CQE_SEND_CNT 0x248
150 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
151 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
152 #define DLVRY_Q_0_DEPTH 0x268
153 #define DLVRY_Q_0_WR_PTR 0x26c
154 #define DLVRY_Q_0_RD_PTR 0x270
155 #define HYPER_STREAM_ID_EN_CFG 0xc80
156 #define OQ0_INT_SRC_MSK 0xc90
157 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
158 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
159 #define COMPL_Q_0_DEPTH 0x4e8
160 #define COMPL_Q_0_WR_PTR 0x4ec
161 #define COMPL_Q_0_RD_PTR 0x4f0
162 #define HGC_RXM_DFX_STATUS14 0xae8
163 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
164 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM0_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
167 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM1_OFF)
169 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
170 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
171 HGC_RXM_DFX_STATUS14_MEM2_OFF)
172 #define HGC_RXM_DFX_STATUS15 0xaec
173 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
174 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
175 HGC_RXM_DFX_STATUS15_MEM3_OFF)
176 #define AWQOS_AWCACHE_CFG 0xc84
177 #define ARQOS_ARCACHE_CFG 0xc88
178 #define HILINK_ERR_DFX 0xe04
179 #define SAS_GPIO_CFG_0 0x1000
180 #define SAS_GPIO_CFG_1 0x1004
181 #define SAS_GPIO_TX_0_1 0x1040
182 #define SAS_CFG_DRIVE_VLD 0x1070
184 /* phy registers requiring init */
185 #define PORT_BASE (0x2000)
186 #define PHY_CFG (PORT_BASE + 0x0)
187 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
188 #define PHY_CFG_ENA_OFF 0
189 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
190 #define PHY_CFG_DC_OPT_OFF 2
191 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
192 #define PHY_CFG_PHY_RST_OFF 3
193 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF)
194 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
195 #define CFG_PROG_PHY_LINK_RATE_OFF 0
196 #define CFG_PROG_PHY_LINK_RATE_MSK (0xff << CFG_PROG_PHY_LINK_RATE_OFF)
197 #define CFG_PROG_OOB_PHY_LINK_RATE_OFF 8
198 #define CFG_PROG_OOB_PHY_LINK_RATE_MSK (0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
199 #define PHY_CTRL (PORT_BASE + 0x14)
200 #define PHY_CTRL_RESET_OFF 0
201 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
202 #define CMD_HDR_PIR_OFF 8
203 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF)
204 #define SERDES_CFG (PORT_BASE + 0x1c)
205 #define CFG_ALOS_CHK_DISABLE_OFF 9
206 #define CFG_ALOS_CHK_DISABLE_MSK (0x1 << CFG_ALOS_CHK_DISABLE_OFF)
207 #define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)
208 #define CFG_BIST_MODE_SEL_OFF 0
209 #define CFG_BIST_MODE_SEL_MSK (0xf << CFG_BIST_MODE_SEL_OFF)
210 #define CFG_LOOP_TEST_MODE_OFF 14
211 #define CFG_LOOP_TEST_MODE_MSK (0x3 << CFG_LOOP_TEST_MODE_OFF)
212 #define CFG_RX_BIST_EN_OFF 16
213 #define CFG_RX_BIST_EN_MSK (0x1 << CFG_RX_BIST_EN_OFF)
214 #define CFG_TX_BIST_EN_OFF 17
215 #define CFG_TX_BIST_EN_MSK (0x1 << CFG_TX_BIST_EN_OFF)
216 #define CFG_BIST_TEST_OFF 18
217 #define CFG_BIST_TEST_MSK (0x1 << CFG_BIST_TEST_OFF)
218 #define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)
219 #define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)
220 #define SAS_BIST_ERR_CNT (PORT_BASE + 0x38)
221 #define SL_CFG (PORT_BASE + 0x84)
222 #define AIP_LIMIT (PORT_BASE + 0x90)
223 #define SL_CONTROL (PORT_BASE + 0x94)
224 #define SL_CONTROL_NOTIFY_EN_OFF 0
225 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
226 #define SL_CTA_OFF 17
227 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
228 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
229 #define RX_BCAST_CHG_OFF 1
230 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
231 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
232 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
233 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
234 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
235 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
236 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
237 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
238 #define TXID_AUTO (PORT_BASE + 0xb8)
240 #define CT3_MSK (0x1 << CT3_OFF)
241 #define TX_HARDRST_OFF 2
242 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
243 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
244 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
245 #define STP_LINK_TIMER (PORT_BASE + 0x120)
246 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
247 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
248 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
249 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
250 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
251 #define CHL_INT0 (PORT_BASE + 0x1b4)
252 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
253 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
254 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
255 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
256 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
257 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
258 #define CHL_INT0_NOT_RDY_OFF 4
259 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
260 #define CHL_INT0_PHY_RDY_OFF 5
261 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
262 #define CHL_INT1 (PORT_BASE + 0x1b8)
263 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15
264 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16
265 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17
266 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18
267 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
268 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
269 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
270 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
271 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23
272 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24
273 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26
274 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27
275 #define CHL_INT2 (PORT_BASE + 0x1bc)
276 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
277 #define CHL_INT2_RX_DISP_ERR_OFF 28
278 #define CHL_INT2_RX_CODE_ERR_OFF 29
279 #define CHL_INT2_RX_INVLD_DW_OFF 30
280 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
281 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
282 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
283 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
284 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc)
285 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
286 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
287 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
288 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
289 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
290 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
291 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
292 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
293 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
294 #define DMA_TX_STATUS_BUSY_OFF 0
295 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
296 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
297 #define DMA_RX_STATUS_BUSY_OFF 0
298 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
300 #define COARSETUNE_TIME (PORT_BASE + 0x304)
301 #define TXDEEMPH_G1 (PORT_BASE + 0x350)
302 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
303 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
304 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
305 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394)
306 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
307 #define DFX_FIFO_CTRL (PORT_BASE + 0x3a0)
308 #define DFX_FIFO_CTRL_TRIGGER_MODE_OFF 0
309 #define DFX_FIFO_CTRL_TRIGGER_MODE_MSK (0x7 << DFX_FIFO_CTRL_TRIGGER_MODE_OFF)
310 #define DFX_FIFO_CTRL_DUMP_MODE_OFF 3
311 #define DFX_FIFO_CTRL_DUMP_MODE_MSK (0x7 << DFX_FIFO_CTRL_DUMP_MODE_OFF)
312 #define DFX_FIFO_CTRL_SIGNAL_SEL_OFF 6
313 #define DFX_FIFO_CTRL_SIGNAL_SEL_MSK (0xF << DFX_FIFO_CTRL_SIGNAL_SEL_OFF)
314 #define DFX_FIFO_CTRL_DUMP_DISABLE_OFF 10
315 #define DFX_FIFO_CTRL_DUMP_DISABLE_MSK (0x1 << DFX_FIFO_CTRL_DUMP_DISABLE_OFF)
316 #define DFX_FIFO_TRIGGER (PORT_BASE + 0x3a4)
317 #define DFX_FIFO_TRIGGER_MSK (PORT_BASE + 0x3a8)
318 #define DFX_FIFO_DUMP_MSK (PORT_BASE + 0x3aC)
319 #define DFX_FIFO_RD_DATA (PORT_BASE + 0x3b0)
321 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
322 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
323 #error Max ITCT exceeded
326 #define AXI_MASTER_CFG_BASE (0x5000)
327 #define AM_CTRL_GLOBAL (0x0)
328 #define AM_CTRL_SHUTDOWN_REQ_OFF 0
329 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
330 #define AM_CURR_TRANS_RETURN (0x150)
332 #define AM_CFG_MAX_TRANS (0x5010)
333 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
334 #define AXI_CFG (0x5100)
335 #define AM_ROB_ECC_ERR_ADDR (0x510c)
336 #define AM_ROB_ECC_ERR_ADDR_OFF 0
337 #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff
339 /* RAS registers need init */
340 #define RAS_BASE (0x6000)
341 #define SAS_RAS_INTR0 (RAS_BASE)
342 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
343 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
344 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
345 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
346 #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
347 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
349 /* HW dma structures */
350 /* Delivery queue header */
352 #define CMD_HDR_ABORT_FLAG_OFF 0
353 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
354 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
355 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
356 #define CMD_HDR_RESP_REPORT_OFF 5
357 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
358 #define CMD_HDR_TLR_CTRL_OFF 6
359 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
360 #define CMD_HDR_PORT_OFF 18
361 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
362 #define CMD_HDR_PRIORITY_OFF 27
363 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
364 #define CMD_HDR_CMD_OFF 29
365 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
367 #define CMD_HDR_UNCON_CMD_OFF 3
368 #define CMD_HDR_DIR_OFF 5
369 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
370 #define CMD_HDR_RESET_OFF 7
371 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
372 #define CMD_HDR_VDTL_OFF 10
373 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
374 #define CMD_HDR_FRAME_TYPE_OFF 11
375 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
376 #define CMD_HDR_DEV_ID_OFF 16
377 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
379 #define CMD_HDR_CFL_OFF 0
380 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
381 #define CMD_HDR_NCQ_TAG_OFF 10
382 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
383 #define CMD_HDR_MRFL_OFF 15
384 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
385 #define CMD_HDR_SG_MOD_OFF 24
386 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
388 #define CMD_HDR_IPTT_OFF 0
389 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
391 #define CMD_HDR_DIF_SGL_LEN_OFF 0
392 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
393 #define CMD_HDR_DATA_SGL_LEN_OFF 16
394 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
396 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
397 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
398 #define CMD_HDR_ABORT_IPTT_OFF 16
399 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
401 /* Completion header */
403 #define CMPLT_HDR_CMPLT_OFF 0
404 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
405 #define CMPLT_HDR_ERROR_PHASE_OFF 2
406 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
407 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
408 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
409 #define CMPLT_HDR_RSPNS_GOOD_OFF 11
410 #define CMPLT_HDR_RSPNS_GOOD_MSK (0x1 << CMPLT_HDR_RSPNS_GOOD_OFF)
411 #define CMPLT_HDR_ERX_OFF 12
412 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
413 #define CMPLT_HDR_ABORT_STAT_OFF 13
414 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
416 #define STAT_IO_NOT_VALID 0x1
417 #define STAT_IO_NO_DEVICE 0x2
418 #define STAT_IO_COMPLETE 0x3
419 #define STAT_IO_ABORTED 0x4
421 #define CMPLT_HDR_IPTT_OFF 0
422 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
423 #define CMPLT_HDR_DEV_ID_OFF 16
424 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
426 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
427 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
431 #define ITCT_HDR_DEV_TYPE_OFF 0
432 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
433 #define ITCT_HDR_VALID_OFF 2
434 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
435 #define ITCT_HDR_MCR_OFF 5
436 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
437 #define ITCT_HDR_VLN_OFF 9
438 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
439 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
440 #define ITCT_HDR_AWT_CONTINUE_OFF 25
441 #define ITCT_HDR_PORT_ID_OFF 28
442 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
444 #define ITCT_HDR_INLT_OFF 0
445 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
446 #define ITCT_HDR_RTOLT_OFF 48
447 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
449 struct hisi_sas_protect_iu_v3_hw {
459 struct hisi_sas_complete_v3_hdr {
466 struct hisi_sas_err_record_v3 {
468 __le32 trans_tx_fail_type;
471 __le32 trans_rx_fail_type;
474 __le16 dma_tx_err_type;
475 __le16 sipc_rx_err_type;
478 __le32 dma_rx_err_type;
481 #define RX_DATA_LEN_UNDERFLOW_OFF 6
482 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
484 #define RX_FIS_STATUS_ERR_OFF 0
485 #define RX_FIS_STATUS_ERR_MSK (1 << RX_FIS_STATUS_ERR_OFF)
487 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
488 #define HISI_SAS_MSI_COUNT_V3_HW 32
490 #define DIR_NO_DATA 0
492 #define DIR_TO_DEVICE 2
493 #define DIR_RESERVED 3
495 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
496 ((fis.command == ATA_CMD_READ_LOG_EXT) || \
497 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
498 ((fis.command == ATA_CMD_DEV_RESET) && \
499 ((fis.control & ATA_SRST) != 0)))
501 #define T10_INSRT_EN_OFF 0
502 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF)
503 #define T10_RMV_EN_OFF 1
504 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF)
505 #define T10_RPLC_EN_OFF 2
506 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF)
507 #define T10_CHK_EN_OFF 3
508 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF)
509 #define INCR_LBRT_OFF 5
510 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF)
511 #define USR_DATA_BLOCK_SZ_OFF 20
512 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF)
513 #define T10_CHK_MSK_OFF 16
514 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
515 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
517 #define BASE_VECTORS_V3_HW 16
518 #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1)
520 #define CHNL_INT_STS_MSK 0xeeeeeeee
521 #define CHNL_INT_STS_PHY_MSK 0xe
522 #define CHNL_INT_STS_INT0_MSK BIT(1)
523 #define CHNL_INT_STS_INT1_MSK BIT(2)
524 #define CHNL_INT_STS_INT2_MSK BIT(3)
527 #define BAR_NO_V3_HW 5
530 DSM_FUNC_ERR_HANDLE_MSI = 0,
533 static bool hisi_sas_intr_conv;
534 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
536 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
537 static int prot_mask;
538 module_param(prot_mask, int, 0444);
539 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
541 static void debugfs_work_handler_v3_hw(struct work_struct *work);
542 static void debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba);
544 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
546 void __iomem *regs = hisi_hba->regs + off;
551 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
553 void __iomem *regs = hisi_hba->regs + off;
558 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
561 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
566 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
569 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
574 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
577 void __iomem *regs = hisi_hba->regs + off; \
578 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
581 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
584 void __iomem *regs = hisi_hba->regs + off; \
585 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
588 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
592 /* Global registers init */
593 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
594 (u32)((1ULL << hisi_hba->queue_count) - 1));
595 hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
596 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
597 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
598 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
599 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
600 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
601 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
602 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
604 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
605 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
606 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
607 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
608 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
609 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
610 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
611 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
612 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
613 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
614 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);
615 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
616 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
617 for (i = 0; i < hisi_hba->queue_count; i++)
618 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
620 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
622 for (i = 0; i < hisi_hba->n_phy; i++) {
623 enum sas_linkrate max;
624 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
625 struct asd_sas_phy *sas_phy = &phy->sas_phy;
626 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
629 prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
630 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
631 SAS_LINK_RATE_1_5_GBPS))
632 max = SAS_LINK_RATE_12_0_GBPS;
634 max = sas_phy->phy->maximum_linkrate;
635 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
636 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
638 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
639 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
640 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
641 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
642 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
643 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
644 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
645 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
646 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
647 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
648 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
649 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
650 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
651 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
652 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
653 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
654 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
655 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
657 /* used for 12G negotiate */
658 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
659 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
661 /* get default FFE configuration for BIST */
662 for (j = 0; j < FFE_CFG_MAX; j++) {
663 u32 val = hisi_sas_phy_read32(hisi_hba, i,
664 TXDEEMPH_G1 + (j * 0x4));
665 hisi_hba->debugfs_bist_ffe[i][j] = val;
669 for (i = 0; i < hisi_hba->queue_count; i++) {
671 hisi_sas_write32(hisi_hba,
672 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
673 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
675 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
676 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
678 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
679 HISI_SAS_QUEUE_SLOTS);
681 /* Completion queue */
682 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
683 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
685 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
686 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
688 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
689 HISI_SAS_QUEUE_SLOTS);
693 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
694 lower_32_bits(hisi_hba->itct_dma));
696 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
697 upper_32_bits(hisi_hba->itct_dma));
700 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
701 lower_32_bits(hisi_hba->iost_dma));
703 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
704 upper_32_bits(hisi_hba->iost_dma));
707 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
708 lower_32_bits(hisi_hba->breakpoint_dma));
710 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
711 upper_32_bits(hisi_hba->breakpoint_dma));
713 /* SATA broken msg */
714 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
715 lower_32_bits(hisi_hba->sata_breakpoint_dma));
717 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
718 upper_32_bits(hisi_hba->sata_breakpoint_dma));
720 /* SATA initial fis */
721 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
722 lower_32_bits(hisi_hba->initial_fis_dma));
724 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
725 upper_32_bits(hisi_hba->initial_fis_dma));
727 /* RAS registers init */
728 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
729 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
730 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
731 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
733 /* LED registers init */
734 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
735 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
736 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
737 /* Configure blink generator rate A to 1Hz and B to 4Hz */
738 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
739 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
742 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
744 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
746 cfg &= ~PHY_CFG_DC_OPT_MSK;
747 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
748 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
751 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
753 struct sas_identify_frame identify_frame;
754 u32 *identify_buffer;
756 memset(&identify_frame, 0, sizeof(identify_frame));
757 identify_frame.dev_type = SAS_END_DEVICE;
758 identify_frame.frame_type = 0;
759 identify_frame._un1 = 1;
760 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
761 identify_frame.target_bits = SAS_PROTOCOL_NONE;
762 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
763 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
764 identify_frame.phy_id = phy_no;
765 identify_buffer = (u32 *)(&identify_frame);
767 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
768 __swab32(identify_buffer[0]));
769 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
770 __swab32(identify_buffer[1]));
771 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
772 __swab32(identify_buffer[2]));
773 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
774 __swab32(identify_buffer[3]));
775 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
776 __swab32(identify_buffer[4]));
777 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
778 __swab32(identify_buffer[5]));
781 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
782 struct hisi_sas_device *sas_dev)
784 struct domain_device *device = sas_dev->sas_device;
785 struct device *dev = hisi_hba->dev;
786 u64 qw0, device_id = sas_dev->device_id;
787 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
788 struct domain_device *parent_dev = device->parent;
789 struct asd_sas_port *sas_port = device->port;
790 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
793 memset(itct, 0, sizeof(*itct));
797 switch (sas_dev->dev_type) {
799 case SAS_EDGE_EXPANDER_DEVICE:
800 case SAS_FANOUT_EXPANDER_DEVICE:
801 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
804 case SAS_SATA_PENDING:
805 if (parent_dev && dev_is_expander(parent_dev->dev_type))
806 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
808 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
811 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
815 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
816 (device->linkrate << ITCT_HDR_MCR_OFF) |
817 (1 << ITCT_HDR_VLN_OFF) |
818 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
819 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
820 (port->id << ITCT_HDR_PORT_ID_OFF));
821 itct->qw0 = cpu_to_le64(qw0);
824 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
825 itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
828 if (!dev_is_sata(device))
829 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
830 (0x1ULL << ITCT_HDR_RTOLT_OFF));
833 static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
834 struct hisi_sas_device *sas_dev)
836 DECLARE_COMPLETION_ONSTACK(completion);
837 u64 dev_id = sas_dev->device_id;
838 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
839 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
840 struct device *dev = hisi_hba->dev;
842 sas_dev->completion = &completion;
844 /* clear the itct interrupt state */
845 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
846 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
847 ENT_INT_SRC3_ITC_INT_MSK);
849 /* clear the itct table */
850 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
851 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
853 if (!wait_for_completion_timeout(sas_dev->completion,
854 HISI_SAS_CLEAR_ITCT_TIMEOUT)) {
855 dev_warn(dev, "failed to clear ITCT\n");
859 memset(itct, 0, sizeof(struct hisi_sas_itct));
863 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
864 struct domain_device *device)
866 struct hisi_sas_slot *slot, *slot2;
867 struct hisi_sas_device *sas_dev = device->lldd_dev;
868 u32 cfg_abt_set_query_iptt;
870 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
871 CFG_ABT_SET_QUERY_IPTT);
872 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
873 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
874 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
875 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
876 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
877 cfg_abt_set_query_iptt);
879 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
880 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
881 cfg_abt_set_query_iptt);
882 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
883 1 << CFG_ABT_SET_IPTT_DONE_OFF);
886 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
888 struct device *dev = hisi_hba->dev;
892 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
894 /* Disable all of the PHYs */
895 hisi_sas_stop_phys(hisi_hba);
898 /* Ensure axi bus idle */
899 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
902 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
906 if (ACPI_HANDLE(dev)) {
909 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
910 if (ACPI_FAILURE(s)) {
911 dev_err(dev, "Reset failed\n");
915 dev_err(dev, "no reset method!\n");
922 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
924 struct device *dev = hisi_hba->dev;
925 struct acpi_device *acpi_dev;
926 union acpi_object *obj;
930 rc = reset_hw_v3_hw(hisi_hba);
932 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
937 init_reg_v3_hw(hisi_hba);
939 if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
940 dev_err(dev, "Parse GUID failed\n");
945 * This DSM handles some hardware-related configurations:
946 * 1. Switch over to MSI error handling in kernel
947 * 2. BIOS *may* reset some register values through this method
949 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
950 DSM_FUNC_ERR_HANDLE_MSI, NULL);
952 dev_warn(dev, "can not find DSM method, ignore\n");
956 acpi_dev = ACPI_COMPANION(dev);
957 if (!acpi_device_power_manageable(acpi_dev))
958 dev_notice(dev, "neither _PS0 nor _PR0 is defined\n");
962 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
964 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
966 cfg |= PHY_CFG_ENA_MSK;
967 cfg &= ~PHY_CFG_PHY_RST_MSK;
968 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
971 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
973 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
974 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
975 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
976 BIT(CHL_INT2_RX_CODE_ERR_OFF) |
977 BIT(CHL_INT2_RX_INVLD_DW_OFF);
980 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
982 cfg &= ~PHY_CFG_ENA_MSK;
983 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
987 state = hisi_sas_read32(hisi_hba, PHY_STATE);
988 if (state & BIT(phy_no)) {
989 cfg |= PHY_CFG_PHY_RST_MSK;
990 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
995 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
996 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
997 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
999 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
1000 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
1003 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1005 config_id_frame_v3_hw(hisi_hba, phy_no);
1006 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
1007 enable_phy_v3_hw(hisi_hba, phy_no);
1010 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1012 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1015 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
1016 if (phy->identify.device_type == SAS_END_DEVICE) {
1017 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1018 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1019 txid_auto | TX_HARDRST_MSK);
1022 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1025 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
1027 return SAS_LINK_RATE_12_0_GBPS;
1030 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
1034 for (i = 0; i < hisi_hba->n_phy; i++) {
1035 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1036 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1038 if (!sas_phy->phy->enabled)
1041 hisi_sas_phy_enable(hisi_hba, i, 1);
1045 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1049 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1050 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1051 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1053 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1054 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1055 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1058 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
1061 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1062 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1064 for (i = 0; i < hisi_hba->n_phy; i++)
1065 if (phy_state & BIT(i))
1066 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1072 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
1074 struct hisi_hba *hisi_hba = dq->hisi_hba;
1075 struct hisi_sas_slot *s, *s1, *s2 = NULL;
1076 int dlvry_queue = dq->id;
1079 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1083 list_del(&s->delivery);
1090 * Ensure that memories for slots built on other CPUs is observed.
1093 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1095 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1098 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
1099 struct hisi_sas_slot *slot,
1100 struct hisi_sas_cmd_hdr *hdr,
1101 struct scatterlist *scatter,
1104 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1105 struct scatterlist *sg;
1108 for_each_sg(scatter, sg, n_elem, i) {
1109 struct hisi_sas_sge *entry = &sge_page->sge[i];
1111 entry->addr = cpu_to_le64(sg_dma_address(sg));
1112 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1113 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1114 entry->data_off = 0;
1117 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1119 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1122 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
1123 struct hisi_sas_slot *slot,
1124 struct hisi_sas_cmd_hdr *hdr,
1125 struct scatterlist *scatter,
1128 struct hisi_sas_sge_dif_page *sge_dif_page;
1129 struct scatterlist *sg;
1132 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1134 for_each_sg(scatter, sg, n_elem, i) {
1135 struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1137 entry->addr = cpu_to_le64(sg_dma_address(sg));
1138 entry->page_ctrl_0 = 0;
1139 entry->page_ctrl_1 = 0;
1140 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1141 entry->data_off = 0;
1144 hdr->dif_prd_table_addr =
1145 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1147 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1150 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1152 unsigned char prot_flags = scsi_cmnd->prot_flags;
1154 if (prot_flags & SCSI_PROT_REF_CHECK)
1155 return T10_CHK_APP_TAG_MSK;
1156 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1159 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1160 struct hisi_sas_protect_iu_v3_hw *prot)
1162 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1163 unsigned int interval = scsi_prot_interval(scsi_cmnd);
1164 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmd_to_rq(scsi_cmnd));
1167 case SCSI_PROT_READ_INSERT:
1168 prot->dw0 |= T10_INSRT_EN_MSK;
1169 prot->lbrtgv = lbrt_chk_val;
1171 case SCSI_PROT_READ_STRIP:
1172 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1173 prot->lbrtcv = lbrt_chk_val;
1174 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1176 case SCSI_PROT_READ_PASS:
1177 prot->dw0 |= T10_CHK_EN_MSK;
1178 prot->lbrtcv = lbrt_chk_val;
1179 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1181 case SCSI_PROT_WRITE_INSERT:
1182 prot->dw0 |= T10_INSRT_EN_MSK;
1183 prot->lbrtgv = lbrt_chk_val;
1185 case SCSI_PROT_WRITE_STRIP:
1186 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1187 prot->lbrtcv = lbrt_chk_val;
1189 case SCSI_PROT_WRITE_PASS:
1190 prot->dw0 |= T10_CHK_EN_MSK;
1191 prot->lbrtcv = lbrt_chk_val;
1192 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1195 WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1203 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1206 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1209 WARN(1, "protection interval (0x%x) invalid\n",
1214 prot->dw0 |= INCR_LBRT_MSK;
1217 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1218 struct hisi_sas_slot *slot)
1220 struct sas_task *task = slot->task;
1221 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1222 struct domain_device *device = task->dev;
1223 struct hisi_sas_device *sas_dev = device->lldd_dev;
1224 struct hisi_sas_port *port = slot->port;
1225 struct sas_ssp_task *ssp_task = &task->ssp_task;
1226 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1227 struct sas_tmf_task *tmf = slot->tmf;
1228 int has_data = 0, priority = !!tmf;
1229 unsigned char prot_op;
1231 u32 dw1 = 0, dw2 = 0, len = 0;
1233 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1234 (2 << CMD_HDR_TLR_CTRL_OFF) |
1235 (port->id << CMD_HDR_PORT_OFF) |
1236 (priority << CMD_HDR_PRIORITY_OFF) |
1237 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1239 dw1 = 1 << CMD_HDR_VDTL_OFF;
1241 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1242 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1244 prot_op = scsi_get_prot_op(scsi_cmnd);
1245 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1246 switch (scsi_cmnd->sc_data_direction) {
1249 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1251 case DMA_FROM_DEVICE:
1253 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1256 dw1 &= ~CMD_HDR_DIR_MSK;
1260 /* map itct entry */
1261 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1263 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1264 + 3) / 4) << CMD_HDR_CFL_OFF) |
1265 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1266 (2 << CMD_HDR_SG_MOD_OFF);
1267 hdr->dw2 = cpu_to_le32(dw2);
1268 hdr->transfer_tags = cpu_to_le32(slot->idx);
1271 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1274 if (scsi_prot_sg_count(scsi_cmnd))
1275 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1276 scsi_prot_sglist(scsi_cmnd),
1280 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1281 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1283 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1284 sizeof(struct ssp_frame_hdr);
1286 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1288 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
1289 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1291 buf_cmd[10] = tmf->tmf;
1293 case TMF_ABORT_TASK:
1294 case TMF_QUERY_TASK:
1296 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1298 tmf->tag_of_task_to_be_managed & 0xff;
1305 if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1306 struct hisi_sas_protect_iu_v3_hw prot;
1309 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1310 dw1 |= CMD_HDR_PIR_MSK;
1311 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1312 sizeof(struct ssp_frame_hdr) +
1313 sizeof(struct ssp_command_iu);
1315 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1316 fill_prot_v3_hw(scsi_cmnd, &prot);
1317 memcpy(buf_cmd_prot, &prot,
1318 sizeof(struct hisi_sas_protect_iu_v3_hw));
1320 * For READ, we need length of info read to memory, while for
1321 * WRITE we need length of data written to the disk.
1323 if (prot_op == SCSI_PROT_WRITE_INSERT ||
1324 prot_op == SCSI_PROT_READ_INSERT ||
1325 prot_op == SCSI_PROT_WRITE_PASS ||
1326 prot_op == SCSI_PROT_READ_PASS) {
1327 unsigned int interval = scsi_prot_interval(scsi_cmnd);
1328 unsigned int ilog2_interval = ilog2(interval);
1330 len = (task->total_xfer_len >> ilog2_interval) * 8;
1334 hdr->dw1 = cpu_to_le32(dw1);
1336 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1339 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1340 struct hisi_sas_slot *slot)
1342 struct sas_task *task = slot->task;
1343 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1344 struct domain_device *device = task->dev;
1345 struct hisi_sas_port *port = slot->port;
1346 struct scatterlist *sg_req;
1347 struct hisi_sas_device *sas_dev = device->lldd_dev;
1348 dma_addr_t req_dma_addr;
1349 unsigned int req_len;
1352 sg_req = &task->smp_task.smp_req;
1353 req_len = sg_dma_len(sg_req);
1354 req_dma_addr = sg_dma_address(sg_req);
1358 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1359 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1360 (2 << CMD_HDR_CMD_OFF)); /* smp */
1362 /* map itct entry */
1363 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1364 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1365 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1368 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1369 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1372 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1374 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1375 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1378 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1379 struct hisi_sas_slot *slot)
1381 struct sas_task *task = slot->task;
1382 struct domain_device *device = task->dev;
1383 struct domain_device *parent_dev = device->parent;
1384 struct hisi_sas_device *sas_dev = device->lldd_dev;
1385 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1386 struct asd_sas_port *sas_port = device->port;
1387 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1389 int has_data = 0, hdr_tag = 0;
1390 u32 dw1 = 0, dw2 = 0;
1392 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1393 if (parent_dev && dev_is_expander(parent_dev->dev_type))
1394 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1396 hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
1398 switch (task->data_dir) {
1401 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1403 case DMA_FROM_DEVICE:
1405 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1408 dw1 &= ~CMD_HDR_DIR_MSK;
1411 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1412 (task->ata_task.fis.control & ATA_SRST))
1413 dw1 |= 1 << CMD_HDR_RESET_OFF;
1415 dw1 |= (hisi_sas_get_ata_protocol(
1416 &task->ata_task.fis, task->data_dir))
1417 << CMD_HDR_FRAME_TYPE_OFF;
1418 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1420 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1421 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1423 hdr->dw1 = cpu_to_le32(dw1);
1426 if (task->ata_task.use_ncq) {
1427 struct ata_queued_cmd *qc = task->uldd_task;
1430 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1431 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1434 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1435 2 << CMD_HDR_SG_MOD_OFF;
1436 hdr->dw2 = cpu_to_le32(dw2);
1439 hdr->transfer_tags = cpu_to_le32(slot->idx);
1442 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1445 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1446 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1447 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1449 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1451 if (likely(!task->ata_task.device_control_reg_update))
1452 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1453 /* fill in command FIS */
1454 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1457 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1458 struct hisi_sas_slot *slot)
1460 struct sas_task *task = slot->task;
1461 struct sas_internal_abort_task *abort = &task->abort_task;
1462 struct domain_device *dev = task->dev;
1463 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1464 struct hisi_sas_port *port = slot->port;
1465 struct hisi_sas_device *sas_dev = dev->lldd_dev;
1466 bool sata = dev_is_sata(dev);
1469 hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /* abort */
1470 (port->id << CMD_HDR_PORT_OFF) |
1471 (sata << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1472 (abort->type << CMD_HDR_ABORT_FLAG_OFF));
1475 hdr->dw1 = cpu_to_le32(sas_dev->device_id
1476 << CMD_HDR_DEV_ID_OFF);
1479 hdr->dw7 = cpu_to_le32(abort->tag << CMD_HDR_ABORT_IPTT_OFF);
1480 hdr->transfer_tags = cpu_to_le32(slot->idx);
1483 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1487 u32 context, port_id, link_rate;
1488 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1489 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1490 struct device *dev = hisi_hba->dev;
1492 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1494 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1495 port_id = (port_id >> (4 * phy_no)) & 0xf;
1496 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1497 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1499 if (port_id == 0xf) {
1500 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1504 sas_phy->linkrate = link_rate;
1505 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1507 /* Check for SATA dev */
1508 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1509 if (context & (1 << phy_no)) {
1510 struct hisi_sas_initial_fis *initial_fis;
1511 struct dev_to_host_fis *fis;
1512 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1513 struct Scsi_Host *shost = hisi_hba->shost;
1515 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1516 initial_fis = &hisi_hba->initial_fis[phy_no];
1517 fis = &initial_fis->fis;
1519 /* check ERR bit of Status Register */
1520 if (fis->status & ATA_ERR) {
1521 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1522 phy_no, fis->status);
1523 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1528 sas_phy->oob_mode = SATA_OOB_MODE;
1529 attached_sas_addr[0] = 0x50;
1530 attached_sas_addr[6] = shost->host_no;
1531 attached_sas_addr[7] = phy_no;
1532 memcpy(sas_phy->attached_sas_addr,
1535 memcpy(sas_phy->frame_rcvd, fis,
1536 sizeof(struct dev_to_host_fis));
1537 phy->phy_type |= PORT_TYPE_SATA;
1538 phy->identify.device_type = SAS_SATA_DEV;
1539 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1540 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1542 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1543 struct sas_identify_frame *id =
1544 (struct sas_identify_frame *)frame_rcvd;
1546 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1547 for (i = 0; i < 6; i++) {
1548 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1549 RX_IDAF_DWORD0 + (i * 4));
1550 frame_rcvd[i] = __swab32(idaf);
1552 sas_phy->oob_mode = SAS_OOB_MODE;
1553 memcpy(sas_phy->attached_sas_addr,
1556 phy->phy_type |= PORT_TYPE_SAS;
1557 phy->identify.device_type = id->dev_type;
1558 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1559 if (phy->identify.device_type == SAS_END_DEVICE)
1560 phy->identify.target_port_protocols =
1562 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1563 phy->identify.target_port_protocols =
1567 phy->port_id = port_id;
1570 * Call pm_runtime_get_noresume() which pairs with
1571 * hisi_sas_phyup_pm_work() -> pm_runtime_put_sync().
1572 * For failure call pm_runtime_put() as we are in a hardirq context.
1574 pm_runtime_get_noresume(dev);
1575 res = hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP_PM);
1577 pm_runtime_put(dev);
1581 spin_lock(&phy->lock);
1582 /* Delete timer and set phy_attached atomically */
1583 del_timer(&phy->timer);
1584 phy->phy_attached = 1;
1585 spin_unlock(&phy->lock);
1587 if (phy->reset_completion)
1588 complete(phy->reset_completion);
1589 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1590 CHL_INT0_SL_PHY_ENABLE_MSK);
1591 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1596 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1598 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1599 u32 phy_state, sl_ctrl, txid_auto;
1600 struct device *dev = hisi_hba->dev;
1602 atomic_inc(&phy->down_cnt);
1604 del_timer(&phy->timer);
1605 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1607 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1608 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1609 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0,
1612 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1613 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1614 sl_ctrl&(~SL_CTA_MSK));
1616 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1617 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1618 txid_auto | CT3_MSK);
1620 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1621 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1626 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1628 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1629 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1632 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1633 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1634 if ((bcast_status & RX_BCAST_CHG_MSK) &&
1635 !test_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
1636 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
1638 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1639 CHL_INT0_SL_RX_BCST_ACK_MSK);
1640 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1645 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1647 struct hisi_hba *hisi_hba = p;
1650 irqreturn_t res = IRQ_NONE;
1652 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1656 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1658 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1659 int rdy = phy_state & (1 << phy_no);
1662 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1664 if (phy_up_v3_hw(phy_no, hisi_hba)
1667 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1669 if (phy_bcast_v3_hw(phy_no, hisi_hba)
1673 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1675 if (phy_down_v3_hw(phy_no, hisi_hba)
1687 static const struct hisi_sas_hw_error port_axi_error[] = {
1689 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
1690 .msg = "dmac_tx_ecc_bad_err",
1693 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
1694 .msg = "dmac_rx_ecc_bad_err",
1697 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1698 .msg = "dma_tx_axi_wr_err",
1701 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1702 .msg = "dma_tx_axi_rd_err",
1705 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1706 .msg = "dma_rx_axi_wr_err",
1709 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1710 .msg = "dma_rx_axi_rd_err",
1713 .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
1714 .msg = "dma_tx_fifo_err",
1717 .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
1718 .msg = "dma_rx_fifo_err",
1721 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
1722 .msg = "dma_tx_axi_ruser_err",
1725 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
1726 .msg = "dma_rx_axi_ruser_err",
1730 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1732 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1733 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1734 struct device *dev = hisi_hba->dev;
1737 irq_value &= ~irq_msk;
1739 dev_warn(dev, "phy%d channel int 1 received with status bits cleared\n",
1744 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1745 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1747 if (!(irq_value & error->irq_msk))
1750 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1751 error->msg, phy_no, irq_value);
1752 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1755 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1758 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1760 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1761 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1762 struct sas_phy *sphy = sas_phy->phy;
1763 unsigned long flags;
1766 spin_lock_irqsave(&phy->lock, flags);
1768 /* loss dword sync */
1769 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1770 sphy->loss_of_dword_sync_count += reg_value;
1772 /* phy reset problem */
1773 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1774 sphy->phy_reset_problem_count += reg_value;
1777 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1778 sphy->invalid_dword_count += reg_value;
1781 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1782 sphy->running_disparity_error_count += reg_value;
1784 /* code violation error */
1785 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1786 phy->code_violation_err_count += reg_value;
1788 spin_unlock_irqrestore(&phy->lock, flags);
1791 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1793 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1794 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1795 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1796 struct pci_dev *pci_dev = hisi_hba->pci_dev;
1797 struct device *dev = hisi_hba->dev;
1798 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1799 BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1800 BIT(CHL_INT2_RX_INVLD_DW_OFF);
1802 irq_value &= ~irq_msk;
1804 dev_warn(dev, "phy%d channel int 2 received with status bits cleared\n",
1809 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1810 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1811 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1814 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1815 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1816 STP_LINK_TIMEOUT_STATE);
1818 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1820 if (reg_value & BIT(4))
1821 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1824 if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1825 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1826 struct sas_phy *sphy = sas_phy->phy;
1828 phy_get_events_v3_hw(hisi_hba, phy_no);
1830 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1831 dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no,
1832 sphy->invalid_dword_count);
1834 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1835 dev_info(dev, "phy%d code violation cnt: %u\n", phy_no,
1836 phy->code_violation_err_count);
1838 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1839 dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1840 sphy->running_disparity_error_count);
1843 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1844 (pci_dev->revision == 0x20)) {
1848 rc = hisi_sas_read32_poll_timeout_atomic(
1849 HILINK_ERR_DFX, reg_value,
1850 !((reg_value >> 8) & BIT(phy_no)),
1853 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1856 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1859 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1861 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1863 if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1864 hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1866 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1867 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1868 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1869 & (~CHL_INT0_NOT_RDY_MSK));
1872 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1874 struct hisi_hba *hisi_hba = p;
1878 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1882 if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
1883 handle_chl_int0_v3_hw(hisi_hba, phy_no);
1885 if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
1886 handle_chl_int1_v3_hw(hisi_hba, phy_no);
1888 if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
1889 handle_chl_int2_v3_hw(hisi_hba, phy_no);
1891 irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
1898 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
1900 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
1901 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
1902 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
1903 .msg = "hgc_dqe_eccbad_intr",
1904 .reg = HGC_DQE_ECC_ADDR,
1907 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
1908 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
1909 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
1910 .msg = "hgc_iost_eccbad_intr",
1911 .reg = HGC_IOST_ECC_ADDR,
1914 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
1915 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
1916 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
1917 .msg = "hgc_itct_eccbad_intr",
1918 .reg = HGC_ITCT_ECC_ADDR,
1921 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
1922 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
1923 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
1924 .msg = "hgc_iostl_eccbad_intr",
1925 .reg = HGC_LM_DFX_STATUS2,
1928 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
1929 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
1930 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
1931 .msg = "hgc_itctl_eccbad_intr",
1932 .reg = HGC_LM_DFX_STATUS2,
1935 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
1936 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
1937 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
1938 .msg = "hgc_cqe_eccbad_intr",
1939 .reg = HGC_CQE_ECC_ADDR,
1942 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
1943 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
1944 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
1945 .msg = "rxm_mem0_eccbad_intr",
1946 .reg = HGC_RXM_DFX_STATUS14,
1949 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
1950 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
1951 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
1952 .msg = "rxm_mem1_eccbad_intr",
1953 .reg = HGC_RXM_DFX_STATUS14,
1956 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
1957 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
1958 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
1959 .msg = "rxm_mem2_eccbad_intr",
1960 .reg = HGC_RXM_DFX_STATUS14,
1963 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
1964 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
1965 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
1966 .msg = "rxm_mem3_eccbad_intr",
1967 .reg = HGC_RXM_DFX_STATUS15,
1970 .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
1971 .msk = AM_ROB_ECC_ERR_ADDR_MSK,
1972 .shift = AM_ROB_ECC_ERR_ADDR_OFF,
1973 .msg = "ooo_ram_eccbad_intr",
1974 .reg = AM_ROB_ECC_ERR_ADDR,
1978 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
1981 struct device *dev = hisi_hba->dev;
1982 const struct hisi_sas_hw_error *ecc_error;
1986 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
1987 ecc_error = &multi_bit_ecc_errors[i];
1988 if (irq_value & ecc_error->irq_msk) {
1989 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
1990 val &= ecc_error->msk;
1991 val >>= ecc_error->shift;
1992 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
1993 ecc_error->msg, irq_value, val);
1994 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1999 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
2001 u32 irq_value, irq_msk;
2003 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2004 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2006 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2008 multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
2010 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2011 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2014 static const struct hisi_sas_hw_error axi_error[] = {
2015 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2016 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2017 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2018 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2019 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2020 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
2021 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
2022 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
2026 static const struct hisi_sas_hw_error fifo_error[] = {
2027 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
2028 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
2029 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
2030 { .msk = BIT(11), .msg = "CMDP_FIFO" },
2031 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2035 static const struct hisi_sas_hw_error fatal_axi_error[] = {
2037 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2038 .msg = "write pointer and depth",
2041 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2042 .msg = "iptt no match slot",
2045 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2046 .msg = "read pointer and depth",
2049 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2050 .reg = HGC_AXI_FIFO_ERR_INFO,
2054 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2055 .reg = HGC_AXI_FIFO_ERR_INFO,
2059 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2060 .msg = "LM add/fetch list",
2063 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2064 .msg = "SAS_HGC_ABT fetch LM list",
2067 .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
2068 .msg = "read dqe poison",
2071 .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
2072 .msg = "read iost poison",
2075 .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
2076 .msg = "read itct poison",
2079 .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
2080 .msg = "read itct ncq poison",
2085 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
2087 u32 irq_value, irq_msk;
2088 struct hisi_hba *hisi_hba = p;
2089 struct device *dev = hisi_hba->dev;
2090 struct pci_dev *pdev = hisi_hba->pci_dev;
2093 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2094 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
2096 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2097 irq_value &= ~irq_msk;
2099 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
2100 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
2102 if (!(irq_value & error->irq_msk))
2106 const struct hisi_sas_hw_error *sub = error->sub;
2107 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
2109 for (; sub->msk || sub->msg; sub++) {
2110 if (!(err_value & sub->msk))
2113 dev_err(dev, "%s error (0x%x) found!\n",
2114 sub->msg, irq_value);
2115 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2118 dev_err(dev, "%s error (0x%x) found!\n",
2119 error->msg, irq_value);
2120 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2123 if (pdev->revision < 0x21) {
2126 reg_val = hisi_sas_read32(hisi_hba,
2127 AXI_MASTER_CFG_BASE +
2129 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2130 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2131 AM_CTRL_GLOBAL, reg_val);
2135 fatal_ecc_int_v3_hw(hisi_hba);
2137 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
2138 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
2139 u32 dev_id = reg_val & ITCT_DEV_MSK;
2140 struct hisi_sas_device *sas_dev =
2141 &hisi_hba->devices[dev_id];
2143 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
2144 dev_dbg(dev, "clear ITCT ok\n");
2145 complete(sas_dev->completion);
2148 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
2149 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
2155 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
2156 struct hisi_sas_slot *slot)
2158 struct task_status_struct *ts = &task->task_status;
2159 struct hisi_sas_complete_v3_hdr *complete_queue =
2160 hisi_hba->complete_hdr[slot->cmplt_queue];
2161 struct hisi_sas_complete_v3_hdr *complete_hdr =
2162 &complete_queue[slot->cmplt_queue_slot];
2163 struct hisi_sas_err_record_v3 *record =
2164 hisi_sas_status_buf_addr_mem(slot);
2165 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
2166 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2167 u16 sipc_rx_err_type = le16_to_cpu(record->sipc_rx_err_type);
2168 u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2170 switch (task->task_proto) {
2171 case SAS_PROTOCOL_SSP:
2172 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2174 * If returned response frame is incorrect because of data underflow,
2175 * but I/O information has been written to the host memory, we examine
2178 if (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&
2179 (complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))
2182 ts->residual = trans_tx_fail_type;
2183 ts->stat = SAS_DATA_UNDERRUN;
2184 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2185 ts->stat = SAS_QUEUE_FULL;
2188 ts->stat = SAS_OPEN_REJECT;
2189 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2192 case SAS_PROTOCOL_SATA:
2193 case SAS_PROTOCOL_STP:
2194 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2195 if ((complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) &&
2196 (sipc_rx_err_type & RX_FIS_STATUS_ERR_MSK)) {
2197 ts->stat = SAS_PROTO_RESPONSE;
2198 } else if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2199 ts->residual = trans_tx_fail_type;
2200 ts->stat = SAS_DATA_UNDERRUN;
2201 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2202 ts->stat = SAS_PHY_DOWN;
2205 ts->stat = SAS_OPEN_REJECT;
2206 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2208 hisi_sas_sata_done(task, slot);
2210 case SAS_PROTOCOL_SMP:
2211 ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2219 static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
2220 struct hisi_sas_slot *slot)
2222 struct sas_task *task = slot->task;
2223 struct hisi_sas_device *sas_dev;
2224 struct device *dev = hisi_hba->dev;
2225 struct task_status_struct *ts;
2226 struct domain_device *device;
2227 struct sas_ha_struct *ha;
2228 struct hisi_sas_complete_v3_hdr *complete_queue =
2229 hisi_hba->complete_hdr[slot->cmplt_queue];
2230 struct hisi_sas_complete_v3_hdr *complete_hdr =
2231 &complete_queue[slot->cmplt_queue_slot];
2232 unsigned long flags;
2233 bool is_internal = slot->is_internal;
2236 if (unlikely(!task || !task->lldd_task || !task->dev))
2239 ts = &task->task_status;
2241 ha = device->port->ha;
2242 sas_dev = device->lldd_dev;
2244 spin_lock_irqsave(&task->task_state_lock, flags);
2245 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2246 spin_unlock_irqrestore(&task->task_state_lock, flags);
2248 memset(ts, 0, sizeof(*ts));
2249 ts->resp = SAS_TASK_COMPLETE;
2251 if (unlikely(!sas_dev)) {
2252 dev_dbg(dev, "slot complete: port has not device\n");
2253 ts->stat = SAS_PHY_DOWN;
2257 dw0 = le32_to_cpu(complete_hdr->dw0);
2258 dw1 = le32_to_cpu(complete_hdr->dw1);
2259 dw3 = le32_to_cpu(complete_hdr->dw3);
2262 * Use SAS+TMF status codes
2264 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
2265 case STAT_IO_ABORTED:
2266 /* this IO has been aborted by abort command */
2267 ts->stat = SAS_ABORTED_TASK;
2269 case STAT_IO_COMPLETE:
2270 /* internal abort command complete */
2271 ts->stat = TMF_RESP_FUNC_SUCC;
2273 case STAT_IO_NO_DEVICE:
2274 ts->stat = TMF_RESP_FUNC_COMPLETE;
2276 case STAT_IO_NOT_VALID:
2278 * abort single IO, the controller can't find the IO
2280 ts->stat = TMF_RESP_FUNC_FAILED;
2286 /* check for erroneous completion */
2287 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
2288 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2290 if (slot_err_v3_hw(hisi_hba, task, slot)) {
2291 if (ts->stat != SAS_DATA_UNDERRUN)
2292 dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d addr=%016llx CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2293 slot->idx, task, sas_dev->device_id,
2294 SAS_ADDR(device->sas_addr),
2295 dw0, dw1, complete_hdr->act, dw3,
2296 error_info[0], error_info[1],
2297 error_info[2], error_info[3]);
2298 if (unlikely(slot->abort)) {
2299 sas_task_abort(task);
2306 switch (task->task_proto) {
2307 case SAS_PROTOCOL_SSP: {
2308 struct ssp_response_iu *iu =
2309 hisi_sas_status_buf_addr_mem(slot) +
2310 sizeof(struct hisi_sas_err_record);
2312 sas_ssp_task_response(dev, task, iu);
2315 case SAS_PROTOCOL_SMP: {
2316 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2317 void *to = page_address(sg_page(sg_resp));
2319 ts->stat = SAS_SAM_STAT_GOOD;
2321 memcpy(to + sg_resp->offset,
2322 hisi_sas_status_buf_addr_mem(slot) +
2323 sizeof(struct hisi_sas_err_record),
2327 case SAS_PROTOCOL_SATA:
2328 case SAS_PROTOCOL_STP:
2329 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2330 ts->stat = SAS_SAM_STAT_GOOD;
2331 hisi_sas_sata_done(task, slot);
2334 ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2338 if (!slot->port->port_attached) {
2339 dev_warn(dev, "slot complete: port %d has removed\n",
2340 slot->port->sas_port.id);
2341 ts->stat = SAS_PHY_DOWN;
2345 spin_lock_irqsave(&task->task_state_lock, flags);
2346 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2347 spin_unlock_irqrestore(&task->task_state_lock, flags);
2348 dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2351 task->task_state_flags |= SAS_TASK_STATE_DONE;
2352 spin_unlock_irqrestore(&task->task_state_lock, flags);
2353 hisi_sas_slot_task_free(hisi_hba, task, slot);
2355 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2356 spin_lock_irqsave(&device->done_lock, flags);
2357 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2358 spin_unlock_irqrestore(&device->done_lock, flags);
2359 dev_info(dev, "slot complete: task(%pK) ignored\n ",
2363 spin_unlock_irqrestore(&device->done_lock, flags);
2366 if (task->task_done)
2367 task->task_done(task);
2370 static irqreturn_t cq_thread_v3_hw(int irq_no, void *p)
2372 struct hisi_sas_cq *cq = p;
2373 struct hisi_hba *hisi_hba = cq->hisi_hba;
2374 struct hisi_sas_slot *slot;
2375 struct hisi_sas_complete_v3_hdr *complete_queue;
2376 u32 rd_point = cq->rd_point, wr_point;
2379 complete_queue = hisi_hba->complete_hdr[queue];
2381 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2384 while (rd_point != wr_point) {
2385 struct hisi_sas_complete_v3_hdr *complete_hdr;
2386 struct device *dev = hisi_hba->dev;
2390 complete_hdr = &complete_queue[rd_point];
2391 dw1 = le32_to_cpu(complete_hdr->dw1);
2393 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2394 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2395 slot = &hisi_hba->slot_info[iptt];
2396 slot->cmplt_queue_slot = rd_point;
2397 slot->cmplt_queue = queue;
2398 slot_complete_v3_hw(hisi_hba, slot);
2400 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2402 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2406 /* update rd_point */
2407 cq->rd_point = rd_point;
2408 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2413 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2415 struct hisi_sas_cq *cq = p;
2416 struct hisi_hba *hisi_hba = cq->hisi_hba;
2419 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2421 return IRQ_WAKE_THREAD;
2424 static void hisi_sas_v3_free_vectors(void *data)
2426 struct pci_dev *pdev = data;
2428 pci_free_irq_vectors(pdev);
2431 static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba)
2434 int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi;
2435 struct Scsi_Host *shost = hisi_hba->shost;
2436 struct pci_dev *pdev = hisi_hba->pci_dev;
2437 struct irq_affinity desc = {
2438 .pre_vectors = BASE_VECTORS_V3_HW,
2441 min_msi = MIN_AFFINE_VECTORS_V3_HW;
2442 vectors = pci_alloc_irq_vectors_affinity(pdev,
2451 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW;
2452 shost->nr_hw_queues = hisi_hba->cq_nvecs;
2454 devm_add_action(&pdev->dev, hisi_sas_v3_free_vectors, pdev);
2458 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2460 struct device *dev = hisi_hba->dev;
2461 struct pci_dev *pdev = hisi_hba->pci_dev;
2464 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
2465 int_phy_up_down_bcast_v3_hw, 0,
2466 DRV_NAME " phy", hisi_hba);
2468 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2472 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
2473 int_chnl_int_v3_hw, 0,
2474 DRV_NAME " channel", hisi_hba);
2476 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2480 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
2481 fatal_axi_int_v3_hw, 0,
2482 DRV_NAME " fatal", hisi_hba);
2484 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2488 if (hisi_sas_intr_conv)
2489 dev_info(dev, "Enable interrupt converge\n");
2491 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2492 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2493 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2494 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
2497 cq->irq_no = pci_irq_vector(pdev, nr);
2498 rc = devm_request_threaded_irq(dev, cq->irq_no,
2502 DRV_NAME " cq", cq);
2504 dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
2508 cq->irq_mask = pci_irq_get_affinity(pdev, i + BASE_VECTORS_V3_HW);
2509 if (!cq->irq_mask) {
2510 dev_err(dev, "could not get cq%d irq affinity!\n", i);
2518 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2522 rc = hw_init_v3_hw(hisi_hba);
2526 rc = interrupt_init_v3_hw(hisi_hba);
2533 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2534 struct sas_phy_linkrates *r)
2536 enum sas_linkrate max = r->maximum_linkrate;
2537 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
2538 PROG_PHY_LINK_RATE);
2540 prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
2541 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2542 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2543 prog_phy_link_rate);
2546 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2548 struct pci_dev *pdev = hisi_hba->pci_dev;
2551 synchronize_irq(pci_irq_vector(pdev, 1));
2552 synchronize_irq(pci_irq_vector(pdev, 2));
2553 synchronize_irq(pci_irq_vector(pdev, 11));
2554 for (i = 0; i < hisi_hba->queue_count; i++)
2555 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2557 for (i = 0; i < hisi_hba->cq_nvecs; i++)
2558 synchronize_irq(pci_irq_vector(pdev, i + 16));
2560 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2561 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2562 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2563 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2565 for (i = 0; i < hisi_hba->n_phy; i++) {
2566 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2567 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2568 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2569 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2570 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2574 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2576 return hisi_sas_read32(hisi_hba, PHY_STATE);
2579 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2581 struct device *dev = hisi_hba->dev;
2582 u32 status, reg_val;
2585 interrupt_disable_v3_hw(hisi_hba);
2586 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2588 hisi_sas_stop_phys(hisi_hba);
2592 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2594 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2595 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2596 AM_CTRL_GLOBAL, reg_val);
2598 /* wait until bus idle */
2599 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2600 AM_CURR_TRANS_RETURN, status,
2601 status == 0x3, 10, 100);
2603 dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2610 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2612 struct device *dev = hisi_hba->dev;
2615 rc = disable_host_v3_hw(hisi_hba);
2617 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2621 hisi_sas_init_mem(hisi_hba);
2623 return hw_init_v3_hw(hisi_hba);
2626 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2627 u8 reg_index, u8 reg_count, u8 *write_data)
2629 struct device *dev = hisi_hba->dev;
2630 u32 *data = (u32 *)write_data;
2634 case SAS_GPIO_REG_TX:
2635 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2636 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2637 reg_index, reg_index + reg_count - 1);
2641 for (i = 0; i < reg_count; i++)
2642 hisi_sas_write32(hisi_hba,
2643 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2647 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2655 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2656 int delay_ms, int timeout_ms)
2658 struct device *dev = hisi_hba->dev;
2659 int entries, entries_old = 0, time;
2661 for (time = 0; time < timeout_ms; time += delay_ms) {
2662 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2663 if (entries == entries_old)
2666 entries_old = entries;
2670 if (time >= timeout_ms) {
2671 dev_dbg(dev, "Wait commands complete timeout!\n");
2675 dev_dbg(dev, "wait commands complete %dms\n", time);
2678 static ssize_t intr_conv_v3_hw_show(struct device *dev,
2679 struct device_attribute *attr, char *buf)
2681 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2683 static DEVICE_ATTR_RO(intr_conv_v3_hw);
2685 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2687 /* config those registers between enable and disable PHYs */
2688 hisi_sas_stop_phys(hisi_hba);
2690 if (hisi_hba->intr_coal_ticks == 0 ||
2691 hisi_hba->intr_coal_count == 0) {
2692 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
2693 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
2694 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
2696 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2697 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2698 hisi_hba->intr_coal_ticks);
2699 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2700 hisi_hba->intr_coal_count);
2702 phys_init_v3_hw(hisi_hba);
2705 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2706 struct device_attribute *attr,
2709 struct Scsi_Host *shost = class_to_shost(dev);
2710 struct hisi_hba *hisi_hba = shost_priv(shost);
2712 return scnprintf(buf, PAGE_SIZE, "%u\n",
2713 hisi_hba->intr_coal_ticks);
2716 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2717 struct device_attribute *attr,
2718 const char *buf, size_t count)
2720 struct Scsi_Host *shost = class_to_shost(dev);
2721 struct hisi_hba *hisi_hba = shost_priv(shost);
2722 u32 intr_coal_ticks;
2725 ret = kstrtou32(buf, 10, &intr_coal_ticks);
2727 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2731 if (intr_coal_ticks >= BIT(24)) {
2732 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2736 hisi_hba->intr_coal_ticks = intr_coal_ticks;
2738 config_intr_coal_v3_hw(hisi_hba);
2742 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2744 static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2745 struct device_attribute
2748 struct Scsi_Host *shost = class_to_shost(dev);
2749 struct hisi_hba *hisi_hba = shost_priv(shost);
2751 return scnprintf(buf, PAGE_SIZE, "%u\n",
2752 hisi_hba->intr_coal_count);
2755 static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2756 struct device_attribute
2757 *attr, const char *buf, size_t count)
2759 struct Scsi_Host *shost = class_to_shost(dev);
2760 struct hisi_hba *hisi_hba = shost_priv(shost);
2761 u32 intr_coal_count;
2764 ret = kstrtou32(buf, 10, &intr_coal_count);
2766 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2770 if (intr_coal_count >= BIT(8)) {
2771 dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2775 hisi_hba->intr_coal_count = intr_coal_count;
2777 config_intr_coal_v3_hw(hisi_hba);
2781 static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2783 static int slave_configure_v3_hw(struct scsi_device *sdev)
2785 struct Scsi_Host *shost = dev_to_shost(&sdev->sdev_gendev);
2786 struct hisi_hba *hisi_hba = shost_priv(shost);
2787 int ret = hisi_sas_slave_configure(sdev);
2788 struct device *dev = hisi_hba->dev;
2789 unsigned int max_sectors;
2794 if (sdev->type == TYPE_ENCLOSURE)
2797 if (!device_link_add(&sdev->sdev_gendev, dev,
2798 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)) {
2799 if (pm_runtime_enabled(dev)) {
2800 dev_info(dev, "add device link failed, disable runtime PM for the host\n");
2801 pm_runtime_disable(dev);
2805 /* Set according to IOMMU IOVA caching limit */
2806 max_sectors = min_t(size_t, queue_max_hw_sectors(sdev->request_queue),
2807 (PAGE_SIZE * 32) >> SECTOR_SHIFT);
2809 blk_queue_max_hw_sectors(sdev->request_queue, max_sectors);
2814 static struct attribute *host_v3_hw_attrs[] = {
2815 &dev_attr_phy_event_threshold.attr,
2816 &dev_attr_intr_conv_v3_hw.attr,
2817 &dev_attr_intr_coal_ticks_v3_hw.attr,
2818 &dev_attr_intr_coal_count_v3_hw.attr,
2822 ATTRIBUTE_GROUPS(host_v3_hw);
2824 #define HISI_SAS_DEBUGFS_REG(x) {#x, x}
2826 struct hisi_sas_debugfs_reg_lu {
2831 struct hisi_sas_debugfs_reg {
2832 const struct hisi_sas_debugfs_reg_lu *lu;
2837 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
2838 HISI_SAS_DEBUGFS_REG(PHY_CFG),
2839 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
2840 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
2841 HISI_SAS_DEBUGFS_REG(PHY_CTRL),
2842 HISI_SAS_DEBUGFS_REG(SL_CFG),
2843 HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
2844 HISI_SAS_DEBUGFS_REG(SL_CONTROL),
2845 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
2846 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
2847 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
2848 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
2849 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
2850 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
2851 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
2852 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
2853 HISI_SAS_DEBUGFS_REG(TXID_AUTO),
2854 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
2855 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
2856 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
2857 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
2858 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
2859 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
2860 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
2861 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
2862 HISI_SAS_DEBUGFS_REG(CHL_INT0),
2863 HISI_SAS_DEBUGFS_REG(CHL_INT1),
2864 HISI_SAS_DEBUGFS_REG(CHL_INT2),
2865 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
2866 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
2867 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
2868 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
2869 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
2870 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
2871 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
2872 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
2873 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
2874 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
2875 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
2876 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
2877 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
2878 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
2879 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
2880 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
2881 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
2882 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
2883 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
2884 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
2888 static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
2889 .lu = debugfs_port_reg_lu,
2891 .base_off = PORT_BASE,
2894 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
2895 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
2896 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
2897 HISI_SAS_DEBUGFS_REG(PHY_STATE),
2898 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
2899 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
2900 HISI_SAS_DEBUGFS_REG(ITCT_CLR),
2901 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
2902 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
2903 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
2904 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
2905 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
2906 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
2907 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
2908 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
2909 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
2910 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
2911 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
2912 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
2913 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
2914 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
2915 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
2916 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
2917 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
2918 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
2919 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
2920 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
2921 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
2922 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
2923 HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
2924 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
2925 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
2926 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
2927 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
2928 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
2929 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
2930 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
2931 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
2932 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
2933 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
2934 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
2935 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
2936 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
2937 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
2938 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
2939 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
2940 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
2941 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
2942 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
2943 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
2944 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
2945 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
2946 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
2947 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
2948 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
2949 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
2950 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
2951 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
2952 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
2953 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
2954 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
2955 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
2956 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
2957 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
2961 static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
2962 .lu = debugfs_global_reg_lu,
2966 static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
2967 HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
2968 HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
2969 HISI_SAS_DEBUGFS_REG(AXI_CFG),
2970 HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
2974 static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
2975 .lu = debugfs_axi_reg_lu,
2977 .base_off = AXI_MASTER_CFG_BASE,
2980 static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
2981 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
2982 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
2983 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
2984 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
2985 HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
2986 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
2987 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
2991 static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
2992 .lu = debugfs_ras_reg_lu,
2994 .base_off = RAS_BASE,
2997 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
2999 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3001 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
3003 wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000);
3005 hisi_sas_sync_irqs(hisi_hba);
3008 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
3010 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
3011 (u32)((1ULL << hisi_hba->queue_count) - 1));
3013 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3016 static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
3017 enum hisi_sas_debugfs_cache_type type,
3020 u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
3021 HISI_SAS_IOST_ITCT_CACHE_NUM;
3022 struct device *dev = hisi_hba->dev;
3026 hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);
3028 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
3029 val = hisi_sas_read32(hisi_hba, TAB_DFX);
3030 if (val == 0xffffffff)
3034 if (val != 0xffffffff) {
3035 dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
3039 memset(buf, 0, cache_dw_size * 4);
3042 for (i = 1; i < cache_dw_size; i++)
3043 buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
3046 static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
3049 int phy_no = hisi_hba->debugfs_bist_phy_no;
3053 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
3056 for (i = 0; i < FFE_CFG_MAX; i++)
3057 hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
3058 hisi_hba->debugfs_bist_ffe[phy_no][i]);
3061 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3062 reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
3063 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3066 static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
3069 int phy_no = hisi_hba->debugfs_bist_phy_no;
3071 /* disable loopback */
3072 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
3073 reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3075 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);
3078 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3079 reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
3080 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3082 /* restore the linkrate */
3083 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
3084 /* init OOB link rate as 1.5 Gbits */
3085 reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3086 reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3087 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
3090 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
3093 #define SAS_PHY_BIST_CODE_INIT 0x1
3094 #define SAS_PHY_BIST_CODE1_INIT 0X80
3095 static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
3097 u32 reg_val, mode_tmp;
3098 u32 linkrate = hisi_hba->debugfs_bist_linkrate;
3099 u32 phy_no = hisi_hba->debugfs_bist_phy_no;
3100 u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
3101 u32 code_mode = hisi_hba->debugfs_bist_code_mode;
3102 u32 path_mode = hisi_hba->debugfs_bist_mode;
3103 u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
3104 struct device *dev = hisi_hba->dev;
3106 dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
3107 phy_no, linkrate, code_mode, path_mode,
3108 ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
3109 ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
3110 ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
3111 ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
3112 fix_code[FIXED_CODE_1]);
3113 mode_tmp = path_mode ? 2 : 1;
3115 /* some preparations before bist test */
3116 hisi_sas_bist_test_prep_v3_hw(hisi_hba);
3118 /* set linkrate of bit test*/
3119 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3120 PROG_PHY_LINK_RATE);
3121 reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3122 reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3123 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
3126 /* set code mode of bit test */
3127 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3129 reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
3130 CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3132 reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
3133 (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
3135 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3138 /* set the bist init value */
3139 if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
3140 reg_val = hisi_hba->debugfs_bist_fixed_code[0];
3141 hisi_sas_phy_write32(hisi_hba, phy_no,
3142 SAS_PHY_BIST_CODE, reg_val);
3144 reg_val = hisi_hba->debugfs_bist_fixed_code[1];
3145 hisi_sas_phy_write32(hisi_hba, phy_no,
3146 SAS_PHY_BIST_CODE1, reg_val);
3148 hisi_sas_phy_write32(hisi_hba, phy_no,
3150 SAS_PHY_BIST_CODE_INIT);
3151 hisi_sas_phy_write32(hisi_hba, phy_no,
3153 SAS_PHY_BIST_CODE1_INIT);
3157 reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
3158 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3161 /* clear error bit */
3163 hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
3165 /* disable bist test and recover it */
3166 hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
3167 phy_no, SAS_BIST_ERR_CNT);
3168 hisi_sas_bist_test_restore_v3_hw(hisi_hba);
3174 static int hisi_sas_map_queues(struct Scsi_Host *shost)
3176 struct hisi_hba *hisi_hba = shost_priv(shost);
3177 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
3179 return blk_mq_pci_map_queues(qmap, hisi_hba->pci_dev,
3180 BASE_VECTORS_V3_HW);
3183 static struct scsi_host_template sht_v3_hw = {
3185 .proc_name = DRV_NAME,
3186 .module = THIS_MODULE,
3187 .queuecommand = sas_queuecommand,
3188 .dma_need_drain = ata_scsi_dma_need_drain,
3189 .target_alloc = sas_target_alloc,
3190 .slave_configure = slave_configure_v3_hw,
3191 .scan_finished = hisi_sas_scan_finished,
3192 .scan_start = hisi_sas_scan_start,
3193 .map_queues = hisi_sas_map_queues,
3194 .change_queue_depth = sas_change_queue_depth,
3195 .bios_param = sas_bios_param,
3197 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
3198 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT,
3199 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3200 .eh_device_reset_handler = sas_eh_device_reset_handler,
3201 .eh_target_reset_handler = sas_eh_target_reset_handler,
3202 .slave_alloc = hisi_sas_slave_alloc,
3203 .target_destroy = sas_target_destroy,
3205 #ifdef CONFIG_COMPAT
3206 .compat_ioctl = sas_ioctl,
3208 .shost_groups = host_v3_hw_groups,
3209 .tag_alloc_policy = BLK_TAG_ALLOC_RR,
3210 .host_reset = hisi_sas_host_reset,
3214 static const struct hisi_sas_hw hisi_sas_v3_hw = {
3215 .setup_itct = setup_itct_v3_hw,
3216 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
3217 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
3218 .clear_itct = clear_itct_v3_hw,
3219 .sl_notify_ssp = sl_notify_ssp_v3_hw,
3220 .prep_ssp = prep_ssp_v3_hw,
3221 .prep_smp = prep_smp_v3_hw,
3222 .prep_stp = prep_ata_v3_hw,
3223 .prep_abort = prep_abort_v3_hw,
3224 .start_delivery = start_delivery_v3_hw,
3225 .phys_init = phys_init_v3_hw,
3226 .phy_start = start_phy_v3_hw,
3227 .phy_disable = disable_phy_v3_hw,
3228 .phy_hard_reset = phy_hard_reset_v3_hw,
3229 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
3230 .phy_set_linkrate = phy_set_linkrate_v3_hw,
3231 .dereg_device = dereg_device_v3_hw,
3232 .soft_reset = soft_reset_v3_hw,
3233 .get_phys_state = get_phys_state_v3_hw,
3234 .get_events = phy_get_events_v3_hw,
3235 .write_gpio = write_gpio_v3_hw,
3236 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
3237 .debugfs_snapshot_regs = debugfs_snapshot_regs_v3_hw,
3240 static struct Scsi_Host *
3241 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
3243 struct Scsi_Host *shost;
3244 struct hisi_hba *hisi_hba;
3245 struct device *dev = &pdev->dev;
3247 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
3249 dev_err(dev, "shost alloc failed\n");
3252 hisi_hba = shost_priv(shost);
3254 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
3255 INIT_WORK(&hisi_hba->debugfs_work, debugfs_work_handler_v3_hw);
3256 hisi_hba->hw = &hisi_sas_v3_hw;
3257 hisi_hba->pci_dev = pdev;
3258 hisi_hba->dev = dev;
3259 hisi_hba->shost = shost;
3260 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
3262 if (prot_mask & ~HISI_SAS_PROT_MASK)
3263 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
3266 hisi_hba->prot_mask = prot_mask;
3268 if (hisi_sas_get_fw_info(hisi_hba) < 0)
3271 if (hisi_sas_alloc(hisi_hba)) {
3272 hisi_sas_free(hisi_hba);
3278 scsi_host_put(shost);
3279 dev_err(dev, "shost alloc failed\n");
3283 static void debugfs_snapshot_cq_reg_v3_hw(struct hisi_hba *hisi_hba)
3285 int queue_entry_size = hisi_hba->hw->complete_hdr_size;
3286 int dump_index = hisi_hba->debugfs_dump_index;
3289 for (i = 0; i < hisi_hba->queue_count; i++)
3290 memcpy(hisi_hba->debugfs_cq[dump_index][i].complete_hdr,
3291 hisi_hba->complete_hdr[i],
3292 HISI_SAS_QUEUE_SLOTS * queue_entry_size);
3295 static void debugfs_snapshot_dq_reg_v3_hw(struct hisi_hba *hisi_hba)
3297 int queue_entry_size = sizeof(struct hisi_sas_cmd_hdr);
3298 int dump_index = hisi_hba->debugfs_dump_index;
3301 for (i = 0; i < hisi_hba->queue_count; i++) {
3302 struct hisi_sas_cmd_hdr *debugfs_cmd_hdr, *cmd_hdr;
3305 debugfs_cmd_hdr = hisi_hba->debugfs_dq[dump_index][i].hdr;
3306 cmd_hdr = hisi_hba->cmd_hdr[i];
3308 for (j = 0; j < HISI_SAS_QUEUE_SLOTS; j++)
3309 memcpy(&debugfs_cmd_hdr[j], &cmd_hdr[j],
3314 static void debugfs_snapshot_port_reg_v3_hw(struct hisi_hba *hisi_hba)
3316 int dump_index = hisi_hba->debugfs_dump_index;
3317 const struct hisi_sas_debugfs_reg *port = &debugfs_port_reg;
3322 for (phy_cnt = 0; phy_cnt < hisi_hba->n_phy; phy_cnt++) {
3323 databuf = hisi_hba->debugfs_port_reg[dump_index][phy_cnt].data;
3324 for (i = 0; i < port->count; i++, databuf++) {
3325 offset = port->base_off + 4 * i;
3326 *databuf = hisi_sas_phy_read32(hisi_hba, phy_cnt,
3332 static void debugfs_snapshot_global_reg_v3_hw(struct hisi_hba *hisi_hba)
3334 int dump_index = hisi_hba->debugfs_dump_index;
3335 u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL].data;
3338 for (i = 0; i < debugfs_axi_reg.count; i++, databuf++)
3339 *databuf = hisi_sas_read32(hisi_hba, 4 * i);
3342 static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba)
3344 int dump_index = hisi_hba->debugfs_dump_index;
3345 u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI].data;
3346 const struct hisi_sas_debugfs_reg *axi = &debugfs_axi_reg;
3349 for (i = 0; i < axi->count; i++, databuf++)
3350 *databuf = hisi_sas_read32(hisi_hba, 4 * i + axi->base_off);
3353 static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba)
3355 int dump_index = hisi_hba->debugfs_dump_index;
3356 u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS].data;
3357 const struct hisi_sas_debugfs_reg *ras = &debugfs_ras_reg;
3360 for (i = 0; i < ras->count; i++, databuf++)
3361 *databuf = hisi_sas_read32(hisi_hba, 4 * i + ras->base_off);
3364 static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba)
3366 int dump_index = hisi_hba->debugfs_dump_index;
3367 void *cachebuf = hisi_hba->debugfs_itct_cache[dump_index].cache;
3368 void *databuf = hisi_hba->debugfs_itct[dump_index].itct;
3369 struct hisi_sas_itct *itct;
3372 read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_ITCT_CACHE, cachebuf);
3374 itct = hisi_hba->itct;
3376 for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3377 memcpy(databuf, itct, sizeof(struct hisi_sas_itct));
3378 databuf += sizeof(struct hisi_sas_itct);
3382 static void debugfs_snapshot_iost_reg_v3_hw(struct hisi_hba *hisi_hba)
3384 int dump_index = hisi_hba->debugfs_dump_index;
3385 int max_command_entries = HISI_SAS_MAX_COMMANDS;
3386 void *cachebuf = hisi_hba->debugfs_iost_cache[dump_index].cache;
3387 void *databuf = hisi_hba->debugfs_iost[dump_index].iost;
3388 struct hisi_sas_iost *iost;
3391 read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_IOST_CACHE, cachebuf);
3393 iost = hisi_hba->iost;
3395 for (i = 0; i < max_command_entries; i++, iost++) {
3396 memcpy(databuf, iost, sizeof(struct hisi_sas_iost));
3397 databuf += sizeof(struct hisi_sas_iost);
3402 debugfs_to_reg_name_v3_hw(int off, int base_off,
3403 const struct hisi_sas_debugfs_reg_lu *lu)
3405 for (; lu->name; lu++) {
3406 if (off == lu->off - base_off)
3413 static void debugfs_print_reg_v3_hw(u32 *regs_val, struct seq_file *s,
3414 const struct hisi_sas_debugfs_reg *reg)
3418 for (i = 0; i < reg->count; i++) {
3422 name = debugfs_to_reg_name_v3_hw(off, reg->base_off,
3426 seq_printf(s, "0x%08x 0x%08x %s\n", off,
3429 seq_printf(s, "0x%08x 0x%08x\n", off,
3434 static int debugfs_global_v3_hw_show(struct seq_file *s, void *p)
3436 struct hisi_sas_debugfs_regs *global = s->private;
3438 debugfs_print_reg_v3_hw(global->data, s,
3439 &debugfs_global_reg);
3443 DEFINE_SHOW_ATTRIBUTE(debugfs_global_v3_hw);
3445 static int debugfs_axi_v3_hw_show(struct seq_file *s, void *p)
3447 struct hisi_sas_debugfs_regs *axi = s->private;
3449 debugfs_print_reg_v3_hw(axi->data, s,
3454 DEFINE_SHOW_ATTRIBUTE(debugfs_axi_v3_hw);
3456 static int debugfs_ras_v3_hw_show(struct seq_file *s, void *p)
3458 struct hisi_sas_debugfs_regs *ras = s->private;
3460 debugfs_print_reg_v3_hw(ras->data, s,
3465 DEFINE_SHOW_ATTRIBUTE(debugfs_ras_v3_hw);
3467 static int debugfs_port_v3_hw_show(struct seq_file *s, void *p)
3469 struct hisi_sas_debugfs_port *port = s->private;
3470 const struct hisi_sas_debugfs_reg *reg_port = &debugfs_port_reg;
3472 debugfs_print_reg_v3_hw(port->data, s, reg_port);
3476 DEFINE_SHOW_ATTRIBUTE(debugfs_port_v3_hw);
3478 static void debugfs_show_row_64_v3_hw(struct seq_file *s, int index,
3479 int sz, __le64 *ptr)
3483 /* completion header size not fixed per HW version */
3484 seq_printf(s, "index %04d:\n\t", index);
3485 for (i = 1; i <= sz / 8; i++, ptr++) {
3486 seq_printf(s, " 0x%016llx", le64_to_cpu(*ptr));
3488 seq_puts(s, "\n\t");
3494 static void debugfs_show_row_32_v3_hw(struct seq_file *s, int index,
3495 int sz, __le32 *ptr)
3499 /* completion header size not fixed per HW version */
3500 seq_printf(s, "index %04d:\n\t", index);
3501 for (i = 1; i <= sz / 4; i++, ptr++) {
3502 seq_printf(s, " 0x%08x", le32_to_cpu(*ptr));
3504 seq_puts(s, "\n\t");
3509 static void debugfs_cq_show_slot_v3_hw(struct seq_file *s, int slot,
3510 struct hisi_sas_debugfs_cq *debugfs_cq)
3512 struct hisi_sas_cq *cq = debugfs_cq->cq;
3513 struct hisi_hba *hisi_hba = cq->hisi_hba;
3514 __le32 *complete_hdr = debugfs_cq->complete_hdr +
3515 (hisi_hba->hw->complete_hdr_size * slot);
3517 debugfs_show_row_32_v3_hw(s, slot,
3518 hisi_hba->hw->complete_hdr_size,
3522 static int debugfs_cq_v3_hw_show(struct seq_file *s, void *p)
3524 struct hisi_sas_debugfs_cq *debugfs_cq = s->private;
3527 for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3528 debugfs_cq_show_slot_v3_hw(s, slot, debugfs_cq);
3532 DEFINE_SHOW_ATTRIBUTE(debugfs_cq_v3_hw);
3534 static void debugfs_dq_show_slot_v3_hw(struct seq_file *s, int slot,
3537 struct hisi_sas_debugfs_dq *debugfs_dq = dq_ptr;
3538 void *cmd_queue = debugfs_dq->hdr;
3539 __le32 *cmd_hdr = cmd_queue +
3540 sizeof(struct hisi_sas_cmd_hdr) * slot;
3542 debugfs_show_row_32_v3_hw(s, slot, sizeof(struct hisi_sas_cmd_hdr),
3546 static int debugfs_dq_v3_hw_show(struct seq_file *s, void *p)
3550 for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3551 debugfs_dq_show_slot_v3_hw(s, slot, s->private);
3555 DEFINE_SHOW_ATTRIBUTE(debugfs_dq_v3_hw);
3557 static int debugfs_iost_v3_hw_show(struct seq_file *s, void *p)
3559 struct hisi_sas_debugfs_iost *debugfs_iost = s->private;
3560 struct hisi_sas_iost *iost = debugfs_iost->iost;
3561 int i, max_command_entries = HISI_SAS_MAX_COMMANDS;
3563 for (i = 0; i < max_command_entries; i++, iost++) {
3564 __le64 *data = &iost->qw0;
3566 debugfs_show_row_64_v3_hw(s, i, sizeof(*iost), data);
3571 DEFINE_SHOW_ATTRIBUTE(debugfs_iost_v3_hw);
3573 static int debugfs_iost_cache_v3_hw_show(struct seq_file *s, void *p)
3575 struct hisi_sas_debugfs_iost_cache *debugfs_iost_cache = s->private;
3576 struct hisi_sas_iost_itct_cache *iost_cache =
3577 debugfs_iost_cache->cache;
3578 u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3582 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, iost_cache++) {
3584 * Data struct of IOST cache:
3585 * Data[1]: BIT0~15: Table index
3587 * Data[2]~[9]: IOST table
3589 tab_idx = (iost_cache->data[1] & 0xffff);
3590 iost = (__le64 *)iost_cache;
3592 debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, iost);
3597 DEFINE_SHOW_ATTRIBUTE(debugfs_iost_cache_v3_hw);
3599 static int debugfs_itct_v3_hw_show(struct seq_file *s, void *p)
3602 struct hisi_sas_debugfs_itct *debugfs_itct = s->private;
3603 struct hisi_sas_itct *itct = debugfs_itct->itct;
3605 for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3606 __le64 *data = &itct->qw0;
3608 debugfs_show_row_64_v3_hw(s, i, sizeof(*itct), data);
3613 DEFINE_SHOW_ATTRIBUTE(debugfs_itct_v3_hw);
3615 static int debugfs_itct_cache_v3_hw_show(struct seq_file *s, void *p)
3617 struct hisi_sas_debugfs_itct_cache *debugfs_itct_cache = s->private;
3618 struct hisi_sas_iost_itct_cache *itct_cache =
3619 debugfs_itct_cache->cache;
3620 u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3624 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, itct_cache++) {
3626 * Data struct of ITCT cache:
3627 * Data[1]: BIT0~15: Table index
3629 * Data[2]~[9]: ITCT table
3631 tab_idx = itct_cache->data[1] & 0xffff;
3632 itct = (__le64 *)itct_cache;
3634 debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, itct);
3639 DEFINE_SHOW_ATTRIBUTE(debugfs_itct_cache_v3_hw);
3641 static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba)
3643 u64 *debugfs_timestamp;
3644 int dump_index = hisi_hba->debugfs_dump_index;
3645 struct dentry *dump_dentry;
3646 struct dentry *dentry;
3652 snprintf(name, 256, "%d", dump_index);
3654 dump_dentry = debugfs_create_dir(name, hisi_hba->debugfs_dump_dentry);
3656 debugfs_timestamp = &hisi_hba->debugfs_timestamp[dump_index];
3658 debugfs_create_u64("timestamp", 0400, dump_dentry,
3661 debugfs_create_file("global", 0400, dump_dentry,
3662 &hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL],
3663 &debugfs_global_v3_hw_fops);
3665 /* Create port dir and files */
3666 dentry = debugfs_create_dir("port", dump_dentry);
3667 for (p = 0; p < hisi_hba->n_phy; p++) {
3668 snprintf(name, 256, "%d", p);
3670 debugfs_create_file(name, 0400, dentry,
3671 &hisi_hba->debugfs_port_reg[dump_index][p],
3672 &debugfs_port_v3_hw_fops);
3675 /* Create CQ dir and files */
3676 dentry = debugfs_create_dir("cq", dump_dentry);
3677 for (c = 0; c < hisi_hba->queue_count; c++) {
3678 snprintf(name, 256, "%d", c);
3680 debugfs_create_file(name, 0400, dentry,
3681 &hisi_hba->debugfs_cq[dump_index][c],
3682 &debugfs_cq_v3_hw_fops);
3685 /* Create DQ dir and files */
3686 dentry = debugfs_create_dir("dq", dump_dentry);
3687 for (d = 0; d < hisi_hba->queue_count; d++) {
3688 snprintf(name, 256, "%d", d);
3690 debugfs_create_file(name, 0400, dentry,
3691 &hisi_hba->debugfs_dq[dump_index][d],
3692 &debugfs_dq_v3_hw_fops);
3695 debugfs_create_file("iost", 0400, dump_dentry,
3696 &hisi_hba->debugfs_iost[dump_index],
3697 &debugfs_iost_v3_hw_fops);
3699 debugfs_create_file("iost_cache", 0400, dump_dentry,
3700 &hisi_hba->debugfs_iost_cache[dump_index],
3701 &debugfs_iost_cache_v3_hw_fops);
3703 debugfs_create_file("itct", 0400, dump_dentry,
3704 &hisi_hba->debugfs_itct[dump_index],
3705 &debugfs_itct_v3_hw_fops);
3707 debugfs_create_file("itct_cache", 0400, dump_dentry,
3708 &hisi_hba->debugfs_itct_cache[dump_index],
3709 &debugfs_itct_cache_v3_hw_fops);
3711 debugfs_create_file("axi", 0400, dump_dentry,
3712 &hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI],
3713 &debugfs_axi_v3_hw_fops);
3715 debugfs_create_file("ras", 0400, dump_dentry,
3716 &hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS],
3717 &debugfs_ras_v3_hw_fops);
3720 static void debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba)
3722 int debugfs_dump_index = hisi_hba->debugfs_dump_index;
3723 struct device *dev = hisi_hba->dev;
3724 u64 timestamp = local_clock();
3726 if (debugfs_dump_index >= hisi_sas_debugfs_dump_count) {
3727 dev_warn(dev, "dump count exceeded!\n");
3731 do_div(timestamp, NSEC_PER_MSEC);
3732 hisi_hba->debugfs_timestamp[debugfs_dump_index] = timestamp;
3734 debugfs_snapshot_prepare_v3_hw(hisi_hba);
3736 debugfs_snapshot_global_reg_v3_hw(hisi_hba);
3737 debugfs_snapshot_port_reg_v3_hw(hisi_hba);
3738 debugfs_snapshot_axi_reg_v3_hw(hisi_hba);
3739 debugfs_snapshot_ras_reg_v3_hw(hisi_hba);
3740 debugfs_snapshot_cq_reg_v3_hw(hisi_hba);
3741 debugfs_snapshot_dq_reg_v3_hw(hisi_hba);
3742 debugfs_snapshot_itct_reg_v3_hw(hisi_hba);
3743 debugfs_snapshot_iost_reg_v3_hw(hisi_hba);
3745 debugfs_create_files_v3_hw(hisi_hba);
3747 debugfs_snapshot_restore_v3_hw(hisi_hba);
3748 hisi_hba->debugfs_dump_index++;
3751 static ssize_t debugfs_trigger_dump_v3_hw_write(struct file *file,
3752 const char __user *user_buf,
3753 size_t count, loff_t *ppos)
3755 struct hisi_hba *hisi_hba = file->f_inode->i_private;
3758 if (hisi_hba->debugfs_dump_index >= hisi_sas_debugfs_dump_count)
3764 if (copy_from_user(buf, user_buf, count))
3770 queue_work(hisi_hba->wq, &hisi_hba->debugfs_work);
3775 static const struct file_operations debugfs_trigger_dump_v3_hw_fops = {
3776 .write = &debugfs_trigger_dump_v3_hw_write,
3777 .owner = THIS_MODULE,
3781 HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL = 0,
3782 HISI_SAS_BIST_LOOPBACK_MODE_SERDES,
3783 HISI_SAS_BIST_LOOPBACK_MODE_REMOTE,
3786 static const struct {
3789 } debugfs_loop_linkrate_v3_hw[] = {
3790 { SAS_LINK_RATE_1_5_GBPS, "1.5 Gbit" },
3791 { SAS_LINK_RATE_3_0_GBPS, "3.0 Gbit" },
3792 { SAS_LINK_RATE_6_0_GBPS, "6.0 Gbit" },
3793 { SAS_LINK_RATE_12_0_GBPS, "12.0 Gbit" },
3796 static int debugfs_bist_linkrate_v3_hw_show(struct seq_file *s, void *p)
3798 struct hisi_hba *hisi_hba = s->private;
3801 for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3802 int match = (hisi_hba->debugfs_bist_linkrate ==
3803 debugfs_loop_linkrate_v3_hw[i].value);
3805 seq_printf(s, "%s%s%s ", match ? "[" : "",
3806 debugfs_loop_linkrate_v3_hw[i].name,
3814 static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp,
3815 const char __user *buf,
3816 size_t count, loff_t *ppos)
3818 struct seq_file *m = filp->private_data;
3819 struct hisi_hba *hisi_hba = m->private;
3820 char kbuf[16] = {}, *pkbuf;
3824 if (hisi_hba->debugfs_bist_enable)
3827 if (count >= sizeof(kbuf))
3830 if (copy_from_user(kbuf, buf, count))
3833 pkbuf = strstrip(kbuf);
3835 for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3836 if (!strncmp(debugfs_loop_linkrate_v3_hw[i].name,
3838 hisi_hba->debugfs_bist_linkrate =
3839 debugfs_loop_linkrate_v3_hw[i].value;
3851 static int debugfs_bist_linkrate_v3_hw_open(struct inode *inode,
3854 return single_open(filp, debugfs_bist_linkrate_v3_hw_show,
3858 static const struct file_operations debugfs_bist_linkrate_v3_hw_fops = {
3859 .open = debugfs_bist_linkrate_v3_hw_open,
3861 .write = debugfs_bist_linkrate_v3_hw_write,
3862 .llseek = seq_lseek,
3863 .release = single_release,
3864 .owner = THIS_MODULE,
3867 static const struct {
3870 } debugfs_loop_code_mode_v3_hw[] = {
3871 { HISI_SAS_BIST_CODE_MODE_PRBS7, "PRBS7" },
3872 { HISI_SAS_BIST_CODE_MODE_PRBS23, "PRBS23" },
3873 { HISI_SAS_BIST_CODE_MODE_PRBS31, "PRBS31" },
3874 { HISI_SAS_BIST_CODE_MODE_JTPAT, "JTPAT" },
3875 { HISI_SAS_BIST_CODE_MODE_CJTPAT, "CJTPAT" },
3876 { HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, "SCRAMBED_0" },
3877 { HISI_SAS_BIST_CODE_MODE_TRAIN, "TRAIN" },
3878 { HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, "TRAIN_DONE" },
3879 { HISI_SAS_BIST_CODE_MODE_HFTP, "HFTP" },
3880 { HISI_SAS_BIST_CODE_MODE_MFTP, "MFTP" },
3881 { HISI_SAS_BIST_CODE_MODE_LFTP, "LFTP" },
3882 { HISI_SAS_BIST_CODE_MODE_FIXED_DATA, "FIXED_DATA" },
3885 static int debugfs_bist_code_mode_v3_hw_show(struct seq_file *s, void *p)
3887 struct hisi_hba *hisi_hba = s->private;
3890 for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
3891 int match = (hisi_hba->debugfs_bist_code_mode ==
3892 debugfs_loop_code_mode_v3_hw[i].value);
3894 seq_printf(s, "%s%s%s ", match ? "[" : "",
3895 debugfs_loop_code_mode_v3_hw[i].name,
3903 static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp,
3904 const char __user *buf,
3908 struct seq_file *m = filp->private_data;
3909 struct hisi_hba *hisi_hba = m->private;
3910 char kbuf[16] = {}, *pkbuf;
3914 if (hisi_hba->debugfs_bist_enable)
3917 if (count >= sizeof(kbuf))
3920 if (copy_from_user(kbuf, buf, count))
3923 pkbuf = strstrip(kbuf);
3925 for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
3926 if (!strncmp(debugfs_loop_code_mode_v3_hw[i].name,
3928 hisi_hba->debugfs_bist_code_mode =
3929 debugfs_loop_code_mode_v3_hw[i].value;
3941 static int debugfs_bist_code_mode_v3_hw_open(struct inode *inode,
3944 return single_open(filp, debugfs_bist_code_mode_v3_hw_show,
3948 static const struct file_operations debugfs_bist_code_mode_v3_hw_fops = {
3949 .open = debugfs_bist_code_mode_v3_hw_open,
3951 .write = debugfs_bist_code_mode_v3_hw_write,
3952 .llseek = seq_lseek,
3953 .release = single_release,
3954 .owner = THIS_MODULE,
3957 static ssize_t debugfs_bist_phy_v3_hw_write(struct file *filp,
3958 const char __user *buf,
3959 size_t count, loff_t *ppos)
3961 struct seq_file *m = filp->private_data;
3962 struct hisi_hba *hisi_hba = m->private;
3963 unsigned int phy_no;
3966 if (hisi_hba->debugfs_bist_enable)
3969 val = kstrtouint_from_user(buf, count, 0, &phy_no);
3973 if (phy_no >= hisi_hba->n_phy)
3976 hisi_hba->debugfs_bist_phy_no = phy_no;
3981 static int debugfs_bist_phy_v3_hw_show(struct seq_file *s, void *p)
3983 struct hisi_hba *hisi_hba = s->private;
3985 seq_printf(s, "%d\n", hisi_hba->debugfs_bist_phy_no);
3990 static int debugfs_bist_phy_v3_hw_open(struct inode *inode,
3993 return single_open(filp, debugfs_bist_phy_v3_hw_show,
3997 static const struct file_operations debugfs_bist_phy_v3_hw_fops = {
3998 .open = debugfs_bist_phy_v3_hw_open,
4000 .write = debugfs_bist_phy_v3_hw_write,
4001 .llseek = seq_lseek,
4002 .release = single_release,
4003 .owner = THIS_MODULE,
4006 static ssize_t debugfs_bist_cnt_v3_hw_write(struct file *filp,
4007 const char __user *buf,
4008 size_t count, loff_t *ppos)
4010 struct seq_file *m = filp->private_data;
4011 struct hisi_hba *hisi_hba = m->private;
4015 if (hisi_hba->debugfs_bist_enable)
4018 val = kstrtouint_from_user(buf, count, 0, &cnt);
4025 hisi_hba->debugfs_bist_cnt = 0;
4029 static int debugfs_bist_cnt_v3_hw_show(struct seq_file *s, void *p)
4031 struct hisi_hba *hisi_hba = s->private;
4033 seq_printf(s, "%u\n", hisi_hba->debugfs_bist_cnt);
4038 static int debugfs_bist_cnt_v3_hw_open(struct inode *inode,
4041 return single_open(filp, debugfs_bist_cnt_v3_hw_show,
4045 static const struct file_operations debugfs_bist_cnt_v3_hw_ops = {
4046 .open = debugfs_bist_cnt_v3_hw_open,
4048 .write = debugfs_bist_cnt_v3_hw_write,
4049 .llseek = seq_lseek,
4050 .release = single_release,
4051 .owner = THIS_MODULE,
4054 static const struct {
4057 } debugfs_loop_modes_v3_hw[] = {
4058 { HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL, "digital" },
4059 { HISI_SAS_BIST_LOOPBACK_MODE_SERDES, "serdes" },
4060 { HISI_SAS_BIST_LOOPBACK_MODE_REMOTE, "remote" },
4063 static int debugfs_bist_mode_v3_hw_show(struct seq_file *s, void *p)
4065 struct hisi_hba *hisi_hba = s->private;
4068 for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4069 int match = (hisi_hba->debugfs_bist_mode ==
4070 debugfs_loop_modes_v3_hw[i].value);
4072 seq_printf(s, "%s%s%s ", match ? "[" : "",
4073 debugfs_loop_modes_v3_hw[i].name,
4081 static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp,
4082 const char __user *buf,
4083 size_t count, loff_t *ppos)
4085 struct seq_file *m = filp->private_data;
4086 struct hisi_hba *hisi_hba = m->private;
4087 char kbuf[16] = {}, *pkbuf;
4091 if (hisi_hba->debugfs_bist_enable)
4094 if (count >= sizeof(kbuf))
4097 if (copy_from_user(kbuf, buf, count))
4100 pkbuf = strstrip(kbuf);
4102 for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4103 if (!strncmp(debugfs_loop_modes_v3_hw[i].name, pkbuf, 16)) {
4104 hisi_hba->debugfs_bist_mode =
4105 debugfs_loop_modes_v3_hw[i].value;
4117 static int debugfs_bist_mode_v3_hw_open(struct inode *inode,
4120 return single_open(filp, debugfs_bist_mode_v3_hw_show,
4124 static const struct file_operations debugfs_bist_mode_v3_hw_fops = {
4125 .open = debugfs_bist_mode_v3_hw_open,
4127 .write = debugfs_bist_mode_v3_hw_write,
4128 .llseek = seq_lseek,
4129 .release = single_release,
4130 .owner = THIS_MODULE,
4133 static ssize_t debugfs_bist_enable_v3_hw_write(struct file *filp,
4134 const char __user *buf,
4135 size_t count, loff_t *ppos)
4137 struct seq_file *m = filp->private_data;
4138 struct hisi_hba *hisi_hba = m->private;
4139 unsigned int enable;
4142 val = kstrtouint_from_user(buf, count, 0, &enable);
4149 if (enable == hisi_hba->debugfs_bist_enable)
4152 val = debugfs_set_bist_v3_hw(hisi_hba, enable);
4156 hisi_hba->debugfs_bist_enable = enable;
4161 static int debugfs_bist_enable_v3_hw_show(struct seq_file *s, void *p)
4163 struct hisi_hba *hisi_hba = s->private;
4165 seq_printf(s, "%d\n", hisi_hba->debugfs_bist_enable);
4170 static int debugfs_bist_enable_v3_hw_open(struct inode *inode,
4173 return single_open(filp, debugfs_bist_enable_v3_hw_show,
4177 static const struct file_operations debugfs_bist_enable_v3_hw_fops = {
4178 .open = debugfs_bist_enable_v3_hw_open,
4180 .write = debugfs_bist_enable_v3_hw_write,
4181 .llseek = seq_lseek,
4182 .release = single_release,
4183 .owner = THIS_MODULE,
4186 static const struct {
4188 } debugfs_ffe_name_v3_hw[FFE_CFG_MAX] = {
4192 { "SAS_12_0_GBPS" },
4194 { "SATA_1_5_GBPS" },
4195 { "SATA_3_0_GBPS" },
4196 { "SATA_6_0_GBPS" },
4199 static ssize_t debugfs_v3_hw_write(struct file *filp,
4200 const char __user *buf,
4201 size_t count, loff_t *ppos)
4203 struct seq_file *m = filp->private_data;
4204 u32 *val = m->private;
4207 res = kstrtouint_from_user(buf, count, 0, val);
4214 static int debugfs_v3_hw_show(struct seq_file *s, void *p)
4216 u32 *val = s->private;
4218 seq_printf(s, "0x%x\n", *val);
4223 static int debugfs_v3_hw_open(struct inode *inode, struct file *filp)
4225 return single_open(filp, debugfs_v3_hw_show,
4229 static const struct file_operations debugfs_v3_hw_fops = {
4230 .open = debugfs_v3_hw_open,
4232 .write = debugfs_v3_hw_write,
4233 .llseek = seq_lseek,
4234 .release = single_release,
4235 .owner = THIS_MODULE,
4238 static ssize_t debugfs_phy_down_cnt_v3_hw_write(struct file *filp,
4239 const char __user *buf,
4240 size_t count, loff_t *ppos)
4242 struct seq_file *s = filp->private_data;
4243 struct hisi_sas_phy *phy = s->private;
4244 unsigned int set_val;
4247 res = kstrtouint_from_user(buf, count, 0, &set_val);
4254 atomic_set(&phy->down_cnt, 0);
4259 static int debugfs_phy_down_cnt_v3_hw_show(struct seq_file *s, void *p)
4261 struct hisi_sas_phy *phy = s->private;
4263 seq_printf(s, "%d\n", atomic_read(&phy->down_cnt));
4268 static int debugfs_phy_down_cnt_v3_hw_open(struct inode *inode,
4271 return single_open(filp, debugfs_phy_down_cnt_v3_hw_show,
4275 static const struct file_operations debugfs_phy_down_cnt_v3_hw_fops = {
4276 .open = debugfs_phy_down_cnt_v3_hw_open,
4278 .write = debugfs_phy_down_cnt_v3_hw_write,
4279 .llseek = seq_lseek,
4280 .release = single_release,
4281 .owner = THIS_MODULE,
4284 enum fifo_dump_mode_v3_hw {
4285 FIFO_DUMP_FORVER = (1U << 0),
4286 FIFO_DUMP_AFTER_TRIGGER = (1U << 1),
4287 FIFO_DUMP_UNTILL_TRIGGER = (1U << 2),
4290 enum fifo_trigger_mode_v3_hw {
4291 FIFO_TRIGGER_EDGE = (1U << 0),
4292 FIFO_TRIGGER_SAME_LEVEL = (1U << 1),
4293 FIFO_TRIGGER_DIFF_LEVEL = (1U << 2),
4296 static int debugfs_is_fifo_config_valid_v3_hw(struct hisi_sas_phy *phy)
4298 struct hisi_hba *hisi_hba = phy->hisi_hba;
4300 if (phy->fifo.signal_sel > 0xf) {
4301 dev_info(hisi_hba->dev, "Invalid signal select: %u\n",
4302 phy->fifo.signal_sel);
4306 switch (phy->fifo.dump_mode) {
4307 case FIFO_DUMP_FORVER:
4308 case FIFO_DUMP_AFTER_TRIGGER:
4309 case FIFO_DUMP_UNTILL_TRIGGER:
4312 dev_info(hisi_hba->dev, "Invalid dump mode: %u\n",
4313 phy->fifo.dump_mode);
4317 /* when FIFO_DUMP_FORVER, no need to check trigger_mode */
4318 if (phy->fifo.dump_mode == FIFO_DUMP_FORVER)
4321 switch (phy->fifo.trigger_mode) {
4322 case FIFO_TRIGGER_EDGE:
4323 case FIFO_TRIGGER_SAME_LEVEL:
4324 case FIFO_TRIGGER_DIFF_LEVEL:
4327 dev_info(hisi_hba->dev, "Invalid trigger mode: %u\n",
4328 phy->fifo.trigger_mode);
4334 static int debugfs_update_fifo_config_v3_hw(struct hisi_sas_phy *phy)
4336 u32 trigger_mode = phy->fifo.trigger_mode;
4337 u32 signal_sel = phy->fifo.signal_sel;
4338 u32 dump_mode = phy->fifo.dump_mode;
4339 struct hisi_hba *hisi_hba = phy->hisi_hba;
4340 int phy_no = phy->sas_phy.id;
4344 /* Check the validity of trace FIFO configuration */
4345 res = debugfs_is_fifo_config_valid_v3_hw(phy);
4349 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4350 /* Disable trace FIFO before update configuration */
4351 reg_val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4353 /* Update trace FIFO configuration */
4354 reg_val &= ~(DFX_FIFO_CTRL_DUMP_MODE_MSK |
4355 DFX_FIFO_CTRL_SIGNAL_SEL_MSK |
4356 DFX_FIFO_CTRL_TRIGGER_MODE_MSK);
4358 reg_val |= ((trigger_mode << DFX_FIFO_CTRL_TRIGGER_MODE_OFF) |
4359 (dump_mode << DFX_FIFO_CTRL_DUMP_MODE_OFF) |
4360 (signal_sel << DFX_FIFO_CTRL_SIGNAL_SEL_OFF));
4361 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4363 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK,
4364 phy->fifo.dump_msk);
4366 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER,
4369 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK,
4370 phy->fifo.trigger_msk);
4372 /* Enable trace FIFO after updated configuration */
4373 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4374 reg_val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4375 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4380 static ssize_t debugfs_fifo_update_cfg_v3_hw_write(struct file *filp,
4381 const char __user *buf,
4382 size_t count, loff_t *ppos)
4384 struct hisi_sas_phy *phy = filp->private_data;
4388 val = kstrtobool_from_user(buf, count, &update);
4395 val = debugfs_update_fifo_config_v3_hw(phy);
4402 static const struct file_operations debugfs_fifo_update_cfg_v3_hw_fops = {
4403 .open = simple_open,
4404 .write = debugfs_fifo_update_cfg_v3_hw_write,
4405 .owner = THIS_MODULE,
4408 static void debugfs_read_fifo_data_v3_hw(struct hisi_sas_phy *phy)
4410 struct hisi_hba *hisi_hba = phy->hisi_hba;
4411 u32 *buf = phy->fifo.rd_data;
4412 int phy_no = phy->sas_phy.id;
4416 memset(buf, 0, sizeof(phy->fifo.rd_data));
4418 /* Disable trace FIFO before read data */
4419 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4420 val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4421 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4423 for (i = 0; i < HISI_SAS_FIFO_DATA_DW_SIZE; i++) {
4424 val = hisi_sas_phy_read32(hisi_hba, phy_no,
4429 /* Enable trace FIFO after read data */
4430 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4431 val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4432 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4435 static int debugfs_fifo_data_v3_hw_show(struct seq_file *s, void *p)
4437 struct hisi_sas_phy *phy = s->private;
4439 debugfs_read_fifo_data_v3_hw(phy);
4441 debugfs_show_row_32_v3_hw(s, 0, HISI_SAS_FIFO_DATA_DW_SIZE * 4,
4446 DEFINE_SHOW_ATTRIBUTE(debugfs_fifo_data_v3_hw);
4448 static void debugfs_fifo_init_v3_hw(struct hisi_hba *hisi_hba)
4452 hisi_hba->debugfs_fifo_dentry =
4453 debugfs_create_dir("fifo", hisi_hba->debugfs_dir);
4455 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4456 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
4457 struct dentry *port_dentry;
4461 /* get default configuration for trace FIFO */
4462 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4463 val &= DFX_FIFO_CTRL_DUMP_MODE_MSK;
4464 val >>= DFX_FIFO_CTRL_DUMP_MODE_OFF;
4465 phy->fifo.dump_mode = val;
4467 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4468 val &= DFX_FIFO_CTRL_TRIGGER_MODE_MSK;
4469 val >>= DFX_FIFO_CTRL_TRIGGER_MODE_OFF;
4470 phy->fifo.trigger_mode = val;
4472 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4473 val &= DFX_FIFO_CTRL_SIGNAL_SEL_MSK;
4474 val >>= DFX_FIFO_CTRL_SIGNAL_SEL_OFF;
4475 phy->fifo.signal_sel = val;
4477 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK);
4478 phy->fifo.dump_msk = val;
4480 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER);
4481 phy->fifo.trigger = val;
4482 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK);
4483 phy->fifo.trigger_msk = val;
4485 snprintf(name, 256, "%d", phy_no);
4486 port_dentry = debugfs_create_dir(name,
4487 hisi_hba->debugfs_fifo_dentry);
4489 debugfs_create_file("update_config", 0200, port_dentry, phy,
4490 &debugfs_fifo_update_cfg_v3_hw_fops);
4492 debugfs_create_file("signal_sel", 0600, port_dentry,
4493 &phy->fifo.signal_sel,
4494 &debugfs_v3_hw_fops);
4496 debugfs_create_file("dump_msk", 0600, port_dentry,
4497 &phy->fifo.dump_msk,
4498 &debugfs_v3_hw_fops);
4500 debugfs_create_file("dump_mode", 0600, port_dentry,
4501 &phy->fifo.dump_mode,
4502 &debugfs_v3_hw_fops);
4504 debugfs_create_file("trigger_mode", 0600, port_dentry,
4505 &phy->fifo.trigger_mode,
4506 &debugfs_v3_hw_fops);
4508 debugfs_create_file("trigger", 0600, port_dentry,
4510 &debugfs_v3_hw_fops);
4512 debugfs_create_file("trigger_msk", 0600, port_dentry,
4513 &phy->fifo.trigger_msk,
4514 &debugfs_v3_hw_fops);
4516 debugfs_create_file("fifo_data", 0400, port_dentry, phy,
4517 &debugfs_fifo_data_v3_hw_fops);
4521 static void debugfs_work_handler_v3_hw(struct work_struct *work)
4523 struct hisi_hba *hisi_hba =
4524 container_of(work, struct hisi_hba, debugfs_work);
4526 debugfs_snapshot_regs_v3_hw(hisi_hba);
4529 static void debugfs_release_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4531 struct device *dev = hisi_hba->dev;
4534 devm_kfree(dev, hisi_hba->debugfs_iost_cache[dump_index].cache);
4535 devm_kfree(dev, hisi_hba->debugfs_itct_cache[dump_index].cache);
4536 devm_kfree(dev, hisi_hba->debugfs_iost[dump_index].iost);
4537 devm_kfree(dev, hisi_hba->debugfs_itct[dump_index].itct);
4539 for (i = 0; i < hisi_hba->queue_count; i++)
4540 devm_kfree(dev, hisi_hba->debugfs_dq[dump_index][i].hdr);
4542 for (i = 0; i < hisi_hba->queue_count; i++)
4544 hisi_hba->debugfs_cq[dump_index][i].complete_hdr);
4546 for (i = 0; i < DEBUGFS_REGS_NUM; i++)
4547 devm_kfree(dev, hisi_hba->debugfs_regs[dump_index][i].data);
4549 for (i = 0; i < hisi_hba->n_phy; i++)
4550 devm_kfree(dev, hisi_hba->debugfs_port_reg[dump_index][i].data);
4553 static const struct hisi_sas_debugfs_reg *debugfs_reg_array_v3_hw[DEBUGFS_REGS_NUM] = {
4554 [DEBUGFS_GLOBAL] = &debugfs_global_reg,
4555 [DEBUGFS_AXI] = &debugfs_axi_reg,
4556 [DEBUGFS_RAS] = &debugfs_ras_reg,
4559 static int debugfs_alloc_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4561 const struct hisi_sas_hw *hw = hisi_hba->hw;
4562 struct device *dev = hisi_hba->dev;
4566 for (r = 0; r < DEBUGFS_REGS_NUM; r++) {
4567 struct hisi_sas_debugfs_regs *regs =
4568 &hisi_hba->debugfs_regs[dump_index][r];
4570 sz = debugfs_reg_array_v3_hw[r]->count * 4;
4571 regs->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4574 regs->hisi_hba = hisi_hba;
4577 sz = debugfs_port_reg.count * 4;
4578 for (p = 0; p < hisi_hba->n_phy; p++) {
4579 struct hisi_sas_debugfs_port *port =
4580 &hisi_hba->debugfs_port_reg[dump_index][p];
4582 port->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4585 port->phy = &hisi_hba->phy[p];
4588 sz = hw->complete_hdr_size * HISI_SAS_QUEUE_SLOTS;
4589 for (c = 0; c < hisi_hba->queue_count; c++) {
4590 struct hisi_sas_debugfs_cq *cq =
4591 &hisi_hba->debugfs_cq[dump_index][c];
4593 cq->complete_hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4594 if (!cq->complete_hdr)
4596 cq->cq = &hisi_hba->cq[c];
4599 sz = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
4600 for (d = 0; d < hisi_hba->queue_count; d++) {
4601 struct hisi_sas_debugfs_dq *dq =
4602 &hisi_hba->debugfs_dq[dump_index][d];
4604 dq->hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4607 dq->dq = &hisi_hba->dq[d];
4610 sz = HISI_SAS_MAX_COMMANDS * sizeof(struct hisi_sas_iost);
4612 hisi_hba->debugfs_iost[dump_index].iost =
4613 devm_kmalloc(dev, sz, GFP_KERNEL);
4614 if (!hisi_hba->debugfs_iost[dump_index].iost)
4617 sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4618 sizeof(struct hisi_sas_iost_itct_cache);
4620 hisi_hba->debugfs_iost_cache[dump_index].cache =
4621 devm_kmalloc(dev, sz, GFP_KERNEL);
4622 if (!hisi_hba->debugfs_iost_cache[dump_index].cache)
4625 sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4626 sizeof(struct hisi_sas_iost_itct_cache);
4628 hisi_hba->debugfs_itct_cache[dump_index].cache =
4629 devm_kmalloc(dev, sz, GFP_KERNEL);
4630 if (!hisi_hba->debugfs_itct_cache[dump_index].cache)
4633 /* New memory allocation must be locate before itct */
4634 sz = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
4636 hisi_hba->debugfs_itct[dump_index].itct =
4637 devm_kmalloc(dev, sz, GFP_KERNEL);
4638 if (!hisi_hba->debugfs_itct[dump_index].itct)
4643 for (i = 0; i < hisi_sas_debugfs_dump_count; i++)
4644 debugfs_release_v3_hw(hisi_hba, i);
4648 static void debugfs_phy_down_cnt_init_v3_hw(struct hisi_hba *hisi_hba)
4650 struct dentry *dir = debugfs_create_dir("phy_down_cnt",
4651 hisi_hba->debugfs_dir);
4655 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4656 snprintf(name, 16, "%d", phy_no);
4657 debugfs_create_file(name, 0600, dir,
4658 &hisi_hba->phy[phy_no],
4659 &debugfs_phy_down_cnt_v3_hw_fops);
4663 static void debugfs_bist_init_v3_hw(struct hisi_hba *hisi_hba)
4665 struct dentry *ports_dentry;
4668 hisi_hba->debugfs_bist_dentry =
4669 debugfs_create_dir("bist", hisi_hba->debugfs_dir);
4670 debugfs_create_file("link_rate", 0600,
4671 hisi_hba->debugfs_bist_dentry, hisi_hba,
4672 &debugfs_bist_linkrate_v3_hw_fops);
4674 debugfs_create_file("code_mode", 0600,
4675 hisi_hba->debugfs_bist_dentry, hisi_hba,
4676 &debugfs_bist_code_mode_v3_hw_fops);
4678 debugfs_create_file("fixed_code", 0600,
4679 hisi_hba->debugfs_bist_dentry,
4680 &hisi_hba->debugfs_bist_fixed_code[0],
4681 &debugfs_v3_hw_fops);
4683 debugfs_create_file("fixed_code_1", 0600,
4684 hisi_hba->debugfs_bist_dentry,
4685 &hisi_hba->debugfs_bist_fixed_code[1],
4686 &debugfs_v3_hw_fops);
4688 debugfs_create_file("phy_id", 0600, hisi_hba->debugfs_bist_dentry,
4689 hisi_hba, &debugfs_bist_phy_v3_hw_fops);
4691 debugfs_create_file("cnt", 0600, hisi_hba->debugfs_bist_dentry,
4692 hisi_hba, &debugfs_bist_cnt_v3_hw_ops);
4694 debugfs_create_file("loopback_mode", 0600,
4695 hisi_hba->debugfs_bist_dentry,
4696 hisi_hba, &debugfs_bist_mode_v3_hw_fops);
4698 debugfs_create_file("enable", 0600, hisi_hba->debugfs_bist_dentry,
4699 hisi_hba, &debugfs_bist_enable_v3_hw_fops);
4701 ports_dentry = debugfs_create_dir("port", hisi_hba->debugfs_bist_dentry);
4703 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4704 struct dentry *port_dentry;
4705 struct dentry *ffe_dentry;
4709 snprintf(name, 256, "%d", phy_no);
4710 port_dentry = debugfs_create_dir(name, ports_dentry);
4711 ffe_dentry = debugfs_create_dir("ffe", port_dentry);
4712 for (i = 0; i < FFE_CFG_MAX; i++) {
4715 debugfs_create_file(debugfs_ffe_name_v3_hw[i].name,
4717 &hisi_hba->debugfs_bist_ffe[phy_no][i],
4718 &debugfs_v3_hw_fops);
4722 hisi_hba->debugfs_bist_linkrate = SAS_LINK_RATE_1_5_GBPS;
4725 static void debugfs_init_v3_hw(struct hisi_hba *hisi_hba)
4727 struct device *dev = hisi_hba->dev;
4730 hisi_hba->debugfs_dir = debugfs_create_dir(dev_name(dev),
4731 hisi_sas_debugfs_dir);
4732 debugfs_create_file("trigger_dump", 0200,
4733 hisi_hba->debugfs_dir,
4735 &debugfs_trigger_dump_v3_hw_fops);
4737 /* create bist structures */
4738 debugfs_bist_init_v3_hw(hisi_hba);
4740 hisi_hba->debugfs_dump_dentry =
4741 debugfs_create_dir("dump", hisi_hba->debugfs_dir);
4743 debugfs_phy_down_cnt_init_v3_hw(hisi_hba);
4744 debugfs_fifo_init_v3_hw(hisi_hba);
4746 for (i = 0; i < hisi_sas_debugfs_dump_count; i++) {
4747 if (debugfs_alloc_v3_hw(hisi_hba, i)) {
4748 debugfs_remove_recursive(hisi_hba->debugfs_dir);
4749 dev_dbg(dev, "failed to init debugfs!\n");
4755 static void debugfs_exit_v3_hw(struct hisi_hba *hisi_hba)
4757 debugfs_remove_recursive(hisi_hba->debugfs_dir);
4761 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4763 struct Scsi_Host *shost;
4764 struct hisi_hba *hisi_hba;
4765 struct device *dev = &pdev->dev;
4766 struct asd_sas_phy **arr_phy;
4767 struct asd_sas_port **arr_port;
4768 struct sas_ha_struct *sha;
4769 int rc, phy_nr, port_nr, i;
4771 rc = pcim_enable_device(pdev);
4775 pci_set_master(pdev);
4777 rc = pcim_iomap_regions(pdev, 1 << BAR_NO_V3_HW, DRV_NAME);
4781 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4783 dev_err(dev, "No usable DMA addressing method\n");
4788 shost = hisi_sas_shost_alloc_pci(pdev);
4794 sha = SHOST_TO_SAS_HA(shost);
4795 hisi_hba = shost_priv(shost);
4796 dev_set_drvdata(dev, sha);
4798 hisi_hba->regs = pcim_iomap_table(pdev)[BAR_NO_V3_HW];
4799 if (!hisi_hba->regs) {
4800 dev_err(dev, "cannot map register\n");
4802 goto err_out_free_host;
4805 phy_nr = port_nr = hisi_hba->n_phy;
4807 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
4808 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
4809 if (!arr_phy || !arr_port) {
4811 goto err_out_free_host;
4814 sha->sas_phy = arr_phy;
4815 sha->sas_port = arr_port;
4816 sha->core.shost = shost;
4817 sha->lldd_ha = hisi_hba;
4819 shost->transportt = hisi_sas_stt;
4820 shost->max_id = HISI_SAS_MAX_DEVICES;
4821 shost->max_lun = ~0;
4822 shost->max_channel = 1;
4823 shost->max_cmd_len = 16;
4824 shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
4825 shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
4827 sha->sas_ha_name = DRV_NAME;
4829 sha->lldd_module = THIS_MODULE;
4830 sha->sas_addr = &hisi_hba->sas_addr[0];
4831 sha->num_phys = hisi_hba->n_phy;
4833 for (i = 0; i < hisi_hba->n_phy; i++) {
4834 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
4835 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
4838 if (hisi_hba->prot_mask) {
4839 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
4841 scsi_host_set_prot(hisi_hba->shost, prot_mask);
4842 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
4843 scsi_host_set_guard(hisi_hba->shost,
4844 SHOST_DIX_GUARD_CRC);
4847 if (hisi_sas_debugfs_enable)
4848 debugfs_init_v3_hw(hisi_hba);
4850 rc = interrupt_preinit_v3_hw(hisi_hba);
4852 goto err_out_undo_debugfs;
4854 rc = scsi_add_host(shost, dev);
4856 goto err_out_undo_debugfs;
4858 rc = sas_register_ha(sha);
4860 goto err_out_remove_host;
4862 rc = hisi_sas_v3_init(hisi_hba);
4864 goto err_out_unregister_ha;
4866 scsi_scan_host(shost);
4868 pm_runtime_set_autosuspend_delay(dev, 5000);
4869 pm_runtime_use_autosuspend(dev);
4871 * For the situation that there are ATA disks connected with SAS
4872 * controller, it additionally creates ata_port which will affect the
4873 * child_count of hisi_hba->dev. Even if suspended all the disks,
4874 * ata_port is still and the child_count of hisi_hba->dev is not 0.
4875 * So use pm_suspend_ignore_children() to ignore the effect to
4878 pm_suspend_ignore_children(dev, true);
4879 pm_runtime_put_noidle(&pdev->dev);
4883 err_out_unregister_ha:
4884 sas_unregister_ha(sha);
4885 err_out_remove_host:
4886 scsi_remove_host(shost);
4887 err_out_undo_debugfs:
4888 debugfs_exit_v3_hw(hisi_hba);
4890 hisi_sas_free(hisi_hba);
4891 scsi_host_put(shost);
4897 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
4901 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 1), hisi_hba);
4902 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 2), hisi_hba);
4903 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 11), hisi_hba);
4904 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
4905 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
4906 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
4908 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq);
4912 static void hisi_sas_v3_remove(struct pci_dev *pdev)
4914 struct device *dev = &pdev->dev;
4915 struct sas_ha_struct *sha = dev_get_drvdata(dev);
4916 struct hisi_hba *hisi_hba = sha->lldd_ha;
4917 struct Scsi_Host *shost = sha->core.shost;
4919 pm_runtime_get_noresume(dev);
4920 del_timer_sync(&hisi_hba->timer);
4922 sas_unregister_ha(sha);
4923 flush_workqueue(hisi_hba->wq);
4924 sas_remove_host(sha->core.shost);
4926 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
4927 hisi_sas_free(hisi_hba);
4928 debugfs_exit_v3_hw(hisi_hba);
4929 scsi_host_put(shost);
4932 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
4934 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4935 struct hisi_hba *hisi_hba = sha->lldd_ha;
4936 struct device *dev = hisi_hba->dev;
4939 dev_info(dev, "FLR prepare\n");
4940 down(&hisi_hba->sem);
4941 set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
4942 hisi_sas_controller_reset_prepare(hisi_hba);
4944 rc = disable_host_v3_hw(hisi_hba);
4946 dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
4949 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
4951 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4952 struct hisi_hba *hisi_hba = sha->lldd_ha;
4953 struct device *dev = hisi_hba->dev;
4956 hisi_sas_init_mem(hisi_hba);
4958 rc = hw_init_v3_hw(hisi_hba);
4960 dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
4964 hisi_sas_controller_reset_done(hisi_hba);
4965 dev_info(dev, "FLR done\n");
4969 /* instances of the controller */
4973 static int _suspend_v3_hw(struct device *device)
4975 struct pci_dev *pdev = to_pci_dev(device);
4976 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4977 struct hisi_hba *hisi_hba = sha->lldd_ha;
4978 struct device *dev = hisi_hba->dev;
4979 struct Scsi_Host *shost = hisi_hba->shost;
4982 if (!pdev->pm_cap) {
4983 dev_err(dev, "PCI PM not supported\n");
4987 if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
4990 dev_warn(dev, "entering suspend state\n");
4992 scsi_block_requests(shost);
4993 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
4994 flush_workqueue(hisi_hba->wq);
4996 rc = disable_host_v3_hw(hisi_hba);
4998 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
4999 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5000 clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5001 scsi_unblock_requests(shost);
5005 hisi_sas_init_mem(hisi_hba);
5007 hisi_sas_release_tasks(hisi_hba);
5009 sas_suspend_ha(sha);
5011 dev_warn(dev, "end of suspending controller\n");
5015 static int _resume_v3_hw(struct device *device)
5017 struct pci_dev *pdev = to_pci_dev(device);
5018 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5019 struct hisi_hba *hisi_hba = sha->lldd_ha;
5020 struct Scsi_Host *shost = hisi_hba->shost;
5021 struct device *dev = hisi_hba->dev;
5023 pci_power_t device_state = pdev->current_state;
5025 dev_warn(dev, "resuming from operating state [D%d]\n",
5028 scsi_unblock_requests(shost);
5029 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5031 sas_prep_resume_ha(sha);
5032 rc = hw_init_v3_hw(hisi_hba);
5034 scsi_remove_host(shost);
5037 phys_init_v3_hw(hisi_hba);
5040 * If a directly-attached disk is removed during suspend, a deadlock
5041 * may occur, as the PHYE_RESUME_TIMEOUT processing will require the
5042 * hisi_hba->device to be active, which can only happen when resume
5043 * completes. So don't wait for the HA event workqueue to drain upon
5046 sas_resume_ha_no_sync(sha);
5047 clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5049 dev_warn(dev, "end of resuming controller\n");
5054 static int __maybe_unused suspend_v3_hw(struct device *device)
5056 struct pci_dev *pdev = to_pci_dev(device);
5057 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5058 struct hisi_hba *hisi_hba = sha->lldd_ha;
5061 set_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5063 rc = _suspend_v3_hw(device);
5065 clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5070 static int __maybe_unused resume_v3_hw(struct device *device)
5072 struct pci_dev *pdev = to_pci_dev(device);
5073 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5074 struct hisi_hba *hisi_hba = sha->lldd_ha;
5075 int rc = _resume_v3_hw(device);
5077 clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5082 static const struct pci_device_id sas_v3_pci_table[] = {
5083 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
5086 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
5088 static const struct pci_error_handlers hisi_sas_err_handler = {
5089 .reset_prepare = hisi_sas_reset_prepare_v3_hw,
5090 .reset_done = hisi_sas_reset_done_v3_hw,
5093 static UNIVERSAL_DEV_PM_OPS(hisi_sas_v3_pm_ops,
5098 static struct pci_driver sas_v3_pci_driver = {
5100 .id_table = sas_v3_pci_table,
5101 .probe = hisi_sas_v3_probe,
5102 .remove = hisi_sas_v3_remove,
5103 .err_handler = &hisi_sas_err_handler,
5104 .driver.pm = &hisi_sas_v3_pm_ops,
5107 module_pci_driver(sas_v3_pci_driver);
5108 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
5110 MODULE_LICENSE("GPL");
5111 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
5112 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
5113 MODULE_ALIAS("pci:" DRV_NAME);