Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-2.6-microblaze.git] / drivers / pwm / pwm-rockchip.c
1 /*
2  * PWM driver for Rockchip SoCs
3  *
4  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5  * Copyright (C) 2014 ROCKCHIP, Inc.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  */
11
12 #include <linux/clk.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/time.h>
20
21 #define PWM_CTRL_TIMER_EN       (1 << 0)
22 #define PWM_CTRL_OUTPUT_EN      (1 << 3)
23
24 #define PWM_ENABLE              (1 << 0)
25 #define PWM_CONTINUOUS          (1 << 1)
26 #define PWM_DUTY_POSITIVE       (1 << 3)
27 #define PWM_DUTY_NEGATIVE       (0 << 3)
28 #define PWM_INACTIVE_NEGATIVE   (0 << 4)
29 #define PWM_INACTIVE_POSITIVE   (1 << 4)
30 #define PWM_POLARITY_MASK       (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
31 #define PWM_OUTPUT_LEFT         (0 << 5)
32 #define PWM_LOCK_EN             (1 << 6)
33 #define PWM_LP_DISABLE          (0 << 8)
34
35 struct rockchip_pwm_chip {
36         struct pwm_chip chip;
37         struct clk *clk;
38         struct clk *pclk;
39         const struct rockchip_pwm_data *data;
40         void __iomem *base;
41 };
42
43 struct rockchip_pwm_regs {
44         unsigned long duty;
45         unsigned long period;
46         unsigned long cntr;
47         unsigned long ctrl;
48 };
49
50 struct rockchip_pwm_data {
51         struct rockchip_pwm_regs regs;
52         unsigned int prescaler;
53         bool supports_polarity;
54         bool supports_lock;
55         u32 enable_conf;
56 };
57
58 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
59 {
60         return container_of(c, struct rockchip_pwm_chip, chip);
61 }
62
63 static void rockchip_pwm_get_state(struct pwm_chip *chip,
64                                    struct pwm_device *pwm,
65                                    struct pwm_state *state)
66 {
67         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
68         u32 enable_conf = pc->data->enable_conf;
69         unsigned long clk_rate;
70         u64 tmp;
71         u32 val;
72         int ret;
73
74         ret = clk_enable(pc->pclk);
75         if (ret)
76                 return;
77
78         clk_rate = clk_get_rate(pc->clk);
79
80         tmp = readl_relaxed(pc->base + pc->data->regs.period);
81         tmp *= pc->data->prescaler * NSEC_PER_SEC;
82         state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
83
84         tmp = readl_relaxed(pc->base + pc->data->regs.duty);
85         tmp *= pc->data->prescaler * NSEC_PER_SEC;
86         state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
87
88         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
89         if (pc->data->supports_polarity)
90                 state->enabled = ((val & enable_conf) != enable_conf) ?
91                                  false : true;
92         else
93                 state->enabled = ((val & enable_conf) == enable_conf) ?
94                                  true : false;
95
96         if (pc->data->supports_polarity) {
97                 if (!(val & PWM_DUTY_POSITIVE))
98                         state->polarity = PWM_POLARITY_INVERSED;
99         }
100
101         clk_disable(pc->pclk);
102 }
103
104 static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
105                                struct pwm_state *state)
106 {
107         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
108         unsigned long period, duty;
109         u64 clk_rate, div;
110         u32 ctrl;
111
112         clk_rate = clk_get_rate(pc->clk);
113
114         /*
115          * Since period and duty cycle registers have a width of 32
116          * bits, every possible input period can be obtained using the
117          * default prescaler value for all practical clock rate values.
118          */
119         div = clk_rate * state->period;
120         period = DIV_ROUND_CLOSEST_ULL(div,
121                                        pc->data->prescaler * NSEC_PER_SEC);
122
123         div = clk_rate * state->duty_cycle;
124         duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
125
126         /*
127          * Lock the period and duty of previous configuration, then
128          * change the duty and period, that would not be effective.
129          */
130         ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
131         if (pc->data->supports_lock) {
132                 ctrl |= PWM_LOCK_EN;
133                 writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
134         }
135
136         writel(period, pc->base + pc->data->regs.period);
137         writel(duty, pc->base + pc->data->regs.duty);
138
139         if (pc->data->supports_polarity) {
140                 ctrl &= ~PWM_POLARITY_MASK;
141                 if (state->polarity == PWM_POLARITY_INVERSED)
142                         ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
143                 else
144                         ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
145         }
146
147         /*
148          * Unlock and set polarity at the same time,
149          * the configuration of duty, period and polarity
150          * would be effective together at next period.
151          */
152         if (pc->data->supports_lock)
153                 ctrl &= ~PWM_LOCK_EN;
154
155         writel(ctrl, pc->base + pc->data->regs.ctrl);
156 }
157
158 static int rockchip_pwm_enable(struct pwm_chip *chip,
159                                struct pwm_device *pwm,
160                                bool enable)
161 {
162         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
163         u32 enable_conf = pc->data->enable_conf;
164         int ret;
165         u32 val;
166
167         if (enable) {
168                 ret = clk_enable(pc->clk);
169                 if (ret)
170                         return ret;
171         }
172
173         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
174
175         if (enable)
176                 val |= enable_conf;
177         else
178                 val &= ~enable_conf;
179
180         writel_relaxed(val, pc->base + pc->data->regs.ctrl);
181
182         if (!enable)
183                 clk_disable(pc->clk);
184
185         return 0;
186 }
187
188 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
189                               struct pwm_state *state)
190 {
191         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
192         struct pwm_state curstate;
193         bool enabled;
194         int ret = 0;
195
196         ret = clk_enable(pc->pclk);
197         if (ret)
198                 return ret;
199
200         pwm_get_state(pwm, &curstate);
201         enabled = curstate.enabled;
202
203         if (state->polarity != curstate.polarity && enabled &&
204             !pc->data->supports_lock) {
205                 ret = rockchip_pwm_enable(chip, pwm, false);
206                 if (ret)
207                         goto out;
208                 enabled = false;
209         }
210
211         rockchip_pwm_config(chip, pwm, state);
212         if (state->enabled != enabled) {
213                 ret = rockchip_pwm_enable(chip, pwm, state->enabled);
214                 if (ret)
215                         goto out;
216         }
217
218         /*
219          * Update the state with the real hardware, which can differ a bit
220          * because of period/duty_cycle approximation.
221          */
222         rockchip_pwm_get_state(chip, pwm, state);
223
224 out:
225         clk_disable(pc->pclk);
226
227         return ret;
228 }
229
230 static const struct pwm_ops rockchip_pwm_ops = {
231         .get_state = rockchip_pwm_get_state,
232         .apply = rockchip_pwm_apply,
233         .owner = THIS_MODULE,
234 };
235
236 static const struct rockchip_pwm_data pwm_data_v1 = {
237         .regs = {
238                 .duty = 0x04,
239                 .period = 0x08,
240                 .cntr = 0x00,
241                 .ctrl = 0x0c,
242         },
243         .prescaler = 2,
244         .supports_polarity = false,
245         .supports_lock = false,
246         .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
247 };
248
249 static const struct rockchip_pwm_data pwm_data_v2 = {
250         .regs = {
251                 .duty = 0x08,
252                 .period = 0x04,
253                 .cntr = 0x00,
254                 .ctrl = 0x0c,
255         },
256         .prescaler = 1,
257         .supports_polarity = true,
258         .supports_lock = false,
259         .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
260                        PWM_CONTINUOUS,
261 };
262
263 static const struct rockchip_pwm_data pwm_data_vop = {
264         .regs = {
265                 .duty = 0x08,
266                 .period = 0x04,
267                 .cntr = 0x0c,
268                 .ctrl = 0x00,
269         },
270         .prescaler = 1,
271         .supports_polarity = true,
272         .supports_lock = false,
273         .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
274                        PWM_CONTINUOUS,
275 };
276
277 static const struct rockchip_pwm_data pwm_data_v3 = {
278         .regs = {
279                 .duty = 0x08,
280                 .period = 0x04,
281                 .cntr = 0x00,
282                 .ctrl = 0x0c,
283         },
284         .prescaler = 1,
285         .supports_polarity = true,
286         .supports_lock = true,
287         .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
288                        PWM_CONTINUOUS,
289 };
290
291 static const struct of_device_id rockchip_pwm_dt_ids[] = {
292         { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
293         { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
294         { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
295         { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
296         { /* sentinel */ }
297 };
298 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
299
300 static int rockchip_pwm_probe(struct platform_device *pdev)
301 {
302         const struct of_device_id *id;
303         struct rockchip_pwm_chip *pc;
304         struct resource *r;
305         int ret, count;
306
307         id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
308         if (!id)
309                 return -EINVAL;
310
311         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
312         if (!pc)
313                 return -ENOMEM;
314
315         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
316         pc->base = devm_ioremap_resource(&pdev->dev, r);
317         if (IS_ERR(pc->base))
318                 return PTR_ERR(pc->base);
319
320         pc->clk = devm_clk_get(&pdev->dev, "pwm");
321         if (IS_ERR(pc->clk)) {
322                 pc->clk = devm_clk_get(&pdev->dev, NULL);
323                 if (IS_ERR(pc->clk)) {
324                         ret = PTR_ERR(pc->clk);
325                         if (ret != -EPROBE_DEFER)
326                                 dev_err(&pdev->dev, "Can't get bus clk: %d\n",
327                                         ret);
328                         return ret;
329                 }
330         }
331
332         count = of_count_phandle_with_args(pdev->dev.of_node,
333                                            "clocks", "#clock-cells");
334         if (count == 2)
335                 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
336         else
337                 pc->pclk = pc->clk;
338
339         if (IS_ERR(pc->pclk)) {
340                 ret = PTR_ERR(pc->pclk);
341                 if (ret != -EPROBE_DEFER)
342                         dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
343                 return ret;
344         }
345
346         ret = clk_prepare_enable(pc->clk);
347         if (ret) {
348                 dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
349                 return ret;
350         }
351
352         ret = clk_prepare(pc->pclk);
353         if (ret) {
354                 dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret);
355                 goto err_clk;
356         }
357
358         platform_set_drvdata(pdev, pc);
359
360         pc->data = id->data;
361         pc->chip.dev = &pdev->dev;
362         pc->chip.ops = &rockchip_pwm_ops;
363         pc->chip.base = -1;
364         pc->chip.npwm = 1;
365
366         if (pc->data->supports_polarity) {
367                 pc->chip.of_xlate = of_pwm_xlate_with_flags;
368                 pc->chip.of_pwm_n_cells = 3;
369         }
370
371         ret = pwmchip_add(&pc->chip);
372         if (ret < 0) {
373                 clk_unprepare(pc->clk);
374                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
375                 goto err_pclk;
376         }
377
378         /* Keep the PWM clk enabled if the PWM appears to be up and running. */
379         if (!pwm_is_enabled(pc->chip.pwms))
380                 clk_disable(pc->clk);
381
382         return 0;
383
384 err_pclk:
385         clk_unprepare(pc->pclk);
386 err_clk:
387         clk_disable_unprepare(pc->clk);
388
389         return ret;
390 }
391
392 static int rockchip_pwm_remove(struct platform_device *pdev)
393 {
394         struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
395
396         /*
397          * Disable the PWM clk before unpreparing it if the PWM device is still
398          * running. This should only happen when the last PWM user left it
399          * enabled, or when nobody requested a PWM that was previously enabled
400          * by the bootloader.
401          *
402          * FIXME: Maybe the core should disable all PWM devices in
403          * pwmchip_remove(). In this case we'd only have to call
404          * clk_unprepare() after pwmchip_remove().
405          *
406          */
407         if (pwm_is_enabled(pc->chip.pwms))
408                 clk_disable(pc->clk);
409
410         clk_unprepare(pc->pclk);
411         clk_unprepare(pc->clk);
412
413         return pwmchip_remove(&pc->chip);
414 }
415
416 static struct platform_driver rockchip_pwm_driver = {
417         .driver = {
418                 .name = "rockchip-pwm",
419                 .of_match_table = rockchip_pwm_dt_ids,
420         },
421         .probe = rockchip_pwm_probe,
422         .remove = rockchip_pwm_remove,
423 };
424 module_platform_driver(rockchip_pwm_driver);
425
426 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
427 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
428 MODULE_LICENSE("GPL v2");