drivers/platform/x86/amd/pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <asm/amd_nb.h>
  14 #include <linux/acpi.h>
  15 #include <linux/bitfield.h>
  16 #include <linux/bits.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/io.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/limits.h>
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/rtc.h>
  26 #include <linux/serio.h>
  27 #include <linux/suspend.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/uaccess.h>
  30
  31 /* SMU communication registers */
  32 #define AMD_PMC_REGISTER_MESSAGE        0x538
  33 #define AMD_PMC_REGISTER_RESPONSE       0x980
  34 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  35
  36 /* PMC Scratch Registers */
  37 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  38 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  39
  40 /* STB Registers */
  41 #define AMD_PMC_STB_PMI_0               0x03E30600
  42 #define AMD_PMC_STB_S2IDLE_PREPARE      0xC6000001
  43 #define AMD_PMC_STB_S2IDLE_RESTORE      0xC6000002
  44 #define AMD_PMC_STB_S2IDLE_CHECK        0xC6000003
  45 #define AMD_PMC_STB_DUMMY_PC            0xC6000007
  46
  47 /* STB S2D(Spill to DRAM) has different message port offset */
  48 #define AMD_S2D_REGISTER_MESSAGE        0xA20
  49 #define AMD_S2D_REGISTER_RESPONSE       0xA80
  50 #define AMD_S2D_REGISTER_ARGUMENT       0xA88
  51
  52 /* STB Spill to DRAM Parameters */
  53 #define S2D_TELEMETRY_BYTES_MAX         0x100000
  54 #define S2D_TELEMETRY_DRAMBYTES_MAX     0x1000000
  55
  56 /* Base address of SMU for mapping physical address to virtual address */
  57 #define AMD_PMC_MAPPING_SIZE            0x01000
  58 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  59 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  60 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  61 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  62 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  63
  64 /* SMU Response Codes */
  65 #define AMD_PMC_RESULT_OK                    0x01
  66 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  67 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  68 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  69 #define AMD_PMC_RESULT_FAILED                0xFF
  70
  71 /* FCH SSC Registers */
  72 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  73 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  74 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  75 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  76 #define FCH_SSC_MAPPING_SIZE            0x800
  77 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  78 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  79
  80 /* SMU Message Definations */
  81 #define SMU_MSG_GETSMUVERSION           0x02
  82 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  83 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  84 #define SMU_MSG_LOG_START               0x06
  85 #define SMU_MSG_LOG_RESET               0x07
  86 #define SMU_MSG_LOG_DUMP_DATA           0x08
  87 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  88 /* List of supported CPU ids */
  89 #define AMD_CPU_ID_RV                   0x15D0
  90 #define AMD_CPU_ID_RN                   0x1630
  91 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  92 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  93 #define AMD_CPU_ID_YC                   0x14B5
  94 #define AMD_CPU_ID_CB                   0x14D8
  95 #define AMD_CPU_ID_PS                   0x14E8
  96 #define AMD_CPU_ID_SP                   0x14A4
  97
  98 #define PMC_MSG_DELAY_MIN_US            50
  99 #define RESPONSE_REGISTER_LOOP_MAX      20000
 100
 101 #define DELAY_MIN_US            2000
 102 #define DELAY_MAX_US            3000
 103 #define FIFO_SIZE               4096
 104
 105 enum amd_pmc_def {
 106         MSG_TEST = 0x01,
 107         MSG_OS_HINT_PCO,
 108         MSG_OS_HINT_RN,
 109 };
 110
 111 enum s2d_arg {
 112         S2D_TELEMETRY_SIZE = 0x01,
 113         S2D_PHYS_ADDR_LOW,
 114         S2D_PHYS_ADDR_HIGH,
 115         S2D_NUM_SAMPLES,
 116         S2D_DRAM_SIZE,
 117 };
 118
 119 struct amd_pmc_bit_map {
 120         const char *name;
 121         u32 bit_mask;
 122 };
 123
 124 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 125         {"DISPLAY",     BIT(0)},
 126         {"CPU",         BIT(1)},
 127         {"GFX",         BIT(2)},
 128         {"VDD",         BIT(3)},
 129         {"ACP",         BIT(4)},
 130         {"VCN",         BIT(5)},
 131         {"ISP",         BIT(6)},
 132         {"NBIO",        BIT(7)},
 133         {"DF",          BIT(8)},
 134         {"USB3_0",      BIT(9)},
 135         {"USB3_1",      BIT(10)},
 136         {"LAPIC",       BIT(11)},
 137         {"USB3_2",      BIT(12)},
 138         {"USB3_3",      BIT(13)},
 139         {"USB3_4",      BIT(14)},
 140         {"USB4_0",      BIT(15)},
 141         {"USB4_1",      BIT(16)},
 142         {"MPM",         BIT(17)},
 143         {"JPEG",        BIT(18)},
 144         {"IPU",         BIT(19)},
 145         {"UMSCH",       BIT(20)},
 146         {}
 147 };
 148
 149 struct amd_pmc_dev {
 150         void __iomem *regbase;
 151         void __iomem *smu_virt_addr;
 152         void __iomem *stb_virt_addr;
 153         void __iomem *fch_virt_addr;
 154         bool msg_port;
 155         u32 base_addr;
 156         u32 cpu_id;
 157         u32 active_ips;
 158         u32 dram_size;
 159         u32 num_ips;
 160         u32 s2d_msg_id;
 161 /* SMU version information */
 162         u8 smu_program;
 163         u8 major;
 164         u8 minor;
 165         u8 rev;
 166         struct device *dev;
 167         struct pci_dev *rdev;
 168         struct mutex lock; /* generic mutex lock */
 169         struct dentry *dbgfs_dir;
 170 };
 171
 172 static bool enable_stb;
 173 module_param(enable_stb, bool, 0644);
 174 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 175
 176 static bool disable_workarounds;
 177 module_param(disable_workarounds, bool, 0644);
 178 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
 179
 180 static struct amd_pmc_dev pmc;
 181 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 182 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 183 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 184
 185 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 186 {
 187         return ioread32(dev->regbase + reg_offset);
 188 }
 189
 190 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 191 {
 192         iowrite32(val, dev->regbase + reg_offset);
 193 }
 194
 195 struct smu_metrics {
 196         u32 table_version;
 197         u32 hint_count;
 198         u32 s0i3_last_entry_status;
 199         u32 timein_s0i2;
 200         u64 timeentering_s0i3_lastcapture;
 201         u64 timeentering_s0i3_totaltime;
 202         u64 timeto_resume_to_os_lastcapture;
 203         u64 timeto_resume_to_os_totaltime;
 204         u64 timein_s0i3_lastcapture;
 205         u64 timein_s0i3_totaltime;
 206         u64 timein_swdrips_lastcapture;
 207         u64 timein_swdrips_totaltime;
 208         u64 timecondition_notmet_lastcapture[32];
 209         u64 timecondition_notmet_totaltime[32];
 210 } __packed;
 211
 212 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 213 {
 214         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 215         u32 size = FIFO_SIZE * sizeof(u32);
 216         u32 *buf;
 217         int rc;
 218
 219         buf = kzalloc(size, GFP_KERNEL);
 220         if (!buf)
 221                 return -ENOMEM;
 222
 223         rc = amd_pmc_read_stb(dev, buf);
 224         if (rc) {
 225                 kfree(buf);
 226                 return rc;
 227         }
 228
 229         filp->private_data = buf;
 230         return rc;
 231 }
 232
 233 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 234                                         loff_t *pos)
 235 {
 236         if (!filp->private_data)
 237                 return -EINVAL;
 238
 239         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 240                                        FIFO_SIZE * sizeof(u32));
 241 }
 242
 243 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 244 {
 245         kfree(filp->private_data);
 246         return 0;
 247 }
 248
 249 static const struct file_operations amd_pmc_stb_debugfs_fops = {
 250         .owner = THIS_MODULE,
 251         .open = amd_pmc_stb_debugfs_open,
 252         .read = amd_pmc_stb_debugfs_read,
 253         .release = amd_pmc_stb_debugfs_release,
 254 };
 255
 256 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
 257 {
 258         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 259         u32 *buf, fsize, num_samples, stb_rdptr_offset = 0;
 260         int ret;
 261
 262         /* Write dummy postcode while reading the STB buffer */
 263         ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC);
 264         if (ret)
 265                 dev_err(dev->dev, "error writing to STB: %d\n", ret);
 266
 267         buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
 268         if (!buf)
 269                 return -ENOMEM;
 270
 271         /* Spill to DRAM num_samples uses separate SMU message port */
 272         dev->msg_port = 1;
 273
 274         /* Get the num_samples to calculate the last push location */
 275         ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, true);
 276         /* Clear msg_port for other SMU operation */
 277         dev->msg_port = 0;
 278         if (ret) {
 279                 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret);
 280                 kfree(buf);
 281                 return ret;
 282         }
 283
 284         /* Start capturing data from the last push location */
 285         if (num_samples > S2D_TELEMETRY_BYTES_MAX) {
 286                 fsize  = S2D_TELEMETRY_BYTES_MAX;
 287                 stb_rdptr_offset = num_samples - fsize;
 288         } else {
 289                 fsize = num_samples;
 290                 stb_rdptr_offset = 0;
 291         }
 292
 293         memcpy_fromio(buf, dev->stb_virt_addr + stb_rdptr_offset, fsize);
 294         filp->private_data = buf;
 295
 296         return 0;
 297 }
 298
 299 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
 300                                            loff_t *pos)
 301 {
 302         if (!filp->private_data)
 303                 return -EINVAL;
 304
 305         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 306                                         S2D_TELEMETRY_BYTES_MAX);
 307 }
 308
 309 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
 310 {
 311         kfree(filp->private_data);
 312         return 0;
 313 }
 314
 315 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
 316         .owner = THIS_MODULE,
 317         .open = amd_pmc_stb_debugfs_open_v2,
 318         .read = amd_pmc_stb_debugfs_read_v2,
 319         .release = amd_pmc_stb_debugfs_release_v2,
 320 };
 321
 322 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
 323 {
 324         switch (dev->cpu_id) {
 325         case AMD_CPU_ID_PCO:
 326         case AMD_CPU_ID_RN:
 327         case AMD_CPU_ID_YC:
 328         case AMD_CPU_ID_CB:
 329                 dev->num_ips = 12;
 330                 dev->s2d_msg_id = 0xBE;
 331                 break;
 332         case AMD_CPU_ID_PS:
 333                 dev->num_ips = 21;
 334                 dev->s2d_msg_id = 0x85;
 335                 break;
 336         }
 337 }
 338
 339 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 340 {
 341         if (dev->cpu_id == AMD_CPU_ID_PCO) {
 342                 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
 343                 return -EINVAL;
 344         }
 345
 346         /* Get Active devices list from SMU */
 347         if (!dev->active_ips)
 348                 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true);
 349
 350         /* Get dram address */
 351         if (!dev->smu_virt_addr) {
 352                 u32 phys_addr_low, phys_addr_hi;
 353                 u64 smu_phys_addr;
 354
 355                 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true);
 356                 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true);
 357                 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 358
 359                 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
 360                                                   sizeof(struct smu_metrics));
 361                 if (!dev->smu_virt_addr)
 362                         return -ENOMEM;
 363         }
 364
 365         /* Start the logging */
 366         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false);
 367         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false);
 368
 369         return 0;
 370 }
 371
 372 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
 373 {
 374         if (!pdev->smu_virt_addr) {
 375                 int ret = amd_pmc_setup_smu_logging(pdev);
 376
 377                 if (ret)
 378                         return ret;
 379         }
 380
 381         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 382                 return -ENODEV;
 383         memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
 384         return 0;
 385 }
 386
 387 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
 388 {
 389         struct smu_metrics table;
 390
 391         if (get_metrics_table(pdev, &table))
 392                 return;
 393
 394         if (!table.s0i3_last_entry_status)
 395                 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
 396         pm_report_hw_sleep_time(table.s0i3_last_entry_status ?
 397                                 table.timein_s0i3_lastcapture : 0);
 398 }
 399
 400 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 401 {
 402         int rc;
 403         u32 val;
 404
 405         if (dev->cpu_id == AMD_CPU_ID_PCO)
 406                 return -ENODEV;
 407
 408         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true);
 409         if (rc)
 410                 return rc;
 411
 412         dev->smu_program = (val >> 24) & GENMASK(7, 0);
 413         dev->major = (val >> 16) & GENMASK(7, 0);
 414         dev->minor = (val >> 8) & GENMASK(7, 0);
 415         dev->rev = (val >> 0) & GENMASK(7, 0);
 416
 417         dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
 418                 dev->smu_program, dev->major, dev->minor, dev->rev);
 419
 420         return 0;
 421 }
 422
 423 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
 424                                    char *buf)
 425 {
 426         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 427
 428         if (!dev->major) {
 429                 int rc = amd_pmc_get_smu_version(dev);
 430
 431                 if (rc)
 432                         return rc;
 433         }
 434         return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
 435 }
 436
 437 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
 438                                    char *buf)
 439 {
 440         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 441
 442         if (!dev->major) {
 443                 int rc = amd_pmc_get_smu_version(dev);
 444
 445                 if (rc)
 446                         return rc;
 447         }
 448         return sysfs_emit(buf, "%u\n", dev->smu_program);
 449 }
 450
 451 static DEVICE_ATTR_RO(smu_fw_version);
 452 static DEVICE_ATTR_RO(smu_program);
 453
 454 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
 455 {
 456         struct device *dev = kobj_to_dev(kobj);
 457         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 458
 459         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 460                 return 0;
 461         return 0444;
 462 }
 463
 464 static struct attribute *pmc_attrs[] = {
 465         &dev_attr_smu_fw_version.attr,
 466         &dev_attr_smu_program.attr,
 467         NULL,
 468 };
 469
 470 static struct attribute_group pmc_attr_group = {
 471         .attrs = pmc_attrs,
 472         .is_visible = pmc_attr_is_visible,
 473 };
 474
 475 static const struct attribute_group *pmc_groups[] = {
 476         &pmc_attr_group,
 477         NULL,
 478 };
 479
 480 static int smu_fw_info_show(struct seq_file *s, void *unused)
 481 {
 482         struct amd_pmc_dev *dev = s->private;
 483         struct smu_metrics table;
 484         int idx;
 485
 486         if (get_metrics_table(dev, &table))
 487                 return -EINVAL;
 488
 489         seq_puts(s, "\n=== SMU Statistics ===\n");
 490         seq_printf(s, "Table Version: %d\n", table.table_version);
 491         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 492         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 493                    "Unknown/Fail");
 494         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 495         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 496         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 497                    table.timeto_resume_to_os_lastcapture);
 498
 499         seq_puts(s, "\n=== Active time (in us) ===\n");
 500         for (idx = 0 ; idx < dev->num_ips ; idx++) {
 501                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 502                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 503                                    table.timecondition_notmet_lastcapture[idx]);
 504         }
 505
 506         return 0;
 507 }
 508 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 509
 510 static int s0ix_stats_show(struct seq_file *s, void *unused)
 511 {
 512         struct amd_pmc_dev *dev = s->private;
 513         u64 entry_time, exit_time, residency;
 514
 515         /* Use FCH registers to get the S0ix stats */
 516         if (!dev->fch_virt_addr) {
 517                 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 518                 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 519                 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 520
 521                 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 522                 if (!dev->fch_virt_addr)
 523                         return -ENOMEM;
 524         }
 525
 526         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 527         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 528
 529         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 530         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 531
 532         /* It's in 48MHz. We need to convert it */
 533         residency = exit_time - entry_time;
 534         do_div(residency, 48);
 535
 536         seq_puts(s, "=== S0ix statistics ===\n");
 537         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 538         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 539         seq_printf(s, "Residency Time: %lld\n", residency);
 540
 541         return 0;
 542 }
 543 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 544
 545 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 546                                  struct seq_file *s)
 547 {
 548         u32 val;
 549         int rc;
 550
 551         switch (pdev->cpu_id) {
 552         case AMD_CPU_ID_CZN:
 553                 /* we haven't yet read SMU version */
 554                 if (!pdev->major) {
 555                         rc = amd_pmc_get_smu_version(pdev);
 556                         if (rc)
 557                                 return rc;
 558                 }
 559                 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
 560                         val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 561                 else
 562                         return -EINVAL;
 563                 break;
 564         case AMD_CPU_ID_YC:
 565         case AMD_CPU_ID_CB:
 566         case AMD_CPU_ID_PS:
 567                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 568                 break;
 569         default:
 570                 return -EINVAL;
 571         }
 572
 573         if (dev)
 574                 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val);
 575
 576         if (s)
 577                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 578
 579         return 0;
 580 }
 581
 582 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 583 {
 584         return amd_pmc_idlemask_read(s->private, NULL, s);
 585 }
 586 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 587
 588 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 589 {
 590         debugfs_remove_recursive(dev->dbgfs_dir);
 591 }
 592
 593 static bool amd_pmc_is_stb_supported(struct amd_pmc_dev *dev)
 594 {
 595         switch (dev->cpu_id) {
 596         case AMD_CPU_ID_YC:
 597         case AMD_CPU_ID_CB:
 598         case AMD_CPU_ID_PS:
 599                 return true;
 600         default:
 601                 return false;
 602         }
 603 }
 604
 605 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 606 {
 607         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 608         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 609                             &smu_fw_info_fops);
 610         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 611                             &s0ix_stats_fops);
 612         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 613                             &amd_pmc_idlemask_fops);
 614         /* Enable STB only when the module_param is set */
 615         if (enable_stb) {
 616                 if (amd_pmc_is_stb_supported(dev))
 617                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 618                                             &amd_pmc_stb_debugfs_fops_v2);
 619                 else
 620                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 621                                             &amd_pmc_stb_debugfs_fops);
 622         }
 623 }
 624
 625 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 626 {
 627         u32 value, message, argument, response;
 628
 629         if (dev->msg_port) {
 630                 message = AMD_S2D_REGISTER_MESSAGE;
 631                 argument = AMD_S2D_REGISTER_ARGUMENT;
 632                 response = AMD_S2D_REGISTER_RESPONSE;
 633         } else {
 634                 message = AMD_PMC_REGISTER_MESSAGE;
 635                 argument = AMD_PMC_REGISTER_ARGUMENT;
 636                 response = AMD_PMC_REGISTER_RESPONSE;
 637         }
 638
 639         value = amd_pmc_reg_read(dev, response);
 640         dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 641
 642         value = amd_pmc_reg_read(dev, argument);
 643         dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 644
 645         value = amd_pmc_reg_read(dev, message);
 646         dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 647 }
 648
 649 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 650 {
 651         int rc;
 652         u32 val, message, argument, response;
 653
 654         mutex_lock(&dev->lock);
 655
 656         if (dev->msg_port) {
 657                 message = AMD_S2D_REGISTER_MESSAGE;
 658                 argument = AMD_S2D_REGISTER_ARGUMENT;
 659                 response = AMD_S2D_REGISTER_RESPONSE;
 660         } else {
 661                 message = AMD_PMC_REGISTER_MESSAGE;
 662                 argument = AMD_PMC_REGISTER_ARGUMENT;
 663                 response = AMD_PMC_REGISTER_RESPONSE;
 664         }
 665
 666         /* Wait until we get a valid response */
 667         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 668                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 669                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 670         if (rc) {
 671                 dev_err(dev->dev, "failed to talk to SMU\n");
 672                 goto out_unlock;
 673         }
 674
 675         /* Write zero to response register */
 676         amd_pmc_reg_write(dev, response, 0);
 677
 678         /* Write argument into response register */
 679         amd_pmc_reg_write(dev, argument, arg);
 680
 681         /* Write message ID to message ID register */
 682         amd_pmc_reg_write(dev, message, msg);
 683
 684         /* Wait until we get a valid response */
 685         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 686                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 687                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 688         if (rc) {
 689                 dev_err(dev->dev, "SMU response timed out\n");
 690                 goto out_unlock;
 691         }
 692
 693         switch (val) {
 694         case AMD_PMC_RESULT_OK:
 695                 if (ret) {
 696                         /* PMFW may take longer time to return back the data */
 697                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 698                         *data = amd_pmc_reg_read(dev, argument);
 699                 }
 700                 break;
 701         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 702                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 703                 rc = -EBUSY;
 704                 goto out_unlock;
 705         case AMD_PMC_RESULT_CMD_UNKNOWN:
 706                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 707                 rc = -EINVAL;
 708                 goto out_unlock;
 709         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 710         case AMD_PMC_RESULT_FAILED:
 711         default:
 712                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 713                 rc = -EIO;
 714                 goto out_unlock;
 715         }
 716
 717 out_unlock:
 718         mutex_unlock(&dev->lock);
 719         amd_pmc_dump_registers(dev);
 720         return rc;
 721 }
 722
 723 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 724 {
 725         switch (dev->cpu_id) {
 726         case AMD_CPU_ID_PCO:
 727                 return MSG_OS_HINT_PCO;
 728         case AMD_CPU_ID_RN:
 729         case AMD_CPU_ID_YC:
 730         case AMD_CPU_ID_CB:
 731         case AMD_CPU_ID_PS:
 732                 return MSG_OS_HINT_RN;
 733         }
 734         return -EINVAL;
 735 }
 736
 737 static int amd_pmc_czn_wa_irq1(struct amd_pmc_dev *pdev)
 738 {
 739         struct device *d;
 740         int rc;
 741
 742         if (!pdev->major) {
 743                 rc = amd_pmc_get_smu_version(pdev);
 744                 if (rc)
 745                         return rc;
 746         }
 747
 748         if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
 749                 return 0;
 750
 751         d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
 752         if (!d)
 753                 return 0;
 754         if (device_may_wakeup(d)) {
 755                 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
 756                 disable_irq_wake(1);
 757                 device_set_wakeup_enable(d, false);
 758         }
 759         put_device(d);
 760
 761         return 0;
 762 }
 763
 764 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 765 {
 766         struct rtc_device *rtc_device;
 767         time64_t then, now, duration;
 768         struct rtc_wkalrm alarm;
 769         struct rtc_time tm;
 770         int rc;
 771
 772         /* we haven't yet read SMU version */
 773         if (!pdev->major) {
 774                 rc = amd_pmc_get_smu_version(pdev);
 775                 if (rc)
 776                         return rc;
 777         }
 778
 779         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 780                 return 0;
 781
 782         rtc_device = rtc_class_open("rtc0");
 783         if (!rtc_device)
 784                 return 0;
 785         rc = rtc_read_alarm(rtc_device, &alarm);
 786         if (rc)
 787                 return rc;
 788         if (!alarm.enabled) {
 789                 dev_dbg(pdev->dev, "alarm not enabled\n");
 790                 return 0;
 791         }
 792         rc = rtc_read_time(rtc_device, &tm);
 793         if (rc)
 794                 return rc;
 795         then = rtc_tm_to_time64(&alarm.time);
 796         now = rtc_tm_to_time64(&tm);
 797         duration = then-now;
 798
 799         /* in the past */
 800         if (then < now)
 801                 return 0;
 802
 803         /* will be stored in upper 16 bits of s0i3 hint argument,
 804          * so timer wakeup from s0i3 is limited to ~18 hours or less
 805          */
 806         if (duration <= 4 || duration > U16_MAX)
 807                 return -EINVAL;
 808
 809         *arg |= (duration << 16);
 810         rc = rtc_alarm_irq_enable(rtc_device, 0);
 811         pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration);
 812
 813         return rc;
 814 }
 815
 816 static void amd_pmc_s2idle_prepare(void)
 817 {
 818         struct amd_pmc_dev *pdev = &pmc;
 819         int rc;
 820         u8 msg;
 821         u32 arg = 1;
 822
 823         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 824         amd_pmc_setup_smu_logging(pdev);
 825
 826         /* Activate CZN specific platform bug workarounds */
 827         if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
 828                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 829                 if (rc) {
 830                         dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
 831                         return;
 832                 }
 833         }
 834
 835         msg = amd_pmc_get_os_hint(pdev);
 836         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false);
 837         if (rc) {
 838                 dev_err(pdev->dev, "suspend failed: %d\n", rc);
 839                 return;
 840         }
 841
 842         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
 843         if (rc)
 844                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 845 }
 846
 847 static void amd_pmc_s2idle_check(void)
 848 {
 849         struct amd_pmc_dev *pdev = &pmc;
 850         struct smu_metrics table;
 851         int rc;
 852
 853         /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
 854         if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
 855             table.s0i3_last_entry_status)
 856                 usleep_range(10000, 20000);
 857
 858         /* Dump the IdleMask before we add to the STB */
 859         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 860
 861         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
 862         if (rc)
 863                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 864 }
 865
 866 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
 867 {
 868         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 869                 return -ENODEV;
 870
 871         return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false);
 872 }
 873
 874 static void amd_pmc_s2idle_restore(void)
 875 {
 876         struct amd_pmc_dev *pdev = &pmc;
 877         int rc;
 878         u8 msg;
 879
 880         msg = amd_pmc_get_os_hint(pdev);
 881         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false);
 882         if (rc)
 883                 dev_err(pdev->dev, "resume failed: %d\n", rc);
 884
 885         /* Let SMU know that we are looking for stats */
 886         amd_pmc_dump_data(pdev);
 887
 888         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
 889         if (rc)
 890                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 891
 892         /* Notify on failed entry */
 893         amd_pmc_validate_deepest(pdev);
 894 }
 895
 896 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
 897         .prepare = amd_pmc_s2idle_prepare,
 898         .check = amd_pmc_s2idle_check,
 899         .restore = amd_pmc_s2idle_restore,
 900 };
 901
 902 static int amd_pmc_suspend_handler(struct device *dev)
 903 {
 904         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 905
 906         if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
 907                 int rc = amd_pmc_czn_wa_irq1(pdev);
 908
 909                 if (rc) {
 910                         dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
 911                         return rc;
 912                 }
 913         }
 914
 915         return 0;
 916 }
 917
 918 static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL);
 919
 920 static const struct pci_device_id pmc_pci_ids[] = {
 921         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
 922         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
 923         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 924         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 925         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 926         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 927         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 928         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
 929         { }
 930 };
 931
 932 static int amd_pmc_get_dram_size(struct amd_pmc_dev *dev)
 933 {
 934         int ret;
 935
 936         switch (dev->cpu_id) {
 937         case AMD_CPU_ID_YC:
 938                 if (!(dev->major > 90 || (dev->major == 90 && dev->minor > 39))) {
 939                         ret = -EINVAL;
 940                         goto err_dram_size;
 941                 }
 942                 break;
 943         default:
 944                 ret = -EINVAL;
 945                 goto err_dram_size;
 946         }
 947
 948         ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, true);
 949         if (ret || !dev->dram_size)
 950                 goto err_dram_size;
 951
 952         return 0;
 953
 954 err_dram_size:
 955         dev_err(dev->dev, "DRAM size command not supported for this platform\n");
 956         return ret;
 957 }
 958
 959 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
 960 {
 961         u32 phys_addr_low, phys_addr_hi;
 962         u64 stb_phys_addr;
 963         u32 size = 0;
 964         int ret;
 965
 966         /* Spill to DRAM feature uses separate SMU message port */
 967         dev->msg_port = 1;
 968
 969         /* Get num of IP blocks within the SoC */
 970         amd_pmc_get_ip_info(dev);
 971
 972         amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, true);
 973         if (size != S2D_TELEMETRY_BYTES_MAX)
 974                 return -EIO;
 975
 976         /* Get DRAM size */
 977         ret = amd_pmc_get_dram_size(dev);
 978         if (ret)
 979                 dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
 980
 981         /* Get STB DRAM address */
 982         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, true);
 983         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, true);
 984
 985         stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 986
 987         /* Clear msg_port for other SMU operation */
 988         dev->msg_port = 0;
 989
 990         dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size);
 991         if (!dev->stb_virt_addr)
 992                 return -ENOMEM;
 993
 994         return 0;
 995 }
 996
 997 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 998 {
 999         int err;
1000
1001         err = amd_smn_write(0, AMD_PMC_STB_PMI_0, data);
1002         if (err) {
1003                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n", AMD_PMC_STB_PMI_0);
1004                 return pcibios_err_to_errno(err);
1005         }
1006
1007         return 0;
1008 }
1009
1010 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
1011 {
1012         int i, err;
1013
1014         for (i = 0; i < FIFO_SIZE; i++) {
1015                 err = amd_smn_read(0, AMD_PMC_STB_PMI_0, buf++);
1016                 if (err) {
1017                         dev_err(dev->dev, "error reading data from stb: 0x%X\n", AMD_PMC_STB_PMI_0);
1018                         return pcibios_err_to_errno(err);
1019                 }
1020         }
1021
1022         return 0;
1023 }
1024
1025 static int amd_pmc_probe(struct platform_device *pdev)
1026 {
1027         struct amd_pmc_dev *dev = &pmc;
1028         struct pci_dev *rdev;
1029         u32 base_addr_lo, base_addr_hi;
1030         u64 base_addr;
1031         int err;
1032         u32 val;
1033
1034         dev->dev = &pdev->dev;
1035
1036         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
1037         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
1038                 err = -ENODEV;
1039                 goto err_pci_dev_put;
1040         }
1041
1042         dev->cpu_id = rdev->device;
1043
1044         if (dev->cpu_id == AMD_CPU_ID_SP) {
1045                 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
1046                 err = -ENODEV;
1047                 goto err_pci_dev_put;
1048         }
1049
1050         dev->rdev = rdev;
1051         err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
1052         if (err) {
1053                 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
1054                 err = pcibios_err_to_errno(err);
1055                 goto err_pci_dev_put;
1056         }
1057
1058         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
1059
1060         err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
1061         if (err) {
1062                 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
1063                 err = pcibios_err_to_errno(err);
1064                 goto err_pci_dev_put;
1065         }
1066
1067         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
1068         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
1069
1070         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
1071                                     AMD_PMC_MAPPING_SIZE);
1072         if (!dev->regbase) {
1073                 err = -ENOMEM;
1074                 goto err_pci_dev_put;
1075         }
1076
1077         mutex_init(&dev->lock);
1078
1079         if (enable_stb && amd_pmc_is_stb_supported(dev)) {
1080                 err = amd_pmc_s2d_init(dev);
1081                 if (err)
1082                         goto err_pci_dev_put;
1083         }
1084
1085         platform_set_drvdata(pdev, dev);
1086         if (IS_ENABLED(CONFIG_SUSPEND)) {
1087                 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
1088                 if (err)
1089                         dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
1090         }
1091
1092         amd_pmc_dbgfs_register(dev);
1093         pm_report_max_hw_sleep(U64_MAX);
1094         return 0;
1095
1096 err_pci_dev_put:
1097         pci_dev_put(rdev);
1098         return err;
1099 }
1100
1101 static void amd_pmc_remove(struct platform_device *pdev)
1102 {
1103         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
1104
1105         if (IS_ENABLED(CONFIG_SUSPEND))
1106                 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
1107         amd_pmc_dbgfs_unregister(dev);
1108         pci_dev_put(dev->rdev);
1109         mutex_destroy(&dev->lock);
1110 }
1111
1112 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
1113         {"AMDI0005", 0},
1114         {"AMDI0006", 0},
1115         {"AMDI0007", 0},
1116         {"AMDI0008", 0},
1117         {"AMDI0009", 0},
1118         {"AMD0004", 0},
1119         {"AMD0005", 0},
1120         { }
1121 };
1122 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
1123
1124 static struct platform_driver amd_pmc_driver = {
1125         .driver = {
1126                 .name = "amd_pmc",
1127                 .acpi_match_table = amd_pmc_acpi_ids,
1128                 .dev_groups = pmc_groups,
1129                 .pm = pm_sleep_ptr(&amd_pmc_pm),
1130         },
1131         .probe = amd_pmc_probe,
1132         .remove_new = amd_pmc_remove,
1133 };
1134 module_platform_driver(amd_pmc_driver);
1135
1136 MODULE_LICENSE("GPL v2");
1137 MODULE_DESCRIPTION("AMD PMC Driver");