drivers/pinctrl/sh-pfc/pfc-r8a77970.c

   1 /*
   2  * R8A77970 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
   6  *
   7  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
   8  *
   9  * R-Car Gen3 processor support - PFC hardware block.
  10  *
  11  * Copyright (C) 2015  Renesas Electronics Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; version 2 of the License.
  16  */
  17
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20
  21 #include "core.h"
  22 #include "sh_pfc.h"
  23
  24 #define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH
  25
  26 #define CPU_ALL_PORT(fn, sfx)                                           \
  27         PORT_GP_CFG_22(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  28         PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),                          \
  29         PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  30         PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  31         PORT_GP_CFG_6(4,  fn, sfx, CFG_FLAGS),                          \
  32         PORT_GP_CFG_15(5, fn, sfx, CFG_FLAGS)
  33 /*
  34  * F_() : just information
  35  * FM() : macro for FN_xxx / xxx_MARK
  36  */
  37
  38 /* GPSR0 */
  39 #define GPSR0_21        F_(DU_EXODDF_DU_ODDF_DISP_CDE,  IP2_23_20)
  40 #define GPSR0_20        F_(DU_EXVSYNC_DU_VSYNC,         IP2_19_16)
  41 #define GPSR0_19        F_(DU_EXHSYNC_DU_HSYNC,         IP2_15_12)
  42 #define GPSR0_18        F_(DU_DOTCLKOUT,                IP2_11_8)
  43 #define GPSR0_17        F_(DU_DB7,                      IP2_7_4)
  44 #define GPSR0_16        F_(DU_DB6,                      IP2_3_0)
  45 #define GPSR0_15        F_(DU_DB5,                      IP1_31_28)
  46 #define GPSR0_14        F_(DU_DB4,                      IP1_27_24)
  47 #define GPSR0_13        F_(DU_DB3,                      IP1_23_20)
  48 #define GPSR0_12        F_(DU_DB2,                      IP1_19_16)
  49 #define GPSR0_11        F_(DU_DG7,                      IP1_15_12)
  50 #define GPSR0_10        F_(DU_DG6,                      IP1_11_8)
  51 #define GPSR0_9         F_(DU_DG5,                      IP1_7_4)
  52 #define GPSR0_8         F_(DU_DG4,                      IP1_3_0)
  53 #define GPSR0_7         F_(DU_DG3,                      IP0_31_28)
  54 #define GPSR0_6         F_(DU_DG2,                      IP0_27_24)
  55 #define GPSR0_5         F_(DU_DR7,                      IP0_23_20)
  56 #define GPSR0_4         F_(DU_DR6,                      IP0_19_16)
  57 #define GPSR0_3         F_(DU_DR5,                      IP0_15_12)
  58 #define GPSR0_2         F_(DU_DR4,                      IP0_11_8)
  59 #define GPSR0_1         F_(DU_DR3,                      IP0_7_4)
  60 #define GPSR0_0         F_(DU_DR2,                      IP0_3_0)
  61
  62 /* GPSR1 */
  63 #define GPSR1_27        F_(DIGRF_CLKOUT,        IP8_27_24)
  64 #define GPSR1_26        F_(DIGRF_CLKIN,         IP8_23_20)
  65 #define GPSR1_25        F_(CANFD_CLK_A,         IP8_19_16)
  66 #define GPSR1_24        F_(CANFD1_RX,           IP8_15_12)
  67 #define GPSR1_23        F_(CANFD1_TX,           IP8_11_8)
  68 #define GPSR1_22        F_(CANFD0_RX_A,         IP8_7_4)
  69 #define GPSR1_21        F_(CANFD0_TX_A,         IP8_3_0)
  70 #define GPSR1_20        F_(AVB0_AVTP_CAPTURE,   IP7_31_28)
  71 #define GPSR1_19        FM(AVB0_AVTP_MATCH)
  72 #define GPSR1_18        FM(AVB0_LINK)
  73 #define GPSR1_17        FM(AVB0_PHY_INT)
  74 #define GPSR1_16        FM(AVB0_MAGIC)
  75 #define GPSR1_15        FM(AVB0_MDC)
  76 #define GPSR1_14        FM(AVB0_MDIO)
  77 #define GPSR1_13        FM(AVB0_TXCREFCLK)
  78 #define GPSR1_12        FM(AVB0_TD3)
  79 #define GPSR1_11        FM(AVB0_TD2)
  80 #define GPSR1_10        FM(AVB0_TD1)
  81 #define GPSR1_9         FM(AVB0_TD0)
  82 #define GPSR1_8         FM(AVB0_TXC)
  83 #define GPSR1_7         FM(AVB0_TX_CTL)
  84 #define GPSR1_6         FM(AVB0_RD3)
  85 #define GPSR1_5         FM(AVB0_RD2)
  86 #define GPSR1_4         FM(AVB0_RD1)
  87 #define GPSR1_3         FM(AVB0_RD0)
  88 #define GPSR1_2         FM(AVB0_RXC)
  89 #define GPSR1_1         FM(AVB0_RX_CTL)
  90 #define GPSR1_0         F_(IRQ0,                IP2_27_24)
  91
  92 /* GPSR2 */
  93 #define GPSR2_16        F_(VI0_FIELD,           IP4_31_28)
  94 #define GPSR2_15        F_(VI0_DATA11,          IP4_27_24)
  95 #define GPSR2_14        F_(VI0_DATA10,          IP4_23_20)
  96 #define GPSR2_13        F_(VI0_DATA9,           IP4_19_16)
  97 #define GPSR2_12        F_(VI0_DATA8,           IP4_15_12)
  98 #define GPSR2_11        F_(VI0_DATA7,           IP4_11_8)
  99 #define GPSR2_10        F_(VI0_DATA6,           IP4_7_4)
 100 #define GPSR2_9         F_(VI0_DATA5,           IP4_3_0)
 101 #define GPSR2_8         F_(VI0_DATA4,           IP3_31_28)
 102 #define GPSR2_7         F_(VI0_DATA3,           IP3_27_24)
 103 #define GPSR2_6         F_(VI0_DATA2,           IP3_23_20)
 104 #define GPSR2_5         F_(VI0_DATA1,           IP3_19_16)
 105 #define GPSR2_4         F_(VI0_DATA0,           IP3_15_12)
 106 #define GPSR2_3         F_(VI0_VSYNC_N,         IP3_11_8)
 107 #define GPSR2_2         F_(VI0_HSYNC_N,         IP3_7_4)
 108 #define GPSR2_1         F_(VI0_CLKENB,          IP3_3_0)
 109 #define GPSR2_0         F_(VI0_CLK,             IP2_31_28)
 110
 111 /* GPSR3 */
 112 #define GPSR3_16        F_(VI1_FIELD,           IP7_3_0)
 113 #define GPSR3_15        F_(VI1_DATA11,          IP6_31_28)
 114 #define GPSR3_14        F_(VI1_DATA10,          IP6_27_24)
 115 #define GPSR3_13        F_(VI1_DATA9,           IP6_23_20)
 116 #define GPSR3_12        F_(VI1_DATA8,           IP6_19_16)
 117 #define GPSR3_11        F_(VI1_DATA7,           IP6_15_12)
 118 #define GPSR3_10        F_(VI1_DATA6,           IP6_11_8)
 119 #define GPSR3_9         F_(VI1_DATA5,           IP6_7_4)
 120 #define GPSR3_8         F_(VI1_DATA4,           IP6_3_0)
 121 #define GPSR3_7         F_(VI1_DATA3,           IP5_31_28)
 122 #define GPSR3_6         F_(VI1_DATA2,           IP5_27_24)
 123 #define GPSR3_5         F_(VI1_DATA1,           IP5_23_20)
 124 #define GPSR3_4         F_(VI1_DATA0,           IP5_19_16)
 125 #define GPSR3_3         F_(VI1_VSYNC_N,         IP5_15_12)
 126 #define GPSR3_2         F_(VI1_HSYNC_N,         IP5_11_8)
 127 #define GPSR3_1         F_(VI1_CLKENB,          IP5_7_4)
 128 #define GPSR3_0         F_(VI1_CLK,             IP5_3_0)
 129
 130 /* GPSR4 */
 131 #define GPSR4_5         F_(SDA2,                IP7_27_24)
 132 #define GPSR4_4         F_(SCL2,                IP7_23_20)
 133 #define GPSR4_3         F_(SDA1,                IP7_19_16)
 134 #define GPSR4_2         F_(SCL1,                IP7_15_12)
 135 #define GPSR4_1         F_(SDA0,                IP7_11_8)
 136 #define GPSR4_0         F_(SCL0,                IP7_7_4)
 137
 138 /* GPSR5 */
 139 #define GPSR5_14        FM(RPC_INT_N)
 140 #define GPSR5_13        FM(RPC_WP_N)
 141 #define GPSR5_12        FM(RPC_RESET_N)
 142 #define GPSR5_11        FM(QSPI1_SSL)
 143 #define GPSR5_10        FM(QSPI1_IO3)
 144 #define GPSR5_9         FM(QSPI1_IO2)
 145 #define GPSR5_8         FM(QSPI1_MISO_IO1)
 146 #define GPSR5_7         FM(QSPI1_MOSI_IO0)
 147 #define GPSR5_6         FM(QSPI1_SPCLK)
 148 #define GPSR5_5         FM(QSPI0_SSL)
 149 #define GPSR5_4         FM(QSPI0_IO3)
 150 #define GPSR5_3         FM(QSPI0_IO2)
 151 #define GPSR5_2         FM(QSPI0_MISO_IO1)
 152 #define GPSR5_1         FM(QSPI0_MOSI_IO0)
 153 #define GPSR5_0         FM(QSPI0_SPCLK)
 154
 155
 156 /* IPSRx */             /* 0 */                         /* 1 */                 /* 2 */         /* 3 */         /* 4 */                 /* 5 */         /* 6 - F */
 157 #define IP0_3_0         FM(DU_DR2)                      FM(HSCK0)               F_(0, 0)        FM(A0)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 158 #define IP0_7_4         FM(DU_DR3)                      FM(HRTS0_N)             F_(0, 0)        FM(A1)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 159 #define IP0_11_8        FM(DU_DR4)                      FM(HCTS0_N)             F_(0, 0)        FM(A2)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 160 #define IP0_15_12       FM(DU_DR5)                      FM(HTX0)                F_(0, 0)        FM(A3)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 161 #define IP0_19_16       FM(DU_DR6)                      FM(MSIOF3_RXD)          F_(0, 0)        FM(A4)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 162 #define IP0_23_20       FM(DU_DR7)                      FM(MSIOF3_TXD)          F_(0, 0)        FM(A5)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 163 #define IP0_27_24       FM(DU_DG2)                      FM(MSIOF3_SS1)          F_(0, 0)        FM(A6)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 164 #define IP0_31_28       FM(DU_DG3)                      FM(MSIOF3_SS2)          F_(0, 0)        FM(A7)          FM(PWMFSW0)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 165 #define IP1_3_0         FM(DU_DG4)                      F_(0, 0)                F_(0, 0)        FM(A8)          FM(FSO_CFE_0_N_A)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 166 #define IP1_7_4         FM(DU_DG5)                      F_(0, 0)                F_(0, 0)        FM(A9)          FM(FSO_CFE_1_N_A)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 167 #define IP1_11_8        FM(DU_DG6)                      F_(0, 0)                F_(0, 0)        FM(A10)         FM(FSO_TOE_N_A)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 168 #define IP1_15_12       FM(DU_DG7)                      F_(0, 0)                F_(0, 0)        FM(A11)         FM(IRQ1)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 169 #define IP1_19_16       FM(DU_DB2)                      F_(0, 0)                F_(0, 0)        FM(A12)         FM(IRQ2)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 170 #define IP1_23_20       FM(DU_DB3)                      F_(0, 0)                F_(0, 0)        FM(A13)         FM(FXR_CLKOUT1)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 171 #define IP1_27_24       FM(DU_DB4)                      F_(0, 0)                F_(0, 0)        FM(A14)         FM(FXR_CLKOUT2)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 172 #define IP1_31_28       FM(DU_DB5)                      F_(0, 0)                F_(0, 0)        FM(A15)         FM(FXR_TXENA_N)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 173 #define IP2_3_0         FM(DU_DB6)                      F_(0, 0)                F_(0, 0)        FM(A16)         FM(FXR_TXENB_N)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 174 #define IP2_7_4         FM(DU_DB7)                      F_(0, 0)                F_(0, 0)        FM(A17)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 175 #define IP2_11_8        FM(DU_DOTCLKOUT)                FM(SCIF_CLK_A)          F_(0, 0)        FM(A18)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 176 #define IP2_15_12       FM(DU_EXHSYNC_DU_HSYNC)         FM(HRX0)                F_(0, 0)        FM(A19)         FM(IRQ3)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 177 #define IP2_19_16       FM(DU_EXVSYNC_DU_VSYNC)         FM(MSIOF3_SCK)          F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 178 #define IP2_23_20       FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(MSIOF3_SYNC)         F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 179 #define IP2_27_24       FM(IRQ0)                        FM(CC5_OSCOUT)          F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 180 #define IP2_31_28       FM(VI0_CLK)                     FM(MSIOF2_SCK)          FM(SCK3)        F_(0, 0)        FM(HSCK3)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 181 #define IP3_3_0         FM(VI0_CLKENB)                  FM(MSIOF2_RXD)          FM(RX3)         FM(RD_WR_N)     FM(HCTS3_N)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 182 #define IP3_7_4         FM(VI0_HSYNC_N)                 FM(MSIOF2_TXD)          FM(TX3)         F_(0, 0)        FM(HRTS3_N)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 183 #define IP3_11_8        FM(VI0_VSYNC_N)                 FM(MSIOF2_SYNC)         FM(CTS3_N)      F_(0, 0)        FM(HTX3)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 184 #define IP3_15_12       FM(VI0_DATA0)                   FM(MSIOF2_SS1)          FM(RTS3_N_TANS) F_(0, 0)        FM(HRX3)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 185 #define IP3_19_16       FM(VI0_DATA1)                   FM(MSIOF2_SS2)          FM(SCK1)        F_(0, 0)        FM(SPEEDIN_A)           F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 186 #define IP3_23_20       FM(VI0_DATA2)                   FM(AVB0_AVTP_PPS)       FM(SDA3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 187 #define IP3_27_24       FM(VI0_DATA3)                   FM(HSCK1)               FM(SCL3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 188 #define IP3_31_28       FM(VI0_DATA4)                   FM(HRTS1_N)             FM(RX1_A)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 189 #define IP4_3_0         FM(VI0_DATA5)                   FM(HCTS1_N)             FM(TX1_A)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 190 #define IP4_7_4         FM(VI0_DATA6)                   FM(HTX1)                FM(CTS1_N)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 191 #define IP4_11_8        FM(VI0_DATA7)                   FM(HRX1)                FM(RTS1_N_TANS) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 192 #define IP4_15_12       FM(VI0_DATA8)                   FM(HSCK2)               FM(PWM0_A)      FM(A22)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 193 #define IP4_19_16       FM(VI0_DATA9)                   FM(HCTS2_N)             FM(PWM1_A)      FM(A23)         FM(FSO_CFE_0_N_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 194 #define IP4_23_20       FM(VI0_DATA10)                  FM(HRTS2_N)             FM(PWM2_A)      FM(A24)         FM(FSO_CFE_1_N_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 195 #define IP4_27_24       FM(VI0_DATA11)                  FM(HTX2)                FM(PWM3_A)      FM(A25)         FM(FSO_TOE_N_B)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 196 #define IP4_31_28       FM(VI0_FIELD)                   FM(HRX2)                FM(PWM4_A)      FM(CS1_N)       FM(FSCLKST2_N_A)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 197 #define IP5_3_0         FM(VI1_CLK)                     FM(MSIOF1_RXD)          F_(0, 0)        FM(CS0_N)       F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 198 #define IP5_7_4         FM(VI1_CLKENB)                  FM(MSIOF1_TXD)          F_(0, 0)        FM(D0)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 199 #define IP5_11_8        FM(VI1_HSYNC_N)                 FM(MSIOF1_SCK)          F_(0, 0)        FM(D1)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 200 #define IP5_15_12       FM(VI1_VSYNC_N)                 FM(MSIOF1_SYNC)         F_(0, 0)        FM(D2)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 201 #define IP5_19_16       FM(VI1_DATA0)                   FM(MSIOF1_SS1)          F_(0, 0)        FM(D3)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 202 #define IP5_23_20       FM(VI1_DATA1)                   FM(MSIOF1_SS2)          F_(0, 0)        FM(D4)          FM(MMC_CMD)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 203 #define IP5_27_24       FM(VI1_DATA2)                   FM(CANFD0_TX_B)         F_(0, 0)        FM(D5)          FM(MMC_D0)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 204 #define IP5_31_28       FM(VI1_DATA3)                   FM(CANFD0_RX_B)         F_(0, 0)        FM(D6)          FM(MMC_D1)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 205 #define IP6_3_0         FM(VI1_DATA4)                   FM(CANFD_CLK_B)         F_(0, 0)        FM(D7)          FM(MMC_D2)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 206 #define IP6_7_4         FM(VI1_DATA5)                   F_(0,0)                 FM(SCK4)        FM(D8)          FM(MMC_D3)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 207 #define IP6_11_8        FM(VI1_DATA6)                   F_(0,0)                 FM(RX4)         FM(D9)          FM(MMC_CLK)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 208 #define IP6_15_12       FM(VI1_DATA7)                   F_(0,0)                 FM(TX4)         FM(D10)         FM(MMC_D4)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 209 #define IP6_19_16       FM(VI1_DATA8)                   F_(0,0)                 FM(CTS4_N)      FM(D11)         FM(MMC_D5)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 210 #define IP6_23_20       FM(VI1_DATA9)                   F_(0,0)                 FM(RTS4_N_TANS) FM(D12)         FM(MMC_D6)              FM(SCL3_B)      F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 211 #define IP6_27_24       FM(VI1_DATA10)                  F_(0,0)                 F_(0, 0)        FM(D13)         FM(MMC_D7)              FM(SDA3_B)      F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 212 #define IP6_31_28       FM(VI1_DATA11)                  FM(SCL4)                FM(IRQ4)        FM(D14)         FM(MMC_WP)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 213 #define IP7_3_0         FM(VI1_FIELD)                   FM(SDA4)                FM(IRQ5)        FM(D15)         FM(MMC_CD)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 214 #define IP7_7_4         FM(SCL0)                        FM(DU_DR0)              FM(TPU0TO0)     FM(CLKOUT)      F_(0, 0)                FM(MSIOF0_RXD)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 215 #define IP7_11_8        FM(SDA0)                        FM(DU_DR1)              FM(TPU0TO1)     FM(BS_N)        FM(SCK0)                FM(MSIOF0_TXD)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 216 #define IP7_15_12       FM(SCL1)                        FM(DU_DG0)              FM(TPU0TO2)     FM(RD_N)        FM(CTS0_N)              FM(MSIOF0_SCK)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP7_19_16       FM(SDA1)                        FM(DU_DG1)              FM(TPU0TO3)     FM(WE0_N)       FM(RTS0_N_TANS)         FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP7_23_20       FM(SCL2)                        FM(DU_DB0)              FM(TCLK1_A)     FM(WE1_N)       FM(RX0)                 FM(MSIOF0_SS1)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP7_27_24       FM(SDA2)                        FM(DU_DB1)              FM(TCLK2_A)     FM(EX_WAIT0)    FM(TX0)                 FM(MSIOF0_SS2)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP7_31_28       FM(AVB0_AVTP_CAPTURE)           F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(FSCLKST2_N_B)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP8_3_0         FM(CANFD0_TX_A)                 FM(FXR_TXDA)            FM(PWM0_B)      FM(DU_DISP)     FM(FSCLKST2_N_C)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP8_7_4         FM(CANFD0_RX_A)                 FM(RXDA_EXTFXR)         FM(PWM1_B)      FM(DU_CDE)      F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP8_11_8        FM(CANFD1_TX)                   FM(FXR_TXDB)            FM(PWM2_B)      FM(TCLK1_B)     FM(TX1_B)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP8_15_12       FM(CANFD1_RX)                   FM(RXDB_EXTFXR)         FM(PWM3_B)      FM(TCLK2_B)     FM(RX1_B)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP8_19_16       FM(CANFD_CLK_A)                 FM(CLK_EXTFXR)          FM(PWM4_B)      FM(SPEEDIN_B)   FM(SCIF_CLK_B)          F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP8_23_20       FM(DIGRF_CLKIN)                 FM(DIGRF_CLKEN_IN)      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP8_27_24       FM(DIGRF_CLKOUT)                FM(DIGRF_CLKEN_OUT)     F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP8_31_28       F_(0, 0)                        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)  F_(0, 0) F_(0, 0) F_(0, 0)
 229
 230 #define PINMUX_GPSR     \
 231 \
 232                 GPSR1_27 \
 233                 GPSR1_26 \
 234                 GPSR1_25 \
 235                 GPSR1_24 \
 236                 GPSR1_23 \
 237                 GPSR1_22 \
 238 GPSR0_21        GPSR1_21 \
 239 GPSR0_20        GPSR1_20 \
 240 GPSR0_19        GPSR1_19 \
 241 GPSR0_18        GPSR1_18 \
 242 GPSR0_17        GPSR1_17 \
 243 GPSR0_16        GPSR1_16        GPSR2_16        GPSR3_16 \
 244 GPSR0_15        GPSR1_15        GPSR2_15        GPSR3_15 \
 245 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14                        GPSR5_14 \
 246 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13                        GPSR5_13 \
 247 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12                        GPSR5_12 \
 248 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11                        GPSR5_11 \
 249 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10                        GPSR5_10 \
 250 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9                         GPSR5_9 \
 251 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8                         GPSR5_8 \
 252 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7                         GPSR5_7 \
 253 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6                         GPSR5_6 \
 254 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5 \
 255 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4 \
 256 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3 \
 257 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2 \
 258 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1 \
 259 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0
 260
 261 #define PINMUX_IPSR     \
 262 \
 263 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 264 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 265 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 266 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 267 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 268 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 269 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 270 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 271 \
 272 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 273 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 274 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 275 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
 276 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 277 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 278 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 279 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 280 \
 281 FM(IP8_3_0)     IP8_3_0 \
 282 FM(IP8_7_4)     IP8_7_4 \
 283 FM(IP8_11_8)    IP8_11_8 \
 284 FM(IP8_15_12)   IP8_15_12 \
 285 FM(IP8_19_16)   IP8_19_16 \
 286 FM(IP8_23_20)   IP8_23_20 \
 287 FM(IP8_27_24)   IP8_27_24 \
 288 FM(IP8_31_28)   IP8_31_28
 289
 290 /* MOD_SEL0 */          /* 0 */                 /* 1 */
 291 #define MOD_SEL0_11     FM(SEL_I2C3_0)          FM(SEL_I2C3_1)
 292 #define MOD_SEL0_10     FM(SEL_HSCIF0_0)        FM(SEL_HSCIF0_1)
 293 #define MOD_SEL0_9      FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 294 #define MOD_SEL0_8      FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 295 #define MOD_SEL0_7      FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 296 #define MOD_SEL0_6      FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 297 #define MOD_SEL0_5      FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 298 #define MOD_SEL0_4      FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 299 #define MOD_SEL0_3      FM(SEL_PWM0_0)          FM(SEL_PWM0_1)
 300 #define MOD_SEL0_2      FM(SEL_RFSO_0)          FM(SEL_RFSO_1)
 301 #define MOD_SEL0_1      FM(SEL_RSP_0)           FM(SEL_RSP_1)
 302 #define MOD_SEL0_0      FM(SEL_TMU_0)           FM(SEL_TMU_1)
 303
 304 #define PINMUX_MOD_SELS \
 305 \
 306 MOD_SEL0_11 \
 307 MOD_SEL0_10 \
 308 MOD_SEL0_9 \
 309 MOD_SEL0_8 \
 310 MOD_SEL0_7 \
 311 MOD_SEL0_6 \
 312 MOD_SEL0_5 \
 313 MOD_SEL0_4 \
 314 MOD_SEL0_3 \
 315 MOD_SEL0_2 \
 316 MOD_SEL0_1 \
 317 MOD_SEL0_0
 318
 319 enum {
 320         PINMUX_RESERVED = 0,
 321
 322         PINMUX_DATA_BEGIN,
 323         GP_ALL(DATA),
 324         PINMUX_DATA_END,
 325
 326 #define F_(x, y)
 327 #define FM(x)   FN_##x,
 328         PINMUX_FUNCTION_BEGIN,
 329         GP_ALL(FN),
 330         PINMUX_GPSR
 331         PINMUX_IPSR
 332         PINMUX_MOD_SELS
 333         PINMUX_FUNCTION_END,
 334 #undef F_
 335 #undef FM
 336
 337 #define F_(x, y)
 338 #define FM(x)   x##_MARK,
 339         PINMUX_MARK_BEGIN,
 340         PINMUX_GPSR
 341         PINMUX_IPSR
 342         PINMUX_MOD_SELS
 343         PINMUX_MARK_END,
 344 #undef F_
 345 #undef FM
 346 };
 347
 348 static const u16 pinmux_data[] = {
 349         PINMUX_DATA_GP_ALL(),
 350
 351         PINMUX_SINGLE(AVB0_RX_CTL),
 352         PINMUX_SINGLE(AVB0_RXC),
 353         PINMUX_SINGLE(AVB0_RD0),
 354         PINMUX_SINGLE(AVB0_RD1),
 355         PINMUX_SINGLE(AVB0_RD2),
 356         PINMUX_SINGLE(AVB0_RD3),
 357         PINMUX_SINGLE(AVB0_TX_CTL),
 358         PINMUX_SINGLE(AVB0_TXC),
 359         PINMUX_SINGLE(AVB0_TD0),
 360         PINMUX_SINGLE(AVB0_TD1),
 361         PINMUX_SINGLE(AVB0_TD2),
 362         PINMUX_SINGLE(AVB0_TD3),
 363         PINMUX_SINGLE(AVB0_TXCREFCLK),
 364         PINMUX_SINGLE(AVB0_MDIO),
 365         PINMUX_SINGLE(AVB0_MDC),
 366         PINMUX_SINGLE(AVB0_MAGIC),
 367         PINMUX_SINGLE(AVB0_PHY_INT),
 368         PINMUX_SINGLE(AVB0_LINK),
 369         PINMUX_SINGLE(AVB0_AVTP_MATCH),
 370
 371         PINMUX_SINGLE(QSPI0_SPCLK),
 372         PINMUX_SINGLE(QSPI0_MOSI_IO0),
 373         PINMUX_SINGLE(QSPI0_MISO_IO1),
 374         PINMUX_SINGLE(QSPI0_IO2),
 375         PINMUX_SINGLE(QSPI0_IO3),
 376         PINMUX_SINGLE(QSPI0_SSL),
 377         PINMUX_SINGLE(QSPI1_SPCLK),
 378         PINMUX_SINGLE(QSPI1_MOSI_IO0),
 379         PINMUX_SINGLE(QSPI1_MISO_IO1),
 380         PINMUX_SINGLE(QSPI1_IO2),
 381         PINMUX_SINGLE(QSPI1_IO3),
 382         PINMUX_SINGLE(QSPI1_SSL),
 383         PINMUX_SINGLE(RPC_RESET_N),
 384         PINMUX_SINGLE(RPC_WP_N),
 385         PINMUX_SINGLE(RPC_INT_N),
 386
 387         /* IPSR0 */
 388         PINMUX_IPSR_GPSR(IP0_3_0,       DU_DR2),
 389         PINMUX_IPSR_GPSR(IP0_3_0,       HSCK0),
 390         PINMUX_IPSR_GPSR(IP0_3_0,       A0),
 391
 392         PINMUX_IPSR_GPSR(IP0_7_4,       DU_DR3),
 393         PINMUX_IPSR_GPSR(IP0_7_4,       HRTS0_N),
 394         PINMUX_IPSR_GPSR(IP0_7_4,       A1),
 395
 396         PINMUX_IPSR_GPSR(IP0_11_8,      DU_DR4),
 397         PINMUX_IPSR_GPSR(IP0_11_8,      HCTS0_N),
 398         PINMUX_IPSR_GPSR(IP0_11_8,      A2),
 399
 400         PINMUX_IPSR_GPSR(IP0_15_12,     DU_DR5),
 401         PINMUX_IPSR_GPSR(IP0_15_12,     HTX0),
 402         PINMUX_IPSR_GPSR(IP0_15_12,     A3),
 403
 404         PINMUX_IPSR_GPSR(IP0_19_16,     DU_DR6),
 405         PINMUX_IPSR_GPSR(IP0_19_16,     MSIOF3_RXD),
 406         PINMUX_IPSR_GPSR(IP0_19_16,     A4),
 407
 408         PINMUX_IPSR_GPSR(IP0_23_20,     DU_DR7),
 409         PINMUX_IPSR_GPSR(IP0_23_20,     MSIOF3_TXD),
 410         PINMUX_IPSR_GPSR(IP0_23_20,     A5),
 411
 412         PINMUX_IPSR_GPSR(IP0_27_24,     DU_DG2),
 413         PINMUX_IPSR_GPSR(IP0_27_24,     MSIOF3_SS1),
 414         PINMUX_IPSR_GPSR(IP0_27_24,     A6),
 415
 416         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DG3),
 417         PINMUX_IPSR_GPSR(IP0_31_28,     MSIOF3_SS2),
 418         PINMUX_IPSR_GPSR(IP0_31_28,     A7),
 419         PINMUX_IPSR_GPSR(IP0_31_28,     PWMFSW0),
 420
 421         /* IPSR1 */
 422         PINMUX_IPSR_GPSR(IP1_3_0,       DU_DG4),
 423         PINMUX_IPSR_GPSR(IP1_3_0,       A8),
 424         PINMUX_IPSR_MSEL(IP1_3_0,       FSO_CFE_0_N_A,  SEL_RFSO_0),
 425
 426         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DG5),
 427         PINMUX_IPSR_GPSR(IP1_7_4,       A9),
 428         PINMUX_IPSR_MSEL(IP1_7_4,       FSO_CFE_1_N_A,  SEL_RFSO_0),
 429
 430         PINMUX_IPSR_GPSR(IP1_11_8,      DU_DG6),
 431         PINMUX_IPSR_GPSR(IP1_11_8,      A10),
 432         PINMUX_IPSR_MSEL(IP1_11_8,      FSO_TOE_N_A,    SEL_RFSO_0),
 433
 434         PINMUX_IPSR_GPSR(IP1_15_12,     DU_DG7),
 435         PINMUX_IPSR_GPSR(IP1_15_12,     A11),
 436         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ1),
 437
 438         PINMUX_IPSR_GPSR(IP1_19_16,     DU_DB2),
 439         PINMUX_IPSR_GPSR(IP1_19_16,     A12),
 440         PINMUX_IPSR_GPSR(IP1_19_16,     IRQ2),
 441
 442         PINMUX_IPSR_GPSR(IP1_23_20,     DU_DB3),
 443         PINMUX_IPSR_GPSR(IP1_23_20,     A13),
 444         PINMUX_IPSR_GPSR(IP1_23_20,     FXR_CLKOUT1),
 445
 446         PINMUX_IPSR_GPSR(IP1_27_24,     DU_DB4),
 447         PINMUX_IPSR_GPSR(IP1_27_24,     A14),
 448         PINMUX_IPSR_GPSR(IP1_27_24,     FXR_CLKOUT2),
 449
 450         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB5),
 451         PINMUX_IPSR_GPSR(IP1_31_28,     A15),
 452         PINMUX_IPSR_GPSR(IP1_31_28,     FXR_TXENA_N),
 453
 454         /* IPSR2 */
 455         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB6),
 456         PINMUX_IPSR_GPSR(IP2_3_0,       A16),
 457         PINMUX_IPSR_GPSR(IP2_3_0,       FXR_TXENB_N),
 458
 459         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB7),
 460         PINMUX_IPSR_GPSR(IP2_7_4,       A17),
 461
 462         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DOTCLKOUT),
 463         PINMUX_IPSR_MSEL(IP2_11_8,      SCIF_CLK_A,     SEL_HSCIF0_0),
 464         PINMUX_IPSR_GPSR(IP2_11_8,      A18),
 465
 466         PINMUX_IPSR_GPSR(IP2_15_12,     DU_EXHSYNC_DU_HSYNC),
 467         PINMUX_IPSR_GPSR(IP2_15_12,     HRX0),
 468         PINMUX_IPSR_GPSR(IP2_15_12,     A19),
 469         PINMUX_IPSR_GPSR(IP2_15_12,     IRQ3),
 470
 471         PINMUX_IPSR_GPSR(IP2_19_16,     DU_EXVSYNC_DU_VSYNC),
 472         PINMUX_IPSR_GPSR(IP2_19_16,     MSIOF3_SCK),
 473
 474         PINMUX_IPSR_GPSR(IP2_23_20,     DU_EXODDF_DU_ODDF_DISP_CDE),
 475         PINMUX_IPSR_GPSR(IP2_23_20,     MSIOF3_SYNC),
 476
 477         PINMUX_IPSR_GPSR(IP2_27_24,     IRQ0),
 478         PINMUX_IPSR_GPSR(IP2_27_24,     CC5_OSCOUT),
 479
 480         PINMUX_IPSR_GPSR(IP2_31_28,     VI0_CLK),
 481         PINMUX_IPSR_GPSR(IP2_31_28,     MSIOF2_SCK),
 482         PINMUX_IPSR_GPSR(IP2_31_28,     SCK3),
 483         PINMUX_IPSR_GPSR(IP2_31_28,     HSCK3),
 484
 485         /* IPSR3 */
 486         PINMUX_IPSR_GPSR(IP3_3_0,       VI0_CLKENB),
 487         PINMUX_IPSR_GPSR(IP3_3_0,       MSIOF2_RXD),
 488         PINMUX_IPSR_GPSR(IP3_3_0,       RX3),
 489         PINMUX_IPSR_GPSR(IP3_3_0,       RD_WR_N),
 490         PINMUX_IPSR_GPSR(IP3_3_0,       HCTS3_N),
 491
 492         PINMUX_IPSR_GPSR(IP3_7_4,       VI0_HSYNC_N),
 493         PINMUX_IPSR_GPSR(IP3_7_4,       MSIOF2_TXD),
 494         PINMUX_IPSR_GPSR(IP3_7_4,       TX3),
 495         PINMUX_IPSR_GPSR(IP3_7_4,       HRTS3_N),
 496
 497         PINMUX_IPSR_GPSR(IP3_11_8,      VI0_VSYNC_N),
 498         PINMUX_IPSR_GPSR(IP3_11_8,      MSIOF2_SYNC),
 499         PINMUX_IPSR_GPSR(IP3_11_8,      CTS3_N),
 500         PINMUX_IPSR_GPSR(IP3_11_8,      HTX3),
 501
 502         PINMUX_IPSR_GPSR(IP3_15_12,     VI0_DATA0),
 503         PINMUX_IPSR_GPSR(IP3_15_12,     MSIOF2_SS1),
 504         PINMUX_IPSR_GPSR(IP3_15_12,     RTS3_N_TANS),
 505         PINMUX_IPSR_GPSR(IP3_15_12,     HRX3),
 506
 507         PINMUX_IPSR_GPSR(IP3_19_16,     VI0_DATA1),
 508         PINMUX_IPSR_GPSR(IP3_19_16,     MSIOF2_SS2),
 509         PINMUX_IPSR_GPSR(IP3_19_16,     SCK1),
 510         PINMUX_IPSR_MSEL(IP3_19_16,     SPEEDIN_A,      SEL_RSP_0),
 511
 512         PINMUX_IPSR_GPSR(IP3_23_20,     VI0_DATA2),
 513         PINMUX_IPSR_GPSR(IP3_23_20,     AVB0_AVTP_PPS),
 514         PINMUX_IPSR_MSEL(IP3_23_20,     SDA3_A,         SEL_I2C3_0),
 515
 516         PINMUX_IPSR_GPSR(IP3_27_24,     VI0_DATA3),
 517         PINMUX_IPSR_GPSR(IP3_27_24,     HSCK1),
 518         PINMUX_IPSR_MSEL(IP3_27_24,     SCL3_A,         SEL_I2C3_0),
 519
 520         PINMUX_IPSR_GPSR(IP3_31_28,     VI0_DATA4),
 521         PINMUX_IPSR_GPSR(IP3_31_28,     HRTS1_N),
 522         PINMUX_IPSR_MSEL(IP3_31_28,     RX1_A,  SEL_SCIF1_0),
 523
 524         /* IPSR4 */
 525         PINMUX_IPSR_GPSR(IP4_3_0,       VI0_DATA5),
 526         PINMUX_IPSR_GPSR(IP4_3_0,       HCTS1_N),
 527         PINMUX_IPSR_MSEL(IP4_3_0,       TX1_A,  SEL_SCIF1_0),
 528
 529         PINMUX_IPSR_GPSR(IP4_7_4,       VI0_DATA6),
 530         PINMUX_IPSR_GPSR(IP4_7_4,       HTX1),
 531         PINMUX_IPSR_GPSR(IP4_7_4,       CTS1_N),
 532
 533         PINMUX_IPSR_GPSR(IP4_11_8,      VI0_DATA7),
 534         PINMUX_IPSR_GPSR(IP4_11_8,      HRX1),
 535         PINMUX_IPSR_GPSR(IP4_11_8,      RTS1_N_TANS),
 536
 537         PINMUX_IPSR_GPSR(IP4_15_12,     VI0_DATA8),
 538         PINMUX_IPSR_GPSR(IP4_15_12,     HSCK2),
 539         PINMUX_IPSR_MSEL(IP4_15_12,     PWM0_A, SEL_PWM0_0),
 540
 541         PINMUX_IPSR_GPSR(IP4_19_16,     VI0_DATA9),
 542         PINMUX_IPSR_GPSR(IP4_19_16,     HCTS2_N),
 543         PINMUX_IPSR_MSEL(IP4_19_16,     PWM1_A, SEL_PWM1_0),
 544         PINMUX_IPSR_MSEL(IP4_19_16,     FSO_CFE_0_N_B,  SEL_RFSO_1),
 545
 546         PINMUX_IPSR_GPSR(IP4_23_20,     VI0_DATA10),
 547         PINMUX_IPSR_GPSR(IP4_23_20,     HRTS2_N),
 548         PINMUX_IPSR_MSEL(IP4_23_20,     PWM2_A, SEL_PWM2_0),
 549         PINMUX_IPSR_MSEL(IP4_23_20,     FSO_CFE_1_N_B,  SEL_RFSO_1),
 550
 551         PINMUX_IPSR_GPSR(IP4_27_24,     VI0_DATA11),
 552         PINMUX_IPSR_GPSR(IP4_27_24,     HTX2),
 553         PINMUX_IPSR_MSEL(IP4_27_24,     PWM3_A, SEL_PWM3_0),
 554         PINMUX_IPSR_MSEL(IP4_27_24,     FSO_TOE_N_B,    SEL_RFSO_1),
 555
 556         PINMUX_IPSR_GPSR(IP4_31_28,     VI0_FIELD),
 557         PINMUX_IPSR_GPSR(IP4_31_28,     HRX2),
 558         PINMUX_IPSR_MSEL(IP4_31_28,     PWM4_A, SEL_PWM4_0),
 559         PINMUX_IPSR_GPSR(IP4_31_28,     CS1_N),
 560         PINMUX_IPSR_GPSR(IP4_31_28,     FSCLKST2_N_A),
 561
 562         /* IPSR5 */
 563         PINMUX_IPSR_GPSR(IP5_3_0,       VI1_CLK),
 564         PINMUX_IPSR_GPSR(IP5_3_0,       MSIOF1_RXD),
 565         PINMUX_IPSR_GPSR(IP5_3_0,       CS0_N),
 566
 567         PINMUX_IPSR_GPSR(IP5_7_4,       VI1_CLKENB),
 568         PINMUX_IPSR_GPSR(IP5_7_4,       MSIOF1_TXD),
 569         PINMUX_IPSR_GPSR(IP5_7_4,       D0),
 570
 571         PINMUX_IPSR_GPSR(IP5_11_8,      VI1_HSYNC_N),
 572         PINMUX_IPSR_GPSR(IP5_11_8,      MSIOF1_SCK),
 573         PINMUX_IPSR_GPSR(IP5_11_8,      D1),
 574
 575         PINMUX_IPSR_GPSR(IP5_15_12,     VI1_VSYNC_N),
 576         PINMUX_IPSR_GPSR(IP5_15_12,     MSIOF1_SYNC),
 577         PINMUX_IPSR_GPSR(IP5_15_12,     D2),
 578
 579         PINMUX_IPSR_GPSR(IP5_19_16,     VI1_DATA0),
 580         PINMUX_IPSR_GPSR(IP5_19_16,     MSIOF1_SS1),
 581         PINMUX_IPSR_GPSR(IP5_19_16,     D3),
 582
 583         PINMUX_IPSR_GPSR(IP5_23_20,     VI1_DATA1),
 584         PINMUX_IPSR_GPSR(IP5_23_20,     MSIOF1_SS2),
 585         PINMUX_IPSR_GPSR(IP5_23_20,     D4),
 586         PINMUX_IPSR_GPSR(IP5_23_20,     MMC_CMD),
 587
 588         PINMUX_IPSR_GPSR(IP5_27_24,     VI1_DATA2),
 589         PINMUX_IPSR_MSEL(IP5_27_24,     CANFD0_TX_B,    SEL_CANFD0_1),
 590         PINMUX_IPSR_GPSR(IP5_27_24,     D5),
 591         PINMUX_IPSR_GPSR(IP5_27_24,     MMC_D0),
 592
 593         PINMUX_IPSR_GPSR(IP5_31_28,     VI1_DATA3),
 594         PINMUX_IPSR_MSEL(IP5_31_28,     CANFD0_RX_B,    SEL_CANFD0_1),
 595         PINMUX_IPSR_GPSR(IP5_31_28,     D6),
 596         PINMUX_IPSR_GPSR(IP5_31_28,     MMC_D1),
 597
 598         /* IPSR6 */
 599         PINMUX_IPSR_GPSR(IP6_3_0,       VI1_DATA4),
 600         PINMUX_IPSR_MSEL(IP6_3_0,       CANFD_CLK_B,    SEL_CANFD0_1),
 601         PINMUX_IPSR_GPSR(IP6_3_0,       D7),
 602         PINMUX_IPSR_GPSR(IP6_3_0,       MMC_D2),
 603
 604         PINMUX_IPSR_GPSR(IP6_7_4,       VI1_DATA5),
 605         PINMUX_IPSR_GPSR(IP6_7_4,       SCK4),
 606         PINMUX_IPSR_GPSR(IP6_7_4,       D8),
 607         PINMUX_IPSR_GPSR(IP6_7_4,       MMC_D3),
 608
 609         PINMUX_IPSR_GPSR(IP6_11_8,      VI1_DATA6),
 610         PINMUX_IPSR_GPSR(IP6_11_8,      RX4),
 611         PINMUX_IPSR_GPSR(IP6_11_8,      D9),
 612         PINMUX_IPSR_GPSR(IP6_11_8,      MMC_CLK),
 613
 614         PINMUX_IPSR_GPSR(IP6_15_12,     VI1_DATA7),
 615         PINMUX_IPSR_GPSR(IP6_15_12,     TX4),
 616         PINMUX_IPSR_GPSR(IP6_15_12,     D10),
 617         PINMUX_IPSR_GPSR(IP6_15_12,     MMC_D4),
 618
 619         PINMUX_IPSR_GPSR(IP6_19_16,     VI1_DATA8),
 620         PINMUX_IPSR_GPSR(IP6_19_16,     CTS4_N),
 621         PINMUX_IPSR_GPSR(IP6_19_16,     D11),
 622         PINMUX_IPSR_GPSR(IP6_19_16,     MMC_D5),
 623
 624         PINMUX_IPSR_GPSR(IP6_23_20,     VI1_DATA9),
 625         PINMUX_IPSR_GPSR(IP6_23_20,     RTS4_N_TANS),
 626         PINMUX_IPSR_GPSR(IP6_23_20,     D12),
 627         PINMUX_IPSR_GPSR(IP6_23_20,     MMC_D6),
 628         PINMUX_IPSR_MSEL(IP6_23_20,     SCL3_B, SEL_I2C3_1),
 629
 630         PINMUX_IPSR_GPSR(IP6_27_24,     VI1_DATA10),
 631         PINMUX_IPSR_GPSR(IP6_27_24,     D13),
 632         PINMUX_IPSR_GPSR(IP6_27_24,     MMC_D7),
 633         PINMUX_IPSR_MSEL(IP6_27_24,     SDA3_B, SEL_I2C3_1),
 634
 635         PINMUX_IPSR_GPSR(IP6_31_28,     VI1_DATA11),
 636         PINMUX_IPSR_GPSR(IP6_31_28,     SCL4),
 637         PINMUX_IPSR_GPSR(IP6_31_28,     IRQ4),
 638         PINMUX_IPSR_GPSR(IP6_31_28,     D14),
 639         PINMUX_IPSR_GPSR(IP6_31_28,     MMC_WP),
 640
 641         /* IPSR7 */
 642         PINMUX_IPSR_GPSR(IP7_3_0,       VI1_FIELD),
 643         PINMUX_IPSR_GPSR(IP7_3_0,       SDA4),
 644         PINMUX_IPSR_GPSR(IP7_3_0,       IRQ5),
 645         PINMUX_IPSR_GPSR(IP7_3_0,       D15),
 646         PINMUX_IPSR_GPSR(IP7_3_0,       MMC_CD),
 647
 648         PINMUX_IPSR_GPSR(IP7_7_4,       SCL0),
 649         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR0),
 650         PINMUX_IPSR_GPSR(IP7_7_4,       TPU0TO0),
 651         PINMUX_IPSR_GPSR(IP7_7_4,       CLKOUT),
 652         PINMUX_IPSR_GPSR(IP7_7_4,       MSIOF0_RXD),
 653
 654         PINMUX_IPSR_GPSR(IP7_11_8,      SDA0),
 655         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR1),
 656         PINMUX_IPSR_GPSR(IP7_11_8,      TPU0TO1),
 657         PINMUX_IPSR_GPSR(IP7_11_8,      BS_N),
 658         PINMUX_IPSR_GPSR(IP7_11_8,      SCK0),
 659         PINMUX_IPSR_GPSR(IP7_11_8,      MSIOF0_TXD),
 660
 661         PINMUX_IPSR_GPSR(IP7_15_12,     SCL1),
 662         PINMUX_IPSR_GPSR(IP7_15_12,     DU_DG0),
 663         PINMUX_IPSR_GPSR(IP7_15_12,     TPU0TO2),
 664         PINMUX_IPSR_GPSR(IP7_15_12,     RD_N),
 665         PINMUX_IPSR_GPSR(IP7_15_12,     CTS0_N),
 666         PINMUX_IPSR_GPSR(IP7_15_12,     MSIOF0_SCK),
 667
 668         PINMUX_IPSR_GPSR(IP7_19_16,     SDA1),
 669         PINMUX_IPSR_GPSR(IP7_19_16,     DU_DG1),
 670         PINMUX_IPSR_GPSR(IP7_19_16,     TPU0TO3),
 671         PINMUX_IPSR_GPSR(IP7_19_16,     WE0_N),
 672         PINMUX_IPSR_GPSR(IP7_19_16,     RTS0_N_TANS),
 673         PINMUX_IPSR_GPSR(IP7_19_16,     MSIOF0_SYNC),
 674
 675         PINMUX_IPSR_GPSR(IP7_23_20,     SCL2),
 676         PINMUX_IPSR_GPSR(IP7_23_20,     DU_DB0),
 677         PINMUX_IPSR_MSEL(IP7_23_20,     TCLK1_A,        SEL_TMU_0),
 678         PINMUX_IPSR_GPSR(IP7_23_20,     WE1_N),
 679         PINMUX_IPSR_GPSR(IP7_23_20,     RX0),
 680         PINMUX_IPSR_GPSR(IP7_23_20,     MSIOF0_SS1),
 681
 682         PINMUX_IPSR_GPSR(IP7_27_24,     SDA2),
 683         PINMUX_IPSR_GPSR(IP7_27_24,     DU_DB1),
 684         PINMUX_IPSR_MSEL(IP7_27_24,     TCLK2_A,        SEL_TMU_0),
 685         PINMUX_IPSR_GPSR(IP7_27_24,     EX_WAIT0),
 686         PINMUX_IPSR_GPSR(IP7_27_24,     TX0),
 687         PINMUX_IPSR_GPSR(IP7_27_24,     MSIOF0_SS2),
 688
 689         PINMUX_IPSR_GPSR(IP7_31_28,     AVB0_AVTP_CAPTURE),
 690         PINMUX_IPSR_GPSR(IP7_31_28,     FSCLKST2_N_B),
 691
 692         /* IPSR8 */
 693         PINMUX_IPSR_MSEL(IP8_3_0,       CANFD0_TX_A,    SEL_CANFD0_0),
 694         PINMUX_IPSR_GPSR(IP8_3_0,       FXR_TXDA),
 695         PINMUX_IPSR_MSEL(IP8_3_0,       PWM0_B,         SEL_PWM0_1),
 696         PINMUX_IPSR_GPSR(IP8_3_0,       DU_DISP),
 697         PINMUX_IPSR_GPSR(IP8_3_0,       FSCLKST2_N_C),
 698
 699         PINMUX_IPSR_MSEL(IP8_7_4,       CANFD0_RX_A,    SEL_CANFD0_0),
 700         PINMUX_IPSR_GPSR(IP8_7_4,       RXDA_EXTFXR),
 701         PINMUX_IPSR_MSEL(IP8_7_4,       PWM1_B,         SEL_PWM1_1),
 702         PINMUX_IPSR_GPSR(IP8_7_4,       DU_CDE),
 703
 704         PINMUX_IPSR_GPSR(IP8_11_8,      CANFD1_TX),
 705         PINMUX_IPSR_GPSR(IP8_11_8,      FXR_TXDB),
 706         PINMUX_IPSR_MSEL(IP8_11_8,      PWM2_B,         SEL_PWM2_1),
 707         PINMUX_IPSR_MSEL(IP8_11_8,      TCLK1_B,        SEL_TMU_1),
 708         PINMUX_IPSR_MSEL(IP8_11_8,      TX1_B,          SEL_SCIF1_1),
 709
 710         PINMUX_IPSR_GPSR(IP8_15_12,     CANFD1_RX),
 711         PINMUX_IPSR_GPSR(IP8_15_12,     RXDB_EXTFXR),
 712         PINMUX_IPSR_MSEL(IP8_15_12,     PWM3_B,         SEL_PWM3_1),
 713         PINMUX_IPSR_MSEL(IP8_15_12,     TCLK2_B,        SEL_TMU_1),
 714         PINMUX_IPSR_MSEL(IP8_15_12,     RX1_B,          SEL_SCIF1_1),
 715
 716         PINMUX_IPSR_MSEL(IP8_19_16,     CANFD_CLK_A,    SEL_CANFD0_0),
 717         PINMUX_IPSR_GPSR(IP8_19_16,     CLK_EXTFXR),
 718         PINMUX_IPSR_MSEL(IP8_19_16,     PWM4_B,         SEL_PWM4_1),
 719         PINMUX_IPSR_MSEL(IP8_19_16,     SPEEDIN_B,      SEL_RSP_1),
 720         PINMUX_IPSR_MSEL(IP8_19_16,     SCIF_CLK_B,     SEL_HSCIF0_1),
 721
 722         PINMUX_IPSR_GPSR(IP8_23_20,     DIGRF_CLKIN),
 723         PINMUX_IPSR_GPSR(IP8_23_20,     DIGRF_CLKEN_IN),
 724
 725         PINMUX_IPSR_GPSR(IP8_27_24,     DIGRF_CLKOUT),
 726         PINMUX_IPSR_GPSR(IP8_27_24,     DIGRF_CLKEN_OUT),
 727 };
 728
 729 static const struct sh_pfc_pin pinmux_pins[] = {
 730         PINMUX_GPIO_GP_ALL(),
 731 };
 732
 733 /* - AVB0 ------------------------------------------------------------------- */
 734 static const unsigned int avb0_link_pins[] = {
 735         /* AVB0_LINK */
 736         RCAR_GP_PIN(1, 18),
 737 };
 738 static const unsigned int avb0_link_mux[] = {
 739         AVB0_LINK_MARK,
 740 };
 741 static const unsigned int avb0_magic_pins[] = {
 742         /* AVB0_MAGIC */
 743         RCAR_GP_PIN(1, 16),
 744 };
 745 static const unsigned int avb0_magic_mux[] = {
 746         AVB0_MAGIC_MARK,
 747 };
 748 static const unsigned int avb0_phy_int_pins[] = {
 749         /* AVB0_PHY_INT */
 750         RCAR_GP_PIN(1, 17),
 751 };
 752 static const unsigned int avb0_phy_int_mux[] = {
 753         AVB0_PHY_INT_MARK,
 754 };
 755 static const unsigned int avb0_mdio_pins[] = {
 756         /* AVB0_MDC, AVB0_MDIO */
 757         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
 758 };
 759 static const unsigned int avb0_mdio_mux[] = {
 760         AVB0_MDC_MARK, AVB0_MDIO_MARK,
 761 };
 762 static const unsigned int avb0_rgmii_pins[] = {
 763         /*
 764          * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
 765          * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
 766          */
 767         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
 768         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
 769         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
 770         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
 771         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
 772         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
 773 };
 774 static const unsigned int avb0_rgmii_mux[] = {
 775         AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
 776         AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
 777         AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
 778         AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
 779 };
 780 static const unsigned int avb0_txcrefclk_pins[] = {
 781         /* AVB0_TXCREFCLK */
 782         RCAR_GP_PIN(1, 13),
 783 };
 784 static const unsigned int avb0_txcrefclk_mux[] = {
 785         AVB0_TXCREFCLK_MARK,
 786 };
 787 static const unsigned int avb0_avtp_pps_pins[] = {
 788         /* AVB0_AVTP_PPS */
 789         RCAR_GP_PIN(2, 6),
 790 };
 791 static const unsigned int avb0_avtp_pps_mux[] = {
 792         AVB0_AVTP_PPS_MARK,
 793 };
 794 static const unsigned int avb0_avtp_capture_pins[] = {
 795         /* AVB0_AVTP_CAPTURE */
 796         RCAR_GP_PIN(1, 20),
 797 };
 798 static const unsigned int avb0_avtp_capture_mux[] = {
 799         AVB0_AVTP_CAPTURE_MARK,
 800 };
 801 static const unsigned int avb0_avtp_match_pins[] = {
 802         /* AVB0_AVTP_MATCH */
 803         RCAR_GP_PIN(1, 19),
 804 };
 805 static const unsigned int avb0_avtp_match_mux[] = {
 806         AVB0_AVTP_MATCH_MARK,
 807 };
 808
 809 /* - CANFD Clock ------------------------------------------------------------ */
 810 static const unsigned int canfd_clk_a_pins[] = {
 811         /* CANFD_CLK */
 812         RCAR_GP_PIN(1, 25),
 813 };
 814 static const unsigned int canfd_clk_a_mux[] = {
 815         CANFD_CLK_A_MARK,
 816 };
 817 static const unsigned int canfd_clk_b_pins[] = {
 818         /* CANFD_CLK */
 819         RCAR_GP_PIN(3, 8),
 820 };
 821 static const unsigned int canfd_clk_b_mux[] = {
 822         CANFD_CLK_B_MARK,
 823 };
 824
 825 /* - CANFD0 ----------------------------------------------------------------- */
 826 static const unsigned int canfd0_data_a_pins[] = {
 827         /* TX, RX */
 828         RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
 829 };
 830 static const unsigned int canfd0_data_a_mux[] = {
 831         CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
 832 };
 833 static const unsigned int canfd0_data_b_pins[] = {
 834         /* TX, RX */
 835         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 836 };
 837 static const unsigned int canfd0_data_b_mux[] = {
 838         CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
 839 };
 840
 841 /* - CANFD1 ----------------------------------------------------------------- */
 842 static const unsigned int canfd1_data_pins[] = {
 843         /* TX, RX */
 844         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
 845 };
 846 static const unsigned int canfd1_data_mux[] = {
 847         CANFD1_TX_MARK, CANFD1_RX_MARK,
 848 };
 849
 850 /* - DU --------------------------------------------------------------------- */
 851 static const unsigned int du_rgb666_pins[] = {
 852         /* R[7:2], G[7:2], B[7:2] */
 853         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
 854         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 855         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
 856         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
 857         RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
 858         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
 859 };
 860 static const unsigned int du_rgb666_mux[] = {
 861         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
 862         DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
 863         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
 864         DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
 865         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
 866         DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
 867 };
 868 static const unsigned int du_clk_out_pins[] = {
 869         /* DOTCLKOUT */
 870         RCAR_GP_PIN(0, 18),
 871 };
 872 static const unsigned int du_clk_out_mux[] = {
 873         DU_DOTCLKOUT_MARK,
 874 };
 875 static const unsigned int du_sync_pins[] = {
 876         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 877         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 878 };
 879 static const unsigned int du_sync_mux[] = {
 880         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
 881 };
 882 static const unsigned int du_oddf_pins[] = {
 883         /* EXODDF/ODDF/DISP/CDE */
 884         RCAR_GP_PIN(0, 21),
 885 };
 886 static const unsigned int du_oddf_mux[] = {
 887         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
 888 };
 889 static const unsigned int du_cde_pins[] = {
 890         /* CDE */
 891         RCAR_GP_PIN(1, 22),
 892 };
 893 static const unsigned int du_cde_mux[] = {
 894         DU_CDE_MARK,
 895 };
 896 static const unsigned int du_disp_pins[] = {
 897         /* DISP */
 898         RCAR_GP_PIN(1, 21),
 899 };
 900 static const unsigned int du_disp_mux[] = {
 901         DU_DISP_MARK,
 902 };
 903
 904 /* - HSCIF0 ----------------------------------------------------------------- */
 905 static const unsigned int hscif0_data_pins[] = {
 906         /* HRX, HTX */
 907         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
 908 };
 909 static const unsigned int hscif0_data_mux[] = {
 910         HRX0_MARK, HTX0_MARK,
 911 };
 912 static const unsigned int hscif0_clk_pins[] = {
 913         /* HSCK */
 914         RCAR_GP_PIN(0, 0),
 915 };
 916 static const unsigned int hscif0_clk_mux[] = {
 917         HSCK0_MARK,
 918 };
 919 static const unsigned int hscif0_ctrl_pins[] = {
 920         /* HRTS#, HCTS# */
 921         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
 922 };
 923 static const unsigned int hscif0_ctrl_mux[] = {
 924         HRTS0_N_MARK, HCTS0_N_MARK,
 925 };
 926
 927 /* - HSCIF1 ----------------------------------------------------------------- */
 928 static const unsigned int hscif1_data_pins[] = {
 929         /* HRX, HTX */
 930         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
 931 };
 932 static const unsigned int hscif1_data_mux[] = {
 933         HRX1_MARK, HTX1_MARK,
 934 };
 935 static const unsigned int hscif1_clk_pins[] = {
 936         /* HSCK */
 937         RCAR_GP_PIN(2, 7),
 938 };
 939 static const unsigned int hscif1_clk_mux[] = {
 940         HSCK1_MARK,
 941 };
 942 static const unsigned int hscif1_ctrl_pins[] = {
 943         /* HRTS#, HCTS# */
 944         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
 945 };
 946 static const unsigned int hscif1_ctrl_mux[] = {
 947         HRTS1_N_MARK, HCTS1_N_MARK,
 948 };
 949
 950 /* - HSCIF2 ----------------------------------------------------------------- */
 951 static const unsigned int hscif2_data_pins[] = {
 952         /* HRX, HTX */
 953         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
 954 };
 955 static const unsigned int hscif2_data_mux[] = {
 956         HRX2_MARK, HTX2_MARK,
 957 };
 958 static const unsigned int hscif2_clk_pins[] = {
 959         /* HSCK */
 960         RCAR_GP_PIN(2, 12),
 961 };
 962 static const unsigned int hscif2_clk_mux[] = {
 963         HSCK2_MARK,
 964 };
 965 static const unsigned int hscif2_ctrl_pins[] = {
 966         /* HRTS#, HCTS# */
 967         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
 968 };
 969 static const unsigned int hscif2_ctrl_mux[] = {
 970         HRTS2_N_MARK, HCTS2_N_MARK,
 971 };
 972
 973 /* - HSCIF3 ----------------------------------------------------------------- */
 974 static const unsigned int hscif3_data_pins[] = {
 975         /* HRX, HTX */
 976         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
 977 };
 978 static const unsigned int hscif3_data_mux[] = {
 979         HRX3_MARK, HTX3_MARK,
 980 };
 981 static const unsigned int hscif3_clk_pins[] = {
 982         /* HSCK */
 983         RCAR_GP_PIN(2, 0),
 984 };
 985 static const unsigned int hscif3_clk_mux[] = {
 986         HSCK3_MARK,
 987 };
 988 static const unsigned int hscif3_ctrl_pins[] = {
 989         /* HRTS#, HCTS# */
 990         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
 991 };
 992 static const unsigned int hscif3_ctrl_mux[] = {
 993         HRTS3_N_MARK, HCTS3_N_MARK,
 994 };
 995
 996 /* - I2C0 ------------------------------------------------------------------- */
 997 static const unsigned int i2c0_pins[] = {
 998         /* SDA, SCL */
 999         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1000 };
1001 static const unsigned int i2c0_mux[] = {
1002         SDA0_MARK, SCL0_MARK,
1003 };
1004
1005 /* - I2C1 ------------------------------------------------------------------- */
1006 static const unsigned int i2c1_pins[] = {
1007         /* SDA, SCL */
1008         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1009 };
1010 static const unsigned int i2c1_mux[] = {
1011         SDA1_MARK, SCL1_MARK,
1012 };
1013
1014 /* - I2C2 ------------------------------------------------------------------- */
1015 static const unsigned int i2c2_pins[] = {
1016         /* SDA, SCL */
1017         RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1018 };
1019 static const unsigned int i2c2_mux[] = {
1020         SDA2_MARK, SCL2_MARK,
1021 };
1022
1023 /* - I2C3 ------------------------------------------------------------------- */
1024 static const unsigned int i2c3_a_pins[] = {
1025         /* SDA, SCL */
1026         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1027 };
1028 static const unsigned int i2c3_a_mux[] = {
1029         SDA3_A_MARK, SCL3_A_MARK,
1030 };
1031 static const unsigned int i2c3_b_pins[] = {
1032         /* SDA, SCL */
1033         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1034 };
1035 static const unsigned int i2c3_b_mux[] = {
1036         SDA3_B_MARK, SCL3_B_MARK,
1037 };
1038
1039 /* - I2C4 ------------------------------------------------------------------- */
1040 static const unsigned int i2c4_pins[] = {
1041         /* SDA, SCL */
1042         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1043 };
1044 static const unsigned int i2c4_mux[] = {
1045         SDA4_MARK, SCL4_MARK,
1046 };
1047
1048 /* - INTC-EX ---------------------------------------------------------------- */
1049 static const unsigned int intc_ex_irq0_pins[] = {
1050         /* IRQ0 */
1051         RCAR_GP_PIN(1, 0),
1052 };
1053 static const unsigned int intc_ex_irq0_mux[] = {
1054         IRQ0_MARK,
1055 };
1056 static const unsigned int intc_ex_irq1_pins[] = {
1057         /* IRQ1 */
1058         RCAR_GP_PIN(0, 11),
1059 };
1060 static const unsigned int intc_ex_irq1_mux[] = {
1061         IRQ1_MARK,
1062 };
1063 static const unsigned int intc_ex_irq2_pins[] = {
1064         /* IRQ2 */
1065         RCAR_GP_PIN(0, 12),
1066 };
1067 static const unsigned int intc_ex_irq2_mux[] = {
1068         IRQ2_MARK,
1069 };
1070 static const unsigned int intc_ex_irq3_pins[] = {
1071         /* IRQ3 */
1072         RCAR_GP_PIN(0, 19),
1073 };
1074 static const unsigned int intc_ex_irq3_mux[] = {
1075         IRQ3_MARK,
1076 };
1077 static const unsigned int intc_ex_irq4_pins[] = {
1078         /* IRQ4 */
1079         RCAR_GP_PIN(3, 15),
1080 };
1081 static const unsigned int intc_ex_irq4_mux[] = {
1082         IRQ4_MARK,
1083 };
1084 static const unsigned int intc_ex_irq5_pins[] = {
1085         /* IRQ5 */
1086         RCAR_GP_PIN(3, 16),
1087 };
1088 static const unsigned int intc_ex_irq5_mux[] = {
1089         IRQ5_MARK,
1090 };
1091
1092 /* - MMC -------------------------------------------------------------------- */
1093 static const unsigned int mmc_data1_pins[] = {
1094         /* D0 */
1095         RCAR_GP_PIN(3, 6),
1096 };
1097 static const unsigned int mmc_data1_mux[] = {
1098         MMC_D0_MARK,
1099 };
1100 static const unsigned int mmc_data4_pins[] = {
1101         /* D[0:3] */
1102         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1103         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1104 };
1105 static const unsigned int mmc_data4_mux[] = {
1106         MMC_D0_MARK, MMC_D1_MARK,
1107         MMC_D2_MARK, MMC_D3_MARK,
1108 };
1109 static const unsigned int mmc_data8_pins[] = {
1110         /* D[0:7] */
1111         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1112         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1113         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1114         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1115 };
1116 static const unsigned int mmc_data8_mux[] = {
1117         MMC_D0_MARK, MMC_D1_MARK,
1118         MMC_D2_MARK, MMC_D3_MARK,
1119         MMC_D4_MARK, MMC_D5_MARK,
1120         MMC_D6_MARK, MMC_D7_MARK,
1121 };
1122 static const unsigned int mmc_ctrl_pins[] = {
1123         /* CLK, CMD */
1124         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1125 };
1126 static const unsigned int mmc_ctrl_mux[] = {
1127         MMC_CLK_MARK, MMC_CMD_MARK,
1128 };
1129 static const unsigned int mmc_cd_pins[] = {
1130         /* CD */
1131         RCAR_GP_PIN(3, 16),
1132 };
1133 static const unsigned int mmc_cd_mux[] = {
1134         MMC_CD_MARK,
1135 };
1136 static const unsigned int mmc_wp_pins[] = {
1137         /* WP */
1138         RCAR_GP_PIN(3, 15),
1139 };
1140 static const unsigned int mmc_wp_mux[] = {
1141         MMC_WP_MARK,
1142 };
1143
1144 /* - MSIOF0 ----------------------------------------------------------------- */
1145 static const unsigned int msiof0_clk_pins[] = {
1146         /* SCK */
1147         RCAR_GP_PIN(4, 2),
1148 };
1149 static const unsigned int msiof0_clk_mux[] = {
1150         MSIOF0_SCK_MARK,
1151 };
1152 static const unsigned int msiof0_sync_pins[] = {
1153         /* SYNC */
1154         RCAR_GP_PIN(4, 3),
1155 };
1156 static const unsigned int msiof0_sync_mux[] = {
1157         MSIOF0_SYNC_MARK,
1158 };
1159 static const unsigned int msiof0_ss1_pins[] = {
1160         /* SS1 */
1161         RCAR_GP_PIN(4, 4),
1162 };
1163 static const unsigned int msiof0_ss1_mux[] = {
1164         MSIOF0_SS1_MARK,
1165 };
1166 static const unsigned int msiof0_ss2_pins[] = {
1167         /* SS2 */
1168         RCAR_GP_PIN(4, 5),
1169 };
1170 static const unsigned int msiof0_ss2_mux[] = {
1171         MSIOF0_SS2_MARK,
1172 };
1173 static const unsigned int msiof0_txd_pins[] = {
1174         /* TXD */
1175         RCAR_GP_PIN(4, 1),
1176 };
1177 static const unsigned int msiof0_txd_mux[] = {
1178         MSIOF0_TXD_MARK,
1179 };
1180 static const unsigned int msiof0_rxd_pins[] = {
1181         /* RXD */
1182         RCAR_GP_PIN(4, 0),
1183 };
1184 static const unsigned int msiof0_rxd_mux[] = {
1185         MSIOF0_RXD_MARK,
1186 };
1187
1188 /* - MSIOF1 ----------------------------------------------------------------- */
1189 static const unsigned int msiof1_clk_pins[] = {
1190         /* SCK */
1191         RCAR_GP_PIN(3, 2),
1192 };
1193 static const unsigned int msiof1_clk_mux[] = {
1194         MSIOF1_SCK_MARK,
1195 };
1196 static const unsigned int msiof1_sync_pins[] = {
1197         /* SYNC */
1198         RCAR_GP_PIN(3, 3),
1199 };
1200 static const unsigned int msiof1_sync_mux[] = {
1201         MSIOF1_SYNC_MARK,
1202 };
1203 static const unsigned int msiof1_ss1_pins[] = {
1204         /* SS1 */
1205         RCAR_GP_PIN(3, 4),
1206 };
1207 static const unsigned int msiof1_ss1_mux[] = {
1208         MSIOF1_SS1_MARK,
1209 };
1210 static const unsigned int msiof1_ss2_pins[] = {
1211         /* SS2 */
1212         RCAR_GP_PIN(3, 5),
1213 };
1214 static const unsigned int msiof1_ss2_mux[] = {
1215         MSIOF1_SS2_MARK,
1216 };
1217 static const unsigned int msiof1_txd_pins[] = {
1218         /* TXD */
1219         RCAR_GP_PIN(3, 1),
1220 };
1221 static const unsigned int msiof1_txd_mux[] = {
1222         MSIOF1_TXD_MARK,
1223 };
1224 static const unsigned int msiof1_rxd_pins[] = {
1225         /* RXD */
1226         RCAR_GP_PIN(3, 0),
1227 };
1228 static const unsigned int msiof1_rxd_mux[] = {
1229         MSIOF1_RXD_MARK,
1230 };
1231
1232 /* - MSIOF2 ----------------------------------------------------------------- */
1233 static const unsigned int msiof2_clk_pins[] = {
1234         /* SCK */
1235         RCAR_GP_PIN(2, 0),
1236 };
1237 static const unsigned int msiof2_clk_mux[] = {
1238         MSIOF2_SCK_MARK,
1239 };
1240 static const unsigned int msiof2_sync_pins[] = {
1241         /* SYNC */
1242         RCAR_GP_PIN(2, 3),
1243 };
1244 static const unsigned int msiof2_sync_mux[] = {
1245         MSIOF2_SYNC_MARK,
1246 };
1247 static const unsigned int msiof2_ss1_pins[] = {
1248         /* SS1 */
1249         RCAR_GP_PIN(2, 4),
1250 };
1251 static const unsigned int msiof2_ss1_mux[] = {
1252         MSIOF2_SS1_MARK,
1253 };
1254 static const unsigned int msiof2_ss2_pins[] = {
1255         /* SS2 */
1256         RCAR_GP_PIN(2, 5),
1257 };
1258 static const unsigned int msiof2_ss2_mux[] = {
1259         MSIOF2_SS2_MARK,
1260 };
1261 static const unsigned int msiof2_txd_pins[] = {
1262         /* TXD */
1263         RCAR_GP_PIN(2, 2),
1264 };
1265 static const unsigned int msiof2_txd_mux[] = {
1266         MSIOF2_TXD_MARK,
1267 };
1268 static const unsigned int msiof2_rxd_pins[] = {
1269         /* RXD */
1270         RCAR_GP_PIN(2, 1),
1271 };
1272 static const unsigned int msiof2_rxd_mux[] = {
1273         MSIOF2_RXD_MARK,
1274 };
1275
1276 /* - MSIOF3 ----------------------------------------------------------------- */
1277 static const unsigned int msiof3_clk_pins[] = {
1278         /* SCK */
1279         RCAR_GP_PIN(0, 20),
1280 };
1281 static const unsigned int msiof3_clk_mux[] = {
1282         MSIOF3_SCK_MARK,
1283 };
1284 static const unsigned int msiof3_sync_pins[] = {
1285         /* SYNC */
1286         RCAR_GP_PIN(0, 21),
1287 };
1288 static const unsigned int msiof3_sync_mux[] = {
1289         MSIOF3_SYNC_MARK,
1290 };
1291 static const unsigned int msiof3_ss1_pins[] = {
1292         /* SS1 */
1293         RCAR_GP_PIN(0, 6),
1294 };
1295 static const unsigned int msiof3_ss1_mux[] = {
1296         MSIOF3_SS1_MARK,
1297 };
1298 static const unsigned int msiof3_ss2_pins[] = {
1299         /* SS2 */
1300         RCAR_GP_PIN(0, 7),
1301 };
1302 static const unsigned int msiof3_ss2_mux[] = {
1303         MSIOF3_SS2_MARK,
1304 };
1305 static const unsigned int msiof3_txd_pins[] = {
1306         /* TXD */
1307         RCAR_GP_PIN(0, 5),
1308 };
1309 static const unsigned int msiof3_txd_mux[] = {
1310         MSIOF3_TXD_MARK,
1311 };
1312 static const unsigned int msiof3_rxd_pins[] = {
1313         /* RXD */
1314         RCAR_GP_PIN(0, 4),
1315 };
1316 static const unsigned int msiof3_rxd_mux[] = {
1317         MSIOF3_RXD_MARK,
1318 };
1319
1320 /* - PWM0 ------------------------------------------------------------------- */
1321 static const unsigned int pwm0_a_pins[] = {
1322         RCAR_GP_PIN(2, 12),
1323 };
1324 static const unsigned int pwm0_a_mux[] = {
1325         PWM0_A_MARK,
1326 };
1327 static const unsigned int pwm0_b_pins[] = {
1328         RCAR_GP_PIN(1, 21),
1329 };
1330 static const unsigned int pwm0_b_mux[] = {
1331         PWM0_B_MARK,
1332 };
1333
1334 /* - PWM1 ------------------------------------------------------------------- */
1335 static const unsigned int pwm1_a_pins[] = {
1336         RCAR_GP_PIN(2, 13),
1337 };
1338 static const unsigned int pwm1_a_mux[] = {
1339         PWM1_A_MARK,
1340 };
1341 static const unsigned int pwm1_b_pins[] = {
1342         RCAR_GP_PIN(1, 22),
1343 };
1344 static const unsigned int pwm1_b_mux[] = {
1345         PWM1_B_MARK,
1346 };
1347
1348 /* - PWM2 ------------------------------------------------------------------- */
1349 static const unsigned int pwm2_a_pins[] = {
1350         RCAR_GP_PIN(2, 14),
1351 };
1352 static const unsigned int pwm2_a_mux[] = {
1353         PWM2_A_MARK,
1354 };
1355 static const unsigned int pwm2_b_pins[] = {
1356         RCAR_GP_PIN(1, 23),
1357 };
1358 static const unsigned int pwm2_b_mux[] = {
1359         PWM2_B_MARK,
1360 };
1361
1362 /* - PWM3 ------------------------------------------------------------------- */
1363 static const unsigned int pwm3_a_pins[] = {
1364         RCAR_GP_PIN(2, 15),
1365 };
1366 static const unsigned int pwm3_a_mux[] = {
1367         PWM3_A_MARK,
1368 };
1369 static const unsigned int pwm3_b_pins[] = {
1370         RCAR_GP_PIN(1, 24),
1371 };
1372 static const unsigned int pwm3_b_mux[] = {
1373         PWM3_B_MARK,
1374 };
1375
1376 /* - PWM4 ------------------------------------------------------------------- */
1377 static const unsigned int pwm4_a_pins[] = {
1378         RCAR_GP_PIN(2, 16),
1379 };
1380 static const unsigned int pwm4_a_mux[] = {
1381         PWM4_A_MARK,
1382 };
1383 static const unsigned int pwm4_b_pins[] = {
1384         RCAR_GP_PIN(1, 25),
1385 };
1386 static const unsigned int pwm4_b_mux[] = {
1387         PWM4_B_MARK,
1388 };
1389
1390 /* - SCIF Clock ------------------------------------------------------------- */
1391 static const unsigned int scif_clk_a_pins[] = {
1392         /* SCIF_CLK */
1393         RCAR_GP_PIN(0, 18),
1394 };
1395 static const unsigned int scif_clk_a_mux[] = {
1396         SCIF_CLK_A_MARK,
1397 };
1398 static const unsigned int scif_clk_b_pins[] = {
1399         /* SCIF_CLK */
1400         RCAR_GP_PIN(1, 25),
1401 };
1402 static const unsigned int scif_clk_b_mux[] = {
1403         SCIF_CLK_B_MARK,
1404 };
1405
1406 /* - SCIF0 ------------------------------------------------------------------ */
1407 static const unsigned int scif0_data_pins[] = {
1408         /* RX, TX */
1409         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1410 };
1411 static const unsigned int scif0_data_mux[] = {
1412         RX0_MARK, TX0_MARK,
1413 };
1414 static const unsigned int scif0_clk_pins[] = {
1415         /* SCK */
1416         RCAR_GP_PIN(4, 1),
1417 };
1418 static const unsigned int scif0_clk_mux[] = {
1419         SCK0_MARK,
1420 };
1421 static const unsigned int scif0_ctrl_pins[] = {
1422         /* RTS#, CTS# */
1423         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1424 };
1425 static const unsigned int scif0_ctrl_mux[] = {
1426         RTS0_N_TANS_MARK, CTS0_N_MARK,
1427 };
1428
1429 /* - SCIF1 ------------------------------------------------------------------ */
1430 static const unsigned int scif1_data_a_pins[] = {
1431         /* RX, TX */
1432         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1433 };
1434 static const unsigned int scif1_data_a_mux[] = {
1435         RX1_A_MARK, TX1_A_MARK,
1436 };
1437 static const unsigned int scif1_clk_pins[] = {
1438         /* SCK */
1439         RCAR_GP_PIN(2, 5),
1440 };
1441 static const unsigned int scif1_clk_mux[] = {
1442         SCK1_MARK,
1443 };
1444 static const unsigned int scif1_ctrl_pins[] = {
1445         /* RTS#, CTS# */
1446         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1447 };
1448 static const unsigned int scif1_ctrl_mux[] = {
1449         RTS1_N_TANS_MARK, CTS1_N_MARK,
1450 };
1451 static const unsigned int scif1_data_b_pins[] = {
1452         /* RX, TX */
1453         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1454 };
1455 static const unsigned int scif1_data_b_mux[] = {
1456         RX1_B_MARK, TX1_B_MARK,
1457 };
1458
1459 /* - SCIF3 ------------------------------------------------------------------ */
1460 static const unsigned int scif3_data_pins[] = {
1461         /* RX, TX */
1462         RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1463 };
1464 static const unsigned int scif3_data_mux[] = {
1465         RX3_MARK, TX3_MARK,
1466 };
1467 static const unsigned int scif3_clk_pins[] = {
1468         /* SCK */
1469         RCAR_GP_PIN(2, 0),
1470 };
1471 static const unsigned int scif3_clk_mux[] = {
1472         SCK3_MARK,
1473 };
1474 static const unsigned int scif3_ctrl_pins[] = {
1475         /* RTS#, CTS# */
1476         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1477 };
1478 static const unsigned int scif3_ctrl_mux[] = {
1479         RTS3_N_TANS_MARK, CTS3_N_MARK,
1480 };
1481
1482 /* - SCIF4 ------------------------------------------------------------------ */
1483 static const unsigned int scif4_data_pins[] = {
1484         /* RX, TX */
1485         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1486 };
1487 static const unsigned int scif4_data_mux[] = {
1488         RX4_MARK, TX4_MARK,
1489 };
1490 static const unsigned int scif4_clk_pins[] = {
1491         /* SCK */
1492         RCAR_GP_PIN(3, 9),
1493 };
1494 static const unsigned int scif4_clk_mux[] = {
1495         SCK4_MARK,
1496 };
1497 static const unsigned int scif4_ctrl_pins[] = {
1498         /* RTS#, CTS# */
1499         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1500 };
1501 static const unsigned int scif4_ctrl_mux[] = {
1502         RTS4_N_TANS_MARK, CTS4_N_MARK,
1503 };
1504
1505 /* - TMU -------------------------------------------------------------------- */
1506 static const unsigned int tmu_tclk1_a_pins[] = {
1507         /* TCLK1 */
1508         RCAR_GP_PIN(4, 4),
1509 };
1510 static const unsigned int tmu_tclk1_a_mux[] = {
1511         TCLK1_A_MARK,
1512 };
1513 static const unsigned int tmu_tclk1_b_pins[] = {
1514         /* TCLK1 */
1515         RCAR_GP_PIN(1, 23),
1516 };
1517 static const unsigned int tmu_tclk1_b_mux[] = {
1518         TCLK1_B_MARK,
1519 };
1520 static const unsigned int tmu_tclk2_a_pins[] = {
1521         /* TCLK2 */
1522         RCAR_GP_PIN(4, 5),
1523 };
1524 static const unsigned int tmu_tclk2_a_mux[] = {
1525         TCLK2_A_MARK,
1526 };
1527 static const unsigned int tmu_tclk2_b_pins[] = {
1528         /* TCLK2 */
1529         RCAR_GP_PIN(1, 24),
1530 };
1531 static const unsigned int tmu_tclk2_b_mux[] = {
1532         TCLK2_B_MARK,
1533 };
1534
1535 /* - VIN0 ------------------------------------------------------------------- */
1536 static const unsigned int vin0_data8_pins[] = {
1537         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1538         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1539         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1540         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1541 };
1542 static const unsigned int vin0_data8_mux[] = {
1543         VI0_DATA0_MARK, VI0_DATA1_MARK,
1544         VI0_DATA2_MARK, VI0_DATA3_MARK,
1545         VI0_DATA4_MARK, VI0_DATA5_MARK,
1546         VI0_DATA6_MARK, VI0_DATA7_MARK,
1547 };
1548 static const unsigned int vin0_data10_pins[] = {
1549         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1550         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1551         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1552         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1553         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1554 };
1555 static const unsigned int vin0_data10_mux[] = {
1556         VI0_DATA0_MARK, VI0_DATA1_MARK,
1557         VI0_DATA2_MARK, VI0_DATA3_MARK,
1558         VI0_DATA4_MARK, VI0_DATA5_MARK,
1559         VI0_DATA6_MARK, VI0_DATA7_MARK,
1560         VI0_DATA8_MARK,  VI0_DATA9_MARK,
1561 };
1562 static const unsigned int vin0_data12_pins[] = {
1563         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1564         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1565         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1566         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1567         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1568         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1569 };
1570 static const unsigned int vin0_data12_mux[] = {
1571         VI0_DATA0_MARK, VI0_DATA1_MARK,
1572         VI0_DATA2_MARK, VI0_DATA3_MARK,
1573         VI0_DATA4_MARK, VI0_DATA5_MARK,
1574         VI0_DATA6_MARK, VI0_DATA7_MARK,
1575         VI0_DATA8_MARK,  VI0_DATA9_MARK,
1576         VI0_DATA10_MARK, VI0_DATA11_MARK,
1577 };
1578 static const unsigned int vin0_sync_pins[] = {
1579         /* HSYNC#, VSYNC# */
1580         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1581 };
1582 static const unsigned int vin0_sync_mux[] = {
1583         VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1584 };
1585 static const unsigned int vin0_field_pins[] = {
1586         /* FIELD */
1587         RCAR_GP_PIN(2, 16),
1588 };
1589 static const unsigned int vin0_field_mux[] = {
1590         VI0_FIELD_MARK,
1591 };
1592 static const unsigned int vin0_clkenb_pins[] = {
1593         /* CLKENB */
1594         RCAR_GP_PIN(2, 1),
1595 };
1596 static const unsigned int vin0_clkenb_mux[] = {
1597         VI0_CLKENB_MARK,
1598 };
1599 static const unsigned int vin0_clk_pins[] = {
1600         /* CLK */
1601         RCAR_GP_PIN(2, 0),
1602 };
1603 static const unsigned int vin0_clk_mux[] = {
1604         VI0_CLK_MARK,
1605 };
1606
1607 /* - VIN1 ------------------------------------------------------------------- */
1608 static const unsigned int vin1_data8_pins[] = {
1609         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1610         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1611         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1612         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1613 };
1614 static const unsigned int vin1_data8_mux[] = {
1615         VI1_DATA0_MARK, VI1_DATA1_MARK,
1616         VI1_DATA2_MARK, VI1_DATA3_MARK,
1617         VI1_DATA4_MARK, VI1_DATA5_MARK,
1618         VI1_DATA6_MARK, VI1_DATA7_MARK,
1619 };
1620 static const unsigned int vin1_data10_pins[] = {
1621         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1622         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1623         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1624         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1625         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1626 };
1627 static const unsigned int vin1_data10_mux[] = {
1628         VI1_DATA0_MARK, VI1_DATA1_MARK,
1629         VI1_DATA2_MARK, VI1_DATA3_MARK,
1630         VI1_DATA4_MARK, VI1_DATA5_MARK,
1631         VI1_DATA6_MARK, VI1_DATA7_MARK,
1632         VI1_DATA8_MARK,  VI1_DATA9_MARK,
1633 };
1634 static const unsigned int vin1_data12_pins[] = {
1635         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1636         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1637         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1638         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1639         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1640         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1641 };
1642 static const unsigned int vin1_data12_mux[] = {
1643         VI1_DATA0_MARK, VI1_DATA1_MARK,
1644         VI1_DATA2_MARK, VI1_DATA3_MARK,
1645         VI1_DATA4_MARK, VI1_DATA5_MARK,
1646         VI1_DATA6_MARK, VI1_DATA7_MARK,
1647         VI1_DATA8_MARK,  VI1_DATA9_MARK,
1648         VI1_DATA10_MARK, VI1_DATA11_MARK,
1649 };
1650 static const unsigned int vin1_sync_pins[] = {
1651         /* HSYNC#, VSYNC# */
1652         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1653 };
1654 static const unsigned int vin1_sync_mux[] = {
1655         VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1656 };
1657 static const unsigned int vin1_field_pins[] = {
1658         RCAR_GP_PIN(3, 16),
1659 };
1660 static const unsigned int vin1_field_mux[] = {
1661         /* FIELD */
1662         VI1_FIELD_MARK,
1663 };
1664 static const unsigned int vin1_clkenb_pins[] = {
1665         RCAR_GP_PIN(3, 1),
1666 };
1667 static const unsigned int vin1_clkenb_mux[] = {
1668         /* CLKENB */
1669         VI1_CLKENB_MARK,
1670 };
1671 static const unsigned int vin1_clk_pins[] = {
1672         RCAR_GP_PIN(3, 0),
1673 };
1674 static const unsigned int vin1_clk_mux[] = {
1675         /* CLK */
1676         VI1_CLK_MARK,
1677 };
1678
1679 static const struct sh_pfc_pin_group pinmux_groups[] = {
1680         SH_PFC_PIN_GROUP(avb0_link),
1681         SH_PFC_PIN_GROUP(avb0_magic),
1682         SH_PFC_PIN_GROUP(avb0_phy_int),
1683         SH_PFC_PIN_GROUP(avb0_mdio),
1684         SH_PFC_PIN_GROUP(avb0_rgmii),
1685         SH_PFC_PIN_GROUP(avb0_txcrefclk),
1686         SH_PFC_PIN_GROUP(avb0_avtp_pps),
1687         SH_PFC_PIN_GROUP(avb0_avtp_capture),
1688         SH_PFC_PIN_GROUP(avb0_avtp_match),
1689         SH_PFC_PIN_GROUP(canfd_clk_a),
1690         SH_PFC_PIN_GROUP(canfd_clk_b),
1691         SH_PFC_PIN_GROUP(canfd0_data_a),
1692         SH_PFC_PIN_GROUP(canfd0_data_b),
1693         SH_PFC_PIN_GROUP(canfd1_data),
1694         SH_PFC_PIN_GROUP(du_rgb666),
1695         SH_PFC_PIN_GROUP(du_clk_out),
1696         SH_PFC_PIN_GROUP(du_sync),
1697         SH_PFC_PIN_GROUP(du_oddf),
1698         SH_PFC_PIN_GROUP(du_cde),
1699         SH_PFC_PIN_GROUP(du_disp),
1700         SH_PFC_PIN_GROUP(hscif0_data),
1701         SH_PFC_PIN_GROUP(hscif0_clk),
1702         SH_PFC_PIN_GROUP(hscif0_ctrl),
1703         SH_PFC_PIN_GROUP(hscif1_data),
1704         SH_PFC_PIN_GROUP(hscif1_clk),
1705         SH_PFC_PIN_GROUP(hscif1_ctrl),
1706         SH_PFC_PIN_GROUP(hscif2_data),
1707         SH_PFC_PIN_GROUP(hscif2_clk),
1708         SH_PFC_PIN_GROUP(hscif2_ctrl),
1709         SH_PFC_PIN_GROUP(hscif3_data),
1710         SH_PFC_PIN_GROUP(hscif3_clk),
1711         SH_PFC_PIN_GROUP(hscif3_ctrl),
1712         SH_PFC_PIN_GROUP(i2c0),
1713         SH_PFC_PIN_GROUP(i2c1),
1714         SH_PFC_PIN_GROUP(i2c2),
1715         SH_PFC_PIN_GROUP(i2c3_a),
1716         SH_PFC_PIN_GROUP(i2c3_b),
1717         SH_PFC_PIN_GROUP(i2c4),
1718         SH_PFC_PIN_GROUP(intc_ex_irq0),
1719         SH_PFC_PIN_GROUP(intc_ex_irq1),
1720         SH_PFC_PIN_GROUP(intc_ex_irq2),
1721         SH_PFC_PIN_GROUP(intc_ex_irq3),
1722         SH_PFC_PIN_GROUP(intc_ex_irq4),
1723         SH_PFC_PIN_GROUP(intc_ex_irq5),
1724         SH_PFC_PIN_GROUP(mmc_data1),
1725         SH_PFC_PIN_GROUP(mmc_data4),
1726         SH_PFC_PIN_GROUP(mmc_data8),
1727         SH_PFC_PIN_GROUP(mmc_ctrl),
1728         SH_PFC_PIN_GROUP(mmc_cd),
1729         SH_PFC_PIN_GROUP(mmc_wp),
1730         SH_PFC_PIN_GROUP(msiof0_clk),
1731         SH_PFC_PIN_GROUP(msiof0_sync),
1732         SH_PFC_PIN_GROUP(msiof0_ss1),
1733         SH_PFC_PIN_GROUP(msiof0_ss2),
1734         SH_PFC_PIN_GROUP(msiof0_txd),
1735         SH_PFC_PIN_GROUP(msiof0_rxd),
1736         SH_PFC_PIN_GROUP(msiof1_clk),
1737         SH_PFC_PIN_GROUP(msiof1_sync),
1738         SH_PFC_PIN_GROUP(msiof1_ss1),
1739         SH_PFC_PIN_GROUP(msiof1_ss2),
1740         SH_PFC_PIN_GROUP(msiof1_txd),
1741         SH_PFC_PIN_GROUP(msiof1_rxd),
1742         SH_PFC_PIN_GROUP(msiof2_clk),
1743         SH_PFC_PIN_GROUP(msiof2_sync),
1744         SH_PFC_PIN_GROUP(msiof2_ss1),
1745         SH_PFC_PIN_GROUP(msiof2_ss2),
1746         SH_PFC_PIN_GROUP(msiof2_txd),
1747         SH_PFC_PIN_GROUP(msiof2_rxd),
1748         SH_PFC_PIN_GROUP(msiof3_clk),
1749         SH_PFC_PIN_GROUP(msiof3_sync),
1750         SH_PFC_PIN_GROUP(msiof3_ss1),
1751         SH_PFC_PIN_GROUP(msiof3_ss2),
1752         SH_PFC_PIN_GROUP(msiof3_txd),
1753         SH_PFC_PIN_GROUP(msiof3_rxd),
1754         SH_PFC_PIN_GROUP(pwm0_a),
1755         SH_PFC_PIN_GROUP(pwm0_b),
1756         SH_PFC_PIN_GROUP(pwm1_a),
1757         SH_PFC_PIN_GROUP(pwm1_b),
1758         SH_PFC_PIN_GROUP(pwm2_a),
1759         SH_PFC_PIN_GROUP(pwm2_b),
1760         SH_PFC_PIN_GROUP(pwm3_a),
1761         SH_PFC_PIN_GROUP(pwm3_b),
1762         SH_PFC_PIN_GROUP(pwm4_a),
1763         SH_PFC_PIN_GROUP(pwm4_b),
1764         SH_PFC_PIN_GROUP(scif_clk_a),
1765         SH_PFC_PIN_GROUP(scif_clk_b),
1766         SH_PFC_PIN_GROUP(scif0_data),
1767         SH_PFC_PIN_GROUP(scif0_clk),
1768         SH_PFC_PIN_GROUP(scif0_ctrl),
1769         SH_PFC_PIN_GROUP(scif1_data_a),
1770         SH_PFC_PIN_GROUP(scif1_clk),
1771         SH_PFC_PIN_GROUP(scif1_ctrl),
1772         SH_PFC_PIN_GROUP(scif1_data_b),
1773         SH_PFC_PIN_GROUP(scif3_data),
1774         SH_PFC_PIN_GROUP(scif3_clk),
1775         SH_PFC_PIN_GROUP(scif3_ctrl),
1776         SH_PFC_PIN_GROUP(scif4_data),
1777         SH_PFC_PIN_GROUP(scif4_clk),
1778         SH_PFC_PIN_GROUP(scif4_ctrl),
1779         SH_PFC_PIN_GROUP(tmu_tclk1_a),
1780         SH_PFC_PIN_GROUP(tmu_tclk1_b),
1781         SH_PFC_PIN_GROUP(tmu_tclk2_a),
1782         SH_PFC_PIN_GROUP(tmu_tclk2_b),
1783         SH_PFC_PIN_GROUP(vin0_data8),
1784         SH_PFC_PIN_GROUP(vin0_data10),
1785         SH_PFC_PIN_GROUP(vin0_data12),
1786         SH_PFC_PIN_GROUP(vin0_sync),
1787         SH_PFC_PIN_GROUP(vin0_field),
1788         SH_PFC_PIN_GROUP(vin0_clkenb),
1789         SH_PFC_PIN_GROUP(vin0_clk),
1790         SH_PFC_PIN_GROUP(vin1_data8),
1791         SH_PFC_PIN_GROUP(vin1_data10),
1792         SH_PFC_PIN_GROUP(vin1_data12),
1793         SH_PFC_PIN_GROUP(vin1_sync),
1794         SH_PFC_PIN_GROUP(vin1_field),
1795         SH_PFC_PIN_GROUP(vin1_clkenb),
1796         SH_PFC_PIN_GROUP(vin1_clk),
1797 };
1798
1799 static const char * const avb0_groups[] = {
1800         "avb0_link",
1801         "avb0_magic",
1802         "avb0_phy_int",
1803         "avb0_mdio",
1804         "avb0_rgmii",
1805         "avb0_txcrefclk",
1806         "avb0_avtp_pps",
1807         "avb0_avtp_capture",
1808         "avb0_avtp_match",
1809 };
1810
1811 static const char * const canfd_clk_groups[] = {
1812         "canfd_clk_a",
1813         "canfd_clk_b",
1814 };
1815
1816 static const char * const canfd0_groups[] = {
1817         "canfd0_data_a",
1818         "canfd0_data_b",
1819 };
1820
1821 static const char * const canfd1_groups[] = {
1822         "canfd1_data",
1823 };
1824
1825 static const char * const du_groups[] = {
1826         "du_rgb666",
1827         "du_clk_out",
1828         "du_sync",
1829         "du_oddf",
1830         "du_cde",
1831         "du_disp",
1832 };
1833
1834 static const char * const hscif0_groups[] = {
1835         "hscif0_data",
1836         "hscif0_clk",
1837         "hscif0_ctrl",
1838 };
1839
1840 static const char * const hscif1_groups[] = {
1841         "hscif1_data",
1842         "hscif1_clk",
1843         "hscif1_ctrl",
1844 };
1845
1846 static const char * const hscif2_groups[] = {
1847         "hscif2_data",
1848         "hscif2_clk",
1849         "hscif2_ctrl",
1850 };
1851
1852 static const char * const hscif3_groups[] = {
1853         "hscif3_data",
1854         "hscif3_clk",
1855         "hscif3_ctrl",
1856 };
1857
1858 static const char * const i2c0_groups[] = {
1859         "i2c0",
1860 };
1861
1862 static const char * const i2c1_groups[] = {
1863         "i2c1",
1864 };
1865
1866 static const char * const i2c2_groups[] = {
1867         "i2c2",
1868 };
1869
1870 static const char * const i2c3_groups[] = {
1871         "i2c3_a",
1872         "i2c3_b",
1873 };
1874
1875 static const char * const i2c4_groups[] = {
1876         "i2c4",
1877 };
1878
1879 static const char * const intc_ex_groups[] = {
1880         "intc_ex_irq0",
1881         "intc_ex_irq1",
1882         "intc_ex_irq2",
1883         "intc_ex_irq3",
1884         "intc_ex_irq4",
1885         "intc_ex_irq5",
1886 };
1887
1888 static const char * const mmc_groups[] = {
1889         "mmc_data1",
1890         "mmc_data4",
1891         "mmc_data8",
1892         "mmc_ctrl",
1893         "mmc_cd",
1894         "mmc_wp",
1895 };
1896
1897 static const char * const msiof0_groups[] = {
1898         "msiof0_clk",
1899         "msiof0_sync",
1900         "msiof0_ss1",
1901         "msiof0_ss2",
1902         "msiof0_txd",
1903         "msiof0_rxd",
1904 };
1905
1906 static const char * const msiof1_groups[] = {
1907         "msiof1_clk",
1908         "msiof1_sync",
1909         "msiof1_ss1",
1910         "msiof1_ss2",
1911         "msiof1_txd",
1912         "msiof1_rxd",
1913 };
1914
1915 static const char * const msiof2_groups[] = {
1916         "msiof2_clk",
1917         "msiof2_sync",
1918         "msiof2_ss1",
1919         "msiof2_ss2",
1920         "msiof2_txd",
1921         "msiof2_rxd",
1922 };
1923
1924 static const char * const msiof3_groups[] = {
1925         "msiof3_clk",
1926         "msiof3_sync",
1927         "msiof3_ss1",
1928         "msiof3_ss2",
1929         "msiof3_txd",
1930         "msiof3_rxd",
1931 };
1932
1933 static const char * const pwm0_groups[] = {
1934         "pwm0_a",
1935         "pwm0_b",
1936 };
1937
1938 static const char * const pwm1_groups[] = {
1939         "pwm1_a",
1940         "pwm1_b",
1941 };
1942
1943 static const char * const pwm2_groups[] = {
1944         "pwm2_a",
1945         "pwm2_b",
1946 };
1947
1948 static const char * const pwm3_groups[] = {
1949         "pwm3_a",
1950         "pwm3_b",
1951 };
1952
1953 static const char * const pwm4_groups[] = {
1954         "pwm4_a",
1955         "pwm4_b",
1956 };
1957
1958 static const char * const scif_clk_groups[] = {
1959         "scif_clk_a",
1960         "scif_clk_b",
1961 };
1962
1963 static const char * const scif0_groups[] = {
1964         "scif0_data",
1965         "scif0_clk",
1966         "scif0_ctrl",
1967 };
1968
1969 static const char * const scif1_groups[] = {
1970         "scif1_data_a",
1971         "scif1_clk",
1972         "scif1_ctrl",
1973         "scif1_data_b",
1974 };
1975
1976 static const char * const scif3_groups[] = {
1977         "scif3_data",
1978         "scif3_clk",
1979         "scif3_ctrl",
1980 };
1981
1982 static const char * const scif4_groups[] = {
1983         "scif4_data",
1984         "scif4_clk",
1985         "scif4_ctrl",
1986 };
1987
1988 static const char * const tmu_groups[] = {
1989         "tmu_tclk1_a",
1990         "tmu_tclk1_b",
1991         "tmu_tclk2_a",
1992         "tmu_tclk2_b",
1993 };
1994
1995 static const char * const vin0_groups[] = {
1996         "vin0_data8",
1997         "vin0_data10",
1998         "vin0_data12",
1999         "vin0_sync",
2000         "vin0_field",
2001         "vin0_clkenb",
2002         "vin0_clk",
2003 };
2004
2005 static const char * const vin1_groups[] = {
2006         "vin1_data8",
2007         "vin1_data10",
2008         "vin1_data12",
2009         "vin1_sync",
2010         "vin1_field",
2011         "vin1_clkenb",
2012         "vin1_clk",
2013 };
2014
2015 static const struct sh_pfc_function pinmux_functions[] = {
2016         SH_PFC_FUNCTION(avb0),
2017         SH_PFC_FUNCTION(canfd_clk),
2018         SH_PFC_FUNCTION(canfd0),
2019         SH_PFC_FUNCTION(canfd1),
2020         SH_PFC_FUNCTION(du),
2021         SH_PFC_FUNCTION(hscif0),
2022         SH_PFC_FUNCTION(hscif1),
2023         SH_PFC_FUNCTION(hscif2),
2024         SH_PFC_FUNCTION(hscif3),
2025         SH_PFC_FUNCTION(i2c0),
2026         SH_PFC_FUNCTION(i2c1),
2027         SH_PFC_FUNCTION(i2c2),
2028         SH_PFC_FUNCTION(i2c3),
2029         SH_PFC_FUNCTION(i2c4),
2030         SH_PFC_FUNCTION(intc_ex),
2031         SH_PFC_FUNCTION(mmc),
2032         SH_PFC_FUNCTION(msiof0),
2033         SH_PFC_FUNCTION(msiof1),
2034         SH_PFC_FUNCTION(msiof2),
2035         SH_PFC_FUNCTION(msiof3),
2036         SH_PFC_FUNCTION(pwm0),
2037         SH_PFC_FUNCTION(pwm1),
2038         SH_PFC_FUNCTION(pwm2),
2039         SH_PFC_FUNCTION(pwm3),
2040         SH_PFC_FUNCTION(pwm4),
2041         SH_PFC_FUNCTION(scif_clk),
2042         SH_PFC_FUNCTION(scif0),
2043         SH_PFC_FUNCTION(scif1),
2044         SH_PFC_FUNCTION(scif3),
2045         SH_PFC_FUNCTION(scif4),
2046         SH_PFC_FUNCTION(tmu),
2047         SH_PFC_FUNCTION(vin0),
2048         SH_PFC_FUNCTION(vin1),
2049 };
2050
2051 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2052 #define F_(x, y)        FN_##y
2053 #define FM(x)           FN_##x
2054         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2055                 0, 0,
2056                 0, 0,
2057                 0, 0,
2058                 0, 0,
2059                 0, 0,
2060                 0, 0,
2061                 0, 0,
2062                 0, 0,
2063                 0, 0,
2064                 0, 0,
2065                 GP_0_21_FN,     GPSR0_21,
2066                 GP_0_20_FN,     GPSR0_20,
2067                 GP_0_19_FN,     GPSR0_19,
2068                 GP_0_18_FN,     GPSR0_18,
2069                 GP_0_17_FN,     GPSR0_17,
2070                 GP_0_16_FN,     GPSR0_16,
2071                 GP_0_15_FN,     GPSR0_15,
2072                 GP_0_14_FN,     GPSR0_14,
2073                 GP_0_13_FN,     GPSR0_13,
2074                 GP_0_12_FN,     GPSR0_12,
2075                 GP_0_11_FN,     GPSR0_11,
2076                 GP_0_10_FN,     GPSR0_10,
2077                 GP_0_9_FN,      GPSR0_9,
2078                 GP_0_8_FN,      GPSR0_8,
2079                 GP_0_7_FN,      GPSR0_7,
2080                 GP_0_6_FN,      GPSR0_6,
2081                 GP_0_5_FN,      GPSR0_5,
2082                 GP_0_4_FN,      GPSR0_4,
2083                 GP_0_3_FN,      GPSR0_3,
2084                 GP_0_2_FN,      GPSR0_2,
2085                 GP_0_1_FN,      GPSR0_1,
2086                 GP_0_0_FN,      GPSR0_0, }
2087         },
2088         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2089                 0, 0,
2090                 0, 0,
2091                 0, 0,
2092                 0, 0,
2093                 GP_1_27_FN,     GPSR1_27,
2094                 GP_1_26_FN,     GPSR1_26,
2095                 GP_1_25_FN,     GPSR1_25,
2096                 GP_1_24_FN,     GPSR1_24,
2097                 GP_1_23_FN,     GPSR1_23,
2098                 GP_1_22_FN,     GPSR1_22,
2099                 GP_1_21_FN,     GPSR1_21,
2100                 GP_1_20_FN,     GPSR1_20,
2101                 GP_1_19_FN,     GPSR1_19,
2102                 GP_1_18_FN,     GPSR1_18,
2103                 GP_1_17_FN,     GPSR1_17,
2104                 GP_1_16_FN,     GPSR1_16,
2105                 GP_1_15_FN,     GPSR1_15,
2106                 GP_1_14_FN,     GPSR1_14,
2107                 GP_1_13_FN,     GPSR1_13,
2108                 GP_1_12_FN,     GPSR1_12,
2109                 GP_1_11_FN,     GPSR1_11,
2110                 GP_1_10_FN,     GPSR1_10,
2111                 GP_1_9_FN,      GPSR1_9,
2112                 GP_1_8_FN,      GPSR1_8,
2113                 GP_1_7_FN,      GPSR1_7,
2114                 GP_1_6_FN,      GPSR1_6,
2115                 GP_1_5_FN,      GPSR1_5,
2116                 GP_1_4_FN,      GPSR1_4,
2117                 GP_1_3_FN,      GPSR1_3,
2118                 GP_1_2_FN,      GPSR1_2,
2119                 GP_1_1_FN,      GPSR1_1,
2120                 GP_1_0_FN,      GPSR1_0, }
2121         },
2122         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2123                 0, 0,
2124                 0, 0,
2125                 0, 0,
2126                 0, 0,
2127                 0, 0,
2128                 0, 0,
2129                 0, 0,
2130                 0, 0,
2131                 0, 0,
2132                 0, 0,
2133                 0, 0,
2134                 0, 0,
2135                 0, 0,
2136                 0, 0,
2137                 0, 0,
2138                 GP_2_16_FN,     GPSR2_16,
2139                 GP_2_15_FN,     GPSR2_15,
2140                 GP_2_14_FN,     GPSR2_14,
2141                 GP_2_13_FN,     GPSR2_13,
2142                 GP_2_12_FN,     GPSR2_12,
2143                 GP_2_11_FN,     GPSR2_11,
2144                 GP_2_10_FN,     GPSR2_10,
2145                 GP_2_9_FN,      GPSR2_9,
2146                 GP_2_8_FN,      GPSR2_8,
2147                 GP_2_7_FN,      GPSR2_7,
2148                 GP_2_6_FN,      GPSR2_6,
2149                 GP_2_5_FN,      GPSR2_5,
2150                 GP_2_4_FN,      GPSR2_4,
2151                 GP_2_3_FN,      GPSR2_3,
2152                 GP_2_2_FN,      GPSR2_2,
2153                 GP_2_1_FN,      GPSR2_1,
2154                 GP_2_0_FN,      GPSR2_0, }
2155         },
2156         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2157                 0, 0,
2158                 0, 0,
2159                 0, 0,
2160                 0, 0,
2161                 0, 0,
2162                 0, 0,
2163                 0, 0,
2164                 0, 0,
2165                 0, 0,
2166                 0, 0,
2167                 0, 0,
2168                 0, 0,
2169                 0, 0,
2170                 0, 0,
2171                 0, 0,
2172                 GP_3_16_FN,     GPSR3_16,
2173                 GP_3_15_FN,     GPSR3_15,
2174                 GP_3_14_FN,     GPSR3_14,
2175                 GP_3_13_FN,     GPSR3_13,
2176                 GP_3_12_FN,     GPSR3_12,
2177                 GP_3_11_FN,     GPSR3_11,
2178                 GP_3_10_FN,     GPSR3_10,
2179                 GP_3_9_FN,      GPSR3_9,
2180                 GP_3_8_FN,      GPSR3_8,
2181                 GP_3_7_FN,      GPSR3_7,
2182                 GP_3_6_FN,      GPSR3_6,
2183                 GP_3_5_FN,      GPSR3_5,
2184                 GP_3_4_FN,      GPSR3_4,
2185                 GP_3_3_FN,      GPSR3_3,
2186                 GP_3_2_FN,      GPSR3_2,
2187                 GP_3_1_FN,      GPSR3_1,
2188                 GP_3_0_FN,      GPSR3_0, }
2189         },
2190         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2191                 0, 0,
2192                 0, 0,
2193                 0, 0,
2194                 0, 0,
2195                 0, 0,
2196                 0, 0,
2197                 0, 0,
2198                 0, 0,
2199                 0, 0,
2200                 0, 0,
2201                 0, 0,
2202                 0, 0,
2203                 0, 0,
2204                 0, 0,
2205                 0, 0,
2206                 0, 0,
2207                 0, 0,
2208                 0, 0,
2209                 0, 0,
2210                 0, 0,
2211                 0, 0,
2212                 0, 0,
2213                 0, 0,
2214                 0, 0,
2215                 0, 0,
2216                 0, 0,
2217                 GP_4_5_FN,      GPSR4_5,
2218                 GP_4_4_FN,      GPSR4_4,
2219                 GP_4_3_FN,      GPSR4_3,
2220                 GP_4_2_FN,      GPSR4_2,
2221                 GP_4_1_FN,      GPSR4_1,
2222                 GP_4_0_FN,      GPSR4_0, }
2223         },
2224         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2225                 0, 0,
2226                 0, 0,
2227                 0, 0,
2228                 0, 0,
2229                 0, 0,
2230                 0, 0,
2231                 0, 0,
2232                 0, 0,
2233                 0, 0,
2234                 0, 0,
2235                 0, 0,
2236                 0, 0,
2237                 0, 0,
2238                 0, 0,
2239                 0, 0,
2240                 0, 0,
2241                 0, 0,
2242                 GP_5_14_FN,     GPSR5_14,
2243                 GP_5_13_FN,     GPSR5_13,
2244                 GP_5_12_FN,     GPSR5_12,
2245                 GP_5_11_FN,     GPSR5_11,
2246                 GP_5_10_FN,     GPSR5_10,
2247                 GP_5_9_FN,      GPSR5_9,
2248                 GP_5_8_FN,      GPSR5_8,
2249                 GP_5_7_FN,      GPSR5_7,
2250                 GP_5_6_FN,      GPSR5_6,
2251                 GP_5_5_FN,      GPSR5_5,
2252                 GP_5_4_FN,      GPSR5_4,
2253                 GP_5_3_FN,      GPSR5_3,
2254                 GP_5_2_FN,      GPSR5_2,
2255                 GP_5_1_FN,      GPSR5_1,
2256                 GP_5_0_FN,      GPSR5_0, }
2257         },
2258 #undef F_
2259 #undef FM
2260
2261 #define F_(x, y)        x,
2262 #define FM(x)           FN_##x,
2263         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2264                 IP0_31_28
2265                 IP0_27_24
2266                 IP0_23_20
2267                 IP0_19_16
2268                 IP0_15_12
2269                 IP0_11_8
2270                 IP0_7_4
2271                 IP0_3_0 }
2272         },
2273         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2274                 IP1_31_28
2275                 IP1_27_24
2276                 IP1_23_20
2277                 IP1_19_16
2278                 IP1_15_12
2279                 IP1_11_8
2280                 IP1_7_4
2281                 IP1_3_0 }
2282         },
2283         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2284                 IP2_31_28
2285                 IP2_27_24
2286                 IP2_23_20
2287                 IP2_19_16
2288                 IP2_15_12
2289                 IP2_11_8
2290                 IP2_7_4
2291                 IP2_3_0 }
2292         },
2293         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2294                 IP3_31_28
2295                 IP3_27_24
2296                 IP3_23_20
2297                 IP3_19_16
2298                 IP3_15_12
2299                 IP3_11_8
2300                 IP3_7_4
2301                 IP3_3_0 }
2302         },
2303         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2304                 IP4_31_28
2305                 IP4_27_24
2306                 IP4_23_20
2307                 IP4_19_16
2308                 IP4_15_12
2309                 IP4_11_8
2310                 IP4_7_4
2311                 IP4_3_0 }
2312         },
2313         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2314                 IP5_31_28
2315                 IP5_27_24
2316                 IP5_23_20
2317                 IP5_19_16
2318                 IP5_15_12
2319                 IP5_11_8
2320                 IP5_7_4
2321                 IP5_3_0 }
2322         },
2323         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2324                 IP6_31_28
2325                 IP6_27_24
2326                 IP6_23_20
2327                 IP6_19_16
2328                 IP6_15_12
2329                 IP6_11_8
2330                 IP6_7_4
2331                 IP6_3_0 }
2332         },
2333         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2334                 IP7_31_28
2335                 IP7_27_24
2336                 IP7_23_20
2337                 IP7_19_16
2338                 IP7_15_12
2339                 IP7_11_8
2340                 IP7_7_4
2341                 IP7_3_0 }
2342         },
2343         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2344                 IP8_31_28
2345                 IP8_27_24
2346                 IP8_23_20
2347                 IP8_19_16
2348                 IP8_15_12
2349                 IP8_11_8
2350                 IP8_7_4
2351                 IP8_3_0 }
2352         },
2353 #undef F_
2354 #undef FM
2355
2356 #define F_(x, y)        x,
2357 #define FM(x)           FN_##x,
2358         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2359                              4, 4, 4, 4,
2360                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
2361                 /* RESERVED 31, 30, 29, 28 */
2362                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2363                 /* RESERVED 27, 26, 25, 24 */
2364                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2365                 /* RESERVED 23, 22, 21, 20 */
2366                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2367                 /* RESERVED 19, 18, 17, 16 */
2368                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2369                 /* RESERVED 15, 14, 13, 12 */
2370                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2371                 MOD_SEL0_11
2372                 MOD_SEL0_10
2373                 MOD_SEL0_9
2374                 MOD_SEL0_8
2375                 MOD_SEL0_7
2376                 MOD_SEL0_6
2377                 MOD_SEL0_5
2378                 MOD_SEL0_4
2379                 MOD_SEL0_3
2380                 MOD_SEL0_2
2381                 MOD_SEL0_1
2382                 MOD_SEL0_0 }
2383         },
2384         { },
2385 };
2386
2387 enum ioctrl_regs {
2388         IOCTRL30,
2389         IOCTRL31,
2390         IOCTRL32,
2391 };
2392
2393 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2394         [IOCTRL30] = { 0xe6060380 },
2395         [IOCTRL31] = { 0xe6060384 },
2396         [IOCTRL32] = { 0xe6060388 },
2397         { /* sentinel */ },
2398 };
2399
2400 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2401                                    u32 *pocctrl)
2402 {
2403         int bit = pin & 0x1f;
2404
2405         *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
2406         if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2407                 return bit;
2408         if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2409                 return bit + 22;
2410
2411         *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
2412         if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2413                 return bit - 10;
2414         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2415                 return bit + 7;
2416
2417         return -EINVAL;
2418 }
2419
2420 static const struct sh_pfc_soc_operations pinmux_ops = {
2421         .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2422 };
2423
2424 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2425         .name = "r8a77970_pfc",
2426         .ops = &pinmux_ops,
2427         .unlock_reg = 0xe6060000, /* PMMR */
2428
2429         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2430
2431         .pins = pinmux_pins,
2432         .nr_pins = ARRAY_SIZE(pinmux_pins),
2433         .groups = pinmux_groups,
2434         .nr_groups = ARRAY_SIZE(pinmux_groups),
2435         .functions = pinmux_functions,
2436         .nr_functions = ARRAY_SIZE(pinmux_functions),
2437
2438         .cfg_regs = pinmux_config_regs,
2439         .ioctrl_regs = pinmux_ioctrl_regs,
2440
2441         .pinmux_data = pinmux_data,
2442         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2443 };