drivers/pinctrl/renesas/pfc-r8a7791.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a7791/r8a7743 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2013 Renesas Electronics Corporation
   6  * Copyright (C) 2014-2017 Cogent Embedded, Inc.
   7  */
   8
   9 #include <linux/errno.h>
  10 #include <linux/kernel.h>
  11
  12 #include "sh_pfc.h"
  13
  14 /*
  15  * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
  16  * which case they support both 3.3V and 1.8V signalling.
  17  */
  18 #define CPU_ALL_GP(fn, sfx)                                             \
  19         PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  20         PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  21         PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  22         PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  23         PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  24         PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  25         PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
  26         PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  27         PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  28         PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  29         PORT_GP_CFG_1(6, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  30         PORT_GP_CFG_1(6, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  31         PORT_GP_CFG_1(6, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  32         PORT_GP_CFG_1(6, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  33         PORT_GP_CFG_1(6, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  34         PORT_GP_CFG_7(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),              \
  35         PORT_GP_1(7, 7, fn, sfx),                                       \
  36         PORT_GP_1(7, 8, fn, sfx),                                       \
  37         PORT_GP_1(7, 9, fn, sfx),                                       \
  38         PORT_GP_CFG_1(7, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  39         PORT_GP_CFG_1(7, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  40         PORT_GP_CFG_1(7, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  41         PORT_GP_CFG_1(7, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  42         PORT_GP_CFG_1(7, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  43         PORT_GP_CFG_1(7, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  44         PORT_GP_CFG_1(7, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  45         PORT_GP_CFG_1(7, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  46         PORT_GP_CFG_1(7, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  47         PORT_GP_CFG_1(7, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  48         PORT_GP_CFG_1(7, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  49         PORT_GP_CFG_1(7, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  50         PORT_GP_CFG_1(7, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  51         PORT_GP_CFG_1(7, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  52         PORT_GP_CFG_1(7, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
  53         PORT_GP_CFG_1(7, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
  54
  55 #define CPU_ALL_NOGP(fn)                                                \
  56         PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN),        \
  57         PIN_NOGP_CFG(AVS1, "AVS1", fn, SH_PFC_PIN_CFG_PULL_UP),         \
  58         PIN_NOGP_CFG(AVS2, "AVS2", fn, SH_PFC_PIN_CFG_PULL_UP),         \
  59         PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),           \
  60         PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),           \
  61         PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),           \
  62         PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
  63
  64 enum {
  65         PINMUX_RESERVED = 0,
  66
  67         PINMUX_DATA_BEGIN,
  68         GP_ALL(DATA),
  69         PINMUX_DATA_END,
  70
  71         PINMUX_FUNCTION_BEGIN,
  72         GP_ALL(FN),
  73
  74         /* GPSR0 */
  75         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  76         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  77         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  78         FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  79         FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  80         FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  81
  82         /* GPSR1 */
  83         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  84         FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  85         FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  86         FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  87         FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  88         FN_IP3_21_20,
  89
  90         /* GPSR2 */
  91         FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  92         FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  93         FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  94         FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  95         FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  96         FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  97         FN_IP6_5_3, FN_IP6_7_6,
  98
  99         /* GPSR3 */
 100         FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
 101         FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
 102         FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
 103         FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
 104         FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
 105         FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
 106         FN_IP9_18_17,
 107
 108         /* GPSR4 */
 109         FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
 110         FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
 111         FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
 112         FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
 113         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
 114         FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
 115         FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
 116         FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
 117
 118         /* GPSR5 */
 119         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
 120         FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
 121         FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
 122         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
 123         FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
 124         FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
 125         FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
 126
 127         /* GPSR6 */
 128         FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
 129         FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
 130         FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
 131         FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
 132         FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
 133         FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
 134         FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
 135         FN_USB1_OVC, FN_DU0_DOTCLKIN,
 136
 137         /* GPSR7 */
 138         FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
 139         FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
 140         FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
 141         FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
 142         FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
 143         FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
 144
 145         /* IPSR0 */
 146         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
 147         FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
 148         FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
 149         FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
 150         FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
 151         FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
 152
 153         /* IPSR1 */
 154         FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
 155         FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
 156         FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
 157         FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
 158         FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
 159         FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
 160         FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
 161         FN_A15, FN_BPFCLK_C,
 162         FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
 163         FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
 164         FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
 165
 166         /* IPSR2 */
 167         FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
 168         FN_A20, FN_SPCLK,
 169         FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
 170         FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
 171         FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
 172         FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
 173         FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
 174         FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
 175         FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
 176         FN_EX_CS1_N, FN_MSIOF2_SCK,
 177         FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
 178         FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
 179
 180         /* IPSR3 */
 181         FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
 182         FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
 183         FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
 184         FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
 185         FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
 186         FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
 187         FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
 188         FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
 189         FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
 190         FN_DREQ0, FN_PWM3, FN_TPU_TO3,
 191         FN_DACK0, FN_DRACK0, FN_REMOCON,
 192         FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
 193         FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
 194         FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
 195         FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
 196
 197         /* IPSR4 */
 198         FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
 199         FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
 200         FN_GLO_I0_D,
 201         FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
 202         FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
 203         FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
 204         FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
 205         FN_GLO_Q1_D, FN_HCTS1_N_E,
 206         FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
 207         FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
 208         FN_SSI_SCK4, FN_GLO_SS_D,
 209         FN_SSI_WS4, FN_GLO_RFON_D,
 210         FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
 211         FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
 212         FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
 213
 214         /* IPSR5 */
 215         FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
 216         FN_MSIOF2_TXD_D, FN_VI1_R3_B,
 217         FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
 218         FN_MSIOF2_SS1_D, FN_VI1_R4_B,
 219         FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
 220         FN_MSIOF2_RXD_D, FN_VI1_R5_B,
 221         FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
 222         FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
 223         FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
 224         FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
 225         FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
 226         FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
 227         FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
 228         FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
 229         FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
 230
 231         /* IPSR6 */
 232         FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
 233         FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
 234         FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 235         FN_SCIFA2_RXD, FN_FMIN_E,
 236         FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 237         FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
 238         FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
 239         FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
 240         FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
 241         FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
 242         FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
 243         FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
 244         FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 245         FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
 246
 247         /* IPSR7 */
 248         FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
 249         FN_SCIF_CLK_B, FN_GPS_MAG_D,
 250         FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
 251         FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
 252         FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
 253         FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
 254         FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
 255         FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
 256         FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
 257         FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
 258         FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
 259         FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
 260         FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
 261         FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
 262         FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
 263         FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
 264         FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
 265         FN_SCIFA1_SCK, FN_SSI_SCK78_B,
 266
 267         /* IPSR8 */
 268         FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
 269         FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
 270         FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
 271         FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
 272         FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
 273         FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
 274         FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
 275         FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
 276         FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
 277         FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
 278         FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
 279         FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
 280         FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
 281         FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
 282         FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
 283         FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
 284         FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
 285
 286         /* IPSR9 */
 287         FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
 288         FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
 289         FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
 290         FN_DU1_DOTCLKOUT0, FN_QCLK,
 291         FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
 292         FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
 293         FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
 294         FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
 295         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
 296         FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
 297         FN_DU1_DISP, FN_QPOLA,
 298         FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
 299         FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
 300         FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
 301         FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
 302         FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
 303         FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
 304         FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
 305         FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
 306
 307         /* IPSR10 */
 308         FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
 309         FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
 310         FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
 311         FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
 312         FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
 313         FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
 314         FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
 315         FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
 316         FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
 317         FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
 318         FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
 319         FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
 320         FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
 321         FN_TS_SDATA0_C, FN_ATACS11_N,
 322         FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
 323         FN_TS_SCK0_C, FN_ATAG1_N,
 324         FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
 325         FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
 326         FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
 327
 328         /* IPSR11 */
 329         FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
 330         FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
 331         FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
 332         FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
 333         FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
 334         FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
 335         FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
 336         FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
 337         FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
 338         FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
 339         FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
 340         FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
 341         FN_VI1_DATA7, FN_AVB_MDC,
 342         FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
 343         FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
 344
 345         /* IPSR12 */
 346         FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
 347         FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
 348         FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
 349         FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
 350         FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
 351         FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
 352         FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
 353         FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
 354         FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
 355         FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
 356         FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
 357         FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
 358         FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
 359         FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
 360         FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
 361         FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
 362         FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
 363
 364         /* IPSR13 */
 365         FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
 366         FN_ADICLK_B, FN_MSIOF0_SS1_C,
 367         FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
 368         FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
 369         FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
 370         FN_ADICHS2_B, FN_MSIOF0_TXD_C,
 371         FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
 372         FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
 373         FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
 374         FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
 375         FN_SCIFA5_TXD_B, FN_TX3_C,
 376         FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
 377         FN_SCIFA5_RXD_B, FN_RX3_C,
 378         FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
 379         FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
 380         FN_SD1_DATA3, FN_IERX_B,
 381         FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
 382
 383         /* IPSR14 */
 384         FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
 385         FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
 386         FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
 387         FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
 388         FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
 389         FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
 390         FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
 391         FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
 392         FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
 393         FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
 394         FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
 395         FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
 396         FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
 397         FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
 398
 399         /* IPSR15 */
 400         FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
 401         FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
 402         FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
 403         FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
 404         FN_PWM5_B, FN_SCIFA3_TXD_C,
 405         FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
 406         FN_VI1_G6_B, FN_SCIFA3_RXD_C,
 407         FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
 408         FN_VI1_G7_B, FN_SCIFA3_SCK_C,
 409         FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
 410         FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
 411         FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
 412         FN_TCLK2, FN_VI1_DATA3_C,
 413         FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
 414         FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
 415
 416         /* IPSR16 */
 417         FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
 418         FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
 419         FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
 420         FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
 421         FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
 422
 423         /* MOD_SEL */
 424         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 425         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
 426         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
 427         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 428         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 429         FN_SEL_SSI9_0, FN_SEL_SSI9_1,
 430         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 431         FN_SEL_QSP_0, FN_SEL_QSP_1,
 432         FN_SEL_SSI7_0, FN_SEL_SSI7_1,
 433         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
 434         FN_SEL_HSCIF1_4,
 435         FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
 436         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 437         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
 438         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 439         FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
 440
 441         /* MOD_SEL2 */
 442         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 443         FN_SEL_SCIF0_4,
 444         FN_SEL_SCIF_0, FN_SEL_SCIF_1,
 445         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 446         FN_SEL_CAN0_4, FN_SEL_CAN0_5,
 447         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 448         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 449         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
 450         FN_SEL_ADG_0, FN_SEL_ADG_1,
 451         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
 452         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 453         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 454         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
 455         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
 456         FN_SEL_SIM_0, FN_SEL_SIM_1,
 457         FN_SEL_SSI8_0, FN_SEL_SSI8_1,
 458
 459         /* MOD_SEL3 */
 460         FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
 461         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
 462         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
 463         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
 464         FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
 465         FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
 466         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
 467         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 468         FN_SEL_MMC_0, FN_SEL_MMC_1,
 469         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 470         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 471         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
 472         FN_SEL_I2C1_4,
 473         FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
 474
 475         /* MOD_SEL4 */
 476         FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
 477         FN_SEL_SOF1_4,
 478         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
 479         FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
 480         FN_SEL_RAD_0, FN_SEL_RAD_1,
 481         FN_SEL_RCN_0, FN_SEL_RCN_1,
 482         FN_SEL_RSP_0, FN_SEL_RSP_1,
 483         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
 484         FN_SEL_SCIF2_4,
 485         FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
 486         FN_SEL_SOF2_4,
 487         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 488         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 489         FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
 490         PINMUX_FUNCTION_END,
 491
 492         PINMUX_MARK_BEGIN,
 493
 494         EX_CS0_N_MARK, RD_N_MARK,
 495
 496         AUDIO_CLKA_MARK,
 497
 498         VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
 499         VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
 500         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
 501
 502         SD1_CLK_MARK,
 503
 504         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 505         DU0_DOTCLKIN_MARK,
 506
 507         /* IPSR0 */
 508         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
 509         D6_MARK, D7_MARK, D8_MARK,
 510         D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
 511         A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
 512         PWM2_B_MARK,
 513         A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
 514         A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
 515         A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
 516
 517         /* IPSR1 */
 518         A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
 519         A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
 520         A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
 521         A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
 522         A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
 523         A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
 524         A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
 525         A15_MARK, BPFCLK_C_MARK,
 526         A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
 527         A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
 528         A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
 529
 530         /* IPSR2 */
 531         A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
 532         SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
 533         A20_MARK, SPCLK_MARK,
 534         A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
 535         A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
 536         A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
 537         A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
 538         A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
 539         RX1_MARK, SCIFA1_RXD_MARK,
 540         CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
 541         CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
 542         EX_CS1_N_MARK, MSIOF2_SCK_MARK,
 543         EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
 544         EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
 545         ATAG0_N_MARK, EX_WAIT1_MARK,
 546
 547         /* IPSR3 */
 548         EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
 549         EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
 550         SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
 551         BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
 552         SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
 553         RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
 554         SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
 555         WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
 556         WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
 557         EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
 558         DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
 559         DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
 560         SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
 561         SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
 562         SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
 563         SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
 564         SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
 565         SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
 566
 567         /* IPSR4 */
 568         SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
 569         SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
 570         MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
 571         SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
 572         MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
 573         SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
 574         SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
 575         HSCK1_E_MARK,
 576         SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
 577         GLO_Q1_D_MARK, HCTS1_N_E_MARK,
 578         SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
 579         SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
 580         SSI_SCK4_MARK, GLO_SS_D_MARK,
 581         SSI_WS4_MARK, GLO_RFON_D_MARK,
 582         SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
 583         SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
 584         MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
 585
 586         /* IPSR5 */
 587         SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
 588         MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
 589         SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
 590         MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
 591         SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
 592         MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
 593         SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
 594         SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
 595         SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
 596         SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
 597         SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
 598         SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
 599         SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
 600         SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
 601         SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
 602
 603         /* IPSR6 */
 604         AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
 605         SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
 606         AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 607         SCIFA2_RXD_MARK, FMIN_E_MARK,
 608         AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
 609         IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
 610         IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
 611         IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
 612         IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
 613         IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
 614         MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
 615         IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
 616         IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 617         I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
 618         IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
 619         GPS_CLK_C_MARK, GPS_CLK_D_MARK,
 620         IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
 621         GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
 622
 623         /* IPSR7 */
 624         IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
 625         SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
 626         DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
 627         SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
 628         DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
 629         SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
 630         DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
 631         DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
 632         DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
 633         DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
 634         DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
 635         DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
 636         DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
 637         SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
 638         DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
 639         SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
 640         DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
 641         SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
 642
 643         /* IPSR8 */
 644         DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
 645         DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
 646         SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
 647         DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
 648         SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
 649         DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
 650         SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
 651         DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
 652         SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
 653         DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
 654         SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
 655         DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
 656         SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
 657         DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
 658         SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
 659         DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
 660         DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
 661         DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
 662
 663         /* IPSR9 */
 664         DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
 665         DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
 666         SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
 667         DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 668         DU1_DOTCLKOUT0_MARK, QCLK_MARK,
 669         DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
 670         TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
 671         DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
 672         DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
 673         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 674         CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
 675         DU1_DISP_MARK, QPOLA_MARK,
 676         DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
 677         VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
 678         VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
 679         VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
 680         VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
 681         VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
 682         VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
 683         HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
 684
 685         /* IPSR10 */
 686         VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
 687         HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
 688         VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
 689         HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
 690         VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
 691         HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
 692         VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
 693         HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
 694         VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
 695         CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
 696         VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
 697         VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
 698         VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
 699         TS_SDATA0_C_MARK, ATACS11_N_MARK,
 700         VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
 701         TS_SCK0_C_MARK, ATAG1_N_MARK,
 702         VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
 703         VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
 704         VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
 705         I2C1_SCL_D_MARK,
 706
 707         /* IPSR11 */
 708         VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
 709         I2C1_SDA_D_MARK,
 710         VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
 711         VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
 712         I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
 713         VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
 714         TX4_B_MARK, SCIFA4_TXD_B_MARK,
 715         VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
 716         RX4_B_MARK, SCIFA4_RXD_B_MARK,
 717         VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
 718         VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
 719         VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
 720         VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
 721         VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
 722         VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
 723         VI1_DATA7_MARK, AVB_MDC_MARK,
 724         ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
 725         ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
 726
 727         /* IPSR12 */
 728         ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
 729         ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
 730         ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
 731         I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
 732         ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
 733         I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
 734         ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
 735         CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
 736         ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
 737         CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
 738         ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
 739         ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
 740         ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
 741         ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
 742         STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
 743         ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
 744         STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
 745         ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
 746
 747         /* IPSR13 */
 748         STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
 749         ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
 750         STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
 751         STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
 752         STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
 753         ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
 754         SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
 755         SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
 756         SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
 757         SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
 758         SCIFA5_TXD_B_MARK, TX3_C_MARK,
 759         SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
 760         SCIFA5_RXD_B_MARK, RX3_C_MARK,
 761         SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
 762         SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
 763         SD1_DATA3_MARK, IERX_B_MARK,
 764         SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
 765
 766         /* IPSR14 */
 767         SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
 768         SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
 769         SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
 770         SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
 771         SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
 772         SCIFA5_TXD_C_MARK,
 773         SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
 774         SCIFA5_RXD_C_MARK,
 775         MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
 776         VI1_CLK_C_MARK, VI1_G0_B_MARK,
 777         MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
 778         VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
 779         MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
 780         MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
 781         MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
 782         VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
 783         MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
 784         VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
 785
 786         /* IPSR15 */
 787         SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
 788         SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
 789         SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
 790         GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
 791         PWM5_B_MARK, SCIFA3_TXD_C_MARK,
 792         GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
 793         VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
 794         GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
 795         VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
 796         HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
 797         TCLK1_MARK, VI1_DATA1_C_MARK,
 798         HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
 799         HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
 800         TCLK2_MARK, VI1_DATA3_C_MARK,
 801         HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
 802         CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
 803         HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
 804         CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
 805
 806         /* IPSR16 */
 807         HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
 808         GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
 809         HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
 810         GLO_SS_C_MARK, VI1_DATA7_C_MARK,
 811         HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
 812         HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
 813         HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
 814         PINMUX_MARK_END,
 815 };
 816
 817 static const u16 pinmux_data[] = {
 818         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 819
 820         PINMUX_SINGLE(EX_CS0_N),
 821         PINMUX_SINGLE(RD_N),
 822         PINMUX_SINGLE(AUDIO_CLKA),
 823         PINMUX_SINGLE(VI0_CLK),
 824         PINMUX_SINGLE(VI0_DATA0_VI0_B0),
 825         PINMUX_SINGLE(VI0_DATA1_VI0_B1),
 826         PINMUX_SINGLE(VI0_DATA2_VI0_B2),
 827         PINMUX_SINGLE(VI0_DATA4_VI0_B4),
 828         PINMUX_SINGLE(VI0_DATA5_VI0_B5),
 829         PINMUX_SINGLE(VI0_DATA6_VI0_B6),
 830         PINMUX_SINGLE(VI0_DATA7_VI0_B7),
 831         PINMUX_SINGLE(USB0_PWEN),
 832         PINMUX_SINGLE(USB0_OVC),
 833         PINMUX_SINGLE(USB1_PWEN),
 834         PINMUX_SINGLE(USB1_OVC),
 835         PINMUX_SINGLE(DU0_DOTCLKIN),
 836         PINMUX_SINGLE(SD1_CLK),
 837
 838         /* IPSR0 */
 839         PINMUX_IPSR_GPSR(IP0_0, D0),
 840         PINMUX_IPSR_GPSR(IP0_1, D1),
 841         PINMUX_IPSR_GPSR(IP0_2, D2),
 842         PINMUX_IPSR_GPSR(IP0_3, D3),
 843         PINMUX_IPSR_GPSR(IP0_4, D4),
 844         PINMUX_IPSR_GPSR(IP0_5, D5),
 845         PINMUX_IPSR_GPSR(IP0_6, D6),
 846         PINMUX_IPSR_GPSR(IP0_7, D7),
 847         PINMUX_IPSR_GPSR(IP0_8, D8),
 848         PINMUX_IPSR_GPSR(IP0_9, D9),
 849         PINMUX_IPSR_GPSR(IP0_10, D10),
 850         PINMUX_IPSR_GPSR(IP0_11, D11),
 851         PINMUX_IPSR_GPSR(IP0_12, D12),
 852         PINMUX_IPSR_GPSR(IP0_13, D13),
 853         PINMUX_IPSR_GPSR(IP0_14, D14),
 854         PINMUX_IPSR_GPSR(IP0_15, D15),
 855         PINMUX_IPSR_GPSR(IP0_18_16, A0),
 856         PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
 857         PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
 858         PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
 859         PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
 860         PINMUX_IPSR_GPSR(IP0_20_19, A1),
 861         PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
 862         PINMUX_IPSR_GPSR(IP0_22_21, A2),
 863         PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
 864         PINMUX_IPSR_GPSR(IP0_24_23, A3),
 865         PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
 866         PINMUX_IPSR_GPSR(IP0_26_25, A4),
 867         PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
 868         PINMUX_IPSR_GPSR(IP0_28_27, A5),
 869         PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
 870         PINMUX_IPSR_GPSR(IP0_30_29, A6),
 871         PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 872
 873         /* IPSR1 */
 874         PINMUX_IPSR_GPSR(IP1_1_0, A7),
 875         PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
 876         PINMUX_IPSR_GPSR(IP1_3_2, A8),
 877         PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
 878         PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
 879         PINMUX_IPSR_GPSR(IP1_5_4, A9),
 880         PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
 881         PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
 882         PINMUX_IPSR_GPSR(IP1_7_6, A10),
 883         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
 884         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
 885         PINMUX_IPSR_GPSR(IP1_10_8, A11),
 886         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
 887         PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
 888         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
 889         PINMUX_IPSR_GPSR(IP1_13_11, A12),
 890         PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
 891         PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
 892         PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
 893         PINMUX_IPSR_GPSR(IP1_16_14, A13),
 894         PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
 895         PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
 896         PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
 897         PINMUX_IPSR_GPSR(IP1_19_17, A14),
 898         PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
 899         PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
 900         PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
 901         PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
 902         PINMUX_IPSR_GPSR(IP1_22_20, A15),
 903         PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
 904         PINMUX_IPSR_GPSR(IP1_25_23, A16),
 905         PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
 906         PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
 907         PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
 908         PINMUX_IPSR_GPSR(IP1_28_26, A17),
 909         PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
 910         PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
 911         PINMUX_IPSR_GPSR(IP1_31_29, A18),
 912         PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
 913         PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
 914         PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 915
 916         /* IPSR2 */
 917         PINMUX_IPSR_GPSR(IP2_2_0, A19),
 918         PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
 919         PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
 920         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
 921         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
 922         PINMUX_IPSR_GPSR(IP2_2_0, A20),
 923         PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
 924         PINMUX_IPSR_GPSR(IP2_6_5, A21),
 925         PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
 926         PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
 927         PINMUX_IPSR_GPSR(IP2_9_7, A22),
 928         PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
 929         PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
 930         PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
 931         PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
 932         PINMUX_IPSR_GPSR(IP2_12_10, A23),
 933         PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
 934         PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
 935         PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
 936         PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
 937         PINMUX_IPSR_GPSR(IP2_15_13, A24),
 938         PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
 939         PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
 940         PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
 941         PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
 942         PINMUX_IPSR_GPSR(IP2_18_16, A25),
 943         PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
 944         PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
 945         PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
 946         PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
 947         PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
 948         PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
 949         PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
 950         PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
 951         PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
 952         PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
 953         PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
 954         PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
 955         PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
 956         PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
 957         PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
 958         PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
 959         PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
 960         PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
 961         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
 962         PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
 963         PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
 964
 965         /* IPSR3 */
 966         PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
 967         PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
 968         PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
 969         PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
 970         PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
 971         PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
 972         PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
 973         PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
 974         PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
 975         PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
 976         PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
 977         PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
 978         PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
 979         PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
 980         PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
 981         PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
 982         PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
 983         PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
 984         PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
 985         PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
 986         PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
 987         PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
 988         PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
 989         PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
 990         PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
 991         PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
 992         PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
 993         PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
 994         PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
 995         PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
 996         PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
 997         PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
 998         PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
 999         PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
1000         PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
1001         PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
1002         PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
1003         PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
1004         PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
1005         PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
1006         PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
1007         PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
1008         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
1009         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
1010         PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
1011         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
1012         PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
1013         PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
1014         PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
1015         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
1016         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
1017         PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
1018         PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
1019         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
1020         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
1021         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
1022
1023         /* IPSR4 */
1024         PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
1025         PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
1026         PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
1027         PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
1028         PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
1029         PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
1030         PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
1031         PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
1032         PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1033         PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1034         PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
1035         PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
1036         PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1037         PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1038         PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1039         PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
1040         PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
1041         PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1042         PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
1043         PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
1044         PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1045         PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1046         PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
1047         PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
1048         PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
1049         PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1050         PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1051         PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1052         PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
1053         PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
1054         PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1055         PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1056         PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
1057         PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
1058         PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
1059         PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
1060         PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
1061         PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1062         PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
1063         PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1064         PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
1065         PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1066         PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
1067         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1068         PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1069         PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1070         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1071         PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
1072
1073         /* IPSR5 */
1074         PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
1075         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1076         PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1077         PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1078         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1079         PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
1080         PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
1081         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1082         PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1083         PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1084         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1085         PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
1086         PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
1087         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1088         PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1089         PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1090         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1091         PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
1092         PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
1093         PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1094         PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1095         PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
1096         PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
1097         PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1098         PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1099         PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
1100         PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1101         PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1102         PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1103         PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1104         PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1105         PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1106         PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1107         PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1108         PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1109         PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1110         PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1111         PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1112         PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1113         PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1114         PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1115         PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1116         PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1117         PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1118         PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1119         PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1120         PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1121         PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1122         PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1123
1124         /* IPSR6 */
1125         PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1126         PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1127         PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1128         PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1129         PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
1130         PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1131         PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
1132         PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1133         PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1134         PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1135         PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1136         PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1137         PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
1138         PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1139         PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
1140         PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1141         PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
1142         PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1143         PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
1144         PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
1145         PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1146         PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
1147         PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
1148         PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1149         PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
1150         PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
1151         PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
1152         PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1153         PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
1154         PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
1155         PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1156         PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
1157         PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1158         PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
1159         PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
1160         PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1161         PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
1162         PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1163         PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
1164         PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1165         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1166         PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
1167         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1168         PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
1169         PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1170         PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1171         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1172         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1173         PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
1174         PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1175         PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1176         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1177         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1178
1179         /* IPSR7 */
1180         PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
1181         PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1182         PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1183         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1184         PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1185         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1186         PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
1187         PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
1188         PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1189         PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1190         PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1191         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1192         PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
1193         PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
1194         PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1195         PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1196         PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1197         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1198         PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
1199         PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
1200         PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1201         PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
1202         PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
1203         PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1204         PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
1205         PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
1206         PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1207         PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
1208         PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
1209         PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1210         PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
1211         PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
1212         PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1213         PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
1214         PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
1215         PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1216         PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
1217         PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
1218         PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1219         PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1220         PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1221         PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1222         PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
1223         PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
1224         PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1225         PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1226         PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1227         PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1228         PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
1229         PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
1230         PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1231         PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
1232         PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1233         PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1234
1235         /* IPSR8 */
1236         PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
1237         PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
1238         PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1239         PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1240         PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
1241         PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
1242         PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1243         PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1244         PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1245         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1246         PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
1247         PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
1248         PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1249         PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1250         PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1251         PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1252         PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
1253         PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
1254         PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1255         PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1256         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1257         PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
1258         PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
1259         PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1260         PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1261         PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1262         PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
1263         PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
1264         PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1265         PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1266         PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1267         PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1268         PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
1269         PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
1270         PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1271         PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1272         PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1273         PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1274         PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
1275         PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
1276         PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1277         PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
1278         PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1279         PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1280         PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
1281         PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
1282         PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1283         PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
1284         PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
1285         PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1286         PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1287         PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
1288         PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
1289         PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1290         PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1291         PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1292
1293         /* IPSR9 */
1294         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
1295         PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
1296         PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
1297         PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1298         PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1299         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
1300         PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
1301         PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
1302         PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1303         PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1304         PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1305         PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
1306         PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
1307         PINMUX_IPSR_GPSR(IP9_7, QCLK),
1308         PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
1309         PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
1310         PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1311         PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1312         PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
1313         PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
1314         PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1315         PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
1316         PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1317         PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
1318         PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1319         PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
1320         PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1321         PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1322         PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
1323         PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
1324         PINMUX_IPSR_GPSR(IP9_16, QPOLA),
1325         PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
1326         PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
1327         PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
1328         PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
1329         PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1330         PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1331         PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1332         PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
1333         PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1334         PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1335         PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1336         PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
1337         PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1338         PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1339         PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1340         PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
1341         PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1342         PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1343         PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1344         PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
1345         PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1346         PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1347         PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
1348         PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
1349         PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1350         PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
1351         PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1352         PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1353         PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
1354
1355         /* IPSR10 */
1356         PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
1357         PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
1358         PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1359         PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
1360         PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1361         PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1362         PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
1363         PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
1364         PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
1365         PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1366         PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
1367         PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1368         PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1369         PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
1370         PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
1371         PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
1372         PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1373         PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
1374         PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1375         PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1376         PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
1377         PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
1378         PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
1379         PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1380         PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1381         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1382         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1383         PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
1384         PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
1385         PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1386         PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1387         PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1388         PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1389         PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1390         PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
1391         PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
1392         PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1393         PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
1394         PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
1395         PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1396         PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
1397         PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
1398         PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1399         PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1400         PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
1401         PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
1402         PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
1403         PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1404         PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1405         PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
1406         PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
1407         PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
1408         PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1409         PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1410         PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
1411         PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
1412         PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1413         PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1414         PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
1415         PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
1416         PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1417         PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1418         PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
1419
1420         /* IPSR11 */
1421         PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
1422         PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
1423         PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1424         PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1425         PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
1426         PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
1427         PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
1428         PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1429         PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1430         PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
1431         PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
1432         PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1433         PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1434         PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1435         PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
1436         PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1437         PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1438         PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1439         PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
1440         PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1441         PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1442         PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1443         PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1444         PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
1445         PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1446         PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1447         PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1448         PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1449         PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
1450         PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1451         PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1452         PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
1453         PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1454         PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1455         PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
1456         PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1457         PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
1458         PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1459         PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
1460         PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1461         PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
1462         PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1463         PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
1464         PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1465         PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
1466         PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1467         PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
1468         PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1469         PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
1470         PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1471         PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
1472         PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
1473         PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
1474         PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
1475         PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
1476         PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
1477         PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
1478
1479         /* IPSR12 */
1480         PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
1481         PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
1482         PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
1483         PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
1484         PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
1485         PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
1486         PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
1487         PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
1488         PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
1489         PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
1490         PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1491         PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
1492         PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1493         PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
1494         PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
1495         PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1496         PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
1497         PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1498         PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
1499         PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
1500         PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1501         PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1502         PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1503         PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
1504         PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
1505         PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1506         PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1507         PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1508         PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
1509         PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
1510         PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1511         PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1512         PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
1513         PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
1514         PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1515         PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
1516         PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
1517         PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1518         PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
1519         PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
1520         PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1521         PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1522         PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
1523         PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1524         PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1525         PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1526         PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1527         PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
1528         PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1529         PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1530         PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1531
1532         /* IPSR13 */
1533         PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1534         PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
1535         PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1536         PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1537         PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1538         PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1539         PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
1540         PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1541         PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1542         PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1543         PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
1544         PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1545         PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1546         PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1547         PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
1548         PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
1549         PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1550         PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1551         PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
1552         PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1553         PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
1554         PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1555         PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
1556         PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1557         PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
1558         PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1559         PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
1560         PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1561         PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
1562         PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1563         PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
1564         PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1565         PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1566         PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1567         PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1568         PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1569         PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
1570         PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1571         PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1572         PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1573         PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1574         PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1575         PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
1576         PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1577         PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
1578         PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1579         PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
1580         PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1581         PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
1582         PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1583         PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
1584         PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1585         PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
1586         PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
1587         PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
1588         PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
1589
1590         /* IPSR14 */
1591         PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
1592         PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
1593         PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
1594         PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
1595         PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
1596         PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
1597         PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
1598         PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
1599         PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
1600         PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
1601         PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
1602         PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
1603         PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
1604         PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
1605         PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
1606         PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
1607         PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
1608         PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
1609         PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1610         PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1611         PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
1612         PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
1613         PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
1614         PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1615         PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1616         PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1617         PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1618         PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1619         PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1620         PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
1621         PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1622         PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1623         PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1624         PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1625         PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
1626         PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1627         PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1628         PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1629         PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
1630         PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1631         PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1632         PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1633         PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
1634         PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1635         PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1636         PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1637         PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1638         PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1639         PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
1640         PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
1641         PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1642         PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1643         PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1644         PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1645         PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1646         PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
1647         PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
1648
1649         /* IPSR15 */
1650         PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1651         PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1652         PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1653         PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
1654         PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1655         PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1656         PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1657         PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1658         PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1659         PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1660         PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1661         PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1662         PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
1663         PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1664         PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1665         PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1666         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1667         PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
1668         PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
1669         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1670         PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1671         PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1672         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1673         PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
1674         PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
1675         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1676         PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1677         PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1678         PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1679         PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1680         PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1681         PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1682         PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1683         PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1684         PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1685         PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1686         PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1687         PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1688         PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1689         PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
1690         PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1691         PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1692         PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1693         PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1694         PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1695         PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1696         PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1697         PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1698         PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1699         PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1700         PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1701
1702         /* IPSR16 */
1703         PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1704         PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1705         PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
1706         PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1707         PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1708         PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1709         PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1710         PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
1711         PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1712         PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1713         PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1714         PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1715         PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
1716         PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1717         PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1718         PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
1719         PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
1720         PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1721         PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1722         PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
1723         PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
1724         PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1725 };
1726
1727 /*
1728  * Pins not associated with a GPIO port.
1729  */
1730 enum {
1731         GP_ASSIGN_LAST(),
1732         NOGP_ALL(),
1733 };
1734
1735 static const struct sh_pfc_pin pinmux_pins[] = {
1736         PINMUX_GPIO_GP_ALL(),
1737         PINMUX_NOGP_ALL(),
1738 };
1739
1740 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
1741 /* - ADI -------------------------------------------------------------------- */
1742 static const unsigned int adi_common_pins[] = {
1743         /* ADIDATA, ADICS/SAMP, ADICLK */
1744         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
1745 };
1746 static const unsigned int adi_common_mux[] = {
1747         /* ADIDATA, ADICS/SAMP, ADICLK */
1748         ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
1749 };
1750 static const unsigned int adi_chsel0_pins[] = {
1751         /* ADICHS 0 */
1752         RCAR_GP_PIN(6, 27),
1753 };
1754 static const unsigned int adi_chsel0_mux[] = {
1755         /* ADICHS 0 */
1756         ADICHS0_MARK,
1757 };
1758 static const unsigned int adi_chsel1_pins[] = {
1759         /* ADICHS 1 */
1760         RCAR_GP_PIN(6, 28),
1761 };
1762 static const unsigned int adi_chsel1_mux[] = {
1763         /* ADICHS 1 */
1764         ADICHS1_MARK,
1765 };
1766 static const unsigned int adi_chsel2_pins[] = {
1767         /* ADICHS 2 */
1768         RCAR_GP_PIN(6, 29),
1769 };
1770 static const unsigned int adi_chsel2_mux[] = {
1771         /* ADICHS 2 */
1772         ADICHS2_MARK,
1773 };
1774 static const unsigned int adi_common_b_pins[] = {
1775         /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1776         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1777 };
1778 static const unsigned int adi_common_b_mux[] = {
1779         /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1780         ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
1781 };
1782 static const unsigned int adi_chsel0_b_pins[] = {
1783         /* ADICHS B 0 */
1784         RCAR_GP_PIN(5, 28),
1785 };
1786 static const unsigned int adi_chsel0_b_mux[] = {
1787         /* ADICHS B 0 */
1788         ADICHS0_B_MARK,
1789 };
1790 static const unsigned int adi_chsel1_b_pins[] = {
1791         /* ADICHS B 1 */
1792         RCAR_GP_PIN(5, 29),
1793 };
1794 static const unsigned int adi_chsel1_b_mux[] = {
1795         /* ADICHS B 1 */
1796         ADICHS1_B_MARK,
1797 };
1798 static const unsigned int adi_chsel2_b_pins[] = {
1799         /* ADICHS B 2 */
1800         RCAR_GP_PIN(5, 30),
1801 };
1802 static const unsigned int adi_chsel2_b_mux[] = {
1803         /* ADICHS B 2 */
1804         ADICHS2_B_MARK,
1805 };
1806 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
1807
1808 /* - Audio Clock ------------------------------------------------------------ */
1809 static const unsigned int audio_clk_a_pins[] = {
1810         /* CLK */
1811         RCAR_GP_PIN(2, 28),
1812 };
1813
1814 static const unsigned int audio_clk_a_mux[] = {
1815         AUDIO_CLKA_MARK,
1816 };
1817
1818 static const unsigned int audio_clk_b_pins[] = {
1819         /* CLK */
1820         RCAR_GP_PIN(2, 29),
1821 };
1822
1823 static const unsigned int audio_clk_b_mux[] = {
1824         AUDIO_CLKB_MARK,
1825 };
1826
1827 static const unsigned int audio_clk_b_b_pins[] = {
1828         /* CLK */
1829         RCAR_GP_PIN(7, 20),
1830 };
1831
1832 static const unsigned int audio_clk_b_b_mux[] = {
1833         AUDIO_CLKB_B_MARK,
1834 };
1835
1836 static const unsigned int audio_clk_c_pins[] = {
1837         /* CLK */
1838         RCAR_GP_PIN(2, 30),
1839 };
1840
1841 static const unsigned int audio_clk_c_mux[] = {
1842         AUDIO_CLKC_MARK,
1843 };
1844
1845 static const unsigned int audio_clkout_pins[] = {
1846         /* CLK */
1847         RCAR_GP_PIN(2, 31),
1848 };
1849
1850 static const unsigned int audio_clkout_mux[] = {
1851         AUDIO_CLKOUT_MARK,
1852 };
1853
1854 /* - AVB -------------------------------------------------------------------- */
1855 static const unsigned int avb_link_pins[] = {
1856         RCAR_GP_PIN(5, 14),
1857 };
1858 static const unsigned int avb_link_mux[] = {
1859         AVB_LINK_MARK,
1860 };
1861 static const unsigned int avb_magic_pins[] = {
1862         RCAR_GP_PIN(5, 11),
1863 };
1864 static const unsigned int avb_magic_mux[] = {
1865         AVB_MAGIC_MARK,
1866 };
1867 static const unsigned int avb_phy_int_pins[] = {
1868         RCAR_GP_PIN(5, 16),
1869 };
1870 static const unsigned int avb_phy_int_mux[] = {
1871         AVB_PHY_INT_MARK,
1872 };
1873 static const unsigned int avb_mdio_pins[] = {
1874         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1875 };
1876 static const unsigned int avb_mdio_mux[] = {
1877         AVB_MDC_MARK, AVB_MDIO_MARK,
1878 };
1879 static const unsigned int avb_mii_pins[] = {
1880         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1881         RCAR_GP_PIN(5, 21),
1882
1883         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1884         RCAR_GP_PIN(5, 3),
1885
1886         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1887         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1888         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1889 };
1890 static const unsigned int avb_mii_mux[] = {
1891         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1892         AVB_TXD3_MARK,
1893
1894         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1895         AVB_RXD3_MARK,
1896
1897         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1898         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1899         AVB_TX_CLK_MARK, AVB_COL_MARK,
1900 };
1901 static const unsigned int avb_gmii_pins[] = {
1902         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1903         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1904         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1905
1906         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1907         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1908         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1909
1910         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1911         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1912         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1913         RCAR_GP_PIN(5, 29),
1914 };
1915 static const unsigned int avb_gmii_mux[] = {
1916         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1917         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1918         AVB_TXD6_MARK, AVB_TXD7_MARK,
1919
1920         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1921         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1922         AVB_RXD6_MARK, AVB_RXD7_MARK,
1923
1924         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1925         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1926         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1927         AVB_COL_MARK,
1928 };
1929
1930 /* - CAN -------------------------------------------------------------------- */
1931
1932 static const unsigned int can0_data_pins[] = {
1933         /* TX, RX */
1934         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1935 };
1936
1937 static const unsigned int can0_data_mux[] = {
1938         CAN0_TX_MARK, CAN0_RX_MARK,
1939 };
1940
1941 static const unsigned int can0_data_b_pins[] = {
1942         /* TX, RX */
1943         RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1944 };
1945
1946 static const unsigned int can0_data_b_mux[] = {
1947         CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1948 };
1949
1950 static const unsigned int can0_data_c_pins[] = {
1951         /* TX, RX */
1952         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1953 };
1954
1955 static const unsigned int can0_data_c_mux[] = {
1956         CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1957 };
1958
1959 static const unsigned int can0_data_d_pins[] = {
1960         /* TX, RX */
1961         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1962 };
1963
1964 static const unsigned int can0_data_d_mux[] = {
1965         CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1966 };
1967
1968 static const unsigned int can0_data_e_pins[] = {
1969         /* TX, RX */
1970         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1971 };
1972
1973 static const unsigned int can0_data_e_mux[] = {
1974         CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1975 };
1976
1977 static const unsigned int can0_data_f_pins[] = {
1978         /* TX, RX */
1979         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1980 };
1981
1982 static const unsigned int can0_data_f_mux[] = {
1983         CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1984 };
1985
1986 static const unsigned int can1_data_pins[] = {
1987         /* TX, RX */
1988          RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1989 };
1990
1991 static const unsigned int can1_data_mux[] = {
1992         CAN1_TX_MARK, CAN1_RX_MARK,
1993 };
1994
1995 static const unsigned int can1_data_b_pins[] = {
1996         /* TX, RX */
1997         RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1998 };
1999
2000 static const unsigned int can1_data_b_mux[] = {
2001         CAN1_TX_B_MARK, CAN1_RX_B_MARK,
2002 };
2003
2004 static const unsigned int can1_data_c_pins[] = {
2005         /* TX, RX */
2006         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
2007 };
2008
2009 static const unsigned int can1_data_c_mux[] = {
2010         CAN1_TX_C_MARK, CAN1_RX_C_MARK,
2011 };
2012
2013 static const unsigned int can1_data_d_pins[] = {
2014         /* TX, RX */
2015          RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
2016 };
2017
2018 static const unsigned int can1_data_d_mux[] = {
2019         CAN1_TX_D_MARK, CAN1_RX_D_MARK,
2020 };
2021
2022 static const unsigned int can_clk_pins[] = {
2023         /* CLK */
2024         RCAR_GP_PIN(7, 2),
2025 };
2026
2027 static const unsigned int can_clk_mux[] = {
2028         CAN_CLK_MARK,
2029 };
2030
2031 static const unsigned int can_clk_b_pins[] = {
2032         /* CLK */
2033         RCAR_GP_PIN(5, 21),
2034 };
2035
2036 static const unsigned int can_clk_b_mux[] = {
2037         CAN_CLK_B_MARK,
2038 };
2039
2040 static const unsigned int can_clk_c_pins[] = {
2041         /* CLK */
2042         RCAR_GP_PIN(4, 30),
2043 };
2044
2045 static const unsigned int can_clk_c_mux[] = {
2046         CAN_CLK_C_MARK,
2047 };
2048
2049 static const unsigned int can_clk_d_pins[] = {
2050         /* CLK */
2051         RCAR_GP_PIN(7, 19),
2052 };
2053
2054 static const unsigned int can_clk_d_mux[] = {
2055         CAN_CLK_D_MARK,
2056 };
2057
2058 /* - DU --------------------------------------------------------------------- */
2059 static const unsigned int du_rgb666_pins[] = {
2060         /* R[7:2], G[7:2], B[7:2] */
2061         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
2062         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
2063         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2064         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2065         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2066         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2067 };
2068 static const unsigned int du_rgb666_mux[] = {
2069         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2070         DU1_DR3_MARK, DU1_DR2_MARK,
2071         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2072         DU1_DG3_MARK, DU1_DG2_MARK,
2073         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2074         DU1_DB3_MARK, DU1_DB2_MARK,
2075 };
2076 static const unsigned int du_rgb888_pins[] = {
2077         /* R[7:0], G[7:0], B[7:0] */
2078         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
2079         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
2080         RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
2081         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2082         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2083         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
2084         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2085         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2086         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2087 };
2088 static const unsigned int du_rgb888_mux[] = {
2089         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2090         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
2091         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2092         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
2093         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2094         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
2095 };
2096 static const unsigned int du_clk_out_0_pins[] = {
2097         /* CLKOUT */
2098         RCAR_GP_PIN(3, 25),
2099 };
2100 static const unsigned int du_clk_out_0_mux[] = {
2101         DU1_DOTCLKOUT0_MARK
2102 };
2103 static const unsigned int du_clk_out_1_pins[] = {
2104         /* CLKOUT */
2105         RCAR_GP_PIN(3, 26),
2106 };
2107 static const unsigned int du_clk_out_1_mux[] = {
2108         DU1_DOTCLKOUT1_MARK
2109 };
2110 static const unsigned int du_sync_pins[] = {
2111         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2112         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
2113 };
2114 static const unsigned int du_sync_mux[] = {
2115         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
2116 };
2117 static const unsigned int du_oddf_pins[] = {
2118         /* EXDISP/EXODDF/EXCDE */
2119         RCAR_GP_PIN(3, 29),
2120 };
2121 static const unsigned int du_oddf_mux[] = {
2122         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
2123 };
2124 static const unsigned int du_cde_pins[] = {
2125         /* CDE */
2126         RCAR_GP_PIN(3, 31),
2127 };
2128 static const unsigned int du_cde_mux[] = {
2129         DU1_CDE_MARK,
2130 };
2131 static const unsigned int du_disp_pins[] = {
2132         /* DISP */
2133         RCAR_GP_PIN(3, 30),
2134 };
2135 static const unsigned int du_disp_mux[] = {
2136         DU1_DISP_MARK,
2137 };
2138 static const unsigned int du0_clk_in_pins[] = {
2139         /* CLKIN */
2140         RCAR_GP_PIN(6, 31),
2141 };
2142 static const unsigned int du0_clk_in_mux[] = {
2143         DU0_DOTCLKIN_MARK
2144 };
2145 static const unsigned int du1_clk_in_pins[] = {
2146         /* CLKIN */
2147         RCAR_GP_PIN(3, 24),
2148 };
2149 static const unsigned int du1_clk_in_mux[] = {
2150         DU1_DOTCLKIN_MARK
2151 };
2152 static const unsigned int du1_clk_in_b_pins[] = {
2153         /* CLKIN */
2154         RCAR_GP_PIN(7, 19),
2155 };
2156 static const unsigned int du1_clk_in_b_mux[] = {
2157         DU1_DOTCLKIN_B_MARK,
2158 };
2159 static const unsigned int du1_clk_in_c_pins[] = {
2160         /* CLKIN */
2161         RCAR_GP_PIN(7, 20),
2162 };
2163 static const unsigned int du1_clk_in_c_mux[] = {
2164         DU1_DOTCLKIN_C_MARK,
2165 };
2166 /* - ETH -------------------------------------------------------------------- */
2167 static const unsigned int eth_link_pins[] = {
2168         /* LINK */
2169         RCAR_GP_PIN(5, 18),
2170 };
2171 static const unsigned int eth_link_mux[] = {
2172         ETH_LINK_MARK,
2173 };
2174 static const unsigned int eth_magic_pins[] = {
2175         /* MAGIC */
2176         RCAR_GP_PIN(5, 22),
2177 };
2178 static const unsigned int eth_magic_mux[] = {
2179         ETH_MAGIC_MARK,
2180 };
2181 static const unsigned int eth_mdio_pins[] = {
2182         /* MDC, MDIO */
2183         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2184 };
2185 static const unsigned int eth_mdio_mux[] = {
2186         ETH_MDC_MARK, ETH_MDIO_MARK,
2187 };
2188 static const unsigned int eth_rmii_pins[] = {
2189         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2190         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2191         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2192         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2193 };
2194 static const unsigned int eth_rmii_mux[] = {
2195         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2196         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2197 };
2198
2199 /* - HSCIF0 ----------------------------------------------------------------- */
2200 static const unsigned int hscif0_data_pins[] = {
2201         /* RX, TX */
2202         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2203 };
2204 static const unsigned int hscif0_data_mux[] = {
2205         HRX0_MARK, HTX0_MARK,
2206 };
2207 static const unsigned int hscif0_clk_pins[] = {
2208         /* SCK */
2209         RCAR_GP_PIN(7, 2),
2210 };
2211 static const unsigned int hscif0_clk_mux[] = {
2212         HSCK0_MARK,
2213 };
2214 static const unsigned int hscif0_ctrl_pins[] = {
2215         /* RTS, CTS */
2216         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2217 };
2218 static const unsigned int hscif0_ctrl_mux[] = {
2219         HRTS0_N_MARK, HCTS0_N_MARK,
2220 };
2221 static const unsigned int hscif0_data_b_pins[] = {
2222         /* RX, TX */
2223         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2224 };
2225 static const unsigned int hscif0_data_b_mux[] = {
2226         HRX0_B_MARK, HTX0_B_MARK,
2227 };
2228 static const unsigned int hscif0_ctrl_b_pins[] = {
2229         /* RTS, CTS */
2230         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2231 };
2232 static const unsigned int hscif0_ctrl_b_mux[] = {
2233         HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2234 };
2235 static const unsigned int hscif0_data_c_pins[] = {
2236         /* RX, TX */
2237         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2238 };
2239 static const unsigned int hscif0_data_c_mux[] = {
2240         HRX0_C_MARK, HTX0_C_MARK,
2241 };
2242 static const unsigned int hscif0_clk_c_pins[] = {
2243         /* SCK */
2244         RCAR_GP_PIN(5, 31),
2245 };
2246 static const unsigned int hscif0_clk_c_mux[] = {
2247         HSCK0_C_MARK,
2248 };
2249 /* - HSCIF1 ----------------------------------------------------------------- */
2250 static const unsigned int hscif1_data_pins[] = {
2251         /* RX, TX */
2252         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2253 };
2254 static const unsigned int hscif1_data_mux[] = {
2255         HRX1_MARK, HTX1_MARK,
2256 };
2257 static const unsigned int hscif1_clk_pins[] = {
2258         /* SCK */
2259         RCAR_GP_PIN(7, 7),
2260 };
2261 static const unsigned int hscif1_clk_mux[] = {
2262         HSCK1_MARK,
2263 };
2264 static const unsigned int hscif1_ctrl_pins[] = {
2265         /* RTS, CTS */
2266         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2267 };
2268 static const unsigned int hscif1_ctrl_mux[] = {
2269         HRTS1_N_MARK, HCTS1_N_MARK,
2270 };
2271 static const unsigned int hscif1_data_b_pins[] = {
2272         /* RX, TX */
2273         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2274 };
2275 static const unsigned int hscif1_data_b_mux[] = {
2276         HRX1_B_MARK, HTX1_B_MARK,
2277 };
2278 static const unsigned int hscif1_data_c_pins[] = {
2279         /* RX, TX */
2280         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2281 };
2282 static const unsigned int hscif1_data_c_mux[] = {
2283         HRX1_C_MARK, HTX1_C_MARK,
2284 };
2285 static const unsigned int hscif1_clk_c_pins[] = {
2286         /* SCK */
2287         RCAR_GP_PIN(7, 16),
2288 };
2289 static const unsigned int hscif1_clk_c_mux[] = {
2290         HSCK1_C_MARK,
2291 };
2292 static const unsigned int hscif1_ctrl_c_pins[] = {
2293         /* RTS, CTS */
2294         RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2295 };
2296 static const unsigned int hscif1_ctrl_c_mux[] = {
2297         HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2298 };
2299 static const unsigned int hscif1_data_d_pins[] = {
2300         /* RX, TX */
2301         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2302 };
2303 static const unsigned int hscif1_data_d_mux[] = {
2304         HRX1_D_MARK, HTX1_D_MARK,
2305 };
2306 static const unsigned int hscif1_data_e_pins[] = {
2307         /* RX, TX */
2308         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2309 };
2310 static const unsigned int hscif1_data_e_mux[] = {
2311         HRX1_C_MARK, HTX1_C_MARK,
2312 };
2313 static const unsigned int hscif1_clk_e_pins[] = {
2314         /* SCK */
2315         RCAR_GP_PIN(2, 6),
2316 };
2317 static const unsigned int hscif1_clk_e_mux[] = {
2318         HSCK1_E_MARK,
2319 };
2320 static const unsigned int hscif1_ctrl_e_pins[] = {
2321         /* RTS, CTS */
2322         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2323 };
2324 static const unsigned int hscif1_ctrl_e_mux[] = {
2325         HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2326 };
2327 /* - HSCIF2 ----------------------------------------------------------------- */
2328 static const unsigned int hscif2_data_pins[] = {
2329         /* RX, TX */
2330         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2331 };
2332 static const unsigned int hscif2_data_mux[] = {
2333         HRX2_MARK, HTX2_MARK,
2334 };
2335 static const unsigned int hscif2_clk_pins[] = {
2336         /* SCK */
2337         RCAR_GP_PIN(4, 15),
2338 };
2339 static const unsigned int hscif2_clk_mux[] = {
2340         HSCK2_MARK,
2341 };
2342 static const unsigned int hscif2_ctrl_pins[] = {
2343         /* RTS, CTS */
2344         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2345 };
2346 static const unsigned int hscif2_ctrl_mux[] = {
2347         HRTS2_N_MARK, HCTS2_N_MARK,
2348 };
2349 static const unsigned int hscif2_data_b_pins[] = {
2350         /* RX, TX */
2351         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2352 };
2353 static const unsigned int hscif2_data_b_mux[] = {
2354         HRX2_B_MARK, HTX2_B_MARK,
2355 };
2356 static const unsigned int hscif2_ctrl_b_pins[] = {
2357         /* RTS, CTS */
2358         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2359 };
2360 static const unsigned int hscif2_ctrl_b_mux[] = {
2361         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2362 };
2363 static const unsigned int hscif2_data_c_pins[] = {
2364         /* RX, TX */
2365         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2366 };
2367 static const unsigned int hscif2_data_c_mux[] = {
2368         HRX2_C_MARK, HTX2_C_MARK,
2369 };
2370 static const unsigned int hscif2_clk_c_pins[] = {
2371         /* SCK */
2372         RCAR_GP_PIN(5, 31),
2373 };
2374 static const unsigned int hscif2_clk_c_mux[] = {
2375         HSCK2_C_MARK,
2376 };
2377 static const unsigned int hscif2_data_d_pins[] = {
2378         /* RX, TX */
2379         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2380 };
2381 static const unsigned int hscif2_data_d_mux[] = {
2382         HRX2_B_MARK, HTX2_D_MARK,
2383 };
2384 /* - I2C0 ------------------------------------------------------------------- */
2385 static const unsigned int i2c0_pins[] = {
2386         /* SCL, SDA */
2387         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2388 };
2389 static const unsigned int i2c0_mux[] = {
2390         I2C0_SCL_MARK, I2C0_SDA_MARK,
2391 };
2392 static const unsigned int i2c0_b_pins[] = {
2393         /* SCL, SDA */
2394         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2395 };
2396 static const unsigned int i2c0_b_mux[] = {
2397         I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2398 };
2399 static const unsigned int i2c0_c_pins[] = {
2400         /* SCL, SDA */
2401         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2402 };
2403 static const unsigned int i2c0_c_mux[] = {
2404         I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2405 };
2406 /* - I2C1 ------------------------------------------------------------------- */
2407 static const unsigned int i2c1_pins[] = {
2408         /* SCL, SDA */
2409         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2410 };
2411 static const unsigned int i2c1_mux[] = {
2412         I2C1_SCL_MARK, I2C1_SDA_MARK,
2413 };
2414 static const unsigned int i2c1_b_pins[] = {
2415         /* SCL, SDA */
2416         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2417 };
2418 static const unsigned int i2c1_b_mux[] = {
2419         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2420 };
2421 static const unsigned int i2c1_c_pins[] = {
2422         /* SCL, SDA */
2423         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2424 };
2425 static const unsigned int i2c1_c_mux[] = {
2426         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2427 };
2428 static const unsigned int i2c1_d_pins[] = {
2429         /* SCL, SDA */
2430         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2431 };
2432 static const unsigned int i2c1_d_mux[] = {
2433         I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2434 };
2435 static const unsigned int i2c1_e_pins[] = {
2436         /* SCL, SDA */
2437         RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2438 };
2439 static const unsigned int i2c1_e_mux[] = {
2440         I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2441 };
2442 /* - I2C2 ------------------------------------------------------------------- */
2443 static const unsigned int i2c2_pins[] = {
2444         /* SCL, SDA */
2445         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2446 };
2447 static const unsigned int i2c2_mux[] = {
2448         I2C2_SCL_MARK, I2C2_SDA_MARK,
2449 };
2450 static const unsigned int i2c2_b_pins[] = {
2451         /* SCL, SDA */
2452         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2453 };
2454 static const unsigned int i2c2_b_mux[] = {
2455         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2456 };
2457 static const unsigned int i2c2_c_pins[] = {
2458         /* SCL, SDA */
2459         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2460 };
2461 static const unsigned int i2c2_c_mux[] = {
2462         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2463 };
2464 static const unsigned int i2c2_d_pins[] = {
2465         /* SCL, SDA */
2466         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2467 };
2468 static const unsigned int i2c2_d_mux[] = {
2469         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2470 };
2471 /* - I2C3 ------------------------------------------------------------------- */
2472 static const unsigned int i2c3_pins[] = {
2473         /* SCL, SDA */
2474         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2475 };
2476 static const unsigned int i2c3_mux[] = {
2477         I2C3_SCL_MARK, I2C3_SDA_MARK,
2478 };
2479 static const unsigned int i2c3_b_pins[] = {
2480         /* SCL, SDA */
2481         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2482 };
2483 static const unsigned int i2c3_b_mux[] = {
2484         I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2485 };
2486 static const unsigned int i2c3_c_pins[] = {
2487         /* SCL, SDA */
2488         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2489 };
2490 static const unsigned int i2c3_c_mux[] = {
2491         I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2492 };
2493 static const unsigned int i2c3_d_pins[] = {
2494         /* SCL, SDA */
2495         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2496 };
2497 static const unsigned int i2c3_d_mux[] = {
2498         I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2499 };
2500 /* - I2C4 ------------------------------------------------------------------- */
2501 static const unsigned int i2c4_pins[] = {
2502         /* SCL, SDA */
2503         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2504 };
2505 static const unsigned int i2c4_mux[] = {
2506         I2C4_SCL_MARK, I2C4_SDA_MARK,
2507 };
2508 static const unsigned int i2c4_b_pins[] = {
2509         /* SCL, SDA */
2510         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2511 };
2512 static const unsigned int i2c4_b_mux[] = {
2513         I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2514 };
2515 static const unsigned int i2c4_c_pins[] = {
2516         /* SCL, SDA */
2517         RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2518 };
2519 static const unsigned int i2c4_c_mux[] = {
2520         I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2521 };
2522 /* - I2C7 ------------------------------------------------------------------- */
2523 static const unsigned int i2c7_pins[] = {
2524         /* SCL, SDA */
2525         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2526 };
2527 static const unsigned int i2c7_mux[] = {
2528         IIC0_SCL_MARK, IIC0_SDA_MARK,
2529 };
2530 static const unsigned int i2c7_b_pins[] = {
2531         /* SCL, SDA */
2532         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2533 };
2534 static const unsigned int i2c7_b_mux[] = {
2535         IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
2536 };
2537 static const unsigned int i2c7_c_pins[] = {
2538         /* SCL, SDA */
2539         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2540 };
2541 static const unsigned int i2c7_c_mux[] = {
2542         IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
2543 };
2544 /* - I2C8 ------------------------------------------------------------------- */
2545 static const unsigned int i2c8_pins[] = {
2546         /* SCL, SDA */
2547         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2548 };
2549 static const unsigned int i2c8_mux[] = {
2550         IIC1_SCL_MARK, IIC1_SDA_MARK,
2551 };
2552 static const unsigned int i2c8_b_pins[] = {
2553         /* SCL, SDA */
2554         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2555 };
2556 static const unsigned int i2c8_b_mux[] = {
2557         IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2558 };
2559 static const unsigned int i2c8_c_pins[] = {
2560         /* SCL, SDA */
2561         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2562 };
2563 static const unsigned int i2c8_c_mux[] = {
2564         IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2565 };
2566 /* - INTC ------------------------------------------------------------------- */
2567 static const unsigned int intc_irq0_pins[] = {
2568         /* IRQ */
2569         RCAR_GP_PIN(7, 10),
2570 };
2571 static const unsigned int intc_irq0_mux[] = {
2572         IRQ0_MARK,
2573 };
2574 static const unsigned int intc_irq1_pins[] = {
2575         /* IRQ */
2576         RCAR_GP_PIN(7, 11),
2577 };
2578 static const unsigned int intc_irq1_mux[] = {
2579         IRQ1_MARK,
2580 };
2581 static const unsigned int intc_irq2_pins[] = {
2582         /* IRQ */
2583         RCAR_GP_PIN(7, 12),
2584 };
2585 static const unsigned int intc_irq2_mux[] = {
2586         IRQ2_MARK,
2587 };
2588 static const unsigned int intc_irq3_pins[] = {
2589         /* IRQ */
2590         RCAR_GP_PIN(7, 13),
2591 };
2592 static const unsigned int intc_irq3_mux[] = {
2593         IRQ3_MARK,
2594 };
2595
2596 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
2597 /* - MLB+ ------------------------------------------------------------------- */
2598 static const unsigned int mlb_3pin_pins[] = {
2599         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2600 };
2601 static const unsigned int mlb_3pin_mux[] = {
2602         MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2603 };
2604 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
2605
2606 /* - MMCIF ------------------------------------------------------------------ */
2607 static const unsigned int mmc_data1_pins[] = {
2608         /* D[0] */
2609         RCAR_GP_PIN(6, 18),
2610 };
2611 static const unsigned int mmc_data1_mux[] = {
2612         MMC_D0_MARK,
2613 };
2614 static const unsigned int mmc_data4_pins[] = {
2615         /* D[0:3] */
2616         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2617         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2618 };
2619 static const unsigned int mmc_data4_mux[] = {
2620         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2621 };
2622 static const unsigned int mmc_data8_pins[] = {
2623         /* D[0:7] */
2624         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2625         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2626         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2627         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2628 };
2629 static const unsigned int mmc_data8_mux[] = {
2630         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2631         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2632 };
2633 static const unsigned int mmc_data8_b_pins[] = {
2634         /* D[0:7] */
2635         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2636         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2637         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2638         RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
2639 };
2640 static const unsigned int mmc_data8_b_mux[] = {
2641         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2642         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
2643 };
2644 static const unsigned int mmc_ctrl_pins[] = {
2645         /* CLK, CMD */
2646         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2647 };
2648 static const unsigned int mmc_ctrl_mux[] = {
2649         MMC_CLK_MARK, MMC_CMD_MARK,
2650 };
2651 /* - MSIOF0 ----------------------------------------------------------------- */
2652 static const unsigned int msiof0_clk_pins[] = {
2653         /* SCK */
2654         RCAR_GP_PIN(6, 24),
2655 };
2656 static const unsigned int msiof0_clk_mux[] = {
2657         MSIOF0_SCK_MARK,
2658 };
2659 static const unsigned int msiof0_sync_pins[] = {
2660         /* SYNC */
2661         RCAR_GP_PIN(6, 25),
2662 };
2663 static const unsigned int msiof0_sync_mux[] = {
2664         MSIOF0_SYNC_MARK,
2665 };
2666 static const unsigned int msiof0_ss1_pins[] = {
2667         /* SS1 */
2668         RCAR_GP_PIN(6, 28),
2669 };
2670 static const unsigned int msiof0_ss1_mux[] = {
2671         MSIOF0_SS1_MARK,
2672 };
2673 static const unsigned int msiof0_ss2_pins[] = {
2674         /* SS2 */
2675         RCAR_GP_PIN(6, 29),
2676 };
2677 static const unsigned int msiof0_ss2_mux[] = {
2678         MSIOF0_SS2_MARK,
2679 };
2680 static const unsigned int msiof0_rx_pins[] = {
2681         /* RXD */
2682         RCAR_GP_PIN(6, 27),
2683 };
2684 static const unsigned int msiof0_rx_mux[] = {
2685         MSIOF0_RXD_MARK,
2686 };
2687 static const unsigned int msiof0_tx_pins[] = {
2688         /* TXD */
2689         RCAR_GP_PIN(6, 26),
2690 };
2691 static const unsigned int msiof0_tx_mux[] = {
2692         MSIOF0_TXD_MARK,
2693 };
2694
2695 static const unsigned int msiof0_clk_b_pins[] = {
2696         /* SCK */
2697         RCAR_GP_PIN(0, 16),
2698 };
2699 static const unsigned int msiof0_clk_b_mux[] = {
2700         MSIOF0_SCK_B_MARK,
2701 };
2702 static const unsigned int msiof0_sync_b_pins[] = {
2703         /* SYNC */
2704         RCAR_GP_PIN(0, 17),
2705 };
2706 static const unsigned int msiof0_sync_b_mux[] = {
2707         MSIOF0_SYNC_B_MARK,
2708 };
2709 static const unsigned int msiof0_ss1_b_pins[] = {
2710         /* SS1 */
2711         RCAR_GP_PIN(0, 18),
2712 };
2713 static const unsigned int msiof0_ss1_b_mux[] = {
2714         MSIOF0_SS1_B_MARK,
2715 };
2716 static const unsigned int msiof0_ss2_b_pins[] = {
2717         /* SS2 */
2718         RCAR_GP_PIN(0, 19),
2719 };
2720 static const unsigned int msiof0_ss2_b_mux[] = {
2721         MSIOF0_SS2_B_MARK,
2722 };
2723 static const unsigned int msiof0_rx_b_pins[] = {
2724         /* RXD */
2725         RCAR_GP_PIN(0, 21),
2726 };
2727 static const unsigned int msiof0_rx_b_mux[] = {
2728         MSIOF0_RXD_B_MARK,
2729 };
2730 static const unsigned int msiof0_tx_b_pins[] = {
2731         /* TXD */
2732         RCAR_GP_PIN(0, 20),
2733 };
2734 static const unsigned int msiof0_tx_b_mux[] = {
2735         MSIOF0_TXD_B_MARK,
2736 };
2737
2738 static const unsigned int msiof0_clk_c_pins[] = {
2739         /* SCK */
2740         RCAR_GP_PIN(5, 26),
2741 };
2742 static const unsigned int msiof0_clk_c_mux[] = {
2743         MSIOF0_SCK_C_MARK,
2744 };
2745 static const unsigned int msiof0_sync_c_pins[] = {
2746         /* SYNC */
2747         RCAR_GP_PIN(5, 25),
2748 };
2749 static const unsigned int msiof0_sync_c_mux[] = {
2750         MSIOF0_SYNC_C_MARK,
2751 };
2752 static const unsigned int msiof0_ss1_c_pins[] = {
2753         /* SS1 */
2754         RCAR_GP_PIN(5, 27),
2755 };
2756 static const unsigned int msiof0_ss1_c_mux[] = {
2757         MSIOF0_SS1_C_MARK,
2758 };
2759 static const unsigned int msiof0_ss2_c_pins[] = {
2760         /* SS2 */
2761         RCAR_GP_PIN(5, 28),
2762 };
2763 static const unsigned int msiof0_ss2_c_mux[] = {
2764         MSIOF0_SS2_C_MARK,
2765 };
2766 static const unsigned int msiof0_rx_c_pins[] = {
2767         /* RXD */
2768         RCAR_GP_PIN(5, 29),
2769 };
2770 static const unsigned int msiof0_rx_c_mux[] = {
2771         MSIOF0_RXD_C_MARK,
2772 };
2773 static const unsigned int msiof0_tx_c_pins[] = {
2774         /* TXD */
2775         RCAR_GP_PIN(5, 30),
2776 };
2777 static const unsigned int msiof0_tx_c_mux[] = {
2778         MSIOF0_TXD_C_MARK,
2779 };
2780 /* - MSIOF1 ----------------------------------------------------------------- */
2781 static const unsigned int msiof1_clk_pins[] = {
2782         /* SCK */
2783         RCAR_GP_PIN(0, 22),
2784 };
2785 static const unsigned int msiof1_clk_mux[] = {
2786         MSIOF1_SCK_MARK,
2787 };
2788 static const unsigned int msiof1_sync_pins[] = {
2789         /* SYNC */
2790         RCAR_GP_PIN(0, 23),
2791 };
2792 static const unsigned int msiof1_sync_mux[] = {
2793         MSIOF1_SYNC_MARK,
2794 };
2795 static const unsigned int msiof1_ss1_pins[] = {
2796         /* SS1 */
2797         RCAR_GP_PIN(0, 24),
2798 };
2799 static const unsigned int msiof1_ss1_mux[] = {
2800         MSIOF1_SS1_MARK,
2801 };
2802 static const unsigned int msiof1_ss2_pins[] = {
2803         /* SS2 */
2804         RCAR_GP_PIN(0, 25),
2805 };
2806 static const unsigned int msiof1_ss2_mux[] = {
2807         MSIOF1_SS2_MARK,
2808 };
2809 static const unsigned int msiof1_rx_pins[] = {
2810         /* RXD */
2811         RCAR_GP_PIN(0, 27),
2812 };
2813 static const unsigned int msiof1_rx_mux[] = {
2814         MSIOF1_RXD_MARK,
2815 };
2816 static const unsigned int msiof1_tx_pins[] = {
2817         /* TXD */
2818         RCAR_GP_PIN(0, 26),
2819 };
2820 static const unsigned int msiof1_tx_mux[] = {
2821         MSIOF1_TXD_MARK,
2822 };
2823
2824 static const unsigned int msiof1_clk_b_pins[] = {
2825         /* SCK */
2826         RCAR_GP_PIN(2, 29),
2827 };
2828 static const unsigned int msiof1_clk_b_mux[] = {
2829         MSIOF1_SCK_B_MARK,
2830 };
2831 static const unsigned int msiof1_sync_b_pins[] = {
2832         /* SYNC */
2833         RCAR_GP_PIN(2, 30),
2834 };
2835 static const unsigned int msiof1_sync_b_mux[] = {
2836         MSIOF1_SYNC_B_MARK,
2837 };
2838 static const unsigned int msiof1_ss1_b_pins[] = {
2839         /* SS1 */
2840         RCAR_GP_PIN(2, 31),
2841 };
2842 static const unsigned int msiof1_ss1_b_mux[] = {
2843         MSIOF1_SS1_B_MARK,
2844 };
2845 static const unsigned int msiof1_ss2_b_pins[] = {
2846         /* SS2 */
2847         RCAR_GP_PIN(7, 16),
2848 };
2849 static const unsigned int msiof1_ss2_b_mux[] = {
2850         MSIOF1_SS2_B_MARK,
2851 };
2852 static const unsigned int msiof1_rx_b_pins[] = {
2853         /* RXD */
2854         RCAR_GP_PIN(7, 18),
2855 };
2856 static const unsigned int msiof1_rx_b_mux[] = {
2857         MSIOF1_RXD_B_MARK,
2858 };
2859 static const unsigned int msiof1_tx_b_pins[] = {
2860         /* TXD */
2861         RCAR_GP_PIN(7, 17),
2862 };
2863 static const unsigned int msiof1_tx_b_mux[] = {
2864         MSIOF1_TXD_B_MARK,
2865 };
2866
2867 static const unsigned int msiof1_clk_c_pins[] = {
2868         /* SCK */
2869         RCAR_GP_PIN(2, 15),
2870 };
2871 static const unsigned int msiof1_clk_c_mux[] = {
2872         MSIOF1_SCK_C_MARK,
2873 };
2874 static const unsigned int msiof1_sync_c_pins[] = {
2875         /* SYNC */
2876         RCAR_GP_PIN(2, 16),
2877 };
2878 static const unsigned int msiof1_sync_c_mux[] = {
2879         MSIOF1_SYNC_C_MARK,
2880 };
2881 static const unsigned int msiof1_rx_c_pins[] = {
2882         /* RXD */
2883         RCAR_GP_PIN(2, 18),
2884 };
2885 static const unsigned int msiof1_rx_c_mux[] = {
2886         MSIOF1_RXD_C_MARK,
2887 };
2888 static const unsigned int msiof1_tx_c_pins[] = {
2889         /* TXD */
2890         RCAR_GP_PIN(2, 17),
2891 };
2892 static const unsigned int msiof1_tx_c_mux[] = {
2893         MSIOF1_TXD_C_MARK,
2894 };
2895
2896 static const unsigned int msiof1_clk_d_pins[] = {
2897         /* SCK */
2898         RCAR_GP_PIN(0, 28),
2899 };
2900 static const unsigned int msiof1_clk_d_mux[] = {
2901         MSIOF1_SCK_D_MARK,
2902 };
2903 static const unsigned int msiof1_sync_d_pins[] = {
2904         /* SYNC */
2905         RCAR_GP_PIN(0, 30),
2906 };
2907 static const unsigned int msiof1_sync_d_mux[] = {
2908         MSIOF1_SYNC_D_MARK,
2909 };
2910 static const unsigned int msiof1_ss1_d_pins[] = {
2911         /* SS1 */
2912         RCAR_GP_PIN(0, 29),
2913 };
2914 static const unsigned int msiof1_ss1_d_mux[] = {
2915         MSIOF1_SS1_D_MARK,
2916 };
2917 static const unsigned int msiof1_rx_d_pins[] = {
2918         /* RXD */
2919         RCAR_GP_PIN(0, 27),
2920 };
2921 static const unsigned int msiof1_rx_d_mux[] = {
2922         MSIOF1_RXD_D_MARK,
2923 };
2924 static const unsigned int msiof1_tx_d_pins[] = {
2925         /* TXD */
2926         RCAR_GP_PIN(0, 26),
2927 };
2928 static const unsigned int msiof1_tx_d_mux[] = {
2929         MSIOF1_TXD_D_MARK,
2930 };
2931
2932 static const unsigned int msiof1_clk_e_pins[] = {
2933         /* SCK */
2934         RCAR_GP_PIN(5, 18),
2935 };
2936 static const unsigned int msiof1_clk_e_mux[] = {
2937         MSIOF1_SCK_E_MARK,
2938 };
2939 static const unsigned int msiof1_sync_e_pins[] = {
2940         /* SYNC */
2941         RCAR_GP_PIN(5, 19),
2942 };
2943 static const unsigned int msiof1_sync_e_mux[] = {
2944         MSIOF1_SYNC_E_MARK,
2945 };
2946 static const unsigned int msiof1_rx_e_pins[] = {
2947         /* RXD */
2948         RCAR_GP_PIN(5, 17),
2949 };
2950 static const unsigned int msiof1_rx_e_mux[] = {
2951         MSIOF1_RXD_E_MARK,
2952 };
2953 static const unsigned int msiof1_tx_e_pins[] = {
2954         /* TXD */
2955         RCAR_GP_PIN(5, 20),
2956 };
2957 static const unsigned int msiof1_tx_e_mux[] = {
2958         MSIOF1_TXD_E_MARK,
2959 };
2960 /* - MSIOF2 ----------------------------------------------------------------- */
2961 static const unsigned int msiof2_clk_pins[] = {
2962         /* SCK */
2963         RCAR_GP_PIN(1, 13),
2964 };
2965 static const unsigned int msiof2_clk_mux[] = {
2966         MSIOF2_SCK_MARK,
2967 };
2968 static const unsigned int msiof2_sync_pins[] = {
2969         /* SYNC */
2970         RCAR_GP_PIN(1, 14),
2971 };
2972 static const unsigned int msiof2_sync_mux[] = {
2973         MSIOF2_SYNC_MARK,
2974 };
2975 static const unsigned int msiof2_ss1_pins[] = {
2976         /* SS1 */
2977         RCAR_GP_PIN(1, 17),
2978 };
2979 static const unsigned int msiof2_ss1_mux[] = {
2980         MSIOF2_SS1_MARK,
2981 };
2982 static const unsigned int msiof2_ss2_pins[] = {
2983         /* SS2 */
2984         RCAR_GP_PIN(1, 18),
2985 };
2986 static const unsigned int msiof2_ss2_mux[] = {
2987         MSIOF2_SS2_MARK,
2988 };
2989 static const unsigned int msiof2_rx_pins[] = {
2990         /* RXD */
2991         RCAR_GP_PIN(1, 16),
2992 };
2993 static const unsigned int msiof2_rx_mux[] = {
2994         MSIOF2_RXD_MARK,
2995 };
2996 static const unsigned int msiof2_tx_pins[] = {
2997         /* TXD */
2998         RCAR_GP_PIN(1, 15),
2999 };
3000 static const unsigned int msiof2_tx_mux[] = {
3001         MSIOF2_TXD_MARK,
3002 };
3003
3004 static const unsigned int msiof2_clk_b_pins[] = {
3005         /* SCK */
3006         RCAR_GP_PIN(3, 0),
3007 };
3008 static const unsigned int msiof2_clk_b_mux[] = {
3009         MSIOF2_SCK_B_MARK,
3010 };
3011 static const unsigned int msiof2_sync_b_pins[] = {
3012         /* SYNC */
3013         RCAR_GP_PIN(3, 1),
3014 };
3015 static const unsigned int msiof2_sync_b_mux[] = {
3016         MSIOF2_SYNC_B_MARK,
3017 };
3018 static const unsigned int msiof2_ss1_b_pins[] = {
3019         /* SS1 */
3020         RCAR_GP_PIN(3, 8),
3021 };
3022 static const unsigned int msiof2_ss1_b_mux[] = {
3023         MSIOF2_SS1_B_MARK,
3024 };
3025 static const unsigned int msiof2_ss2_b_pins[] = {
3026         /* SS2 */
3027         RCAR_GP_PIN(3, 9),
3028 };
3029 static const unsigned int msiof2_ss2_b_mux[] = {
3030         MSIOF2_SS2_B_MARK,
3031 };
3032 static const unsigned int msiof2_rx_b_pins[] = {
3033         /* RXD */
3034         RCAR_GP_PIN(3, 17),
3035 };
3036 static const unsigned int msiof2_rx_b_mux[] = {
3037         MSIOF2_RXD_B_MARK,
3038 };
3039 static const unsigned int msiof2_tx_b_pins[] = {
3040         /* TXD */
3041         RCAR_GP_PIN(3, 16),
3042 };
3043 static const unsigned int msiof2_tx_b_mux[] = {
3044         MSIOF2_TXD_B_MARK,
3045 };
3046
3047 static const unsigned int msiof2_clk_c_pins[] = {
3048         /* SCK */
3049         RCAR_GP_PIN(2, 2),
3050 };
3051 static const unsigned int msiof2_clk_c_mux[] = {
3052         MSIOF2_SCK_C_MARK,
3053 };
3054 static const unsigned int msiof2_sync_c_pins[] = {
3055         /* SYNC */
3056         RCAR_GP_PIN(2, 3),
3057 };
3058 static const unsigned int msiof2_sync_c_mux[] = {
3059         MSIOF2_SYNC_C_MARK,
3060 };
3061 static const unsigned int msiof2_rx_c_pins[] = {
3062         /* RXD */
3063         RCAR_GP_PIN(2, 5),
3064 };
3065 static const unsigned int msiof2_rx_c_mux[] = {
3066         MSIOF2_RXD_C_MARK,
3067 };
3068 static const unsigned int msiof2_tx_c_pins[] = {
3069         /* TXD */
3070         RCAR_GP_PIN(2, 4),
3071 };
3072 static const unsigned int msiof2_tx_c_mux[] = {
3073         MSIOF2_TXD_C_MARK,
3074 };
3075
3076 static const unsigned int msiof2_clk_d_pins[] = {
3077         /* SCK */
3078         RCAR_GP_PIN(2, 14),
3079 };
3080 static const unsigned int msiof2_clk_d_mux[] = {
3081         MSIOF2_SCK_D_MARK,
3082 };
3083 static const unsigned int msiof2_sync_d_pins[] = {
3084         /* SYNC */
3085         RCAR_GP_PIN(2, 15),
3086 };
3087 static const unsigned int msiof2_sync_d_mux[] = {
3088         MSIOF2_SYNC_D_MARK,
3089 };
3090 static const unsigned int msiof2_ss1_d_pins[] = {
3091         /* SS1 */
3092         RCAR_GP_PIN(2, 17),
3093 };
3094 static const unsigned int msiof2_ss1_d_mux[] = {
3095         MSIOF2_SS1_D_MARK,
3096 };
3097 static const unsigned int msiof2_ss2_d_pins[] = {
3098         /* SS2 */
3099         RCAR_GP_PIN(2, 19),
3100 };
3101 static const unsigned int msiof2_ss2_d_mux[] = {
3102         MSIOF2_SS2_D_MARK,
3103 };
3104 static const unsigned int msiof2_rx_d_pins[] = {
3105         /* RXD */
3106         RCAR_GP_PIN(2, 18),
3107 };
3108 static const unsigned int msiof2_rx_d_mux[] = {
3109         MSIOF2_RXD_D_MARK,
3110 };
3111 static const unsigned int msiof2_tx_d_pins[] = {
3112         /* TXD */
3113         RCAR_GP_PIN(2, 16),
3114 };
3115 static const unsigned int msiof2_tx_d_mux[] = {
3116         MSIOF2_TXD_D_MARK,
3117 };
3118
3119 static const unsigned int msiof2_clk_e_pins[] = {
3120         /* SCK */
3121         RCAR_GP_PIN(7, 15),
3122 };
3123 static const unsigned int msiof2_clk_e_mux[] = {
3124         MSIOF2_SCK_E_MARK,
3125 };
3126 static const unsigned int msiof2_sync_e_pins[] = {
3127         /* SYNC */
3128         RCAR_GP_PIN(7, 16),
3129 };
3130 static const unsigned int msiof2_sync_e_mux[] = {
3131         MSIOF2_SYNC_E_MARK,
3132 };
3133 static const unsigned int msiof2_rx_e_pins[] = {
3134         /* RXD */
3135         RCAR_GP_PIN(7, 14),
3136 };
3137 static const unsigned int msiof2_rx_e_mux[] = {
3138         MSIOF2_RXD_E_MARK,
3139 };
3140 static const unsigned int msiof2_tx_e_pins[] = {
3141         /* TXD */
3142         RCAR_GP_PIN(7, 13),
3143 };
3144 static const unsigned int msiof2_tx_e_mux[] = {
3145         MSIOF2_TXD_E_MARK,
3146 };
3147 /* - PWM -------------------------------------------------------------------- */
3148 static const unsigned int pwm0_pins[] = {
3149         RCAR_GP_PIN(6, 14),
3150 };
3151 static const unsigned int pwm0_mux[] = {
3152         PWM0_MARK,
3153 };
3154 static const unsigned int pwm0_b_pins[] = {
3155         RCAR_GP_PIN(5, 30),
3156 };
3157 static const unsigned int pwm0_b_mux[] = {
3158         PWM0_B_MARK,
3159 };
3160 static const unsigned int pwm1_pins[] = {
3161         RCAR_GP_PIN(1, 17),
3162 };
3163 static const unsigned int pwm1_mux[] = {
3164         PWM1_MARK,
3165 };
3166 static const unsigned int pwm1_b_pins[] = {
3167         RCAR_GP_PIN(6, 15),
3168 };
3169 static const unsigned int pwm1_b_mux[] = {
3170         PWM1_B_MARK,
3171 };
3172 static const unsigned int pwm2_pins[] = {
3173         RCAR_GP_PIN(1, 18),
3174 };
3175 static const unsigned int pwm2_mux[] = {
3176         PWM2_MARK,
3177 };
3178 static const unsigned int pwm2_b_pins[] = {
3179         RCAR_GP_PIN(0, 16),
3180 };
3181 static const unsigned int pwm2_b_mux[] = {
3182         PWM2_B_MARK,
3183 };
3184 static const unsigned int pwm3_pins[] = {
3185         RCAR_GP_PIN(1, 24),
3186 };
3187 static const unsigned int pwm3_mux[] = {
3188         PWM3_MARK,
3189 };
3190 static const unsigned int pwm4_pins[] = {
3191         RCAR_GP_PIN(3, 26),
3192 };
3193 static const unsigned int pwm4_mux[] = {
3194         PWM4_MARK,
3195 };
3196 static const unsigned int pwm4_b_pins[] = {
3197         RCAR_GP_PIN(3, 31),
3198 };
3199 static const unsigned int pwm4_b_mux[] = {
3200         PWM4_B_MARK,
3201 };
3202 static const unsigned int pwm5_pins[] = {
3203         RCAR_GP_PIN(7, 21),
3204 };
3205 static const unsigned int pwm5_mux[] = {
3206         PWM5_MARK,
3207 };
3208 static const unsigned int pwm5_b_pins[] = {
3209         RCAR_GP_PIN(7, 20),
3210 };
3211 static const unsigned int pwm5_b_mux[] = {
3212         PWM5_B_MARK,
3213 };
3214 static const unsigned int pwm6_pins[] = {
3215         RCAR_GP_PIN(7, 22),
3216 };
3217 static const unsigned int pwm6_mux[] = {
3218         PWM6_MARK,
3219 };
3220 /* - QSPI ------------------------------------------------------------------- */
3221 static const unsigned int qspi_ctrl_pins[] = {
3222         /* SPCLK, SSL */
3223         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3224 };
3225 static const unsigned int qspi_ctrl_mux[] = {
3226         SPCLK_MARK, SSL_MARK,
3227 };
3228 static const unsigned int qspi_data2_pins[] = {
3229         /* MOSI_IO0, MISO_IO1 */
3230         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3231 };
3232 static const unsigned int qspi_data2_mux[] = {
3233         MOSI_IO0_MARK, MISO_IO1_MARK,
3234 };
3235 static const unsigned int qspi_data4_pins[] = {
3236         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3237         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3238         RCAR_GP_PIN(1, 8),
3239 };
3240 static const unsigned int qspi_data4_mux[] = {
3241         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3242 };
3243
3244 static const unsigned int qspi_ctrl_b_pins[] = {
3245         /* SPCLK, SSL */
3246         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3247 };
3248 static const unsigned int qspi_ctrl_b_mux[] = {
3249         SPCLK_B_MARK, SSL_B_MARK,
3250 };
3251 static const unsigned int qspi_data2_b_pins[] = {
3252         /* MOSI_IO0, MISO_IO1 */
3253         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3254 };
3255 static const unsigned int qspi_data2_b_mux[] = {
3256         MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3257 };
3258 static const unsigned int qspi_data4_b_pins[] = {
3259         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3260         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3261         RCAR_GP_PIN(6, 4),
3262 };
3263 static const unsigned int qspi_data4_b_mux[] = {
3264         MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
3265 };
3266 /* - SCIF0 ------------------------------------------------------------------ */
3267 static const unsigned int scif0_data_pins[] = {
3268         /* RX, TX */
3269         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3270 };
3271 static const unsigned int scif0_data_mux[] = {
3272         RX0_MARK, TX0_MARK,
3273 };
3274 static const unsigned int scif0_data_b_pins[] = {
3275         /* RX, TX */
3276         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3277 };
3278 static const unsigned int scif0_data_b_mux[] = {
3279         RX0_B_MARK, TX0_B_MARK,
3280 };
3281 static const unsigned int scif0_data_c_pins[] = {
3282         /* RX, TX */
3283         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3284 };
3285 static const unsigned int scif0_data_c_mux[] = {
3286         RX0_C_MARK, TX0_C_MARK,
3287 };
3288 static const unsigned int scif0_data_d_pins[] = {
3289         /* RX, TX */
3290         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3291 };
3292 static const unsigned int scif0_data_d_mux[] = {
3293         RX0_D_MARK, TX0_D_MARK,
3294 };
3295 static const unsigned int scif0_data_e_pins[] = {
3296         /* RX, TX */
3297         RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3298 };
3299 static const unsigned int scif0_data_e_mux[] = {
3300         RX0_E_MARK, TX0_E_MARK,
3301 };
3302 /* - SCIF1 ------------------------------------------------------------------ */
3303 static const unsigned int scif1_data_pins[] = {
3304         /* RX, TX */
3305         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3306 };
3307 static const unsigned int scif1_data_mux[] = {
3308         RX1_MARK, TX1_MARK,
3309 };
3310 static const unsigned int scif1_data_b_pins[] = {
3311         /* RX, TX */
3312         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3313 };
3314 static const unsigned int scif1_data_b_mux[] = {
3315         RX1_B_MARK, TX1_B_MARK,
3316 };
3317 static const unsigned int scif1_clk_b_pins[] = {
3318         /* SCK */
3319         RCAR_GP_PIN(3, 10),
3320 };
3321 static const unsigned int scif1_clk_b_mux[] = {
3322         SCIF1_SCK_B_MARK,
3323 };
3324 static const unsigned int scif1_data_c_pins[] = {
3325         /* RX, TX */
3326         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3327 };
3328 static const unsigned int scif1_data_c_mux[] = {
3329         RX1_C_MARK, TX1_C_MARK,
3330 };
3331 static const unsigned int scif1_data_d_pins[] = {
3332         /* RX, TX */
3333         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3334 };
3335 static const unsigned int scif1_data_d_mux[] = {
3336         RX1_D_MARK, TX1_D_MARK,
3337 };
3338 /* - SCIF2 ------------------------------------------------------------------ */
3339 static const unsigned int scif2_data_pins[] = {
3340         /* RX, TX */
3341         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3342 };
3343 static const unsigned int scif2_data_mux[] = {
3344         RX2_MARK, TX2_MARK,
3345 };
3346 static const unsigned int scif2_data_b_pins[] = {
3347         /* RX, TX */
3348         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3349 };
3350 static const unsigned int scif2_data_b_mux[] = {
3351         RX2_B_MARK, TX2_B_MARK,
3352 };
3353 static const unsigned int scif2_clk_b_pins[] = {
3354         /* SCK */
3355         RCAR_GP_PIN(3, 18),
3356 };
3357 static const unsigned int scif2_clk_b_mux[] = {
3358         SCIF2_SCK_B_MARK,
3359 };
3360 static const unsigned int scif2_data_c_pins[] = {
3361         /* RX, TX */
3362         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3363 };
3364 static const unsigned int scif2_data_c_mux[] = {
3365         RX2_C_MARK, TX2_C_MARK,
3366 };
3367 static const unsigned int scif2_data_e_pins[] = {
3368         /* RX, TX */
3369         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3370 };
3371 static const unsigned int scif2_data_e_mux[] = {
3372         RX2_E_MARK, TX2_E_MARK,
3373 };
3374 /* - SCIF3 ------------------------------------------------------------------ */
3375 static const unsigned int scif3_data_pins[] = {
3376         /* RX, TX */
3377         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3378 };
3379 static const unsigned int scif3_data_mux[] = {
3380         RX3_MARK, TX3_MARK,
3381 };
3382 static const unsigned int scif3_clk_pins[] = {
3383         /* SCK */
3384         RCAR_GP_PIN(3, 23),
3385 };
3386 static const unsigned int scif3_clk_mux[] = {
3387         SCIF3_SCK_MARK,
3388 };
3389 static const unsigned int scif3_data_b_pins[] = {
3390         /* RX, TX */
3391         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3392 };
3393 static const unsigned int scif3_data_b_mux[] = {
3394         RX3_B_MARK, TX3_B_MARK,
3395 };
3396 static const unsigned int scif3_clk_b_pins[] = {
3397         /* SCK */
3398         RCAR_GP_PIN(4, 8),
3399 };
3400 static const unsigned int scif3_clk_b_mux[] = {
3401         SCIF3_SCK_B_MARK,
3402 };
3403 static const unsigned int scif3_data_c_pins[] = {
3404         /* RX, TX */
3405         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3406 };
3407 static const unsigned int scif3_data_c_mux[] = {
3408         RX3_C_MARK, TX3_C_MARK,
3409 };
3410 static const unsigned int scif3_data_d_pins[] = {
3411         /* RX, TX */
3412         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3413 };
3414 static const unsigned int scif3_data_d_mux[] = {
3415         RX3_D_MARK, TX3_D_MARK,
3416 };
3417 /* - SCIF4 ------------------------------------------------------------------ */
3418 static const unsigned int scif4_data_pins[] = {
3419         /* RX, TX */
3420         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3421 };
3422 static const unsigned int scif4_data_mux[] = {
3423         RX4_MARK, TX4_MARK,
3424 };
3425 static const unsigned int scif4_data_b_pins[] = {
3426         /* RX, TX */
3427         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3428 };
3429 static const unsigned int scif4_data_b_mux[] = {
3430         RX4_B_MARK, TX4_B_MARK,
3431 };
3432 static const unsigned int scif4_data_c_pins[] = {
3433         /* RX, TX */
3434         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3435 };
3436 static const unsigned int scif4_data_c_mux[] = {
3437         RX4_C_MARK, TX4_C_MARK,
3438 };
3439 /* - SCIF5 ------------------------------------------------------------------ */
3440 static const unsigned int scif5_data_pins[] = {
3441         /* RX, TX */
3442         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3443 };
3444 static const unsigned int scif5_data_mux[] = {
3445         RX5_MARK, TX5_MARK,
3446 };
3447 static const unsigned int scif5_data_b_pins[] = {
3448         /* RX, TX */
3449         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3450 };
3451 static const unsigned int scif5_data_b_mux[] = {
3452         RX5_B_MARK, TX5_B_MARK,
3453 };
3454 /* - SCIFA0 ----------------------------------------------------------------- */
3455 static const unsigned int scifa0_data_pins[] = {
3456         /* RXD, TXD */
3457         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3458 };
3459 static const unsigned int scifa0_data_mux[] = {
3460         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3461 };
3462 static const unsigned int scifa0_data_b_pins[] = {
3463         /* RXD, TXD */
3464         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3465 };
3466 static const unsigned int scifa0_data_b_mux[] = {
3467         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3468 };
3469 /* - SCIFA1 ----------------------------------------------------------------- */
3470 static const unsigned int scifa1_data_pins[] = {
3471         /* RXD, TXD */
3472         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3473 };
3474 static const unsigned int scifa1_data_mux[] = {
3475         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3476 };
3477 static const unsigned int scifa1_clk_pins[] = {
3478         /* SCK */
3479         RCAR_GP_PIN(3, 10),
3480 };
3481 static const unsigned int scifa1_clk_mux[] = {
3482         SCIFA1_SCK_MARK,
3483 };
3484 static const unsigned int scifa1_data_b_pins[] = {
3485         /* RXD, TXD */
3486         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3487 };
3488 static const unsigned int scifa1_data_b_mux[] = {
3489         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3490 };
3491 static const unsigned int scifa1_clk_b_pins[] = {
3492         /* SCK */
3493         RCAR_GP_PIN(1, 0),
3494 };
3495 static const unsigned int scifa1_clk_b_mux[] = {
3496         SCIFA1_SCK_B_MARK,
3497 };
3498 static const unsigned int scifa1_data_c_pins[] = {
3499         /* RXD, TXD */
3500         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3501 };
3502 static const unsigned int scifa1_data_c_mux[] = {
3503         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3504 };
3505 /* - SCIFA2 ----------------------------------------------------------------- */
3506 static const unsigned int scifa2_data_pins[] = {
3507         /* RXD, TXD */
3508         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3509 };
3510 static const unsigned int scifa2_data_mux[] = {
3511         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3512 };
3513 static const unsigned int scifa2_clk_pins[] = {
3514         /* SCK */
3515         RCAR_GP_PIN(3, 18),
3516 };
3517 static const unsigned int scifa2_clk_mux[] = {
3518         SCIFA2_SCK_MARK,
3519 };
3520 static const unsigned int scifa2_data_b_pins[] = {
3521         /* RXD, TXD */
3522         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3523 };
3524 static const unsigned int scifa2_data_b_mux[] = {
3525         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3526 };
3527 /* - SCIFA3 ----------------------------------------------------------------- */
3528 static const unsigned int scifa3_data_pins[] = {
3529         /* RXD, TXD */
3530         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3531 };
3532 static const unsigned int scifa3_data_mux[] = {
3533         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3534 };
3535 static const unsigned int scifa3_clk_pins[] = {
3536         /* SCK */
3537         RCAR_GP_PIN(3, 23),
3538 };
3539 static const unsigned int scifa3_clk_mux[] = {
3540         SCIFA3_SCK_MARK,
3541 };
3542 static const unsigned int scifa3_data_b_pins[] = {
3543         /* RXD, TXD */
3544         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3545 };
3546 static const unsigned int scifa3_data_b_mux[] = {
3547         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3548 };
3549 static const unsigned int scifa3_clk_b_pins[] = {
3550         /* SCK */
3551         RCAR_GP_PIN(4, 8),
3552 };
3553 static const unsigned int scifa3_clk_b_mux[] = {
3554         SCIFA3_SCK_B_MARK,
3555 };
3556 static const unsigned int scifa3_data_c_pins[] = {
3557         /* RXD, TXD */
3558         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3559 };
3560 static const unsigned int scifa3_data_c_mux[] = {
3561         SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3562 };
3563 static const unsigned int scifa3_clk_c_pins[] = {
3564         /* SCK */
3565         RCAR_GP_PIN(7, 22),
3566 };
3567 static const unsigned int scifa3_clk_c_mux[] = {
3568         SCIFA3_SCK_C_MARK,
3569 };
3570 /* - SCIFA4 ----------------------------------------------------------------- */
3571 static const unsigned int scifa4_data_pins[] = {
3572         /* RXD, TXD */
3573         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3574 };
3575 static const unsigned int scifa4_data_mux[] = {
3576         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3577 };
3578 static const unsigned int scifa4_data_b_pins[] = {
3579         /* RXD, TXD */
3580         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3581 };
3582 static const unsigned int scifa4_data_b_mux[] = {
3583         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3584 };
3585 static const unsigned int scifa4_data_c_pins[] = {
3586         /* RXD, TXD */
3587         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3588 };
3589 static const unsigned int scifa4_data_c_mux[] = {
3590         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3591 };
3592 /* - SCIFA5 ----------------------------------------------------------------- */
3593 static const unsigned int scifa5_data_pins[] = {
3594         /* RXD, TXD */
3595         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3596 };
3597 static const unsigned int scifa5_data_mux[] = {
3598         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3599 };
3600 static const unsigned int scifa5_data_b_pins[] = {
3601         /* RXD, TXD */
3602         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3603 };
3604 static const unsigned int scifa5_data_b_mux[] = {
3605         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3606 };
3607 static const unsigned int scifa5_data_c_pins[] = {
3608         /* RXD, TXD */
3609         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3610 };
3611 static const unsigned int scifa5_data_c_mux[] = {
3612         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3613 };
3614 /* - SCIFB0 ----------------------------------------------------------------- */
3615 static const unsigned int scifb0_data_pins[] = {
3616         /* RXD, TXD */
3617         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3618 };
3619 static const unsigned int scifb0_data_mux[] = {
3620         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3621 };
3622 static const unsigned int scifb0_clk_pins[] = {
3623         /* SCK */
3624         RCAR_GP_PIN(7, 2),
3625 };
3626 static const unsigned int scifb0_clk_mux[] = {
3627         SCIFB0_SCK_MARK,
3628 };
3629 static const unsigned int scifb0_ctrl_pins[] = {
3630         /* RTS, CTS */
3631         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3632 };
3633 static const unsigned int scifb0_ctrl_mux[] = {
3634         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3635 };
3636 static const unsigned int scifb0_data_b_pins[] = {
3637         /* RXD, TXD */
3638         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3639 };
3640 static const unsigned int scifb0_data_b_mux[] = {
3641         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3642 };
3643 static const unsigned int scifb0_clk_b_pins[] = {
3644         /* SCK */
3645         RCAR_GP_PIN(5, 31),
3646 };
3647 static const unsigned int scifb0_clk_b_mux[] = {
3648         SCIFB0_SCK_B_MARK,
3649 };
3650 static const unsigned int scifb0_ctrl_b_pins[] = {
3651         /* RTS, CTS */
3652         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3653 };
3654 static const unsigned int scifb0_ctrl_b_mux[] = {
3655         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3656 };
3657 static const unsigned int scifb0_data_c_pins[] = {
3658         /* RXD, TXD */
3659         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3660 };
3661 static const unsigned int scifb0_data_c_mux[] = {
3662         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3663 };
3664 static const unsigned int scifb0_clk_c_pins[] = {
3665         /* SCK */
3666         RCAR_GP_PIN(2, 30),
3667 };
3668 static const unsigned int scifb0_clk_c_mux[] = {
3669         SCIFB0_SCK_C_MARK,
3670 };
3671 static const unsigned int scifb0_data_d_pins[] = {
3672         /* RXD, TXD */
3673         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3674 };
3675 static const unsigned int scifb0_data_d_mux[] = {
3676         SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3677 };
3678 static const unsigned int scifb0_clk_d_pins[] = {
3679         /* SCK */
3680         RCAR_GP_PIN(4, 17),
3681 };
3682 static const unsigned int scifb0_clk_d_mux[] = {
3683         SCIFB0_SCK_D_MARK,
3684 };
3685 /* - SCIFB1 ----------------------------------------------------------------- */
3686 static const unsigned int scifb1_data_pins[] = {
3687         /* RXD, TXD */
3688         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3689 };
3690 static const unsigned int scifb1_data_mux[] = {
3691         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3692 };
3693 static const unsigned int scifb1_clk_pins[] = {
3694         /* SCK */
3695         RCAR_GP_PIN(7, 7),
3696 };
3697 static const unsigned int scifb1_clk_mux[] = {
3698         SCIFB1_SCK_MARK,
3699 };
3700 static const unsigned int scifb1_ctrl_pins[] = {
3701         /* RTS, CTS */
3702         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3703 };
3704 static const unsigned int scifb1_ctrl_mux[] = {
3705         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3706 };
3707 static const unsigned int scifb1_data_b_pins[] = {
3708         /* RXD, TXD */
3709         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3710 };
3711 static const unsigned int scifb1_data_b_mux[] = {
3712         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3713 };
3714 static const unsigned int scifb1_clk_b_pins[] = {
3715         /* SCK */
3716         RCAR_GP_PIN(1, 3),
3717 };
3718 static const unsigned int scifb1_clk_b_mux[] = {
3719         SCIFB1_SCK_B_MARK,
3720 };
3721 static const unsigned int scifb1_data_c_pins[] = {
3722         /* RXD, TXD */
3723         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3724 };
3725 static const unsigned int scifb1_data_c_mux[] = {
3726         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3727 };
3728 static const unsigned int scifb1_clk_c_pins[] = {
3729         /* SCK */
3730         RCAR_GP_PIN(7, 11),
3731 };
3732 static const unsigned int scifb1_clk_c_mux[] = {
3733         SCIFB1_SCK_C_MARK,
3734 };
3735 static const unsigned int scifb1_data_d_pins[] = {
3736         /* RXD, TXD */
3737         RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3738 };
3739 static const unsigned int scifb1_data_d_mux[] = {
3740         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3741 };
3742 /* - SCIFB2 ----------------------------------------------------------------- */
3743 static const unsigned int scifb2_data_pins[] = {
3744         /* RXD, TXD */
3745         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3746 };
3747 static const unsigned int scifb2_data_mux[] = {
3748         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3749 };
3750 static const unsigned int scifb2_clk_pins[] = {
3751         /* SCK */
3752         RCAR_GP_PIN(4, 15),
3753 };
3754 static const unsigned int scifb2_clk_mux[] = {
3755         SCIFB2_SCK_MARK,
3756 };
3757 static const unsigned int scifb2_ctrl_pins[] = {
3758         /* RTS, CTS */
3759         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3760 };
3761 static const unsigned int scifb2_ctrl_mux[] = {
3762         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3763 };
3764 static const unsigned int scifb2_data_b_pins[] = {
3765         /* RXD, TXD */
3766         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3767 };
3768 static const unsigned int scifb2_data_b_mux[] = {
3769         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3770 };
3771 static const unsigned int scifb2_clk_b_pins[] = {
3772         /* SCK */
3773         RCAR_GP_PIN(5, 31),
3774 };
3775 static const unsigned int scifb2_clk_b_mux[] = {
3776         SCIFB2_SCK_B_MARK,
3777 };
3778 static const unsigned int scifb2_ctrl_b_pins[] = {
3779         /* RTS, CTS */
3780         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3781 };
3782 static const unsigned int scifb2_ctrl_b_mux[] = {
3783         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3784 };
3785 static const unsigned int scifb2_data_c_pins[] = {
3786         /* RXD, TXD */
3787         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3788 };
3789 static const unsigned int scifb2_data_c_mux[] = {
3790         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3791 };
3792 static const unsigned int scifb2_clk_c_pins[] = {
3793         /* SCK */
3794         RCAR_GP_PIN(5, 27),
3795 };
3796 static const unsigned int scifb2_clk_c_mux[] = {
3797         SCIFB2_SCK_C_MARK,
3798 };
3799 static const unsigned int scifb2_data_d_pins[] = {
3800         /* RXD, TXD */
3801         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3802 };
3803 static const unsigned int scifb2_data_d_mux[] = {
3804         SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3805 };
3806
3807 /* - SCIF Clock ------------------------------------------------------------- */
3808 static const unsigned int scif_clk_pins[] = {
3809         /* SCIF_CLK */
3810         RCAR_GP_PIN(2, 29),
3811 };
3812 static const unsigned int scif_clk_mux[] = {
3813         SCIF_CLK_MARK,
3814 };
3815 static const unsigned int scif_clk_b_pins[] = {
3816         /* SCIF_CLK */
3817         RCAR_GP_PIN(7, 19),
3818 };
3819 static const unsigned int scif_clk_b_mux[] = {
3820         SCIF_CLK_B_MARK,
3821 };
3822
3823 /* - SDHI0 ------------------------------------------------------------------ */
3824 static const unsigned int sdhi0_data1_pins[] = {
3825         /* D0 */
3826         RCAR_GP_PIN(6, 2),
3827 };
3828 static const unsigned int sdhi0_data1_mux[] = {
3829         SD0_DATA0_MARK,
3830 };
3831 static const unsigned int sdhi0_data4_pins[] = {
3832         /* D[0:3] */
3833         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3834         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3835 };
3836 static const unsigned int sdhi0_data4_mux[] = {
3837         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3838 };
3839 static const unsigned int sdhi0_ctrl_pins[] = {
3840         /* CLK, CMD */
3841         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3842 };
3843 static const unsigned int sdhi0_ctrl_mux[] = {
3844         SD0_CLK_MARK, SD0_CMD_MARK,
3845 };
3846 static const unsigned int sdhi0_cd_pins[] = {
3847         /* CD */
3848         RCAR_GP_PIN(6, 6),
3849 };
3850 static const unsigned int sdhi0_cd_mux[] = {
3851         SD0_CD_MARK,
3852 };
3853 static const unsigned int sdhi0_wp_pins[] = {
3854         /* WP */
3855         RCAR_GP_PIN(6, 7),
3856 };
3857 static const unsigned int sdhi0_wp_mux[] = {
3858         SD0_WP_MARK,
3859 };
3860 /* - SDHI1 ------------------------------------------------------------------ */
3861 static const unsigned int sdhi1_data1_pins[] = {
3862         /* D0 */
3863         RCAR_GP_PIN(6, 10),
3864 };
3865 static const unsigned int sdhi1_data1_mux[] = {
3866         SD1_DATA0_MARK,
3867 };
3868 static const unsigned int sdhi1_data4_pins[] = {
3869         /* D[0:3] */
3870         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3871         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3872 };
3873 static const unsigned int sdhi1_data4_mux[] = {
3874         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3875 };
3876 static const unsigned int sdhi1_ctrl_pins[] = {
3877         /* CLK, CMD */
3878         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3879 };
3880 static const unsigned int sdhi1_ctrl_mux[] = {
3881         SD1_CLK_MARK, SD1_CMD_MARK,
3882 };
3883 static const unsigned int sdhi1_cd_pins[] = {
3884         /* CD */
3885         RCAR_GP_PIN(6, 14),
3886 };
3887 static const unsigned int sdhi1_cd_mux[] = {
3888         SD1_CD_MARK,
3889 };
3890 static const unsigned int sdhi1_wp_pins[] = {
3891         /* WP */
3892         RCAR_GP_PIN(6, 15),
3893 };
3894 static const unsigned int sdhi1_wp_mux[] = {
3895         SD1_WP_MARK,
3896 };
3897 /* - SDHI2 ------------------------------------------------------------------ */
3898 static const unsigned int sdhi2_data1_pins[] = {
3899         /* D0 */
3900         RCAR_GP_PIN(6, 18),
3901 };
3902 static const unsigned int sdhi2_data1_mux[] = {
3903         SD2_DATA0_MARK,
3904 };
3905 static const unsigned int sdhi2_data4_pins[] = {
3906         /* D[0:3] */
3907         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3908         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3909 };
3910 static const unsigned int sdhi2_data4_mux[] = {
3911         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3912 };
3913 static const unsigned int sdhi2_ctrl_pins[] = {
3914         /* CLK, CMD */
3915         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3916 };
3917 static const unsigned int sdhi2_ctrl_mux[] = {
3918         SD2_CLK_MARK, SD2_CMD_MARK,
3919 };
3920 static const unsigned int sdhi2_cd_pins[] = {
3921         /* CD */
3922         RCAR_GP_PIN(6, 22),
3923 };
3924 static const unsigned int sdhi2_cd_mux[] = {
3925         SD2_CD_MARK,
3926 };
3927 static const unsigned int sdhi2_wp_pins[] = {
3928         /* WP */
3929         RCAR_GP_PIN(6, 23),
3930 };
3931 static const unsigned int sdhi2_wp_mux[] = {
3932         SD2_WP_MARK,
3933 };
3934
3935 /* - SSI -------------------------------------------------------------------- */
3936 static const unsigned int ssi0_data_pins[] = {
3937         /* SDATA */
3938         RCAR_GP_PIN(2, 2),
3939 };
3940
3941 static const unsigned int ssi0_data_mux[] = {
3942         SSI_SDATA0_MARK,
3943 };
3944
3945 static const unsigned int ssi0_data_b_pins[] = {
3946         /* SDATA */
3947         RCAR_GP_PIN(3, 4),
3948 };
3949
3950 static const unsigned int ssi0_data_b_mux[] = {
3951         SSI_SDATA0_B_MARK,
3952 };
3953
3954 static const unsigned int ssi0129_ctrl_pins[] = {
3955         /* SCK, WS */
3956         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3957 };
3958
3959 static const unsigned int ssi0129_ctrl_mux[] = {
3960         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3961 };
3962
3963 static const unsigned int ssi0129_ctrl_b_pins[] = {
3964         /* SCK, WS */
3965         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3966 };
3967
3968 static const unsigned int ssi0129_ctrl_b_mux[] = {
3969         SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3970 };
3971
3972 static const unsigned int ssi1_data_pins[] = {
3973         /* SDATA */
3974         RCAR_GP_PIN(2, 5),
3975 };
3976
3977 static const unsigned int ssi1_data_mux[] = {
3978         SSI_SDATA1_MARK,
3979 };
3980
3981 static const unsigned int ssi1_data_b_pins[] = {
3982         /* SDATA */
3983         RCAR_GP_PIN(3, 7),
3984 };
3985
3986 static const unsigned int ssi1_data_b_mux[] = {
3987         SSI_SDATA1_B_MARK,
3988 };
3989
3990 static const unsigned int ssi1_ctrl_pins[] = {
3991         /* SCK, WS */
3992         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3993 };
3994
3995 static const unsigned int ssi1_ctrl_mux[] = {
3996         SSI_SCK1_MARK, SSI_WS1_MARK,
3997 };
3998
3999 static const unsigned int ssi1_ctrl_b_pins[] = {
4000         /* SCK, WS */
4001         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
4002 };
4003
4004 static const unsigned int ssi1_ctrl_b_mux[] = {
4005         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
4006 };
4007
4008 static const unsigned int ssi2_data_pins[] = {
4009         /* SDATA */
4010         RCAR_GP_PIN(2, 8),
4011 };
4012
4013 static const unsigned int ssi2_data_mux[] = {
4014         SSI_SDATA2_MARK,
4015 };
4016
4017 static const unsigned int ssi2_ctrl_pins[] = {
4018         /* SCK, WS */
4019         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4020 };
4021
4022 static const unsigned int ssi2_ctrl_mux[] = {
4023         SSI_SCK2_MARK, SSI_WS2_MARK,
4024 };
4025
4026 static const unsigned int ssi3_data_pins[] = {
4027         /* SDATA */
4028         RCAR_GP_PIN(2, 11),
4029 };
4030
4031 static const unsigned int ssi3_data_mux[] = {
4032         SSI_SDATA3_MARK,
4033 };
4034
4035 static const unsigned int ssi34_ctrl_pins[] = {
4036         /* SCK, WS */
4037         RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
4038 };
4039
4040 static const unsigned int ssi34_ctrl_mux[] = {
4041         SSI_SCK34_MARK, SSI_WS34_MARK,
4042 };
4043
4044 static const unsigned int ssi4_data_pins[] = {
4045         /* SDATA */
4046         RCAR_GP_PIN(2, 14),
4047 };
4048
4049 static const unsigned int ssi4_data_mux[] = {
4050         SSI_SDATA4_MARK,
4051 };
4052
4053 static const unsigned int ssi4_ctrl_pins[] = {
4054         /* SCK, WS */
4055         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
4056 };
4057
4058 static const unsigned int ssi4_ctrl_mux[] = {
4059         SSI_SCK4_MARK, SSI_WS4_MARK,
4060 };
4061
4062 static const unsigned int ssi5_data_pins[] = {
4063         /* SDATA */
4064         RCAR_GP_PIN(2, 17),
4065 };
4066
4067 static const unsigned int ssi5_data_mux[] = {
4068         SSI_SDATA5_MARK,
4069 };
4070
4071 static const unsigned int ssi5_ctrl_pins[] = {
4072         /* SCK, WS */
4073         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4074 };
4075
4076 static const unsigned int ssi5_ctrl_mux[] = {
4077         SSI_SCK5_MARK, SSI_WS5_MARK,
4078 };
4079
4080 static const unsigned int ssi6_data_pins[] = {
4081         /* SDATA */
4082         RCAR_GP_PIN(2, 20),
4083 };
4084
4085 static const unsigned int ssi6_data_mux[] = {
4086         SSI_SDATA6_MARK,
4087 };
4088
4089 static const unsigned int ssi6_ctrl_pins[] = {
4090         /* SCK, WS */
4091         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
4092 };
4093
4094 static const unsigned int ssi6_ctrl_mux[] = {
4095         SSI_SCK6_MARK, SSI_WS6_MARK,
4096 };
4097
4098 static const unsigned int ssi7_data_pins[] = {
4099         /* SDATA */
4100         RCAR_GP_PIN(2, 23),
4101 };
4102
4103 static const unsigned int ssi7_data_mux[] = {
4104         SSI_SDATA7_MARK,
4105 };
4106
4107 static const unsigned int ssi7_data_b_pins[] = {
4108         /* SDATA */
4109         RCAR_GP_PIN(3, 12),
4110 };
4111
4112 static const unsigned int ssi7_data_b_mux[] = {
4113         SSI_SDATA7_B_MARK,
4114 };
4115
4116 static const unsigned int ssi78_ctrl_pins[] = {
4117         /* SCK, WS */
4118         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
4119 };
4120
4121 static const unsigned int ssi78_ctrl_mux[] = {
4122         SSI_SCK78_MARK, SSI_WS78_MARK,
4123 };
4124
4125 static const unsigned int ssi78_ctrl_b_pins[] = {
4126         /* SCK, WS */
4127         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4128 };
4129
4130 static const unsigned int ssi78_ctrl_b_mux[] = {
4131         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
4132 };
4133
4134 static const unsigned int ssi8_data_pins[] = {
4135         /* SDATA */
4136         RCAR_GP_PIN(2, 24),
4137 };
4138
4139 static const unsigned int ssi8_data_mux[] = {
4140         SSI_SDATA8_MARK,
4141 };
4142
4143 static const unsigned int ssi8_data_b_pins[] = {
4144         /* SDATA */
4145         RCAR_GP_PIN(3, 13),
4146 };
4147
4148 static const unsigned int ssi8_data_b_mux[] = {
4149         SSI_SDATA8_B_MARK,
4150 };
4151
4152 static const unsigned int ssi9_data_pins[] = {
4153         /* SDATA */
4154         RCAR_GP_PIN(2, 27),
4155 };
4156
4157 static const unsigned int ssi9_data_mux[] = {
4158         SSI_SDATA9_MARK,
4159 };
4160
4161 static const unsigned int ssi9_data_b_pins[] = {
4162         /* SDATA */
4163         RCAR_GP_PIN(3, 18),
4164 };
4165
4166 static const unsigned int ssi9_data_b_mux[] = {
4167         SSI_SDATA9_B_MARK,
4168 };
4169
4170 static const unsigned int ssi9_ctrl_pins[] = {
4171         /* SCK, WS */
4172         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4173 };
4174
4175 static const unsigned int ssi9_ctrl_mux[] = {
4176         SSI_SCK9_MARK, SSI_WS9_MARK,
4177 };
4178
4179 static const unsigned int ssi9_ctrl_b_pins[] = {
4180         /* SCK, WS */
4181         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4182 };
4183
4184 static const unsigned int ssi9_ctrl_b_mux[] = {
4185         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4186 };
4187
4188 /* - TPU -------------------------------------------------------------------- */
4189 static const unsigned int tpu_to0_pins[] = {
4190         RCAR_GP_PIN(6, 14),
4191 };
4192 static const unsigned int tpu_to0_mux[] = {
4193         TPU_TO0_MARK,
4194 };
4195 static const unsigned int tpu_to1_pins[] = {
4196         RCAR_GP_PIN(1, 17),
4197 };
4198 static const unsigned int tpu_to1_mux[] = {
4199         TPU_TO1_MARK,
4200 };
4201 static const unsigned int tpu_to2_pins[] = {
4202         RCAR_GP_PIN(1, 18),
4203 };
4204 static const unsigned int tpu_to2_mux[] = {
4205         TPU_TO2_MARK,
4206 };
4207 static const unsigned int tpu_to3_pins[] = {
4208         RCAR_GP_PIN(1, 24),
4209 };
4210 static const unsigned int tpu_to3_mux[] = {
4211         TPU_TO3_MARK,
4212 };
4213
4214 /* - USB0 ------------------------------------------------------------------- */
4215 static const unsigned int usb0_pins[] = {
4216         RCAR_GP_PIN(7, 23), /* PWEN */
4217         RCAR_GP_PIN(7, 24), /* OVC */
4218 };
4219 static const unsigned int usb0_mux[] = {
4220         USB0_PWEN_MARK,
4221         USB0_OVC_MARK,
4222 };
4223 /* - USB1 ------------------------------------------------------------------- */
4224 static const unsigned int usb1_pins[] = {
4225         RCAR_GP_PIN(7, 25), /* PWEN */
4226         RCAR_GP_PIN(6, 30), /* OVC */
4227 };
4228 static const unsigned int usb1_mux[] = {
4229         USB1_PWEN_MARK,
4230         USB1_OVC_MARK,
4231 };
4232 /* - VIN0 ------------------------------------------------------------------- */
4233 static const union vin_data vin0_data_pins = {
4234         .data24 = {
4235                 /* B */
4236                 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4237                 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4238                 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4239                 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4240                 /* G */
4241                 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4242                 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4243                 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4244                 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4245                 /* R */
4246                 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4247                 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4248                 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4249                 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4250         },
4251 };
4252 static const union vin_data vin0_data_mux = {
4253         .data24 = {
4254                 /* B */
4255                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4256                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4257                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4258                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4259                 /* G */
4260                 VI0_G0_MARK, VI0_G1_MARK,
4261                 VI0_G2_MARK, VI0_G3_MARK,
4262                 VI0_G4_MARK, VI0_G5_MARK,
4263                 VI0_G6_MARK, VI0_G7_MARK,
4264                 /* R */
4265                 VI0_R0_MARK, VI0_R1_MARK,
4266                 VI0_R2_MARK, VI0_R3_MARK,
4267                 VI0_R4_MARK, VI0_R5_MARK,
4268                 VI0_R6_MARK, VI0_R7_MARK,
4269         },
4270 };
4271 static const unsigned int vin0_data18_pins[] = {
4272         /* B */
4273         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4274         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4275         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4276         /* G */
4277         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4278         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4279         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4280         /* R */
4281         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4282         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4283         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4284 };
4285 static const unsigned int vin0_data18_mux[] = {
4286         /* B */
4287         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4288         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4289         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4290         /* G */
4291         VI0_G2_MARK, VI0_G3_MARK,
4292         VI0_G4_MARK, VI0_G5_MARK,
4293         VI0_G6_MARK, VI0_G7_MARK,
4294         /* R */
4295         VI0_R2_MARK, VI0_R3_MARK,
4296         VI0_R4_MARK, VI0_R5_MARK,
4297         VI0_R6_MARK, VI0_R7_MARK,
4298 };
4299 static const unsigned int vin0_sync_pins[] = {
4300         RCAR_GP_PIN(4, 3), /* HSYNC */
4301         RCAR_GP_PIN(4, 4), /* VSYNC */
4302 };
4303 static const unsigned int vin0_sync_mux[] = {
4304         VI0_HSYNC_N_MARK,
4305         VI0_VSYNC_N_MARK,
4306 };
4307 static const unsigned int vin0_field_pins[] = {
4308         RCAR_GP_PIN(4, 2),
4309 };
4310 static const unsigned int vin0_field_mux[] = {
4311         VI0_FIELD_MARK,
4312 };
4313 static const unsigned int vin0_clkenb_pins[] = {
4314         RCAR_GP_PIN(4, 1),
4315 };
4316 static const unsigned int vin0_clkenb_mux[] = {
4317         VI0_CLKENB_MARK,
4318 };
4319 static const unsigned int vin0_clk_pins[] = {
4320         RCAR_GP_PIN(4, 0),
4321 };
4322 static const unsigned int vin0_clk_mux[] = {
4323         VI0_CLK_MARK,
4324 };
4325 /* - VIN1 ----------------------------------------------------------------- */
4326 static const unsigned int vin1_data8_pins[] = {
4327         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4328         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4329         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4330         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4331 };
4332 static const unsigned int vin1_data8_mux[] = {
4333         VI1_DATA0_MARK, VI1_DATA1_MARK,
4334         VI1_DATA2_MARK, VI1_DATA3_MARK,
4335         VI1_DATA4_MARK, VI1_DATA5_MARK,
4336         VI1_DATA6_MARK, VI1_DATA7_MARK,
4337 };
4338 static const unsigned int vin1_sync_pins[] = {
4339         RCAR_GP_PIN(5, 0), /* HSYNC */
4340         RCAR_GP_PIN(5, 1), /* VSYNC */
4341 };
4342 static const unsigned int vin1_sync_mux[] = {
4343         VI1_HSYNC_N_MARK,
4344         VI1_VSYNC_N_MARK,
4345 };
4346 static const unsigned int vin1_field_pins[] = {
4347         RCAR_GP_PIN(5, 3),
4348 };
4349 static const unsigned int vin1_field_mux[] = {
4350         VI1_FIELD_MARK,
4351 };
4352 static const unsigned int vin1_clkenb_pins[] = {
4353         RCAR_GP_PIN(5, 2),
4354 };
4355 static const unsigned int vin1_clkenb_mux[] = {
4356         VI1_CLKENB_MARK,
4357 };
4358 static const unsigned int vin1_clk_pins[] = {
4359         RCAR_GP_PIN(5, 4),
4360 };
4361 static const unsigned int vin1_clk_mux[] = {
4362         VI1_CLK_MARK,
4363 };
4364 static const union vin_data vin1_data_b_pins = {
4365         .data24 = {
4366                 /* B */
4367                 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4368                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4369                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4370                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4371                 /* G */
4372                 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4373                 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4374                 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4375                 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4376                 /* R */
4377                 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4378                 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4379                 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4380                 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4381         },
4382 };
4383 static const union vin_data vin1_data_b_mux = {
4384         .data24 = {
4385                 /* B */
4386                 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4387                 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4388                 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4389                 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4390                 /* G */
4391                 VI1_G0_B_MARK, VI1_G1_B_MARK,
4392                 VI1_G2_B_MARK, VI1_G3_B_MARK,
4393                 VI1_G4_B_MARK, VI1_G5_B_MARK,
4394                 VI1_G6_B_MARK, VI1_G7_B_MARK,
4395                 /* R */
4396                 VI1_R0_B_MARK, VI1_R1_B_MARK,
4397                 VI1_R2_B_MARK, VI1_R3_B_MARK,
4398                 VI1_R4_B_MARK, VI1_R5_B_MARK,
4399                 VI1_R6_B_MARK, VI1_R7_B_MARK,
4400         },
4401 };
4402 static const unsigned int vin1_data18_b_pins[] = {
4403         /* B */
4404         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4405         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4406         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4407         /* G */
4408         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4409         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4410         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4411         /* R */
4412         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4413         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4414         RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4415 };
4416 static const unsigned int vin1_data18_b_mux[] = {
4417         /* B */
4418         VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4419         VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4420         VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4421         /* G */
4422         VI1_G2_B_MARK, VI1_G3_B_MARK,
4423         VI1_G4_B_MARK, VI1_G5_B_MARK,
4424         VI1_G6_B_MARK, VI1_G7_B_MARK,
4425         /* R */
4426         VI1_R2_B_MARK, VI1_R3_B_MARK,
4427         VI1_R4_B_MARK, VI1_R5_B_MARK,
4428         VI1_R6_B_MARK, VI1_R7_B_MARK,
4429 };
4430 static const unsigned int vin1_sync_b_pins[] = {
4431         RCAR_GP_PIN(3, 17), /* HSYNC */
4432         RCAR_GP_PIN(3, 18), /* VSYNC */
4433 };
4434 static const unsigned int vin1_sync_b_mux[] = {
4435         VI1_HSYNC_N_B_MARK,
4436         VI1_VSYNC_N_B_MARK,
4437 };
4438 static const unsigned int vin1_field_b_pins[] = {
4439         RCAR_GP_PIN(3, 20),
4440 };
4441 static const unsigned int vin1_field_b_mux[] = {
4442         VI1_FIELD_B_MARK,
4443 };
4444 static const unsigned int vin1_clkenb_b_pins[] = {
4445         RCAR_GP_PIN(3, 19),
4446 };
4447 static const unsigned int vin1_clkenb_b_mux[] = {
4448         VI1_CLKENB_B_MARK,
4449 };
4450 static const unsigned int vin1_clk_b_pins[] = {
4451         RCAR_GP_PIN(3, 16),
4452 };
4453 static const unsigned int vin1_clk_b_mux[] = {
4454         VI1_CLK_B_MARK,
4455 };
4456 /* - VIN2 ----------------------------------------------------------------- */
4457 static const unsigned int vin2_data8_pins[] = {
4458         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4459         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4460         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4461         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4462 };
4463 static const unsigned int vin2_data8_mux[] = {
4464         VI2_DATA0_MARK, VI2_DATA1_MARK,
4465         VI2_DATA2_MARK, VI2_DATA3_MARK,
4466         VI2_DATA4_MARK, VI2_DATA5_MARK,
4467         VI2_DATA6_MARK, VI2_DATA7_MARK,
4468 };
4469 static const unsigned int vin2_sync_pins[] = {
4470         RCAR_GP_PIN(4, 15), /* HSYNC */
4471         RCAR_GP_PIN(4, 16), /* VSYNC */
4472 };
4473 static const unsigned int vin2_sync_mux[] = {
4474         VI2_HSYNC_N_MARK,
4475         VI2_VSYNC_N_MARK,
4476 };
4477 static const unsigned int vin2_field_pins[] = {
4478         RCAR_GP_PIN(4, 18),
4479 };
4480 static const unsigned int vin2_field_mux[] = {
4481         VI2_FIELD_MARK,
4482 };
4483 static const unsigned int vin2_clkenb_pins[] = {
4484         RCAR_GP_PIN(4, 17),
4485 };
4486 static const unsigned int vin2_clkenb_mux[] = {
4487         VI2_CLKENB_MARK,
4488 };
4489 static const unsigned int vin2_clk_pins[] = {
4490         RCAR_GP_PIN(4, 19),
4491 };
4492 static const unsigned int vin2_clk_mux[] = {
4493         VI2_CLK_MARK,
4494 };
4495
4496 static const struct {
4497         struct sh_pfc_pin_group common[346];
4498 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
4499         struct sh_pfc_pin_group automotive[9];
4500 #endif
4501 } pinmux_groups = {
4502         .common = {
4503                 SH_PFC_PIN_GROUP(audio_clk_a),
4504                 SH_PFC_PIN_GROUP(audio_clk_b),
4505                 SH_PFC_PIN_GROUP(audio_clk_b_b),
4506                 SH_PFC_PIN_GROUP(audio_clk_c),
4507                 SH_PFC_PIN_GROUP(audio_clkout),
4508                 SH_PFC_PIN_GROUP(avb_link),
4509                 SH_PFC_PIN_GROUP(avb_magic),
4510                 SH_PFC_PIN_GROUP(avb_phy_int),
4511                 SH_PFC_PIN_GROUP(avb_mdio),
4512                 SH_PFC_PIN_GROUP(avb_mii),
4513                 SH_PFC_PIN_GROUP(avb_gmii),
4514                 SH_PFC_PIN_GROUP(can0_data),
4515                 SH_PFC_PIN_GROUP(can0_data_b),
4516                 SH_PFC_PIN_GROUP(can0_data_c),
4517                 SH_PFC_PIN_GROUP(can0_data_d),
4518                 SH_PFC_PIN_GROUP(can0_data_e),
4519                 SH_PFC_PIN_GROUP(can0_data_f),
4520                 SH_PFC_PIN_GROUP(can1_data),
4521                 SH_PFC_PIN_GROUP(can1_data_b),
4522                 SH_PFC_PIN_GROUP(can1_data_c),
4523                 SH_PFC_PIN_GROUP(can1_data_d),
4524                 SH_PFC_PIN_GROUP(can_clk),
4525                 SH_PFC_PIN_GROUP(can_clk_b),
4526                 SH_PFC_PIN_GROUP(can_clk_c),
4527                 SH_PFC_PIN_GROUP(can_clk_d),
4528                 SH_PFC_PIN_GROUP(du_rgb666),
4529                 SH_PFC_PIN_GROUP(du_rgb888),
4530                 SH_PFC_PIN_GROUP(du_clk_out_0),
4531                 SH_PFC_PIN_GROUP(du_clk_out_1),
4532                 SH_PFC_PIN_GROUP(du_sync),
4533                 SH_PFC_PIN_GROUP(du_oddf),
4534                 SH_PFC_PIN_GROUP(du_cde),
4535                 SH_PFC_PIN_GROUP(du_disp),
4536                 SH_PFC_PIN_GROUP(du0_clk_in),
4537                 SH_PFC_PIN_GROUP(du1_clk_in),
4538                 SH_PFC_PIN_GROUP(du1_clk_in_b),
4539                 SH_PFC_PIN_GROUP(du1_clk_in_c),
4540                 SH_PFC_PIN_GROUP(eth_link),
4541                 SH_PFC_PIN_GROUP(eth_magic),
4542                 SH_PFC_PIN_GROUP(eth_mdio),
4543                 SH_PFC_PIN_GROUP(eth_rmii),
4544                 SH_PFC_PIN_GROUP(hscif0_data),
4545                 SH_PFC_PIN_GROUP(hscif0_clk),
4546                 SH_PFC_PIN_GROUP(hscif0_ctrl),
4547                 SH_PFC_PIN_GROUP(hscif0_data_b),
4548                 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4549                 SH_PFC_PIN_GROUP(hscif0_data_c),
4550                 SH_PFC_PIN_GROUP(hscif0_clk_c),
4551                 SH_PFC_PIN_GROUP(hscif1_data),
4552                 SH_PFC_PIN_GROUP(hscif1_clk),
4553                 SH_PFC_PIN_GROUP(hscif1_ctrl),
4554                 SH_PFC_PIN_GROUP(hscif1_data_b),
4555                 SH_PFC_PIN_GROUP(hscif1_data_c),
4556                 SH_PFC_PIN_GROUP(hscif1_clk_c),
4557                 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4558                 SH_PFC_PIN_GROUP(hscif1_data_d),
4559                 SH_PFC_PIN_GROUP(hscif1_data_e),
4560                 SH_PFC_PIN_GROUP(hscif1_clk_e),
4561                 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4562                 SH_PFC_PIN_GROUP(hscif2_data),
4563                 SH_PFC_PIN_GROUP(hscif2_clk),
4564                 SH_PFC_PIN_GROUP(hscif2_ctrl),
4565                 SH_PFC_PIN_GROUP(hscif2_data_b),
4566                 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4567                 SH_PFC_PIN_GROUP(hscif2_data_c),
4568                 SH_PFC_PIN_GROUP(hscif2_clk_c),
4569                 SH_PFC_PIN_GROUP(hscif2_data_d),
4570                 SH_PFC_PIN_GROUP(i2c0),
4571                 SH_PFC_PIN_GROUP(i2c0_b),
4572                 SH_PFC_PIN_GROUP(i2c0_c),
4573                 SH_PFC_PIN_GROUP(i2c1),
4574                 SH_PFC_PIN_GROUP(i2c1_b),
4575                 SH_PFC_PIN_GROUP(i2c1_c),
4576                 SH_PFC_PIN_GROUP(i2c1_d),
4577                 SH_PFC_PIN_GROUP(i2c1_e),
4578                 SH_PFC_PIN_GROUP(i2c2),
4579                 SH_PFC_PIN_GROUP(i2c2_b),
4580                 SH_PFC_PIN_GROUP(i2c2_c),
4581                 SH_PFC_PIN_GROUP(i2c2_d),
4582                 SH_PFC_PIN_GROUP(i2c3),
4583                 SH_PFC_PIN_GROUP(i2c3_b),
4584                 SH_PFC_PIN_GROUP(i2c3_c),
4585                 SH_PFC_PIN_GROUP(i2c3_d),
4586                 SH_PFC_PIN_GROUP(i2c4),
4587                 SH_PFC_PIN_GROUP(i2c4_b),
4588                 SH_PFC_PIN_GROUP(i2c4_c),
4589                 SH_PFC_PIN_GROUP(i2c7),
4590                 SH_PFC_PIN_GROUP(i2c7_b),
4591                 SH_PFC_PIN_GROUP(i2c7_c),
4592                 SH_PFC_PIN_GROUP(i2c8),
4593                 SH_PFC_PIN_GROUP(i2c8_b),
4594                 SH_PFC_PIN_GROUP(i2c8_c),
4595                 SH_PFC_PIN_GROUP(intc_irq0),
4596                 SH_PFC_PIN_GROUP(intc_irq1),
4597                 SH_PFC_PIN_GROUP(intc_irq2),
4598                 SH_PFC_PIN_GROUP(intc_irq3),
4599                 SH_PFC_PIN_GROUP(mmc_data1),
4600                 SH_PFC_PIN_GROUP(mmc_data4),
4601                 SH_PFC_PIN_GROUP(mmc_data8),
4602                 SH_PFC_PIN_GROUP(mmc_data8_b),
4603                 SH_PFC_PIN_GROUP(mmc_ctrl),
4604                 SH_PFC_PIN_GROUP(msiof0_clk),
4605                 SH_PFC_PIN_GROUP(msiof0_sync),
4606                 SH_PFC_PIN_GROUP(msiof0_ss1),
4607                 SH_PFC_PIN_GROUP(msiof0_ss2),
4608                 SH_PFC_PIN_GROUP(msiof0_rx),
4609                 SH_PFC_PIN_GROUP(msiof0_tx),
4610                 SH_PFC_PIN_GROUP(msiof0_clk_b),
4611                 SH_PFC_PIN_GROUP(msiof0_sync_b),
4612                 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4613                 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4614                 SH_PFC_PIN_GROUP(msiof0_rx_b),
4615                 SH_PFC_PIN_GROUP(msiof0_tx_b),
4616                 SH_PFC_PIN_GROUP(msiof0_clk_c),
4617                 SH_PFC_PIN_GROUP(msiof0_sync_c),
4618                 SH_PFC_PIN_GROUP(msiof0_ss1_c),
4619                 SH_PFC_PIN_GROUP(msiof0_ss2_c),
4620                 SH_PFC_PIN_GROUP(msiof0_rx_c),
4621                 SH_PFC_PIN_GROUP(msiof0_tx_c),
4622                 SH_PFC_PIN_GROUP(msiof1_clk),
4623                 SH_PFC_PIN_GROUP(msiof1_sync),
4624                 SH_PFC_PIN_GROUP(msiof1_ss1),
4625                 SH_PFC_PIN_GROUP(msiof1_ss2),
4626                 SH_PFC_PIN_GROUP(msiof1_rx),
4627                 SH_PFC_PIN_GROUP(msiof1_tx),
4628                 SH_PFC_PIN_GROUP(msiof1_clk_b),
4629                 SH_PFC_PIN_GROUP(msiof1_sync_b),
4630                 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4631                 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4632                 SH_PFC_PIN_GROUP(msiof1_rx_b),
4633                 SH_PFC_PIN_GROUP(msiof1_tx_b),
4634                 SH_PFC_PIN_GROUP(msiof1_clk_c),
4635                 SH_PFC_PIN_GROUP(msiof1_sync_c),
4636                 SH_PFC_PIN_GROUP(msiof1_rx_c),
4637                 SH_PFC_PIN_GROUP(msiof1_tx_c),
4638                 SH_PFC_PIN_GROUP(msiof1_clk_d),
4639                 SH_PFC_PIN_GROUP(msiof1_sync_d),
4640                 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4641                 SH_PFC_PIN_GROUP(msiof1_rx_d),
4642                 SH_PFC_PIN_GROUP(msiof1_tx_d),
4643                 SH_PFC_PIN_GROUP(msiof1_clk_e),
4644                 SH_PFC_PIN_GROUP(msiof1_sync_e),
4645                 SH_PFC_PIN_GROUP(msiof1_rx_e),
4646                 SH_PFC_PIN_GROUP(msiof1_tx_e),
4647                 SH_PFC_PIN_GROUP(msiof2_clk),
4648                 SH_PFC_PIN_GROUP(msiof2_sync),
4649                 SH_PFC_PIN_GROUP(msiof2_ss1),
4650                 SH_PFC_PIN_GROUP(msiof2_ss2),
4651                 SH_PFC_PIN_GROUP(msiof2_rx),
4652                 SH_PFC_PIN_GROUP(msiof2_tx),
4653                 SH_PFC_PIN_GROUP(msiof2_clk_b),
4654                 SH_PFC_PIN_GROUP(msiof2_sync_b),
4655                 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4656                 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4657                 SH_PFC_PIN_GROUP(msiof2_rx_b),
4658                 SH_PFC_PIN_GROUP(msiof2_tx_b),
4659                 SH_PFC_PIN_GROUP(msiof2_clk_c),
4660                 SH_PFC_PIN_GROUP(msiof2_sync_c),
4661                 SH_PFC_PIN_GROUP(msiof2_rx_c),
4662                 SH_PFC_PIN_GROUP(msiof2_tx_c),
4663                 SH_PFC_PIN_GROUP(msiof2_clk_d),
4664                 SH_PFC_PIN_GROUP(msiof2_sync_d),
4665                 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4666                 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4667                 SH_PFC_PIN_GROUP(msiof2_rx_d),
4668                 SH_PFC_PIN_GROUP(msiof2_tx_d),
4669                 SH_PFC_PIN_GROUP(msiof2_clk_e),
4670                 SH_PFC_PIN_GROUP(msiof2_sync_e),
4671                 SH_PFC_PIN_GROUP(msiof2_rx_e),
4672                 SH_PFC_PIN_GROUP(msiof2_tx_e),
4673                 SH_PFC_PIN_GROUP(pwm0),
4674                 SH_PFC_PIN_GROUP(pwm0_b),
4675                 SH_PFC_PIN_GROUP(pwm1),
4676                 SH_PFC_PIN_GROUP(pwm1_b),
4677                 SH_PFC_PIN_GROUP(pwm2),
4678                 SH_PFC_PIN_GROUP(pwm2_b),
4679                 SH_PFC_PIN_GROUP(pwm3),
4680                 SH_PFC_PIN_GROUP(pwm4),
4681                 SH_PFC_PIN_GROUP(pwm4_b),
4682                 SH_PFC_PIN_GROUP(pwm5),
4683                 SH_PFC_PIN_GROUP(pwm5_b),
4684                 SH_PFC_PIN_GROUP(pwm6),
4685                 SH_PFC_PIN_GROUP(qspi_ctrl),
4686                 SH_PFC_PIN_GROUP(qspi_data2),
4687                 SH_PFC_PIN_GROUP(qspi_data4),
4688                 SH_PFC_PIN_GROUP(qspi_ctrl_b),
4689                 SH_PFC_PIN_GROUP(qspi_data2_b),
4690                 SH_PFC_PIN_GROUP(qspi_data4_b),
4691                 SH_PFC_PIN_GROUP(scif0_data),
4692                 SH_PFC_PIN_GROUP(scif0_data_b),
4693                 SH_PFC_PIN_GROUP(scif0_data_c),
4694                 SH_PFC_PIN_GROUP(scif0_data_d),
4695                 SH_PFC_PIN_GROUP(scif0_data_e),
4696                 SH_PFC_PIN_GROUP(scif1_data),
4697                 SH_PFC_PIN_GROUP(scif1_data_b),
4698                 SH_PFC_PIN_GROUP(scif1_clk_b),
4699                 SH_PFC_PIN_GROUP(scif1_data_c),
4700                 SH_PFC_PIN_GROUP(scif1_data_d),
4701                 SH_PFC_PIN_GROUP(scif2_data),
4702                 SH_PFC_PIN_GROUP(scif2_data_b),
4703                 SH_PFC_PIN_GROUP(scif2_clk_b),
4704                 SH_PFC_PIN_GROUP(scif2_data_c),
4705                 SH_PFC_PIN_GROUP(scif2_data_e),
4706                 SH_PFC_PIN_GROUP(scif3_data),
4707                 SH_PFC_PIN_GROUP(scif3_clk),
4708                 SH_PFC_PIN_GROUP(scif3_data_b),
4709                 SH_PFC_PIN_GROUP(scif3_clk_b),
4710                 SH_PFC_PIN_GROUP(scif3_data_c),
4711                 SH_PFC_PIN_GROUP(scif3_data_d),
4712                 SH_PFC_PIN_GROUP(scif4_data),
4713                 SH_PFC_PIN_GROUP(scif4_data_b),
4714                 SH_PFC_PIN_GROUP(scif4_data_c),
4715                 SH_PFC_PIN_GROUP(scif5_data),
4716                 SH_PFC_PIN_GROUP(scif5_data_b),
4717                 SH_PFC_PIN_GROUP(scifa0_data),
4718                 SH_PFC_PIN_GROUP(scifa0_data_b),
4719                 SH_PFC_PIN_GROUP(scifa1_data),
4720                 SH_PFC_PIN_GROUP(scifa1_clk),
4721                 SH_PFC_PIN_GROUP(scifa1_data_b),
4722                 SH_PFC_PIN_GROUP(scifa1_clk_b),
4723                 SH_PFC_PIN_GROUP(scifa1_data_c),
4724                 SH_PFC_PIN_GROUP(scifa2_data),
4725                 SH_PFC_PIN_GROUP(scifa2_clk),
4726                 SH_PFC_PIN_GROUP(scifa2_data_b),
4727                 SH_PFC_PIN_GROUP(scifa3_data),
4728                 SH_PFC_PIN_GROUP(scifa3_clk),
4729                 SH_PFC_PIN_GROUP(scifa3_data_b),
4730                 SH_PFC_PIN_GROUP(scifa3_clk_b),
4731                 SH_PFC_PIN_GROUP(scifa3_data_c),
4732                 SH_PFC_PIN_GROUP(scifa3_clk_c),
4733                 SH_PFC_PIN_GROUP(scifa4_data),
4734                 SH_PFC_PIN_GROUP(scifa4_data_b),
4735                 SH_PFC_PIN_GROUP(scifa4_data_c),
4736                 SH_PFC_PIN_GROUP(scifa5_data),
4737                 SH_PFC_PIN_GROUP(scifa5_data_b),
4738                 SH_PFC_PIN_GROUP(scifa5_data_c),
4739                 SH_PFC_PIN_GROUP(scifb0_data),
4740                 SH_PFC_PIN_GROUP(scifb0_clk),
4741                 SH_PFC_PIN_GROUP(scifb0_ctrl),
4742                 SH_PFC_PIN_GROUP(scifb0_data_b),
4743                 SH_PFC_PIN_GROUP(scifb0_clk_b),
4744                 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4745                 SH_PFC_PIN_GROUP(scifb0_data_c),
4746                 SH_PFC_PIN_GROUP(scifb0_clk_c),
4747                 SH_PFC_PIN_GROUP(scifb0_data_d),
4748                 SH_PFC_PIN_GROUP(scifb0_clk_d),
4749                 SH_PFC_PIN_GROUP(scifb1_data),
4750                 SH_PFC_PIN_GROUP(scifb1_clk),
4751                 SH_PFC_PIN_GROUP(scifb1_ctrl),
4752                 SH_PFC_PIN_GROUP(scifb1_data_b),
4753                 SH_PFC_PIN_GROUP(scifb1_clk_b),
4754                 SH_PFC_PIN_GROUP(scifb1_data_c),
4755                 SH_PFC_PIN_GROUP(scifb1_clk_c),
4756                 SH_PFC_PIN_GROUP(scifb1_data_d),
4757                 SH_PFC_PIN_GROUP(scifb2_data),
4758                 SH_PFC_PIN_GROUP(scifb2_clk),
4759                 SH_PFC_PIN_GROUP(scifb2_ctrl),
4760                 SH_PFC_PIN_GROUP(scifb2_data_b),
4761                 SH_PFC_PIN_GROUP(scifb2_clk_b),
4762                 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4763                 SH_PFC_PIN_GROUP(scifb2_data_c),
4764                 SH_PFC_PIN_GROUP(scifb2_clk_c),
4765                 SH_PFC_PIN_GROUP(scifb2_data_d),
4766                 SH_PFC_PIN_GROUP(scif_clk),
4767                 SH_PFC_PIN_GROUP(scif_clk_b),
4768                 SH_PFC_PIN_GROUP(sdhi0_data1),
4769                 SH_PFC_PIN_GROUP(sdhi0_data4),
4770                 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4771                 SH_PFC_PIN_GROUP(sdhi0_cd),
4772                 SH_PFC_PIN_GROUP(sdhi0_wp),
4773                 SH_PFC_PIN_GROUP(sdhi1_data1),
4774                 SH_PFC_PIN_GROUP(sdhi1_data4),
4775                 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4776                 SH_PFC_PIN_GROUP(sdhi1_cd),
4777                 SH_PFC_PIN_GROUP(sdhi1_wp),
4778                 SH_PFC_PIN_GROUP(sdhi2_data1),
4779                 SH_PFC_PIN_GROUP(sdhi2_data4),
4780                 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4781                 SH_PFC_PIN_GROUP(sdhi2_cd),
4782                 SH_PFC_PIN_GROUP(sdhi2_wp),
4783                 SH_PFC_PIN_GROUP(ssi0_data),
4784                 SH_PFC_PIN_GROUP(ssi0_data_b),
4785                 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4786                 SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4787                 SH_PFC_PIN_GROUP(ssi1_data),
4788                 SH_PFC_PIN_GROUP(ssi1_data_b),
4789                 SH_PFC_PIN_GROUP(ssi1_ctrl),
4790                 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4791                 SH_PFC_PIN_GROUP(ssi2_data),
4792                 SH_PFC_PIN_GROUP(ssi2_ctrl),
4793                 SH_PFC_PIN_GROUP(ssi3_data),
4794                 SH_PFC_PIN_GROUP(ssi34_ctrl),
4795                 SH_PFC_PIN_GROUP(ssi4_data),
4796                 SH_PFC_PIN_GROUP(ssi4_ctrl),
4797                 SH_PFC_PIN_GROUP(ssi5_data),
4798                 SH_PFC_PIN_GROUP(ssi5_ctrl),
4799                 SH_PFC_PIN_GROUP(ssi6_data),
4800                 SH_PFC_PIN_GROUP(ssi6_ctrl),
4801                 SH_PFC_PIN_GROUP(ssi7_data),
4802                 SH_PFC_PIN_GROUP(ssi7_data_b),
4803                 SH_PFC_PIN_GROUP(ssi78_ctrl),
4804                 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4805                 SH_PFC_PIN_GROUP(ssi8_data),
4806                 SH_PFC_PIN_GROUP(ssi8_data_b),
4807                 SH_PFC_PIN_GROUP(ssi9_data),
4808                 SH_PFC_PIN_GROUP(ssi9_data_b),
4809                 SH_PFC_PIN_GROUP(ssi9_ctrl),
4810                 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4811                 SH_PFC_PIN_GROUP(tpu_to0),
4812                 SH_PFC_PIN_GROUP(tpu_to1),
4813                 SH_PFC_PIN_GROUP(tpu_to2),
4814                 SH_PFC_PIN_GROUP(tpu_to3),
4815                 SH_PFC_PIN_GROUP(usb0),
4816                 SH_PFC_PIN_GROUP(usb1),
4817                 VIN_DATA_PIN_GROUP(vin0_data, 24),
4818                 VIN_DATA_PIN_GROUP(vin0_data, 20),
4819                 SH_PFC_PIN_GROUP(vin0_data18),
4820                 VIN_DATA_PIN_GROUP(vin0_data, 16),
4821                 VIN_DATA_PIN_GROUP(vin0_data, 12),
4822                 VIN_DATA_PIN_GROUP(vin0_data, 10),
4823                 VIN_DATA_PIN_GROUP(vin0_data, 8),
4824                 SH_PFC_PIN_GROUP(vin0_sync),
4825                 SH_PFC_PIN_GROUP(vin0_field),
4826                 SH_PFC_PIN_GROUP(vin0_clkenb),
4827                 SH_PFC_PIN_GROUP(vin0_clk),
4828                 SH_PFC_PIN_GROUP(vin1_data8),
4829                 SH_PFC_PIN_GROUP(vin1_sync),
4830                 SH_PFC_PIN_GROUP(vin1_field),
4831                 SH_PFC_PIN_GROUP(vin1_clkenb),
4832                 SH_PFC_PIN_GROUP(vin1_clk),
4833                 VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
4834                 VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
4835                 SH_PFC_PIN_GROUP(vin1_data18_b),
4836                 VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
4837                 VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
4838                 VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
4839                 VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
4840                 SH_PFC_PIN_GROUP(vin1_sync_b),
4841                 SH_PFC_PIN_GROUP(vin1_field_b),
4842                 SH_PFC_PIN_GROUP(vin1_clkenb_b),
4843                 SH_PFC_PIN_GROUP(vin1_clk_b),
4844                 SH_PFC_PIN_GROUP(vin2_data8),
4845                 SH_PFC_PIN_GROUP(vin2_sync),
4846                 SH_PFC_PIN_GROUP(vin2_field),
4847                 SH_PFC_PIN_GROUP(vin2_clkenb),
4848                 SH_PFC_PIN_GROUP(vin2_clk),
4849         },
4850 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
4851         .automotive = {
4852                 SH_PFC_PIN_GROUP(adi_common),
4853                 SH_PFC_PIN_GROUP(adi_chsel0),
4854                 SH_PFC_PIN_GROUP(adi_chsel1),
4855                 SH_PFC_PIN_GROUP(adi_chsel2),
4856                 SH_PFC_PIN_GROUP(adi_common_b),
4857                 SH_PFC_PIN_GROUP(adi_chsel0_b),
4858                 SH_PFC_PIN_GROUP(adi_chsel1_b),
4859                 SH_PFC_PIN_GROUP(adi_chsel2_b),
4860                 SH_PFC_PIN_GROUP(mlb_3pin),
4861         }
4862 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
4863 };
4864
4865 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
4866 static const char * const adi_groups[] = {
4867         "adi_common",
4868         "adi_chsel0",
4869         "adi_chsel1",
4870         "adi_chsel2",
4871         "adi_common_b",
4872         "adi_chsel0_b",
4873         "adi_chsel1_b",
4874         "adi_chsel2_b",
4875 };
4876 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
4877
4878 static const char * const audio_clk_groups[] = {
4879         "audio_clk_a",
4880         "audio_clk_b",
4881         "audio_clk_b_b",
4882         "audio_clk_c",
4883         "audio_clkout",
4884 };
4885
4886 static const char * const avb_groups[] = {
4887         "avb_link",
4888         "avb_magic",
4889         "avb_phy_int",
4890         "avb_mdio",
4891         "avb_mii",
4892         "avb_gmii",
4893 };
4894
4895 static const char * const can0_groups[] = {
4896         "can0_data",
4897         "can0_data_b",
4898         "can0_data_c",
4899         "can0_data_d",
4900         "can0_data_e",
4901         "can0_data_f",
4902         /*
4903          * Retained for backwards compatibility, use can_clk_groups in new
4904          * designs.
4905          */
4906         "can_clk",
4907         "can_clk_b",
4908         "can_clk_c",
4909         "can_clk_d",
4910 };
4911
4912 static const char * const can1_groups[] = {
4913         "can1_data",
4914         "can1_data_b",
4915         "can1_data_c",
4916         "can1_data_d",
4917         /*
4918          * Retained for backwards compatibility, use can_clk_groups in new
4919          * designs.
4920          */
4921         "can_clk",
4922         "can_clk_b",
4923         "can_clk_c",
4924         "can_clk_d",
4925 };
4926
4927 /*
4928  * can_clk_groups allows for independent configuration, use can_clk function
4929  * in new designs.
4930  */
4931 static const char * const can_clk_groups[] = {
4932         "can_clk",
4933         "can_clk_b",
4934         "can_clk_c",
4935         "can_clk_d",
4936 };
4937
4938 static const char * const du_groups[] = {
4939         "du_rgb666",
4940         "du_rgb888",
4941         "du_clk_out_0",
4942         "du_clk_out_1",
4943         "du_sync",
4944         "du_oddf",
4945         "du_cde",
4946         "du_disp",
4947 };
4948
4949 static const char * const du0_groups[] = {
4950         "du0_clk_in",
4951 };
4952
4953 static const char * const du1_groups[] = {
4954         "du1_clk_in",
4955         "du1_clk_in_b",
4956         "du1_clk_in_c",
4957 };
4958
4959 static const char * const eth_groups[] = {
4960         "eth_link",
4961         "eth_magic",
4962         "eth_mdio",
4963         "eth_rmii",
4964 };
4965
4966 static const char * const hscif0_groups[] = {
4967         "hscif0_data",
4968         "hscif0_clk",
4969         "hscif0_ctrl",
4970         "hscif0_data_b",
4971         "hscif0_ctrl_b",
4972         "hscif0_data_c",
4973         "hscif0_clk_c",
4974 };
4975
4976 static const char * const hscif1_groups[] = {
4977         "hscif1_data",
4978         "hscif1_clk",
4979         "hscif1_ctrl",
4980         "hscif1_data_b",
4981         "hscif1_data_c",
4982         "hscif1_clk_c",
4983         "hscif1_ctrl_c",
4984         "hscif1_data_d",
4985         "hscif1_data_e",
4986         "hscif1_clk_e",
4987         "hscif1_ctrl_e",
4988 };
4989
4990 static const char * const hscif2_groups[] = {
4991         "hscif2_data",
4992         "hscif2_clk",
4993         "hscif2_ctrl",
4994         "hscif2_data_b",
4995         "hscif2_ctrl_b",
4996         "hscif2_data_c",
4997         "hscif2_clk_c",
4998         "hscif2_data_d",
4999 };
5000
5001 static const char * const i2c0_groups[] = {
5002         "i2c0",
5003         "i2c0_b",
5004         "i2c0_c",
5005 };
5006
5007 static const char * const i2c1_groups[] = {
5008         "i2c1",
5009         "i2c1_b",
5010         "i2c1_c",
5011         "i2c1_d",
5012         "i2c1_e",
5013 };
5014
5015 static const char * const i2c2_groups[] = {
5016         "i2c2",
5017         "i2c2_b",
5018         "i2c2_c",
5019         "i2c2_d",
5020 };
5021
5022 static const char * const i2c3_groups[] = {
5023         "i2c3",
5024         "i2c3_b",
5025         "i2c3_c",
5026         "i2c3_d",
5027 };
5028
5029 static const char * const i2c4_groups[] = {
5030         "i2c4",
5031         "i2c4_b",
5032         "i2c4_c",
5033 };
5034
5035 static const char * const i2c7_groups[] = {
5036         "i2c7",
5037         "i2c7_b",
5038         "i2c7_c",
5039 };
5040
5041 static const char * const i2c8_groups[] = {
5042         "i2c8",
5043         "i2c8_b",
5044         "i2c8_c",
5045 };
5046
5047 static const char * const intc_groups[] = {
5048         "intc_irq0",
5049         "intc_irq1",
5050         "intc_irq2",
5051         "intc_irq3",
5052 };
5053
5054 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
5055 static const char * const mlb_groups[] = {
5056         "mlb_3pin",
5057 };
5058 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
5059
5060 static const char * const mmc_groups[] = {
5061         "mmc_data1",
5062         "mmc_data4",
5063         "mmc_data8",
5064         "mmc_data8_b",
5065         "mmc_ctrl",
5066 };
5067
5068 static const char * const msiof0_groups[] = {
5069         "msiof0_clk",
5070         "msiof0_sync",
5071         "msiof0_ss1",
5072         "msiof0_ss2",
5073         "msiof0_rx",
5074         "msiof0_tx",
5075         "msiof0_clk_b",
5076         "msiof0_sync_b",
5077         "msiof0_ss1_b",
5078         "msiof0_ss2_b",
5079         "msiof0_rx_b",
5080         "msiof0_tx_b",
5081         "msiof0_clk_c",
5082         "msiof0_sync_c",
5083         "msiof0_ss1_c",
5084         "msiof0_ss2_c",
5085         "msiof0_rx_c",
5086         "msiof0_tx_c",
5087 };
5088
5089 static const char * const msiof1_groups[] = {
5090         "msiof1_clk",
5091         "msiof1_sync",
5092         "msiof1_ss1",
5093         "msiof1_ss2",
5094         "msiof1_rx",
5095         "msiof1_tx",
5096         "msiof1_clk_b",
5097         "msiof1_sync_b",
5098         "msiof1_ss1_b",
5099         "msiof1_ss2_b",
5100         "msiof1_rx_b",
5101         "msiof1_tx_b",
5102         "msiof1_clk_c",
5103         "msiof1_sync_c",
5104         "msiof1_rx_c",
5105         "msiof1_tx_c",
5106         "msiof1_clk_d",
5107         "msiof1_sync_d",
5108         "msiof1_ss1_d",
5109         "msiof1_rx_d",
5110         "msiof1_tx_d",
5111         "msiof1_clk_e",
5112         "msiof1_sync_e",
5113         "msiof1_rx_e",
5114         "msiof1_tx_e",
5115 };
5116
5117 static const char * const msiof2_groups[] = {
5118         "msiof2_clk",
5119         "msiof2_sync",
5120         "msiof2_ss1",
5121         "msiof2_ss2",
5122         "msiof2_rx",
5123         "msiof2_tx",
5124         "msiof2_clk_b",
5125         "msiof2_sync_b",
5126         "msiof2_ss1_b",
5127         "msiof2_ss2_b",
5128         "msiof2_rx_b",
5129         "msiof2_tx_b",
5130         "msiof2_clk_c",
5131         "msiof2_sync_c",
5132         "msiof2_rx_c",
5133         "msiof2_tx_c",
5134         "msiof2_clk_d",
5135         "msiof2_sync_d",
5136         "msiof2_ss1_d",
5137         "msiof2_ss2_d",
5138         "msiof2_rx_d",
5139         "msiof2_tx_d",
5140         "msiof2_clk_e",
5141         "msiof2_sync_e",
5142         "msiof2_rx_e",
5143         "msiof2_tx_e",
5144 };
5145
5146 static const char * const pwm0_groups[] = {
5147         "pwm0",
5148         "pwm0_b",
5149 };
5150
5151 static const char * const pwm1_groups[] = {
5152         "pwm1",
5153         "pwm1_b",
5154 };
5155
5156 static const char * const pwm2_groups[] = {
5157         "pwm2",
5158         "pwm2_b",
5159 };
5160
5161 static const char * const pwm3_groups[] = {
5162         "pwm3",
5163 };
5164
5165 static const char * const pwm4_groups[] = {
5166         "pwm4",
5167         "pwm4_b",
5168 };
5169
5170 static const char * const pwm5_groups[] = {
5171         "pwm5",
5172         "pwm5_b",
5173 };
5174
5175 static const char * const pwm6_groups[] = {
5176         "pwm6",
5177 };
5178
5179 static const char * const qspi_groups[] = {
5180         "qspi_ctrl",
5181         "qspi_data2",
5182         "qspi_data4",
5183         "qspi_ctrl_b",
5184         "qspi_data2_b",
5185         "qspi_data4_b",
5186 };
5187
5188 static const char * const scif0_groups[] = {
5189         "scif0_data",
5190         "scif0_data_b",
5191         "scif0_data_c",
5192         "scif0_data_d",
5193         "scif0_data_e",
5194 };
5195
5196 static const char * const scif1_groups[] = {
5197         "scif1_data",
5198         "scif1_data_b",
5199         "scif1_clk_b",
5200         "scif1_data_c",
5201         "scif1_data_d",
5202 };
5203
5204 static const char * const scif2_groups[] = {
5205         "scif2_data",
5206         "scif2_data_b",
5207         "scif2_clk_b",
5208         "scif2_data_c",
5209         "scif2_data_e",
5210 };
5211 static const char * const scif3_groups[] = {
5212         "scif3_data",
5213         "scif3_clk",
5214         "scif3_data_b",
5215         "scif3_clk_b",
5216         "scif3_data_c",
5217         "scif3_data_d",
5218 };
5219 static const char * const scif4_groups[] = {
5220         "scif4_data",
5221         "scif4_data_b",
5222         "scif4_data_c",
5223 };
5224 static const char * const scif5_groups[] = {
5225         "scif5_data",
5226         "scif5_data_b",
5227 };
5228 static const char * const scifa0_groups[] = {
5229         "scifa0_data",
5230         "scifa0_data_b",
5231 };
5232 static const char * const scifa1_groups[] = {
5233         "scifa1_data",
5234         "scifa1_clk",
5235         "scifa1_data_b",
5236         "scifa1_clk_b",
5237         "scifa1_data_c",
5238 };
5239 static const char * const scifa2_groups[] = {
5240         "scifa2_data",
5241         "scifa2_clk",
5242         "scifa2_data_b",
5243 };
5244 static const char * const scifa3_groups[] = {
5245         "scifa3_data",
5246         "scifa3_clk",
5247         "scifa3_data_b",
5248         "scifa3_clk_b",
5249         "scifa3_data_c",
5250         "scifa3_clk_c",
5251 };
5252 static const char * const scifa4_groups[] = {
5253         "scifa4_data",
5254         "scifa4_data_b",
5255         "scifa4_data_c",
5256 };
5257 static const char * const scifa5_groups[] = {
5258         "scifa5_data",
5259         "scifa5_data_b",
5260         "scifa5_data_c",
5261 };
5262 static const char * const scifb0_groups[] = {
5263         "scifb0_data",
5264         "scifb0_clk",
5265         "scifb0_ctrl",
5266         "scifb0_data_b",
5267         "scifb0_clk_b",
5268         "scifb0_ctrl_b",
5269         "scifb0_data_c",
5270         "scifb0_clk_c",
5271         "scifb0_data_d",
5272         "scifb0_clk_d",
5273 };
5274 static const char * const scifb1_groups[] = {
5275         "scifb1_data",
5276         "scifb1_clk",
5277         "scifb1_ctrl",
5278         "scifb1_data_b",
5279         "scifb1_clk_b",
5280         "scifb1_data_c",
5281         "scifb1_clk_c",
5282         "scifb1_data_d",
5283 };
5284 static const char * const scifb2_groups[] = {
5285         "scifb2_data",
5286         "scifb2_clk",
5287         "scifb2_ctrl",
5288         "scifb2_data_b",
5289         "scifb2_clk_b",
5290         "scifb2_ctrl_b",
5291         "scifb2_data_c",
5292         "scifb2_clk_c",
5293         "scifb2_data_d",
5294 };
5295
5296 static const char * const scif_clk_groups[] = {
5297         "scif_clk",
5298         "scif_clk_b",
5299 };
5300
5301 static const char * const sdhi0_groups[] = {
5302         "sdhi0_data1",
5303         "sdhi0_data4",
5304         "sdhi0_ctrl",
5305         "sdhi0_cd",
5306         "sdhi0_wp",
5307 };
5308
5309 static const char * const sdhi1_groups[] = {
5310         "sdhi1_data1",
5311         "sdhi1_data4",
5312         "sdhi1_ctrl",
5313         "sdhi1_cd",
5314         "sdhi1_wp",
5315 };
5316
5317 static const char * const sdhi2_groups[] = {
5318         "sdhi2_data1",
5319         "sdhi2_data4",
5320         "sdhi2_ctrl",
5321         "sdhi2_cd",
5322         "sdhi2_wp",
5323 };
5324
5325 static const char * const ssi_groups[] = {
5326         "ssi0_data",
5327         "ssi0_data_b",
5328         "ssi0129_ctrl",
5329         "ssi0129_ctrl_b",
5330         "ssi1_data",
5331         "ssi1_data_b",
5332         "ssi1_ctrl",
5333         "ssi1_ctrl_b",
5334         "ssi2_data",
5335         "ssi2_ctrl",
5336         "ssi3_data",
5337         "ssi34_ctrl",
5338         "ssi4_data",
5339         "ssi4_ctrl",
5340         "ssi5_data",
5341         "ssi5_ctrl",
5342         "ssi6_data",
5343         "ssi6_ctrl",
5344         "ssi7_data",
5345         "ssi7_data_b",
5346         "ssi78_ctrl",
5347         "ssi78_ctrl_b",
5348         "ssi8_data",
5349         "ssi8_data_b",
5350         "ssi9_data",
5351         "ssi9_data_b",
5352         "ssi9_ctrl",
5353         "ssi9_ctrl_b",
5354 };
5355
5356 static const char * const tpu_groups[] = {
5357         "tpu_to0",
5358         "tpu_to1",
5359         "tpu_to2",
5360         "tpu_to3",
5361 };
5362
5363 static const char * const usb0_groups[] = {
5364         "usb0",
5365 };
5366 static const char * const usb1_groups[] = {
5367         "usb1",
5368 };
5369
5370 static const char * const vin0_groups[] = {
5371         "vin0_data24",
5372         "vin0_data20",
5373         "vin0_data18",
5374         "vin0_data16",
5375         "vin0_data12",
5376         "vin0_data10",
5377         "vin0_data8",
5378         "vin0_sync",
5379         "vin0_field",
5380         "vin0_clkenb",
5381         "vin0_clk",
5382 };
5383
5384 static const char * const vin1_groups[] = {
5385         "vin1_data8",
5386         "vin1_sync",
5387         "vin1_field",
5388         "vin1_clkenb",
5389         "vin1_clk",
5390         "vin1_data24_b",
5391         "vin1_data20_b",
5392         "vin1_data18_b",
5393         "vin1_data16_b",
5394         "vin1_data12_b",
5395         "vin1_data10_b",
5396         "vin1_data8_b",
5397         "vin1_sync_b",
5398         "vin1_field_b",
5399         "vin1_clkenb_b",
5400         "vin1_clk_b",
5401 };
5402
5403 static const char * const vin2_groups[] = {
5404         "vin2_data8",
5405         "vin2_sync",
5406         "vin2_field",
5407         "vin2_clkenb",
5408         "vin2_clk",
5409 };
5410
5411 static const struct {
5412         struct sh_pfc_function common[58];
5413 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
5414         struct sh_pfc_function automotive[2];
5415 #endif
5416 } pinmux_functions = {
5417         .common = {
5418                 SH_PFC_FUNCTION(audio_clk),
5419                 SH_PFC_FUNCTION(avb),
5420                 SH_PFC_FUNCTION(can0),
5421                 SH_PFC_FUNCTION(can1),
5422                 SH_PFC_FUNCTION(can_clk),
5423                 SH_PFC_FUNCTION(du),
5424                 SH_PFC_FUNCTION(du0),
5425                 SH_PFC_FUNCTION(du1),
5426                 SH_PFC_FUNCTION(eth),
5427                 SH_PFC_FUNCTION(hscif0),
5428                 SH_PFC_FUNCTION(hscif1),
5429                 SH_PFC_FUNCTION(hscif2),
5430                 SH_PFC_FUNCTION(i2c0),
5431                 SH_PFC_FUNCTION(i2c1),
5432                 SH_PFC_FUNCTION(i2c2),
5433                 SH_PFC_FUNCTION(i2c3),
5434                 SH_PFC_FUNCTION(i2c4),
5435                 SH_PFC_FUNCTION(i2c7),
5436                 SH_PFC_FUNCTION(i2c8),
5437                 SH_PFC_FUNCTION(intc),
5438                 SH_PFC_FUNCTION(mmc),
5439                 SH_PFC_FUNCTION(msiof0),
5440                 SH_PFC_FUNCTION(msiof1),
5441                 SH_PFC_FUNCTION(msiof2),
5442                 SH_PFC_FUNCTION(pwm0),
5443                 SH_PFC_FUNCTION(pwm1),
5444                 SH_PFC_FUNCTION(pwm2),
5445                 SH_PFC_FUNCTION(pwm3),
5446                 SH_PFC_FUNCTION(pwm4),
5447                 SH_PFC_FUNCTION(pwm5),
5448                 SH_PFC_FUNCTION(pwm6),
5449                 SH_PFC_FUNCTION(qspi),
5450                 SH_PFC_FUNCTION(scif0),
5451                 SH_PFC_FUNCTION(scif1),
5452                 SH_PFC_FUNCTION(scif2),
5453                 SH_PFC_FUNCTION(scif3),
5454                 SH_PFC_FUNCTION(scif4),
5455                 SH_PFC_FUNCTION(scif5),
5456                 SH_PFC_FUNCTION(scifa0),
5457                 SH_PFC_FUNCTION(scifa1),
5458                 SH_PFC_FUNCTION(scifa2),
5459                 SH_PFC_FUNCTION(scifa3),
5460                 SH_PFC_FUNCTION(scifa4),
5461                 SH_PFC_FUNCTION(scifa5),
5462                 SH_PFC_FUNCTION(scifb0),
5463                 SH_PFC_FUNCTION(scifb1),
5464                 SH_PFC_FUNCTION(scifb2),
5465                 SH_PFC_FUNCTION(scif_clk),
5466                 SH_PFC_FUNCTION(sdhi0),
5467                 SH_PFC_FUNCTION(sdhi1),
5468                 SH_PFC_FUNCTION(sdhi2),
5469                 SH_PFC_FUNCTION(ssi),
5470                 SH_PFC_FUNCTION(tpu),
5471                 SH_PFC_FUNCTION(usb0),
5472                 SH_PFC_FUNCTION(usb1),
5473                 SH_PFC_FUNCTION(vin0),
5474                 SH_PFC_FUNCTION(vin1),
5475                 SH_PFC_FUNCTION(vin2),
5476         },
5477 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
5478         .automotive = {
5479                 SH_PFC_FUNCTION(adi),
5480                 SH_PFC_FUNCTION(mlb),
5481         }
5482 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
5483 };
5484
5485 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5486         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
5487                 GP_0_31_FN, FN_IP1_22_20,
5488                 GP_0_30_FN, FN_IP1_19_17,
5489                 GP_0_29_FN, FN_IP1_16_14,
5490                 GP_0_28_FN, FN_IP1_13_11,
5491                 GP_0_27_FN, FN_IP1_10_8,
5492                 GP_0_26_FN, FN_IP1_7_6,
5493                 GP_0_25_FN, FN_IP1_5_4,
5494                 GP_0_24_FN, FN_IP1_3_2,
5495                 GP_0_23_FN, FN_IP1_1_0,
5496                 GP_0_22_FN, FN_IP0_30_29,
5497                 GP_0_21_FN, FN_IP0_28_27,
5498                 GP_0_20_FN, FN_IP0_26_25,
5499                 GP_0_19_FN, FN_IP0_24_23,
5500                 GP_0_18_FN, FN_IP0_22_21,
5501                 GP_0_17_FN, FN_IP0_20_19,
5502                 GP_0_16_FN, FN_IP0_18_16,
5503                 GP_0_15_FN, FN_IP0_15,
5504                 GP_0_14_FN, FN_IP0_14,
5505                 GP_0_13_FN, FN_IP0_13,
5506                 GP_0_12_FN, FN_IP0_12,
5507                 GP_0_11_FN, FN_IP0_11,
5508                 GP_0_10_FN, FN_IP0_10,
5509                 GP_0_9_FN, FN_IP0_9,
5510                 GP_0_8_FN, FN_IP0_8,
5511                 GP_0_7_FN, FN_IP0_7,
5512                 GP_0_6_FN, FN_IP0_6,
5513                 GP_0_5_FN, FN_IP0_5,
5514                 GP_0_4_FN, FN_IP0_4,
5515                 GP_0_3_FN, FN_IP0_3,
5516                 GP_0_2_FN, FN_IP0_2,
5517                 GP_0_1_FN, FN_IP0_1,
5518                 GP_0_0_FN, FN_IP0_0, ))
5519         },
5520         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
5521                 0, 0,
5522                 0, 0,
5523                 0, 0,
5524                 0, 0,
5525                 0, 0,
5526                 0, 0,
5527                 GP_1_25_FN, FN_IP3_21_20,
5528                 GP_1_24_FN, FN_IP3_19_18,
5529                 GP_1_23_FN, FN_IP3_17_16,
5530                 GP_1_22_FN, FN_IP3_15_14,
5531                 GP_1_21_FN, FN_IP3_13_12,
5532                 GP_1_20_FN, FN_IP3_11_9,
5533                 GP_1_19_FN, FN_RD_N,
5534                 GP_1_18_FN, FN_IP3_8_6,
5535                 GP_1_17_FN, FN_IP3_5_3,
5536                 GP_1_16_FN, FN_IP3_2_0,
5537                 GP_1_15_FN, FN_IP2_29_27,
5538                 GP_1_14_FN, FN_IP2_26_25,
5539                 GP_1_13_FN, FN_IP2_24_23,
5540                 GP_1_12_FN, FN_EX_CS0_N,
5541                 GP_1_11_FN, FN_IP2_22_21,
5542                 GP_1_10_FN, FN_IP2_20_19,
5543                 GP_1_9_FN, FN_IP2_18_16,
5544                 GP_1_8_FN, FN_IP2_15_13,
5545                 GP_1_7_FN, FN_IP2_12_10,
5546                 GP_1_6_FN, FN_IP2_9_7,
5547                 GP_1_5_FN, FN_IP2_6_5,
5548                 GP_1_4_FN, FN_IP2_4_3,
5549                 GP_1_3_FN, FN_IP2_2_0,
5550                 GP_1_2_FN, FN_IP1_31_29,
5551                 GP_1_1_FN, FN_IP1_28_26,
5552                 GP_1_0_FN, FN_IP1_25_23, ))
5553         },
5554         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
5555                 GP_2_31_FN, FN_IP6_7_6,
5556                 GP_2_30_FN, FN_IP6_5_3,
5557                 GP_2_29_FN, FN_IP6_2_0,
5558                 GP_2_28_FN, FN_AUDIO_CLKA,
5559                 GP_2_27_FN, FN_IP5_31_29,
5560                 GP_2_26_FN, FN_IP5_28_26,
5561                 GP_2_25_FN, FN_IP5_25_24,
5562                 GP_2_24_FN, FN_IP5_23_22,
5563                 GP_2_23_FN, FN_IP5_21_20,
5564                 GP_2_22_FN, FN_IP5_19_17,
5565                 GP_2_21_FN, FN_IP5_16_15,
5566                 GP_2_20_FN, FN_IP5_14_12,
5567                 GP_2_19_FN, FN_IP5_11_9,
5568                 GP_2_18_FN, FN_IP5_8_6,
5569                 GP_2_17_FN, FN_IP5_5_3,
5570                 GP_2_16_FN, FN_IP5_2_0,
5571                 GP_2_15_FN, FN_IP4_30_28,
5572                 GP_2_14_FN, FN_IP4_27_26,
5573                 GP_2_13_FN, FN_IP4_25_24,
5574                 GP_2_12_FN, FN_IP4_23_22,
5575                 GP_2_11_FN, FN_IP4_21,
5576                 GP_2_10_FN, FN_IP4_20,
5577                 GP_2_9_FN, FN_IP4_19,
5578                 GP_2_8_FN, FN_IP4_18_16,
5579                 GP_2_7_FN, FN_IP4_15_13,
5580                 GP_2_6_FN, FN_IP4_12_10,
5581                 GP_2_5_FN, FN_IP4_9_8,
5582                 GP_2_4_FN, FN_IP4_7_5,
5583                 GP_2_3_FN, FN_IP4_4_2,
5584                 GP_2_2_FN, FN_IP4_1_0,
5585                 GP_2_1_FN, FN_IP3_30_28,
5586                 GP_2_0_FN, FN_IP3_27_25 ))
5587         },
5588         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5589                 GP_3_31_FN, FN_IP9_18_17,
5590                 GP_3_30_FN, FN_IP9_16,
5591                 GP_3_29_FN, FN_IP9_15_13,
5592                 GP_3_28_FN, FN_IP9_12,
5593                 GP_3_27_FN, FN_IP9_11,
5594                 GP_3_26_FN, FN_IP9_10_8,
5595                 GP_3_25_FN, FN_IP9_7,
5596                 GP_3_24_FN, FN_IP9_6,
5597                 GP_3_23_FN, FN_IP9_5_3,
5598                 GP_3_22_FN, FN_IP9_2_0,
5599                 GP_3_21_FN, FN_IP8_30_28,
5600                 GP_3_20_FN, FN_IP8_27_26,
5601                 GP_3_19_FN, FN_IP8_25_24,
5602                 GP_3_18_FN, FN_IP8_23_21,
5603                 GP_3_17_FN, FN_IP8_20_18,
5604                 GP_3_16_FN, FN_IP8_17_15,
5605                 GP_3_15_FN, FN_IP8_14_12,
5606                 GP_3_14_FN, FN_IP8_11_9,
5607                 GP_3_13_FN, FN_IP8_8_6,
5608                 GP_3_12_FN, FN_IP8_5_3,
5609                 GP_3_11_FN, FN_IP8_2_0,
5610                 GP_3_10_FN, FN_IP7_29_27,
5611                 GP_3_9_FN, FN_IP7_26_24,
5612                 GP_3_8_FN, FN_IP7_23_21,
5613                 GP_3_7_FN, FN_IP7_20_19,
5614                 GP_3_6_FN, FN_IP7_18_17,
5615                 GP_3_5_FN, FN_IP7_16_15,
5616                 GP_3_4_FN, FN_IP7_14_13,
5617                 GP_3_3_FN, FN_IP7_12_11,
5618                 GP_3_2_FN, FN_IP7_10_9,
5619                 GP_3_1_FN, FN_IP7_8_6,
5620                 GP_3_0_FN, FN_IP7_5_3 ))
5621         },
5622         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5623                 GP_4_31_FN, FN_IP15_5_4,
5624                 GP_4_30_FN, FN_IP15_3_2,
5625                 GP_4_29_FN, FN_IP15_1_0,
5626                 GP_4_28_FN, FN_IP11_8_6,
5627                 GP_4_27_FN, FN_IP11_5_3,
5628                 GP_4_26_FN, FN_IP11_2_0,
5629                 GP_4_25_FN, FN_IP10_31_29,
5630                 GP_4_24_FN, FN_IP10_28_27,
5631                 GP_4_23_FN, FN_IP10_26_25,
5632                 GP_4_22_FN, FN_IP10_24_22,
5633                 GP_4_21_FN, FN_IP10_21_19,
5634                 GP_4_20_FN, FN_IP10_18_17,
5635                 GP_4_19_FN, FN_IP10_16_15,
5636                 GP_4_18_FN, FN_IP10_14_12,
5637                 GP_4_17_FN, FN_IP10_11_9,
5638                 GP_4_16_FN, FN_IP10_8_6,
5639                 GP_4_15_FN, FN_IP10_5_3,
5640                 GP_4_14_FN, FN_IP10_2_0,
5641                 GP_4_13_FN, FN_IP9_31_29,
5642                 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5643                 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5644                 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5645                 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5646                 GP_4_8_FN, FN_IP9_28_27,
5647                 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5648                 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5649                 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5650                 GP_4_4_FN, FN_IP9_26_25,
5651                 GP_4_3_FN, FN_IP9_24_23,
5652                 GP_4_2_FN, FN_IP9_22_21,
5653                 GP_4_1_FN, FN_IP9_20_19,
5654                 GP_4_0_FN, FN_VI0_CLK ))
5655         },
5656         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5657                 GP_5_31_FN, FN_IP3_24_22,
5658                 GP_5_30_FN, FN_IP13_9_7,
5659                 GP_5_29_FN, FN_IP13_6_5,
5660                 GP_5_28_FN, FN_IP13_4_3,
5661                 GP_5_27_FN, FN_IP13_2_0,
5662                 GP_5_26_FN, FN_IP12_29_27,
5663                 GP_5_25_FN, FN_IP12_26_24,
5664                 GP_5_24_FN, FN_IP12_23_22,
5665                 GP_5_23_FN, FN_IP12_21_20,
5666                 GP_5_22_FN, FN_IP12_19_18,
5667                 GP_5_21_FN, FN_IP12_17_16,
5668                 GP_5_20_FN, FN_IP12_15_13,
5669                 GP_5_19_FN, FN_IP12_12_10,
5670                 GP_5_18_FN, FN_IP12_9_7,
5671                 GP_5_17_FN, FN_IP12_6_4,
5672                 GP_5_16_FN, FN_IP12_3_2,
5673                 GP_5_15_FN, FN_IP12_1_0,
5674                 GP_5_14_FN, FN_IP11_31_30,
5675                 GP_5_13_FN, FN_IP11_29_28,
5676                 GP_5_12_FN, FN_IP11_27,
5677                 GP_5_11_FN, FN_IP11_26,
5678                 GP_5_10_FN, FN_IP11_25,
5679                 GP_5_9_FN, FN_IP11_24,
5680                 GP_5_8_FN, FN_IP11_23,
5681                 GP_5_7_FN, FN_IP11_22,
5682                 GP_5_6_FN, FN_IP11_21,
5683                 GP_5_5_FN, FN_IP11_20,
5684                 GP_5_4_FN, FN_IP11_19,
5685                 GP_5_3_FN, FN_IP11_18_17,
5686                 GP_5_2_FN, FN_IP11_16_15,
5687                 GP_5_1_FN, FN_IP11_14_12,
5688                 GP_5_0_FN, FN_IP11_11_9 ))
5689         },
5690         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
5691                 GP_6_31_FN, FN_DU0_DOTCLKIN,
5692                 GP_6_30_FN, FN_USB1_OVC,
5693                 GP_6_29_FN, FN_IP14_31_29,
5694                 GP_6_28_FN, FN_IP14_28_26,
5695                 GP_6_27_FN, FN_IP14_25_23,
5696                 GP_6_26_FN, FN_IP14_22_20,
5697                 GP_6_25_FN, FN_IP14_19_17,
5698                 GP_6_24_FN, FN_IP14_16_14,
5699                 GP_6_23_FN, FN_IP14_13_11,
5700                 GP_6_22_FN, FN_IP14_10_8,
5701                 GP_6_21_FN, FN_IP14_7,
5702                 GP_6_20_FN, FN_IP14_6,
5703                 GP_6_19_FN, FN_IP14_5,
5704                 GP_6_18_FN, FN_IP14_4,
5705                 GP_6_17_FN, FN_IP14_3,
5706                 GP_6_16_FN, FN_IP14_2,
5707                 GP_6_15_FN, FN_IP14_1_0,
5708                 GP_6_14_FN, FN_IP13_30_28,
5709                 GP_6_13_FN, FN_IP13_27,
5710                 GP_6_12_FN, FN_IP13_26,
5711                 GP_6_11_FN, FN_IP13_25,
5712                 GP_6_10_FN, FN_IP13_24_23,
5713                 GP_6_9_FN, FN_IP13_22,
5714                 GP_6_8_FN, FN_SD1_CLK,
5715                 GP_6_7_FN, FN_IP13_21_19,
5716                 GP_6_6_FN, FN_IP13_18_16,
5717                 GP_6_5_FN, FN_IP13_15,
5718                 GP_6_4_FN, FN_IP13_14,
5719                 GP_6_3_FN, FN_IP13_13,
5720                 GP_6_2_FN, FN_IP13_12,
5721                 GP_6_1_FN, FN_IP13_11,
5722                 GP_6_0_FN, FN_IP13_10 ))
5723         },
5724         { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
5725                 0, 0,
5726                 0, 0,
5727                 0, 0,
5728                 0, 0,
5729                 0, 0,
5730                 0, 0,
5731                 GP_7_25_FN, FN_USB1_PWEN,
5732                 GP_7_24_FN, FN_USB0_OVC,
5733                 GP_7_23_FN, FN_USB0_PWEN,
5734                 GP_7_22_FN, FN_IP15_14_12,
5735                 GP_7_21_FN, FN_IP15_11_9,
5736                 GP_7_20_FN, FN_IP15_8_6,
5737                 GP_7_19_FN, FN_IP7_2_0,
5738                 GP_7_18_FN, FN_IP6_29_27,
5739                 GP_7_17_FN, FN_IP6_26_24,
5740                 GP_7_16_FN, FN_IP6_23_21,
5741                 GP_7_15_FN, FN_IP6_20_19,
5742                 GP_7_14_FN, FN_IP6_18_16,
5743                 GP_7_13_FN, FN_IP6_15_14,
5744                 GP_7_12_FN, FN_IP6_13_12,
5745                 GP_7_11_FN, FN_IP6_11_10,
5746                 GP_7_10_FN, FN_IP6_9_8,
5747                 GP_7_9_FN, FN_IP16_11_10,
5748                 GP_7_8_FN, FN_IP16_9_8,
5749                 GP_7_7_FN, FN_IP16_7_6,
5750                 GP_7_6_FN, FN_IP16_5_3,
5751                 GP_7_5_FN, FN_IP16_2_0,
5752                 GP_7_4_FN, FN_IP15_29_27,
5753                 GP_7_3_FN, FN_IP15_26_24,
5754                 GP_7_2_FN, FN_IP15_23_21,
5755                 GP_7_1_FN, FN_IP15_20_18,
5756                 GP_7_0_FN, FN_IP15_17_15 ))
5757         },
5758         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5759                              GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
5760                                    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
5761                              GROUP(
5762                 /* IP0_31 [1] */
5763                 0, 0,
5764                 /* IP0_30_29 [2] */
5765                 FN_A6, FN_MSIOF1_SCK,
5766                 0, 0,
5767                 /* IP0_28_27 [2] */
5768                 FN_A5, FN_MSIOF0_RXD_B,
5769                 0, 0,
5770                 /* IP0_26_25 [2] */
5771                 FN_A4, FN_MSIOF0_TXD_B,
5772                 0, 0,
5773                 /* IP0_24_23 [2] */
5774                 FN_A3, FN_MSIOF0_SS2_B,
5775                 0, 0,
5776                 /* IP0_22_21 [2] */
5777                 FN_A2, FN_MSIOF0_SS1_B,
5778                 0, 0,
5779                 /* IP0_20_19 [2] */
5780                 FN_A1, FN_MSIOF0_SYNC_B,
5781                 0, 0,
5782                 /* IP0_18_16 [3] */
5783                 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
5784                 0, 0, 0,
5785                 /* IP0_15 [1] */
5786                 FN_D15, 0,
5787                 /* IP0_14 [1] */
5788                 FN_D14, 0,
5789                 /* IP0_13 [1] */
5790                 FN_D13, 0,
5791                 /* IP0_12 [1] */
5792                 FN_D12, 0,
5793                 /* IP0_11 [1] */
5794                 FN_D11, 0,
5795                 /* IP0_10 [1] */
5796                 FN_D10, 0,
5797                 /* IP0_9 [1] */
5798                 FN_D9, 0,
5799                 /* IP0_8 [1] */
5800                 FN_D8, 0,
5801                 /* IP0_7 [1] */
5802                 FN_D7, 0,
5803                 /* IP0_6 [1] */
5804                 FN_D6, 0,
5805                 /* IP0_5 [1] */
5806                 FN_D5, 0,
5807                 /* IP0_4 [1] */
5808                 FN_D4, 0,
5809                 /* IP0_3 [1] */
5810                 FN_D3, 0,
5811                 /* IP0_2 [1] */
5812                 FN_D2, 0,
5813                 /* IP0_1 [1] */
5814                 FN_D1, 0,
5815                 /* IP0_0 [1] */
5816                 FN_D0, 0, ))
5817         },
5818         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5819                              GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
5820                              GROUP(
5821                 /* IP1_31_29 [3] */
5822                 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5823                 0, 0, 0,
5824                 /* IP1_28_26 [3] */
5825                 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
5826                 0, 0, 0, 0,
5827                 /* IP1_25_23 [3] */
5828                 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5829                 0, 0, 0,
5830                 /* IP1_22_20 [3] */
5831                 FN_A15, FN_BPFCLK_C,
5832                 0, 0, 0, 0, 0, 0,
5833                 /* IP1_19_17 [3] */
5834                 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5835                 0, 0, 0,
5836                 /* IP1_16_14 [3] */
5837                 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5838                 0, 0, 0, 0,
5839                 /* IP1_13_11 [3] */
5840                 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
5841                 0, 0, 0, 0,
5842                 /* IP1_10_8 [3] */
5843                 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
5844                 0, 0, 0, 0,
5845                 /* IP1_7_6 [2] */
5846                 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5847                 /* IP1_5_4 [2] */
5848                 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
5849                 /* IP1_3_2 [2] */
5850                 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5851                 /* IP1_1_0 [2] */
5852                 FN_A7, FN_MSIOF1_SYNC,
5853                 0, 0, ))
5854         },
5855         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5856                              GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
5857                              GROUP(
5858                 /* IP2_31_30 [2] */
5859                 0, 0, 0, 0,
5860                 /* IP2_29_27 [3] */
5861                 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5862                 FN_ATAG0_N, 0, FN_EX_WAIT1,
5863                 0, 0,
5864                 /* IP2_26_25 [2] */
5865                 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5866                 /* IP2_24_23 [2] */
5867                 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5868                 /* IP2_22_21 [2] */
5869                 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
5870                 /* IP2_20_19 [2] */
5871                 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
5872                 /* IP2_18_16 [3] */
5873                 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5874                 0, 0,
5875                 /* IP2_15_13 [3] */
5876                 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5877                 0, 0, 0,
5878                 /* IP2_12_10 [3] */
5879                 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5880                 0, 0, 0,
5881                 /* IP2_9_7 [3] */
5882                 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5883                 0, 0, 0,
5884                 /* IP2_6_5 [2] */
5885                 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5886                 /* IP2_4_3 [2] */
5887                 FN_A20, FN_SPCLK, 0, 0,
5888                 /* IP2_2_0 [3] */
5889                 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5890                 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
5891         },
5892         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5893                              GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
5894                              GROUP(
5895                 /* IP3_31 [1] */
5896                 0, 0,
5897                 /* IP3_30_28 [3] */
5898                 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5899                 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5900                 0, 0, 0,
5901                 /* IP3_27_25 [3] */
5902                 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5903                 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5904                 0, 0, 0,
5905                 /* IP3_24_22 [3] */
5906                 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5907                 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5908                 /* IP3_21_20 [2] */
5909                 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5910                 /* IP3_19_18 [2] */
5911                 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5912                 /* IP3_17_16 [2] */
5913                 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5914                 /* IP3_15_14 [2] */
5915                 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5916                 /* IP3_13_12 [2] */
5917                 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5918                 /* IP3_11_9 [3] */
5919                 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5920                 0, 0, 0,
5921                 /* IP3_8_6 [3] */
5922                 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5923                 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5924                 /* IP3_5_3 [3] */
5925                 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5926                 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5927                 /* IP3_2_0 [3] */
5928                 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5929                 0, 0, 0, ))
5930         },
5931         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5932                              GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
5933                                    3, 3, 2),
5934                              GROUP(
5935                 /* IP4_31 [1] */
5936                 0, 0,
5937                 /* IP4_30_28 [3] */
5938                 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5939                 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5940                 0, 0,
5941                 /* IP4_27_26 [2] */
5942                 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5943                 /* IP4_25_24 [2] */
5944                 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5945                 /* IP4_23_22 [2] */
5946                 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5947                 /* IP4_21 [1] */
5948                 FN_SSI_SDATA3, 0,
5949                 /* IP4_20 [1] */
5950                 FN_SSI_WS34, 0,
5951                 /* IP4_19 [1] */
5952                 FN_SSI_SCK34, 0,
5953                 /* IP4_18_16 [3] */
5954                 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5955                 0, 0, 0, 0,
5956                 /* IP4_15_13 [3] */
5957                 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
5958                 FN_GLO_Q1_D, FN_HCTS1_N_E,
5959                 0, 0,
5960                 /* IP4_12_10 [3] */
5961                 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5962                 0, 0, 0,
5963                 /* IP4_9_8 [2] */
5964                 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
5965                 /* IP4_7_5 [3] */
5966                 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
5967                 FN_GLO_I1_D, 0, 0, 0,
5968                 /* IP4_4_2 [3] */
5969                 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
5970                 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5971                 0, 0, 0,
5972                 /* IP4_1_0 [2] */
5973                 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
5974                 ))
5975         },
5976         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5977                              GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
5978                              GROUP(
5979                 /* IP5_31_29 [3] */
5980                 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5981                 0, 0, 0, 0, 0,
5982                 /* IP5_28_26 [3] */
5983                 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5984                 0, 0, 0, 0,
5985                 /* IP5_25_24 [2] */
5986                 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5987                 /* IP5_23_22 [2] */
5988                 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5989                 /* IP5_21_20 [2] */
5990                 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5991                 /* IP5_19_17 [3] */
5992                 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5993                 0, 0, 0, 0,
5994                 /* IP5_16_15 [2] */
5995                 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5996                 /* IP5_14_12 [3] */
5997                 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5998                 0, 0, 0, 0,
5999                 /* IP5_11_9 [3] */
6000                 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
6001                 0, 0, 0, 0,
6002                 /* IP5_8_6 [3] */
6003                 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
6004                 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
6005                 0, 0,
6006                 /* IP5_5_3 [3] */
6007                 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
6008                 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
6009                 0, 0,
6010                 /* IP5_2_0 [3] */
6011                 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
6012                 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
6013                 0, 0, ))
6014         },
6015         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
6016                              GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
6017                              GROUP(
6018                 /* IP6_31_30 [2] */
6019                 0, 0, 0, 0,
6020                 /* IP6_29_27 [3] */
6021                 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
6022                 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
6023                 0, 0, 0,
6024                 /* IP6_26_24 [3] */
6025                 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
6026                 FN_GPS_CLK_C, FN_GPS_CLK_D,
6027                 0, 0, 0,
6028                 /* IP6_23_21 [3] */
6029                 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
6030                 FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
6031                 0, 0, 0,
6032                 /* IP6_20_19 [2] */
6033                 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
6034                 /* IP6_18_16 [3] */
6035                 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
6036                 FN_INTC_IRQ4_N, 0, 0, 0,
6037                 /* IP6_15_14 [2] */
6038                 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
6039                 /* IP6_13_12 [2] */
6040                 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
6041                 /* IP6_11_10 [2] */
6042                 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
6043                 /* IP6_9_8 [2] */
6044                 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
6045                 /* IP6_7_6 [2] */
6046                 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
6047                 /* IP6_5_3 [3] */
6048                 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
6049                 FN_SCIFA2_RXD, FN_FMIN_E,
6050                 0, 0,
6051                 /* IP6_2_0 [3] */
6052                 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
6053                 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
6054                 0, 0, ))
6055         },
6056         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
6057                              GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
6058                              GROUP(
6059                 /* IP7_31_30 [2] */
6060                 0, 0, 0, 0,
6061                 /* IP7_29_27 [3] */
6062                 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
6063                 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
6064                 0, 0,
6065                 /* IP7_26_24 [3] */
6066                 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
6067                 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
6068                 0, 0,
6069                 /* IP7_23_21 [3] */
6070                 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
6071                 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
6072                 0, 0,
6073                 /* IP7_20_19 [2] */
6074                 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
6075                 /* IP7_18_17 [2] */
6076                 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
6077                 /* IP7_16_15 [2] */
6078                 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
6079                 /* IP7_14_13 [2] */
6080                 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
6081                 /* IP7_12_11 [2] */
6082                 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
6083                 /* IP7_10_9 [2] */
6084                 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
6085                 /* IP7_8_6 [3] */
6086                 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
6087                 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
6088                 0, 0,
6089                 /* IP7_5_3 [3] */
6090                 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
6091                 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
6092                 0, 0,
6093                 /* IP7_2_0 [3] */
6094                 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
6095                 FN_SCIF_CLK_B, FN_GPS_MAG_D,
6096                 0, 0, ))
6097         },
6098         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6099                              GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
6100                              GROUP(
6101                 /* IP8_31 [1] */
6102                 0, 0,
6103                 /* IP8_30_28 [3] */
6104                 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
6105                 0, 0, 0,
6106                 /* IP8_27_26 [2] */
6107                 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
6108                 /* IP8_25_24 [2] */
6109                 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
6110                 /* IP8_23_21 [3] */
6111                 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
6112                 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
6113                 0, 0,
6114                 /* IP8_20_18 [3] */
6115                 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
6116                 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
6117                 0, 0,
6118                 /* IP8_17_15 [3] */
6119                 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
6120                 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
6121                 0, 0,
6122                 /* IP8_14_12 [3] */
6123                 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
6124                 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
6125                 0, 0, 0,
6126                 /* IP8_11_9 [3] */
6127                 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
6128                 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
6129                 0, 0, 0,
6130                 /* IP8_8_6 [3] */
6131                 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
6132                 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
6133                 0, 0,
6134                 /* IP8_5_3 [3] */
6135                 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
6136                 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
6137                 0, 0,
6138                 /* IP8_2_0 [3] */
6139                 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6140                 0, 0, 0, ))
6141         },
6142         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6143                              GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
6144                                    1, 1, 3, 3),
6145                              GROUP(
6146                 /* IP9_31_29 [3] */
6147                 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
6148                 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
6149                 /* IP9_28_27 [2] */
6150                 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
6151                 /* IP9_26_25 [2] */
6152                 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
6153                 /* IP9_24_23 [2] */
6154                 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
6155                 /* IP9_22_21 [2] */
6156                 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
6157                 /* IP9_20_19 [2] */
6158                 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
6159                 /* IP9_18_17 [2] */
6160                 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6161                 /* IP9_16 [1] */
6162                 FN_DU1_DISP, FN_QPOLA,
6163                 /* IP9_15_13 [3] */
6164                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
6165                 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
6166                 0, 0, 0,
6167                 /* IP9_12 [1] */
6168                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
6169                 /* IP9_11 [1] */
6170                 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
6171                 /* IP9_10_8 [3] */
6172                 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
6173                 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
6174                 0, 0,
6175                 /* IP9_7 [1] */
6176                 FN_DU1_DOTCLKOUT0, FN_QCLK,
6177                 /* IP9_6 [1] */
6178                 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
6179                 /* IP9_5_3 [3] */
6180                 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
6181                 FN_SCIF3_SCK, FN_SCIFA3_SCK,
6182                 0, 0, 0,
6183                 /* IP9_2_0 [3] */
6184                 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
6185                 0, 0, 0, ))
6186         },
6187         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6188                              GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
6189                              GROUP(
6190                 /* IP10_31_29 [3] */
6191                 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
6192                 0, 0, 0,
6193                 /* IP10_28_27 [2] */
6194                 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
6195                 /* IP10_26_25 [2] */
6196                 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
6197                 /* IP10_24_22 [3] */
6198                 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
6199                 0, 0, 0,
6200                 /* IP10_21_19 [3] */
6201                 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
6202                 FN_TS_SDATA0_C, FN_ATACS11_N,
6203                 0, 0, 0,
6204                 /* IP10_18_17 [2] */
6205                 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6206                 /* IP10_16_15 [2] */
6207                 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6208                 /* IP10_14_12 [3] */
6209                 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
6210                 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6211                 /* IP10_11_9 [3] */
6212                 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
6213                 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
6214                 0, 0,
6215                 /* IP10_8_6 [3] */
6216                 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
6217                 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6218                 /* IP10_5_3 [3] */
6219                 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
6220                 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6221                 /* IP10_2_0 [3] */
6222                 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
6223                 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
6224         },
6225         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6226                              GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
6227                                    2, 3, 3, 3, 3, 3),
6228                              GROUP(
6229                 /* IP11_31_30 [2] */
6230                 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6231                 /* IP11_29_28 [2] */
6232                 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
6233                 /* IP11_27 [1] */
6234                 FN_VI1_DATA7, FN_AVB_MDC,
6235                 /* IP11_26 [1] */
6236                 FN_VI1_DATA6, FN_AVB_MAGIC,
6237                 /* IP11_25 [1] */
6238                 FN_VI1_DATA5, FN_AVB_RX_DV,
6239                 /* IP11_24 [1] */
6240                 FN_VI1_DATA4, FN_AVB_MDIO,
6241                 /* IP11_23 [1] */
6242                 FN_VI1_DATA3, FN_AVB_RX_ER,
6243                 /* IP11_22 [1] */
6244                 FN_VI1_DATA2, FN_AVB_RXD7,
6245                 /* IP11_21 [1] */
6246                 FN_VI1_DATA1, FN_AVB_RXD6,
6247                 /* IP11_20 [1] */
6248                 FN_VI1_DATA0, FN_AVB_RXD5,
6249                 /* IP11_19 [1] */
6250                 FN_VI1_CLK, FN_AVB_RXD4,
6251                 /* IP11_18_17 [2] */
6252                 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6253                 /* IP11_16_15 [2] */
6254                 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6255                 /* IP11_14_12 [3] */
6256                 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6257                 FN_RX4_B, FN_SCIFA4_RXD_B,
6258                 0, 0, 0,
6259                 /* IP11_11_9 [3] */
6260                 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6261                 FN_TX4_B, FN_SCIFA4_TXD_B,
6262                 0, 0, 0,
6263                 /* IP11_8_6 [3] */
6264                 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6265                 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6266                 /* IP11_5_3 [3] */
6267                 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
6268                 0, 0, 0,
6269                 /* IP11_2_0 [3] */
6270                 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
6271                 FN_I2C1_SDA_D, 0, 0, 0, ))
6272         },
6273         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6274                              GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
6275                              GROUP(
6276                 /* IP12_31_30 [2] */
6277                 0, 0, 0, 0,
6278                 /* IP12_29_27 [3] */
6279                 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6280                 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6281                 0, 0, 0,
6282                 /* IP12_26_24 [3] */
6283                 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6284                 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6285                 0, 0, 0,
6286                 /* IP12_23_22 [2] */
6287                 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6288                 /* IP12_21_20 [2] */
6289                 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6290                 /* IP12_19_18 [2] */
6291                 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6292                 /* IP12_17_16 [2] */
6293                 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6294                 /* IP12_15_13 [3] */
6295                 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6296                 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6297                 0, 0, 0,
6298                 /* IP12_12_10 [3] */
6299                 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6300                 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6301                 0, 0, 0,
6302                 /* IP12_9_7 [3] */
6303                 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6304                 FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
6305                 0, 0, 0,
6306                 /* IP12_6_4 [3] */
6307                 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6308                 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
6309                 0, 0, 0,
6310                 /* IP12_3_2 [2] */
6311                 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
6312                 /* IP12_1_0 [2] */
6313                 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
6314         },
6315         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6316                              GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
6317                                    1, 1, 1, 3, 2, 2, 3),
6318                              GROUP(
6319                 /* IP13_31 [1] */
6320                 0, 0,
6321                 /* IP13_30_28 [3] */
6322                 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
6323                 0, 0, 0, 0,
6324                 /* IP13_27 [1] */
6325                 FN_SD1_DATA3, FN_IERX_B,
6326                 /* IP13_26 [1] */
6327                 FN_SD1_DATA2, FN_IECLK_B,
6328                 /* IP13_25 [1] */
6329                 FN_SD1_DATA1, FN_IETX_B,
6330                 /* IP13_24_23 [2] */
6331                 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6332                 /* IP13_22 [1] */
6333                 FN_SD1_CMD, FN_REMOCON_B,
6334                 /* IP13_21_19 [3] */
6335                 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6336                 FN_SCIFA5_RXD_B, FN_RX3_C,
6337                 0, 0,
6338                 /* IP13_18_16 [3] */
6339                 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6340                 FN_SCIFA5_TXD_B, FN_TX3_C,
6341                 0, 0,
6342                 /* IP13_15 [1] */
6343                 FN_SD0_DATA3, FN_SSL_B,
6344                 /* IP13_14 [1] */
6345                 FN_SD0_DATA2, FN_IO3_B,
6346                 /* IP13_13 [1] */
6347                 FN_SD0_DATA1, FN_IO2_B,
6348                 /* IP13_12 [1] */
6349                 FN_SD0_DATA0, FN_MISO_IO1_B,
6350                 /* IP13_11 [1] */
6351                 FN_SD0_CMD, FN_MOSI_IO0_B,
6352                 /* IP13_10 [1] */
6353                 FN_SD0_CLK, FN_SPCLK_B,
6354                 /* IP13_9_7 [3] */
6355                 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6356                 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6357                 0, 0, 0,
6358                 /* IP13_6_5 [2] */
6359                 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6360                 /* IP13_4_3 [2] */
6361                 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6362                 /* IP13_2_0 [3] */
6363                 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6364                 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6365                 0, 0, 0, ))
6366         },
6367         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6368                              GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
6369                                    1, 1, 2),
6370                              GROUP(
6371                 /* IP14_31_29 [3] */
6372                 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6373                 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
6374                 /* IP14_28_26 [3] */
6375                 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6376                 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
6377                 /* IP14_25_23 [3] */
6378                 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6379                 0, 0, 0,
6380                 /* IP14_22_20 [3] */
6381                 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6382                 0, 0, 0,
6383                 /* IP14_19_17 [3] */
6384                 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6385                 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6386                 0, 0,
6387                 /* IP14_16_14 [3] */
6388                 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6389                 FN_VI1_CLK_C, FN_VI1_G0_B,
6390                 0, 0,
6391                 /* IP14_13_11 [3] */
6392                 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6393                 0, 0, 0,
6394                 /* IP14_10_8 [3] */
6395                 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6396                 0, 0, 0,
6397                 /* IP14_7 [1] */
6398                 FN_SD2_DATA3, FN_MMC_D3,
6399                 /* IP14_6 [1] */
6400                 FN_SD2_DATA2, FN_MMC_D2,
6401                 /* IP14_5 [1] */
6402                 FN_SD2_DATA1, FN_MMC_D1,
6403                 /* IP14_4 [1] */
6404                 FN_SD2_DATA0, FN_MMC_D0,
6405                 /* IP14_3 [1] */
6406                 FN_SD2_CMD, FN_MMC_CMD,
6407                 /* IP14_2 [1] */
6408                 FN_SD2_CLK, FN_MMC_CLK,
6409                 /* IP14_1_0 [2] */
6410                 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
6411         },
6412         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6413                              GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
6414                              GROUP(
6415                 /* IP15_31_30 [2] */
6416                 0, 0, 0, 0,
6417                 /* IP15_29_27 [3] */
6418                 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6419                 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6420                 0, 0,
6421                 /* IP15_26_24 [3] */
6422                 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6423                 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6424                 0, 0,
6425                 /* IP15_23_21 [3] */
6426                 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6427                 FN_TCLK2, FN_VI1_DATA3_C, 0,
6428                 /* IP15_20_18 [3] */
6429                 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6430                 0, 0, 0,
6431                 /* IP15_17_15 [3] */
6432                 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6433                 FN_TCLK1, FN_VI1_DATA1_C,
6434                 0, 0,
6435                 /* IP15_14_12 [3] */
6436                 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6437                 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6438                 0, 0,
6439                 /* IP15_11_9 [3] */
6440                 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6441                 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6442                 0, 0,
6443                 /* IP15_8_6 [3] */
6444                 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6445                 FN_PWM5_B, FN_SCIFA3_TXD_C,
6446                 0, 0, 0,
6447                 /* IP15_5_4 [2] */
6448                 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6449                 /* IP15_3_2 [2] */
6450                 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6451                 /* IP15_1_0 [2] */
6452                 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
6453         },
6454         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6455                              GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
6456                              GROUP(
6457                 /* IP16_31_28 [4] */
6458                 0, 0, 0, 0, 0, 0, 0, 0,
6459                 0, 0, 0, 0, 0, 0, 0, 0,
6460                 /* IP16_27_24 [4] */
6461                 0, 0, 0, 0, 0, 0, 0, 0,
6462                 0, 0, 0, 0, 0, 0, 0, 0,
6463                 /* IP16_23_20 [4] */
6464                 0, 0, 0, 0, 0, 0, 0, 0,
6465                 0, 0, 0, 0, 0, 0, 0, 0,
6466                 /* IP16_19_16 [4] */
6467                 0, 0, 0, 0, 0, 0, 0, 0,
6468                 0, 0, 0, 0, 0, 0, 0, 0,
6469                 /* IP16_15_12 [4] */
6470                 0, 0, 0, 0, 0, 0, 0, 0,
6471                 0, 0, 0, 0, 0, 0, 0, 0,
6472                 /* IP16_11_10 [2] */
6473                 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6474                 /* IP16_9_8 [2] */
6475                 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6476                 /* IP16_7_6 [2] */
6477                 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6478                 /* IP16_5_3 [3] */
6479                 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6480                 FN_GLO_SS_C, FN_VI1_DATA7_C,
6481                 0, 0, 0,
6482                 /* IP16_2_0 [3] */
6483                 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6484                 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6485                 0, 0, 0, ))
6486         },
6487         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6488                              GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
6489                                    2, 2, 1, 2, 2, 2),
6490                              GROUP(
6491                 /* RESERVED [1] */
6492                 0, 0,
6493                 /* SEL_SCIF1 [2] */
6494                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6495                 /* SEL_SCIFB [2] */
6496                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6497                 /* SEL_SCIFB2 [2] */
6498                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6499                 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6500                 /* SEL_SCIFB1 [3] */
6501                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6502                 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6503                 0, 0, 0, 0,
6504                 /* SEL_SCIFA1 [2] */
6505                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6506                 /* SEL_SSI9 [1] */
6507                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6508                 /* SEL_SCFA [1] */
6509                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6510                 /* SEL_QSP [1] */
6511                 FN_SEL_QSP_0, FN_SEL_QSP_1,
6512                 /* SEL_SSI7 [1] */
6513                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6514                 /* SEL_HSCIF1 [3] */
6515                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6516                 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6517                 0, 0, 0,
6518                 /* RESERVED [2] */
6519                 0, 0, 0, 0,
6520                 /* SEL_VI1 [2] */
6521                 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6522                 /* RESERVED [2] */
6523                 0, 0, 0, 0,
6524                 /* SEL_TMU [1] */
6525                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6526                 /* SEL_LBS [2] */
6527                 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6528                 /* SEL_TSIF0 [2] */
6529                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6530                 /* SEL_SOF0 [2] */
6531                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
6532         },
6533         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6534                              GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
6535                                    1, 2, 2, 2, 1, 1, 1),
6536                              GROUP(
6537                 /* SEL_SCIF0 [3] */
6538                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6539                 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6540                 0, 0, 0,
6541                 /* RESERVED [1] */
6542                 0, 0,
6543                 /* SEL_SCIF [1] */
6544                 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6545                 /* SEL_CAN0 [3] */
6546                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6547                 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6548                 0, 0,
6549                 /* SEL_CAN1 [2] */
6550                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6551                 /* RESERVED [1] */
6552                 0, 0,
6553                 /* SEL_SCIFA2 [1] */
6554                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6555                 /* SEL_SCIF4 [2] */
6556                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6557                 /* RESERVED [2] */
6558                 0, 0, 0, 0,
6559                 /* SEL_ADG [1] */
6560                 FN_SEL_ADG_0, FN_SEL_ADG_1,
6561                 /* SEL_FM [3] */
6562                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6563                 FN_SEL_FM_3, FN_SEL_FM_4,
6564                 0, 0, 0,
6565                 /* SEL_SCIFA5 [2] */
6566                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6567                 /* RESERVED [1] */
6568                 0, 0,
6569                 /* SEL_GPS [2] */
6570                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6571                 /* SEL_SCIFA4 [2] */
6572                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6573                 /* SEL_SCIFA3 [2] */
6574                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6575                 /* SEL_SIM [1] */
6576                 FN_SEL_SIM_0, FN_SEL_SIM_1,
6577                 /* RESERVED [1] */
6578                 0, 0,
6579                 /* SEL_SSI8 [1] */
6580                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
6581         },
6582         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6583                              GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
6584                                    3, 2, 2, 2, 1),
6585                              GROUP(
6586                 /* SEL_HSCIF2 [2] */
6587                 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6588                 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6589                 /* SEL_CANCLK [2] */
6590                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6591                 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6592                 /* SEL_IIC1 [2] */
6593                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
6594                 /* SEL_IIC0 [2] */
6595                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6596                 /* SEL_I2C4 [2] */
6597                 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
6598                 /* SEL_I2C3 [2] */
6599                 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
6600                 /* SEL_SCIF3 [2] */
6601                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6602                 /* SEL_IEB [2] */
6603                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6604                 /* SEL_MMC [1] */
6605                 FN_SEL_MMC_0, FN_SEL_MMC_1,
6606                 /* SEL_SCIF5 [1] */
6607                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6608                 /* RESERVED [2] */
6609                 0, 0, 0, 0,
6610                 /* SEL_I2C2 [2] */
6611                 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
6612                 /* SEL_I2C1 [3] */
6613                 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
6614                 FN_SEL_I2C1_4,
6615                 0, 0, 0,
6616                 /* SEL_I2C0 [2] */
6617                 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
6618                 /* RESERVED [2] */
6619                 0, 0, 0, 0,
6620                 /* RESERVED [2] */
6621                 0, 0, 0, 0,
6622                 /* RESERVED [1] */
6623                 0, 0, ))
6624         },
6625         { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6626                              GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
6627                                    1, 1, 2, 2, 2, 2),
6628                              GROUP(
6629                 /* SEL_SOF1 [3] */
6630                 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6631                 FN_SEL_SOF1_4,
6632                 0, 0, 0,
6633                 /* SEL_HSCIF0 [2] */
6634                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6635                 /* SEL_DIS [2] */
6636                 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6637                 /* RESERVED [1] */
6638                 0, 0,
6639                 /* SEL_RAD [1] */
6640                 FN_SEL_RAD_0, FN_SEL_RAD_1,
6641                 /* SEL_RCN [1] */
6642                 FN_SEL_RCN_0, FN_SEL_RCN_1,
6643                 /* SEL_RSP [1] */
6644                 FN_SEL_RSP_0, FN_SEL_RSP_1,
6645                 /* SEL_SCIF2 [3] */
6646                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6647                 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6648                 0, 0, 0,
6649                 /* RESERVED [2] */
6650                 0, 0, 0, 0,
6651                 /* RESERVED [2] */
6652                 0, 0, 0, 0,
6653                 /* SEL_SOF2 [3] */
6654                 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6655                 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6656                 0, 0, 0,
6657                 /* RESERVED [1] */
6658                 0, 0,
6659                 /* SEL_SSI1 [1] */
6660                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6661                 /* SEL_SSI0 [1] */
6662                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6663                 /* SEL_SSP [2] */
6664                 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6665                 /* RESERVED [2] */
6666                 0, 0, 0, 0,
6667                 /* RESERVED [2] */
6668                 0, 0, 0, 0,
6669                 /* RESERVED [2] */
6670                 0, 0, 0, 0, ))
6671         },
6672         { },
6673 };
6674
6675 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6676 {
6677         if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
6678                 return -EINVAL;
6679
6680         *pocctrl = 0xe606008c;
6681
6682         return 31 - (pin & 0x1f);
6683 }
6684
6685 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6686         { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
6687                 [ 0] = RCAR_GP_PIN(1,  4),      /* A20 */
6688                 [ 1] = RCAR_GP_PIN(1,  5),      /* A21 */
6689                 [ 2] = RCAR_GP_PIN(1,  6),      /* A22 */
6690                 [ 3] = RCAR_GP_PIN(1,  7),      /* A23 */
6691                 [ 4] = RCAR_GP_PIN(1,  8),      /* A24 */
6692                 [ 5] = RCAR_GP_PIN(6, 31),      /* DU0_DOTCLKIN */
6693                 [ 6] = RCAR_GP_PIN(0,  0),      /* D0 */
6694                 [ 7] = RCAR_GP_PIN(0,  1),      /* D1 */
6695                 [ 8] = RCAR_GP_PIN(0,  2),      /* D2 */
6696                 [ 9] = RCAR_GP_PIN(0,  3),      /* D3 */
6697                 [10] = RCAR_GP_PIN(0,  4),      /* D4 */
6698                 [11] = RCAR_GP_PIN(0,  5),      /* D5 */
6699                 [12] = RCAR_GP_PIN(0,  6),      /* D6 */
6700                 [13] = RCAR_GP_PIN(0,  7),      /* D7 */
6701                 [14] = RCAR_GP_PIN(0,  8),      /* D8 */
6702                 [15] = RCAR_GP_PIN(0,  9),      /* D9 */
6703                 [16] = RCAR_GP_PIN(0, 10),      /* D10 */
6704                 [17] = RCAR_GP_PIN(0, 11),      /* D11 */
6705                 [18] = RCAR_GP_PIN(0, 12),      /* D12 */
6706                 [19] = RCAR_GP_PIN(0, 13),      /* D13 */
6707                 [20] = RCAR_GP_PIN(0, 14),      /* D14 */
6708                 [21] = RCAR_GP_PIN(0, 15),      /* D15 */
6709                 [22] = RCAR_GP_PIN(0, 16),      /* A0 */
6710                 [23] = RCAR_GP_PIN(0, 17),      /* A1 */
6711                 [24] = RCAR_GP_PIN(0, 18),      /* A2 */
6712                 [25] = RCAR_GP_PIN(0, 19),      /* A3 */
6713                 [26] = RCAR_GP_PIN(0, 20),      /* A4 */
6714                 [27] = RCAR_GP_PIN(0, 21),      /* A5 */
6715                 [28] = RCAR_GP_PIN(0, 22),      /* A6 */
6716                 [29] = RCAR_GP_PIN(0, 23),      /* A7 */
6717                 [30] = RCAR_GP_PIN(0, 24),      /* A8 */
6718                 [31] = RCAR_GP_PIN(0, 25),      /* A9 */
6719         } },
6720         { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
6721                 [ 0] = RCAR_GP_PIN(0, 26),      /* A10 */
6722                 [ 1] = RCAR_GP_PIN(0, 27),      /* A11 */
6723                 [ 2] = RCAR_GP_PIN(0, 28),      /* A12 */
6724                 [ 3] = RCAR_GP_PIN(0, 29),      /* A13 */
6725                 [ 4] = RCAR_GP_PIN(0, 30),      /* A14 */
6726                 [ 5] = RCAR_GP_PIN(0, 31),      /* A15 */
6727                 [ 6] = RCAR_GP_PIN(1,  0),      /* A16 */
6728                 [ 7] = RCAR_GP_PIN(1,  1),      /* A17 */
6729                 [ 8] = RCAR_GP_PIN(1,  2),      /* A18 */
6730                 [ 9] = RCAR_GP_PIN(1,  3),      /* A19 */
6731                 [10] = PIN_TRST_N,              /* TRST# */
6732                 [11] = PIN_TCK,                 /* TCK */
6733                 [12] = PIN_TMS,                 /* TMS */
6734                 [13] = PIN_TDI,                 /* TDI */
6735                 [14] = RCAR_GP_PIN(1, 11),      /* CS1#/A26 */
6736                 [15] = RCAR_GP_PIN(1, 12),      /* EX_CS0# */
6737                 [16] = RCAR_GP_PIN(1, 13),      /* EX_CS1# */
6738                 [17] = RCAR_GP_PIN(1, 14),      /* EX_CS2# */
6739                 [18] = RCAR_GP_PIN(1, 15),      /* EX_CS3# */
6740                 [19] = RCAR_GP_PIN(1, 16),      /* EX_CS4# */
6741                 [20] = RCAR_GP_PIN(1, 17),      /* EX_CS5# */
6742                 [21] = RCAR_GP_PIN(1, 18),      /* BS# */
6743                 [22] = RCAR_GP_PIN(1, 19),      /* RD# */
6744                 [23] = RCAR_GP_PIN(1, 20),      /* RD/WR# */
6745                 [24] = RCAR_GP_PIN(1, 21),      /* WE0# */
6746                 [25] = RCAR_GP_PIN(1, 22),      /* WE1# */
6747                 [26] = RCAR_GP_PIN(1, 23),      /* EX_WAIT0 */
6748                 [27] = RCAR_GP_PIN(1, 24),      /* DREQ0 */
6749                 [28] = RCAR_GP_PIN(1, 25),      /* DACK0 */
6750                 [29] = RCAR_GP_PIN(5, 31),      /* SPEEDIN */
6751                 [30] = RCAR_GP_PIN(2,  0),      /* SSI_SCK0129 */
6752                 [31] = RCAR_GP_PIN(2,  1),      /* SSI_WS0129 */
6753         } },
6754         { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
6755                 [ 0] = RCAR_GP_PIN(2,  2),      /* SSI_SDATA0 */
6756                 [ 1] = RCAR_GP_PIN(2,  3),      /* SSI_SCK1 */
6757                 [ 2] = RCAR_GP_PIN(2,  4),      /* SSI_WS1 */
6758                 [ 3] = RCAR_GP_PIN(2,  5),      /* SSI_SDATA1 */
6759                 [ 4] = RCAR_GP_PIN(2,  6),      /* SSI_SCK2 */
6760                 [ 5] = RCAR_GP_PIN(2,  7),      /* SSI_WS2 */
6761                 [ 6] = RCAR_GP_PIN(2,  8),      /* SSI_SDATA2 */
6762                 [ 7] = RCAR_GP_PIN(2,  9),      /* SSI_SCK34 */
6763                 [ 8] = RCAR_GP_PIN(2, 10),      /* SSI_WS34 */
6764                 [ 9] = RCAR_GP_PIN(2, 11),      /* SSI_SDATA3 */
6765                 [10] = RCAR_GP_PIN(2, 12),      /* SSI_SCK4 */
6766                 [11] = RCAR_GP_PIN(2, 13),      /* SSI_WS4 */
6767                 [12] = RCAR_GP_PIN(2, 14),      /* SSI_SDATA4 */
6768                 [13] = RCAR_GP_PIN(2, 15),      /* SSI_SCK5 */
6769                 [14] = RCAR_GP_PIN(2, 16),      /* SSI_WS5 */
6770                 [15] = RCAR_GP_PIN(2, 17),      /* SSI_SDATA5 */
6771                 [16] = RCAR_GP_PIN(2, 18),      /* SSI_SCK6 */
6772                 [17] = RCAR_GP_PIN(2, 19),      /* SSI_WS6 */
6773                 [18] = RCAR_GP_PIN(2, 20),      /* SSI_SDATA6 */
6774                 [19] = RCAR_GP_PIN(2, 21),      /* SSI_SCK78 */
6775                 [20] = RCAR_GP_PIN(2, 22),      /* SSI_WS78 */
6776                 [21] = RCAR_GP_PIN(2, 23),      /* SSI_SDATA7 */
6777                 [22] = RCAR_GP_PIN(2, 24),      /* SSI_SDATA8 */
6778                 [23] = RCAR_GP_PIN(2, 25),      /* SSI_SCK9 */
6779                 [24] = RCAR_GP_PIN(2, 26),      /* SSI_WS9 */
6780                 [25] = RCAR_GP_PIN(2, 27),      /* SSI_SDATA9 */
6781                 [26] = RCAR_GP_PIN(2, 28),      /* AUDIO_CLKA */
6782                 [27] = RCAR_GP_PIN(2, 29),      /* AUDIO_CLKB */
6783                 [28] = RCAR_GP_PIN(2, 30),      /* AUDIO_CLKC */
6784                 [29] = RCAR_GP_PIN(2, 31),      /* AUDIO_CLKOUT */
6785                 [30] = RCAR_GP_PIN(7, 10),      /* IRQ0 */
6786                 [31] = RCAR_GP_PIN(7, 11),      /* IRQ1 */
6787         } },
6788         { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
6789                 [ 0] = RCAR_GP_PIN(7, 12),      /* IRQ2 */
6790                 [ 1] = RCAR_GP_PIN(7, 13),      /* IRQ3 */
6791                 [ 2] = RCAR_GP_PIN(7, 14),      /* IRQ4 */
6792                 [ 3] = RCAR_GP_PIN(7, 15),      /* IRQ5 */
6793                 [ 4] = RCAR_GP_PIN(7, 16),      /* IRQ6 */
6794                 [ 5] = RCAR_GP_PIN(7, 17),      /* IRQ7 */
6795                 [ 6] = RCAR_GP_PIN(7, 18),      /* IRQ8 */
6796                 [ 7] = RCAR_GP_PIN(7, 19),      /* IRQ9 */
6797                 [ 8] = RCAR_GP_PIN(3,  0),      /* DU1_DR0 */
6798                 [ 9] = RCAR_GP_PIN(3,  1),      /* DU1_DR1 */
6799                 [10] = RCAR_GP_PIN(3,  2),      /* DU1_DR2 */
6800                 [11] = RCAR_GP_PIN(3,  3),      /* DU1_DR3 */
6801                 [12] = RCAR_GP_PIN(3,  4),      /* DU1_DR4 */
6802                 [13] = RCAR_GP_PIN(3,  5),      /* DU1_DR5 */
6803                 [14] = RCAR_GP_PIN(3,  6),      /* DU1_DR6 */
6804                 [15] = RCAR_GP_PIN(3,  7),      /* DU1_DR7 */
6805                 [16] = RCAR_GP_PIN(3,  8),      /* DU1_DG0 */
6806                 [17] = RCAR_GP_PIN(3,  9),      /* DU1_DG1 */
6807                 [18] = RCAR_GP_PIN(3, 10),      /* DU1_DG2 */
6808                 [19] = RCAR_GP_PIN(3, 11),      /* DU1_DG3 */
6809                 [20] = RCAR_GP_PIN(3, 12),      /* DU1_DG4 */
6810                 [21] = RCAR_GP_PIN(3, 13),      /* DU1_DG5 */
6811                 [22] = RCAR_GP_PIN(3, 14),      /* DU1_DG6 */
6812                 [23] = RCAR_GP_PIN(3, 15),      /* DU1_DG7 */
6813                 [24] = RCAR_GP_PIN(3, 16),      /* DU1_DB0 */
6814                 [25] = RCAR_GP_PIN(3, 17),      /* DU1_DB1 */
6815                 [26] = RCAR_GP_PIN(3, 18),      /* DU1_DB2 */
6816                 [27] = RCAR_GP_PIN(3, 19),      /* DU1_DB3 */
6817                 [28] = RCAR_GP_PIN(3, 20),      /* DU1_DB4 */
6818                 [29] = RCAR_GP_PIN(3, 21),      /* DU1_DB5 */
6819                 [30] = RCAR_GP_PIN(3, 22),      /* DU1_DB6 */
6820                 [31] = RCAR_GP_PIN(3, 23),      /* DU1_DB7 */
6821         } },
6822         { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
6823                 [ 0] = RCAR_GP_PIN(3, 24),      /* DU1_DOTCLKIN */
6824                 [ 1] = RCAR_GP_PIN(3, 25),      /* DU1_DOTCLKOUT0 */
6825                 [ 2] = RCAR_GP_PIN(3, 26),      /* DU1_DOTCLKOUT1 */
6826                 [ 3] = RCAR_GP_PIN(3, 27),      /* DU1_EXHSYNC_DU1_HSYNC */
6827                 [ 4] = RCAR_GP_PIN(3, 28),      /* DU1_EXVSYNC_DU1_VSYNC */
6828                 [ 5] = RCAR_GP_PIN(3, 29),      /* DU1_EXODDF_DU1_ODDF_DISP_CDE */
6829                 [ 6] = RCAR_GP_PIN(3, 30),      /* DU1_DISP */
6830                 [ 7] = RCAR_GP_PIN(3, 31),      /* DU1_CDE */
6831                 [ 8] = RCAR_GP_PIN(4,  0),      /* VI0_CLK */
6832                 [ 9] = RCAR_GP_PIN(4,  1),      /* VI0_CLKENB */
6833                 [10] = RCAR_GP_PIN(4,  2),      /* VI0_FIELD */
6834                 [11] = RCAR_GP_PIN(4,  3),      /* VI0_HSYNC# */
6835                 [12] = RCAR_GP_PIN(4,  4),      /* VI0_VSYNC# */
6836                 [13] = RCAR_GP_PIN(4,  5),      /* VI0_DATA0_VI0_B0 */
6837                 [14] = RCAR_GP_PIN(4,  6),      /* VI0_DATA1_VI0_B1 */
6838                 [15] = RCAR_GP_PIN(4,  7),      /* VI0_DATA2_VI0_B2 */
6839                 [16] = RCAR_GP_PIN(4,  8),      /* VI0_DATA3_VI0_B3 */
6840                 [17] = RCAR_GP_PIN(4,  9),      /* VI0_DATA4_VI0_B4 */
6841                 [18] = RCAR_GP_PIN(4, 10),      /* VI0_DATA5_VI0_B5 */
6842                 [19] = RCAR_GP_PIN(4, 11),      /* VI0_DATA6_VI0_B6 */
6843                 [20] = RCAR_GP_PIN(4, 12),      /* VI0_DATA7_VI0_B7 */
6844                 [21] = RCAR_GP_PIN(4, 13),      /* VI0_G0 */
6845                 [22] = RCAR_GP_PIN(4, 14),      /* VI0_G1 */
6846                 [23] = RCAR_GP_PIN(4, 15),      /* VI0_G2 */
6847                 [24] = RCAR_GP_PIN(4, 16),      /* VI0_G3 */
6848                 [25] = RCAR_GP_PIN(4, 17),      /* VI0_G4 */
6849                 [26] = RCAR_GP_PIN(4, 18),      /* VI0_G5 */
6850                 [27] = RCAR_GP_PIN(4, 19),      /* VI0_G6 */
6851                 [28] = RCAR_GP_PIN(4, 20),      /* VI0_G7 */
6852                 [29] = RCAR_GP_PIN(4, 21),      /* VI0_R0 */
6853                 [30] = RCAR_GP_PIN(4, 22),      /* VI0_R1 */
6854                 [31] = RCAR_GP_PIN(4, 23),      /* VI0_R2 */
6855         } },
6856         { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
6857                 [ 0] = RCAR_GP_PIN(4, 24),      /* VI0_R3 */
6858                 [ 1] = RCAR_GP_PIN(4, 25),      /* VI0_R4 */
6859                 [ 2] = RCAR_GP_PIN(4, 26),      /* VI0_R5 */
6860                 [ 3] = RCAR_GP_PIN(4, 27),      /* VI0_R6 */
6861                 [ 4] = RCAR_GP_PIN(4, 28),      /* VI0_R7 */
6862                 [ 5] = RCAR_GP_PIN(5,  0),      /* VI1_HSYNC# */
6863                 [ 6] = RCAR_GP_PIN(5,  1),      /* VI1_VSYNC# */
6864                 [ 7] = RCAR_GP_PIN(5,  2),      /* VI1_CLKENB */
6865                 [ 8] = RCAR_GP_PIN(5,  3),      /* VI1_FIELD */
6866                 [ 9] = RCAR_GP_PIN(5,  4),      /* VI1_CLK */
6867                 [10] = RCAR_GP_PIN(5,  5),      /* VI1_DATA0 */
6868                 [11] = RCAR_GP_PIN(5,  6),      /* VI1_DATA1 */
6869                 [12] = RCAR_GP_PIN(5,  7),      /* VI1_DATA2 */
6870                 [13] = RCAR_GP_PIN(5,  8),      /* VI1_DATA3 */
6871                 [14] = RCAR_GP_PIN(5,  9),      /* VI1_DATA4 */
6872                 [15] = RCAR_GP_PIN(5, 10),      /* VI1_DATA5 */
6873                 [16] = RCAR_GP_PIN(5, 11),      /* VI1_DATA6 */
6874                 [17] = RCAR_GP_PIN(5, 12),      /* VI1_DATA7 */
6875                 [18] = RCAR_GP_PIN(5, 13),      /* ETH_MDIO */
6876                 [19] = RCAR_GP_PIN(5, 14),      /* ETH_CRS_DV */
6877                 [20] = RCAR_GP_PIN(5, 15),      /* ETH_RX_ER */
6878                 [21] = RCAR_GP_PIN(5, 16),      /* ETH_RXD0 */
6879                 [22] = RCAR_GP_PIN(5, 17),      /* ETH_RXD1 */
6880                 [23] = RCAR_GP_PIN(5, 18),      /* ETH_LINK */
6881                 [24] = RCAR_GP_PIN(5, 19),      /* ETH_REFCLK */
6882                 [25] = RCAR_GP_PIN(5, 20),      /* ETH_TXD1 */
6883                 [26] = RCAR_GP_PIN(5, 21),      /* ETH_TX_EN */
6884                 [27] = RCAR_GP_PIN(5, 22),      /* ETH_MAGIC */
6885                 [28] = RCAR_GP_PIN(5, 23),      /* ETH_TXD0 */
6886                 [29] = RCAR_GP_PIN(5, 24),      /* ETH_MDC */
6887                 [30] = RCAR_GP_PIN(5, 25),      /* STP_IVCXO27_0 */
6888                 [31] = RCAR_GP_PIN(5, 26),      /* STP_ISCLK_0 */
6889         } },
6890         { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
6891                 [ 0] = RCAR_GP_PIN(5, 27),      /* STP_ISD_0 */
6892                 [ 1] = RCAR_GP_PIN(5, 28),      /* STP_ISEN_0 */
6893                 [ 2] = RCAR_GP_PIN(5, 29),      /* STP_ISSYNC_0 */
6894                 [ 3] = RCAR_GP_PIN(5, 30),      /* STP_OPWM_0 */
6895                 [ 4] = RCAR_GP_PIN(6,  0),      /* SD0_CLK */
6896                 [ 5] = RCAR_GP_PIN(6,  1),      /* SD0_CMD */
6897                 [ 6] = RCAR_GP_PIN(6,  2),      /* SD0_DATA0 */
6898                 [ 7] = RCAR_GP_PIN(6,  3),      /* SD0_DATA1 */
6899                 [ 8] = RCAR_GP_PIN(6,  4),      /* SD0_DATA2 */
6900                 [ 9] = RCAR_GP_PIN(6,  5),      /* SD0_DATA3 */
6901                 [10] = RCAR_GP_PIN(6,  6),      /* SD0_CD */
6902                 [11] = RCAR_GP_PIN(6,  7),      /* SD0_WP */
6903                 [12] = RCAR_GP_PIN(6,  8),      /* SD2_CLK */
6904                 [13] = RCAR_GP_PIN(6,  9),      /* SD2_CMD */
6905                 [14] = RCAR_GP_PIN(6, 10),      /* SD2_DATA0 */
6906                 [15] = RCAR_GP_PIN(6, 11),      /* SD2_DATA1 */
6907                 [16] = RCAR_GP_PIN(6, 12),      /* SD2_DATA2 */
6908                 [17] = RCAR_GP_PIN(6, 13),      /* SD2_DATA3 */
6909                 [18] = RCAR_GP_PIN(6, 14),      /* SD2_CD */
6910                 [19] = RCAR_GP_PIN(6, 15),      /* SD2_WP */
6911                 [20] = RCAR_GP_PIN(6, 16),      /* SD3_CLK */
6912                 [21] = RCAR_GP_PIN(6, 17),      /* SD3_CMD */
6913                 [22] = RCAR_GP_PIN(6, 18),      /* SD3_DATA0 */
6914                 [23] = RCAR_GP_PIN(6, 19),      /* SD3_DATA1 */
6915                 [24] = RCAR_GP_PIN(6, 20),      /* SD3_DATA2 */
6916                 [25] = RCAR_GP_PIN(6, 21),      /* SD3_DATA3 */
6917                 [26] = RCAR_GP_PIN(6, 22),      /* SD3_CD */
6918                 [27] = RCAR_GP_PIN(6, 23),      /* SD3_WP */
6919                 [28] = RCAR_GP_PIN(6, 24),      /* MSIOF0_SCK */
6920                 [29] = RCAR_GP_PIN(6, 25),      /* MSIOF0_SYNC */
6921                 [30] = RCAR_GP_PIN(6, 26),      /* MSIOF0_TXD */
6922                 [31] = RCAR_GP_PIN(6, 27),      /* MSIOF0_RXD */
6923         } },
6924         { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
6925                 /* PUPR7 pull-up pins */
6926                 [ 0] = RCAR_GP_PIN(6, 28),      /* MSIOF0_SS1 */
6927                 [ 1] = RCAR_GP_PIN(6, 29),      /* MSIOF0_SS2 */
6928                 [ 2] = RCAR_GP_PIN(4, 29),      /* SIM0_RST */
6929                 [ 3] = RCAR_GP_PIN(4, 30),      /* SIM0_CLK */
6930                 [ 4] = RCAR_GP_PIN(4, 31),      /* SIM0_D */
6931                 [ 5] = RCAR_GP_PIN(7, 20),      /* GPS_CLK */
6932                 [ 6] = RCAR_GP_PIN(7, 21),      /* GPS_SIGN */
6933                 [ 7] = RCAR_GP_PIN(7, 22),      /* GPS_MAG */
6934                 [ 8] = RCAR_GP_PIN(7,  0),      /* HCTS0# */
6935                 [ 9] = RCAR_GP_PIN(7,  1),      /* HRTS0# */
6936                 [10] = RCAR_GP_PIN(7,  2),      /* HSCK0 */
6937                 [11] = RCAR_GP_PIN(7,  3),      /* HRX0 */
6938                 [12] = RCAR_GP_PIN(7,  4),      /* HTX0 */
6939                 [13] = RCAR_GP_PIN(7,  5),      /* HRX1 */
6940                 [14] = RCAR_GP_PIN(7,  6),      /* HTX1 */
6941                 [15] = SH_PFC_PIN_NONE,
6942                 [16] = SH_PFC_PIN_NONE,
6943                 [17] = SH_PFC_PIN_NONE,
6944                 [18] = RCAR_GP_PIN(1,  9),      /* A25 */
6945                 [19] = SH_PFC_PIN_NONE,
6946                 [20] = RCAR_GP_PIN(1, 10),      /* CS0# */
6947                 [21] = RCAR_GP_PIN(7, 23),      /* USB0_PWEN */
6948                 [22] = RCAR_GP_PIN(7, 24),      /* USB0_OVC */
6949                 [23] = RCAR_GP_PIN(7, 25),      /* USB1_PWEN */
6950                 [24] = RCAR_GP_PIN(6, 30),      /* USB1_OVC */
6951                 [25] = PIN_AVS1,                /* AVS1 */
6952                 [26] = PIN_AVS2,                /* AVS2 */
6953                 [27] = SH_PFC_PIN_NONE,
6954                 [28] = SH_PFC_PIN_NONE,
6955                 [29] = SH_PFC_PIN_NONE,
6956                 [30] = SH_PFC_PIN_NONE,
6957                 [31] = SH_PFC_PIN_NONE,
6958         } },
6959         { PINMUX_BIAS_REG("N/A", 0, "PUPR7", 0xe606011c) {
6960                 /* PUPR7 pull-down pins */
6961                 [ 0] = SH_PFC_PIN_NONE,
6962                 [ 1] = SH_PFC_PIN_NONE,
6963                 [ 2] = SH_PFC_PIN_NONE,
6964                 [ 3] = SH_PFC_PIN_NONE,
6965                 [ 4] = SH_PFC_PIN_NONE,
6966                 [ 5] = SH_PFC_PIN_NONE,
6967                 [ 6] = SH_PFC_PIN_NONE,
6968                 [ 7] = SH_PFC_PIN_NONE,
6969                 [ 8] = SH_PFC_PIN_NONE,
6970                 [ 9] = SH_PFC_PIN_NONE,
6971                 [10] = SH_PFC_PIN_NONE,
6972                 [11] = SH_PFC_PIN_NONE,
6973                 [12] = SH_PFC_PIN_NONE,
6974                 [13] = SH_PFC_PIN_NONE,
6975                 [14] = SH_PFC_PIN_NONE,
6976                 [15] = SH_PFC_PIN_NONE,
6977                 [16] = SH_PFC_PIN_NONE,
6978                 [17] = SH_PFC_PIN_NONE,
6979                 [18] = SH_PFC_PIN_NONE,
6980                 [19] = PIN_ASEBRK_N_ACK,        /* ASEBRK#/ACK */
6981                 [20] = SH_PFC_PIN_NONE,
6982                 [21] = SH_PFC_PIN_NONE,
6983                 [22] = SH_PFC_PIN_NONE,
6984                 [23] = SH_PFC_PIN_NONE,
6985                 [24] = SH_PFC_PIN_NONE,
6986                 [25] = SH_PFC_PIN_NONE,
6987                 [26] = SH_PFC_PIN_NONE,
6988                 [27] = SH_PFC_PIN_NONE,
6989                 [28] = SH_PFC_PIN_NONE,
6990                 [29] = SH_PFC_PIN_NONE,
6991                 [30] = SH_PFC_PIN_NONE,
6992                 [31] = SH_PFC_PIN_NONE,
6993         } },
6994         { /* sentinel */ },
6995 };
6996
6997 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
6998         .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
6999         .get_bias = rcar_pinmux_get_bias,
7000         .set_bias = rcar_pinmux_set_bias,
7001 };
7002
7003 #ifdef CONFIG_PINCTRL_PFC_R8A7743
7004 const struct sh_pfc_soc_info r8a7743_pinmux_info = {
7005         .name = "r8a77430_pfc",
7006         .ops = &r8a7791_pinmux_ops,
7007         .unlock_reg = 0xe6060000, /* PMMR */
7008
7009         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
7010
7011         .pins = pinmux_pins,
7012         .nr_pins = ARRAY_SIZE(pinmux_pins),
7013         .groups = pinmux_groups.common,
7014         .nr_groups = ARRAY_SIZE(pinmux_groups.common),
7015         .functions = pinmux_functions.common,
7016         .nr_functions = ARRAY_SIZE(pinmux_functions.common),
7017
7018         .cfg_regs = pinmux_config_regs,
7019         .bias_regs = pinmux_bias_regs,
7020
7021         .pinmux_data = pinmux_data,
7022         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
7023 };
7024 #endif
7025
7026 #ifdef CONFIG_PINCTRL_PFC_R8A7744
7027 const struct sh_pfc_soc_info r8a7744_pinmux_info = {
7028         .name = "r8a77440_pfc",
7029         .ops = &r8a7791_pinmux_ops,
7030         .unlock_reg = 0xe6060000, /* PMMR */
7031
7032         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
7033
7034         .pins = pinmux_pins,
7035         .nr_pins = ARRAY_SIZE(pinmux_pins),
7036         .groups = pinmux_groups.common,
7037         .nr_groups = ARRAY_SIZE(pinmux_groups.common),
7038         .functions = pinmux_functions.common,
7039         .nr_functions = ARRAY_SIZE(pinmux_functions.common),
7040
7041         .cfg_regs = pinmux_config_regs,
7042         .bias_regs = pinmux_bias_regs,
7043
7044         .pinmux_data = pinmux_data,
7045         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
7046 };
7047 #endif
7048
7049 #ifdef CONFIG_PINCTRL_PFC_R8A7791
7050 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
7051         .name = "r8a77910_pfc",
7052         .ops = &r8a7791_pinmux_ops,
7053         .unlock_reg = 0xe6060000, /* PMMR */
7054
7055         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
7056
7057         .pins = pinmux_pins,
7058         .nr_pins = ARRAY_SIZE(pinmux_pins),
7059         .groups = pinmux_groups.common,
7060         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
7061                      ARRAY_SIZE(pinmux_groups.automotive),
7062         .functions = pinmux_functions.common,
7063         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
7064                         ARRAY_SIZE(pinmux_functions.automotive),
7065
7066         .cfg_regs = pinmux_config_regs,
7067         .bias_regs = pinmux_bias_regs,
7068
7069         .pinmux_data = pinmux_data,
7070         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
7071 };
7072 #endif
7073
7074 #ifdef CONFIG_PINCTRL_PFC_R8A7793
7075 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
7076         .name = "r8a77930_pfc",
7077         .ops = &r8a7791_pinmux_ops,
7078         .unlock_reg = 0xe6060000, /* PMMR */
7079
7080         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
7081
7082         .pins = pinmux_pins,
7083         .nr_pins = ARRAY_SIZE(pinmux_pins),
7084         .groups = pinmux_groups.common,
7085         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
7086                      ARRAY_SIZE(pinmux_groups.automotive),
7087         .functions = pinmux_functions.common,
7088         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
7089                         ARRAY_SIZE(pinmux_functions.automotive),
7090
7091         .cfg_regs = pinmux_config_regs,
7092         .bias_regs = pinmux_bias_regs,
7093
7094         .pinmux_data = pinmux_data,
7095         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
7096 };
7097 #endif