drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "devicetree.h"
  35 #include "pinconf.h"
  36 #include "pinmux.h"
  37
  38 #define DRIVER_NAME                     "pinctrl-single"
  39 #define PCS_OFF_DISABLED                ~0U
  40
  41 /**
  42  * struct pcs_func_vals - mux function register offset and value pair
  43  * @reg:        register virtual address
  44  * @val:        register value
  45  */
  46 struct pcs_func_vals {
  47         void __iomem *reg;
  48         unsigned val;
  49         unsigned mask;
  50 };
  51
  52 /**
  53  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  54  * and value, enable, disable, mask
  55  * @param:      config parameter
  56  * @val:        user input bits in the pinconf register
  57  * @enable:     enable bits in the pinconf register
  58  * @disable:    disable bits in the pinconf register
  59  * @mask:       mask bits in the register value
  60  */
  61 struct pcs_conf_vals {
  62         enum pin_config_param param;
  63         unsigned val;
  64         unsigned enable;
  65         unsigned disable;
  66         unsigned mask;
  67 };
  68
  69 /**
  70  * struct pcs_conf_type - pinconf property name, pinconf param pair
  71  * @name:       property name in DTS file
  72  * @param:      config parameter
  73  */
  74 struct pcs_conf_type {
  75         const char *name;
  76         enum pin_config_param param;
  77 };
  78
  79 /**
  80  * struct pcs_function - pinctrl function
  81  * @name:       pinctrl function name
  82  * @vals:       register and vals array
  83  * @nvals:      number of entries in vals array
  84  * @pgnames:    array of pingroup names the function uses
  85  * @npgnames:   number of pingroup names the function uses
  86  * @node:       list node
  87  */
  88 struct pcs_function {
  89         const char *name;
  90         struct pcs_func_vals *vals;
  91         unsigned nvals;
  92         const char **pgnames;
  93         int npgnames;
  94         struct pcs_conf_vals *conf;
  95         int nconfs;
  96         struct list_head node;
  97 };
  98
  99 /**
 100  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 101  * @offset:     offset base of pins
 102  * @npins:      number pins with the same mux value of gpio function
 103  * @gpiofunc:   mux value of gpio function
 104  * @node:       list node
 105  */
 106 struct pcs_gpiofunc_range {
 107         unsigned offset;
 108         unsigned npins;
 109         unsigned gpiofunc;
 110         struct list_head node;
 111 };
 112
 113 /**
 114  * struct pcs_data - wrapper for data needed by pinctrl framework
 115  * @pa:         pindesc array
 116  * @cur:        index to current element
 117  *
 118  * REVISIT: We should be able to drop this eventually by adding
 119  * support for registering pins individually in the pinctrl
 120  * framework for those drivers that don't need a static array.
 121  */
 122 struct pcs_data {
 123         struct pinctrl_pin_desc *pa;
 124         int cur;
 125 };
 126
 127 /**
 128  * struct pcs_soc_data - SoC specific settings
 129  * @flags:      initial SoC specific PCS_FEAT_xxx values
 130  * @irq:        optional interrupt for the controller
 131  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 132  * @irq_status_mask:    optional SoC specific interrupt status mask
 133  * @rearm:      optional SoC specific wake-up rearm function
 134  */
 135 struct pcs_soc_data {
 136         unsigned flags;
 137         int irq;
 138         unsigned irq_enable_mask;
 139         unsigned irq_status_mask;
 140         void (*rearm)(void);
 141 };
 142
 143 /**
 144  * struct pcs_device - pinctrl device instance
 145  * @res:        resources
 146  * @base:       virtual address of the controller
 147  * @saved_vals: saved values for the controller
 148  * @size:       size of the ioremapped area
 149  * @dev:        device entry
 150  * @np:         device tree node
 151  * @pctl:       pin controller device
 152  * @flags:      mask of PCS_FEAT_xxx values
 153  * @missing_nr_pinctrl_cells: for legacy binding, may go away
 154  * @socdata:    soc specific data
 155  * @lock:       spinlock for register access
 156  * @mutex:      mutex protecting the lists
 157  * @width:      bits per mux register
 158  * @fmask:      function register mask
 159  * @fshift:     function register shift
 160  * @foff:       value to turn mux off
 161  * @fmax:       max number of functions in fmask
 162  * @bits_per_mux: number of bits per mux
 163  * @bits_per_pin: number of bits per pin
 164  * @pins:       physical pins on the SoC
 165  * @gpiofuncs:  list of gpio functions
 166  * @irqs:       list of interrupt registers
 167  * @chip:       chip container for this instance
 168  * @domain:     IRQ domain for this instance
 169  * @desc:       pin controller descriptor
 170  * @read:       register read function to use
 171  * @write:      register write function to use
 172  */
 173 struct pcs_device {
 174         struct resource *res;
 175         void __iomem *base;
 176         void *saved_vals;
 177         unsigned size;
 178         struct device *dev;
 179         struct device_node *np;
 180         struct pinctrl_dev *pctl;
 181         unsigned flags;
 182 #define PCS_CONTEXT_LOSS_OFF    (1 << 3)
 183 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 184 #define PCS_FEAT_IRQ            (1 << 1)
 185 #define PCS_FEAT_PINCONF        (1 << 0)
 186         struct property *missing_nr_pinctrl_cells;
 187         struct pcs_soc_data socdata;
 188         raw_spinlock_t lock;
 189         struct mutex mutex;
 190         unsigned width;
 191         unsigned fmask;
 192         unsigned fshift;
 193         unsigned foff;
 194         unsigned fmax;
 195         bool bits_per_mux;
 196         unsigned bits_per_pin;
 197         struct pcs_data pins;
 198         struct list_head gpiofuncs;
 199         struct list_head irqs;
 200         struct irq_chip chip;
 201         struct irq_domain *domain;
 202         struct pinctrl_desc desc;
 203         unsigned (*read)(void __iomem *reg);
 204         void (*write)(unsigned val, void __iomem *reg);
 205 };
 206
 207 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 208 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 209 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 210
 211 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 212                            unsigned long *config);
 213 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 214                            unsigned long *configs, unsigned num_configs);
 215
 216 static enum pin_config_param pcs_bias[] = {
 217         PIN_CONFIG_BIAS_PULL_DOWN,
 218         PIN_CONFIG_BIAS_PULL_UP,
 219 };
 220
 221 /*
 222  * This lock class tells lockdep that irqchip core that this single
 223  * pinctrl can be in a different category than its parents, so it won't
 224  * report false recursion.
 225  */
 226 static struct lock_class_key pcs_lock_class;
 227
 228 /* Class for the IRQ request mutex */
 229 static struct lock_class_key pcs_request_class;
 230
 231 /*
 232  * REVISIT: Reads and writes could eventually use regmap or something
 233  * generic. But at least on omaps, some mux registers are performance
 234  * critical as they may need to be remuxed every time before and after
 235  * idle. Adding tests for register access width for every read and
 236  * write like regmap is doing is not desired, and caching the registers
 237  * does not help in this case.
 238  */
 239
 240 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 241 {
 242         return readb(reg);
 243 }
 244
 245 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 246 {
 247         return readw(reg);
 248 }
 249
 250 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 251 {
 252         return readl(reg);
 253 }
 254
 255 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 256 {
 257         writeb(val, reg);
 258 }
 259
 260 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 261 {
 262         writew(val, reg);
 263 }
 264
 265 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 266 {
 267         writel(val, reg);
 268 }
 269
 270 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 271                                         struct seq_file *s,
 272                                         unsigned pin)
 273 {
 274         struct pcs_device *pcs;
 275         unsigned val, mux_bytes;
 276         unsigned long offset;
 277         size_t pa;
 278
 279         pcs = pinctrl_dev_get_drvdata(pctldev);
 280
 281         mux_bytes = pcs->width / BITS_PER_BYTE;
 282         offset = pin * mux_bytes;
 283         val = pcs->read(pcs->base + offset);
 284         pa = pcs->res->start + offset;
 285
 286         seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
 287 }
 288
 289 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 290                                 struct pinctrl_map *map, unsigned num_maps)
 291 {
 292         struct pcs_device *pcs;
 293
 294         pcs = pinctrl_dev_get_drvdata(pctldev);
 295         devm_kfree(pcs->dev, map);
 296 }
 297
 298 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 299                                 struct device_node *np_config,
 300                                 struct pinctrl_map **map, unsigned *num_maps);
 301
 302 static const struct pinctrl_ops pcs_pinctrl_ops = {
 303         .get_groups_count = pinctrl_generic_get_group_count,
 304         .get_group_name = pinctrl_generic_get_group_name,
 305         .get_group_pins = pinctrl_generic_get_group_pins,
 306         .pin_dbg_show = pcs_pin_dbg_show,
 307         .dt_node_to_map = pcs_dt_node_to_map,
 308         .dt_free_map = pcs_dt_free_map,
 309 };
 310
 311 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 312                             struct pcs_function **func)
 313 {
 314         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 315         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 316         const struct pinctrl_setting_mux *setting;
 317         struct function_desc *function;
 318         unsigned fselector;
 319
 320         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 321         setting = pdesc->mux_setting;
 322         if (!setting)
 323                 return -ENOTSUPP;
 324         fselector = setting->func;
 325         function = pinmux_generic_get_function(pctldev, fselector);
 326         *func = function->data;
 327         if (!(*func)) {
 328                 dev_err(pcs->dev, "%s could not find function%i\n",
 329                         __func__, fselector);
 330                 return -ENOTSUPP;
 331         }
 332         return 0;
 333 }
 334
 335 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 336         unsigned group)
 337 {
 338         struct pcs_device *pcs;
 339         struct function_desc *function;
 340         struct pcs_function *func;
 341         int i;
 342
 343         pcs = pinctrl_dev_get_drvdata(pctldev);
 344         /* If function mask is null, needn't enable it. */
 345         if (!pcs->fmask)
 346                 return 0;
 347         function = pinmux_generic_get_function(pctldev, fselector);
 348         func = function->data;
 349         if (!func)
 350                 return -EINVAL;
 351
 352         dev_dbg(pcs->dev, "enabling %s function%i\n",
 353                 func->name, fselector);
 354
 355         for (i = 0; i < func->nvals; i++) {
 356                 struct pcs_func_vals *vals;
 357                 unsigned long flags;
 358                 unsigned val, mask;
 359
 360                 vals = &func->vals[i];
 361                 raw_spin_lock_irqsave(&pcs->lock, flags);
 362                 val = pcs->read(vals->reg);
 363
 364                 if (pcs->bits_per_mux)
 365                         mask = vals->mask;
 366                 else
 367                         mask = pcs->fmask;
 368
 369                 val &= ~mask;
 370                 val |= (vals->val & mask);
 371                 pcs->write(val, vals->reg);
 372                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 379                             struct pinctrl_gpio_range *range, unsigned pin)
 380 {
 381         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 382         struct pcs_gpiofunc_range *frange = NULL;
 383         struct list_head *pos, *tmp;
 384         int mux_bytes = 0;
 385         unsigned data;
 386
 387         /* If function mask is null, return directly. */
 388         if (!pcs->fmask)
 389                 return -ENOTSUPP;
 390
 391         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 392                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 393                 if (pin >= frange->offset + frange->npins
 394                         || pin < frange->offset)
 395                         continue;
 396                 mux_bytes = pcs->width / BITS_PER_BYTE;
 397
 398                 if (pcs->bits_per_mux) {
 399                         int byte_num, offset, pin_shift;
 400
 401                         byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
 402                         offset = (byte_num / mux_bytes) * mux_bytes;
 403                         pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
 404                                     pcs->bits_per_pin;
 405
 406                         data = pcs->read(pcs->base + offset);
 407                         data &= ~(pcs->fmask << pin_shift);
 408                         data |= frange->gpiofunc << pin_shift;
 409                         pcs->write(data, pcs->base + offset);
 410                 } else {
 411                         data = pcs->read(pcs->base + pin * mux_bytes);
 412                         data &= ~pcs->fmask;
 413                         data |= frange->gpiofunc;
 414                         pcs->write(data, pcs->base + pin * mux_bytes);
 415                 }
 416                 break;
 417         }
 418         return 0;
 419 }
 420
 421 static const struct pinmux_ops pcs_pinmux_ops = {
 422         .get_functions_count = pinmux_generic_get_function_count,
 423         .get_function_name = pinmux_generic_get_function_name,
 424         .get_function_groups = pinmux_generic_get_function_groups,
 425         .set_mux = pcs_set_mux,
 426         .gpio_request_enable = pcs_request_gpio,
 427 };
 428
 429 /* Clear BIAS value */
 430 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 431 {
 432         unsigned long config;
 433         int i;
 434         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 435                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 436                 pcs_pinconf_set(pctldev, pin, &config, 1);
 437         }
 438 }
 439
 440 /*
 441  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 442  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 443  */
 444 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 445 {
 446         unsigned long config;
 447         int i;
 448
 449         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 450                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 451                 if (!pcs_pinconf_get(pctldev, pin, &config))
 452                         goto out;
 453         }
 454         return true;
 455 out:
 456         return false;
 457 }
 458
 459 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 460                                 unsigned pin, unsigned long *config)
 461 {
 462         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 463         struct pcs_function *func;
 464         enum pin_config_param param;
 465         unsigned offset = 0, data = 0, i, j, ret;
 466
 467         ret = pcs_get_function(pctldev, pin, &func);
 468         if (ret)
 469                 return ret;
 470
 471         for (i = 0; i < func->nconfs; i++) {
 472                 param = pinconf_to_config_param(*config);
 473                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 474                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 475                                 *config = 0;
 476                                 return 0;
 477                         } else {
 478                                 return -ENOTSUPP;
 479                         }
 480                 } else if (param != func->conf[i].param) {
 481                         continue;
 482                 }
 483
 484                 offset = pin * (pcs->width / BITS_PER_BYTE);
 485                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 486                 switch (func->conf[i].param) {
 487                 /* 4 parameters */
 488                 case PIN_CONFIG_BIAS_PULL_DOWN:
 489                 case PIN_CONFIG_BIAS_PULL_UP:
 490                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 491                         if ((data != func->conf[i].enable) ||
 492                             (data == func->conf[i].disable))
 493                                 return -ENOTSUPP;
 494                         *config = 0;
 495                         break;
 496                 /* 2 parameters */
 497                 case PIN_CONFIG_INPUT_SCHMITT:
 498                         for (j = 0; j < func->nconfs; j++) {
 499                                 switch (func->conf[j].param) {
 500                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 501                                         if (data != func->conf[j].enable)
 502                                                 return -ENOTSUPP;
 503                                         break;
 504                                 default:
 505                                         break;
 506                                 }
 507                         }
 508                         *config = data;
 509                         break;
 510                 case PIN_CONFIG_DRIVE_STRENGTH:
 511                 case PIN_CONFIG_SLEW_RATE:
 512                 case PIN_CONFIG_LOW_POWER_MODE:
 513                 default:
 514                         *config = data;
 515                         break;
 516                 }
 517                 return 0;
 518         }
 519         return -ENOTSUPP;
 520 }
 521
 522 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 523                                 unsigned pin, unsigned long *configs,
 524                                 unsigned num_configs)
 525 {
 526         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 527         struct pcs_function *func;
 528         unsigned offset = 0, shift = 0, i, data, ret;
 529         u32 arg;
 530         int j;
 531
 532         ret = pcs_get_function(pctldev, pin, &func);
 533         if (ret)
 534                 return ret;
 535
 536         for (j = 0; j < num_configs; j++) {
 537                 for (i = 0; i < func->nconfs; i++) {
 538                         if (pinconf_to_config_param(configs[j])
 539                                 != func->conf[i].param)
 540                                 continue;
 541
 542                         offset = pin * (pcs->width / BITS_PER_BYTE);
 543                         data = pcs->read(pcs->base + offset);
 544                         arg = pinconf_to_config_argument(configs[j]);
 545                         switch (func->conf[i].param) {
 546                         /* 2 parameters */
 547                         case PIN_CONFIG_INPUT_SCHMITT:
 548                         case PIN_CONFIG_DRIVE_STRENGTH:
 549                         case PIN_CONFIG_SLEW_RATE:
 550                         case PIN_CONFIG_LOW_POWER_MODE:
 551                                 shift = ffs(func->conf[i].mask) - 1;
 552                                 data &= ~func->conf[i].mask;
 553                                 data |= (arg << shift) & func->conf[i].mask;
 554                                 break;
 555                         /* 4 parameters */
 556                         case PIN_CONFIG_BIAS_DISABLE:
 557                                 pcs_pinconf_clear_bias(pctldev, pin);
 558                                 break;
 559                         case PIN_CONFIG_BIAS_PULL_DOWN:
 560                         case PIN_CONFIG_BIAS_PULL_UP:
 561                                 if (arg)
 562                                         pcs_pinconf_clear_bias(pctldev, pin);
 563                                 /* fall through */
 564                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 565                                 data &= ~func->conf[i].mask;
 566                                 if (arg)
 567                                         data |= func->conf[i].enable;
 568                                 else
 569                                         data |= func->conf[i].disable;
 570                                 break;
 571                         default:
 572                                 return -ENOTSUPP;
 573                         }
 574                         pcs->write(data, pcs->base + offset);
 575
 576                         break;
 577                 }
 578                 if (i >= func->nconfs)
 579                         return -ENOTSUPP;
 580         } /* for each config */
 581
 582         return 0;
 583 }
 584
 585 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 586                                 unsigned group, unsigned long *config)
 587 {
 588         const unsigned *pins;
 589         unsigned npins, old = 0;
 590         int i, ret;
 591
 592         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 593         if (ret)
 594                 return ret;
 595         for (i = 0; i < npins; i++) {
 596                 if (pcs_pinconf_get(pctldev, pins[i], config))
 597                         return -ENOTSUPP;
 598                 /* configs do not match between two pins */
 599                 if (i && (old != *config))
 600                         return -ENOTSUPP;
 601                 old = *config;
 602         }
 603         return 0;
 604 }
 605
 606 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 607                                 unsigned group, unsigned long *configs,
 608                                 unsigned num_configs)
 609 {
 610         const unsigned *pins;
 611         unsigned npins;
 612         int i, ret;
 613
 614         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 615         if (ret)
 616                 return ret;
 617         for (i = 0; i < npins; i++) {
 618                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 619                         return -ENOTSUPP;
 620         }
 621         return 0;
 622 }
 623
 624 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 625                                 struct seq_file *s, unsigned pin)
 626 {
 627 }
 628
 629 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 630                                 struct seq_file *s, unsigned selector)
 631 {
 632 }
 633
 634 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 635                                         struct seq_file *s,
 636                                         unsigned long config)
 637 {
 638         pinconf_generic_dump_config(pctldev, s, config);
 639 }
 640
 641 static const struct pinconf_ops pcs_pinconf_ops = {
 642         .pin_config_get = pcs_pinconf_get,
 643         .pin_config_set = pcs_pinconf_set,
 644         .pin_config_group_get = pcs_pinconf_group_get,
 645         .pin_config_group_set = pcs_pinconf_group_set,
 646         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 647         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 648         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 649         .is_generic = true,
 650 };
 651
 652 /**
 653  * pcs_add_pin() - add a pin to the static per controller pin array
 654  * @pcs: pcs driver instance
 655  * @offset: register offset from base
 656  */
 657 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
 658                 unsigned pin_pos)
 659 {
 660         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 661         struct pinctrl_pin_desc *pin;
 662         int i;
 663
 664         i = pcs->pins.cur;
 665         if (i >= pcs->desc.npins) {
 666                 dev_err(pcs->dev, "too many pins, max %i\n",
 667                         pcs->desc.npins);
 668                 return -ENOMEM;
 669         }
 670
 671         if (pcs_soc->irq_enable_mask) {
 672                 unsigned val;
 673
 674                 val = pcs->read(pcs->base + offset);
 675                 if (val & pcs_soc->irq_enable_mask) {
 676                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 677                                 (unsigned long)pcs->res->start + offset, val);
 678                         val &= ~pcs_soc->irq_enable_mask;
 679                         pcs->write(val, pcs->base + offset);
 680                 }
 681         }
 682
 683         pin = &pcs->pins.pa[i];
 684         pin->number = i;
 685         pcs->pins.cur++;
 686
 687         return i;
 688 }
 689
 690 /**
 691  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 692  * @pcs: pcs driver instance
 693  *
 694  * In case of errors, resources are freed in pcs_free_resources.
 695  *
 696  * If your hardware needs holes in the address space, then just set
 697  * up multiple driver instances.
 698  */
 699 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 700 {
 701         int mux_bytes, nr_pins, i;
 702         int num_pins_in_register = 0;
 703
 704         mux_bytes = pcs->width / BITS_PER_BYTE;
 705
 706         if (pcs->bits_per_mux) {
 707                 pcs->bits_per_pin = fls(pcs->fmask);
 708                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 709                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 710         } else {
 711                 nr_pins = pcs->size / mux_bytes;
 712         }
 713
 714         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 715         pcs->pins.pa = devm_kcalloc(pcs->dev,
 716                                 nr_pins, sizeof(*pcs->pins.pa),
 717                                 GFP_KERNEL);
 718         if (!pcs->pins.pa)
 719                 return -ENOMEM;
 720
 721         pcs->desc.pins = pcs->pins.pa;
 722         pcs->desc.npins = nr_pins;
 723
 724         for (i = 0; i < pcs->desc.npins; i++) {
 725                 unsigned offset;
 726                 int res;
 727                 int byte_num;
 728                 int pin_pos = 0;
 729
 730                 if (pcs->bits_per_mux) {
 731                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 732                         offset = (byte_num / mux_bytes) * mux_bytes;
 733                         pin_pos = i % num_pins_in_register;
 734                 } else {
 735                         offset = i * mux_bytes;
 736                 }
 737                 res = pcs_add_pin(pcs, offset, pin_pos);
 738                 if (res < 0) {
 739                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 740                         return res;
 741                 }
 742         }
 743
 744         return 0;
 745 }
 746
 747 /**
 748  * pcs_add_function() - adds a new function to the function list
 749  * @pcs: pcs driver instance
 750  * @np: device node of the mux entry
 751  * @name: name of the function
 752  * @vals: array of mux register value pairs used by the function
 753  * @nvals: number of mux register value pairs
 754  * @pgnames: array of pingroup names for the function
 755  * @npgnames: number of pingroup names
 756  */
 757 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
 758                                         struct device_node *np,
 759                                         const char *name,
 760                                         struct pcs_func_vals *vals,
 761                                         unsigned nvals,
 762                                         const char **pgnames,
 763                                         unsigned npgnames)
 764 {
 765         struct pcs_function *function;
 766         int res;
 767
 768         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 769         if (!function)
 770                 return NULL;
 771
 772         function->vals = vals;
 773         function->nvals = nvals;
 774
 775         res = pinmux_generic_add_function(pcs->pctl, name,
 776                                           pgnames, npgnames,
 777                                           function);
 778         if (res)
 779                 return NULL;
 780
 781         return function;
 782 }
 783
 784 /**
 785  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 786  * @pcs: pcs driver instance
 787  * @offset: register offset from the base
 788  *
 789  * Note that this is OK as long as the pins are in a static array.
 790  */
 791 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 792 {
 793         unsigned index;
 794
 795         if (offset >= pcs->size) {
 796                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 797                         offset, pcs->size);
 798                 return -EINVAL;
 799         }
 800
 801         if (pcs->bits_per_mux)
 802                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 803         else
 804                 index = offset / (pcs->width / BITS_PER_BYTE);
 805
 806         return index;
 807 }
 808
 809 /*
 810  * check whether data matches enable bits or disable bits
 811  * Return value: 1 for matching enable bits, 0 for matching disable bits,
 812  *               and negative value for matching failure.
 813  */
 814 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 815 {
 816         int ret = -EINVAL;
 817
 818         if (data == enable)
 819                 ret = 1;
 820         else if (data == disable)
 821                 ret = 0;
 822         return ret;
 823 }
 824
 825 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 826                        unsigned value, unsigned enable, unsigned disable,
 827                        unsigned mask)
 828 {
 829         (*conf)->param = param;
 830         (*conf)->val = value;
 831         (*conf)->enable = enable;
 832         (*conf)->disable = disable;
 833         (*conf)->mask = mask;
 834         (*conf)++;
 835 }
 836
 837 static void add_setting(unsigned long **setting, enum pin_config_param param,
 838                         unsigned arg)
 839 {
 840         **setting = pinconf_to_config_packed(param, arg);
 841         (*setting)++;
 842 }
 843
 844 /* add pinconf setting with 2 parameters */
 845 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
 846                           const char *name, enum pin_config_param param,
 847                           struct pcs_conf_vals **conf, unsigned long **settings)
 848 {
 849         unsigned value[2], shift;
 850         int ret;
 851
 852         ret = of_property_read_u32_array(np, name, value, 2);
 853         if (ret)
 854                 return;
 855         /* set value & mask */
 856         value[0] &= value[1];
 857         shift = ffs(value[1]) - 1;
 858         /* skip enable & disable */
 859         add_config(conf, param, value[0], 0, 0, value[1]);
 860         add_setting(settings, param, value[0] >> shift);
 861 }
 862
 863 /* add pinconf setting with 4 parameters */
 864 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
 865                           const char *name, enum pin_config_param param,
 866                           struct pcs_conf_vals **conf, unsigned long **settings)
 867 {
 868         unsigned value[4];
 869         int ret;
 870
 871         /* value to set, enable, disable, mask */
 872         ret = of_property_read_u32_array(np, name, value, 4);
 873         if (ret)
 874                 return;
 875         if (!value[3]) {
 876                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
 877                 return;
 878         }
 879         value[0] &= value[3];
 880         value[1] &= value[3];
 881         value[2] &= value[3];
 882         ret = pcs_config_match(value[0], value[1], value[2]);
 883         if (ret < 0)
 884                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
 885         add_config(conf, param, value[0], value[1], value[2], value[3]);
 886         add_setting(settings, param, ret);
 887 }
 888
 889 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
 890                              struct pcs_function *func,
 891                              struct pinctrl_map **map)
 892
 893 {
 894         struct pinctrl_map *m = *map;
 895         int i = 0, nconfs = 0;
 896         unsigned long *settings = NULL, *s = NULL;
 897         struct pcs_conf_vals *conf = NULL;
 898         static const struct pcs_conf_type prop2[] = {
 899                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
 900                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
 901                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
 902                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
 903         };
 904         static const struct pcs_conf_type prop4[] = {
 905                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
 906                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
 907                 { "pinctrl-single,input-schmitt-enable",
 908                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
 909         };
 910
 911         /* If pinconf isn't supported, don't parse properties in below. */
 912         if (!PCS_HAS_PINCONF)
 913                 return 0;
 914
 915         /* cacluate how much properties are supported in current node */
 916         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
 917                 if (of_find_property(np, prop2[i].name, NULL))
 918                         nconfs++;
 919         }
 920         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
 921                 if (of_find_property(np, prop4[i].name, NULL))
 922                         nconfs++;
 923         }
 924         if (!nconfs)
 925                 return 0;
 926
 927         func->conf = devm_kcalloc(pcs->dev,
 928                                   nconfs, sizeof(struct pcs_conf_vals),
 929                                   GFP_KERNEL);
 930         if (!func->conf)
 931                 return -ENOMEM;
 932         func->nconfs = nconfs;
 933         conf = &(func->conf[0]);
 934         m++;
 935         settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
 936                                 GFP_KERNEL);
 937         if (!settings)
 938                 return -ENOMEM;
 939         s = &settings[0];
 940
 941         for (i = 0; i < ARRAY_SIZE(prop2); i++)
 942                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
 943                               &conf, &s);
 944         for (i = 0; i < ARRAY_SIZE(prop4); i++)
 945                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
 946                               &conf, &s);
 947         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
 948         m->data.configs.group_or_pin = np->name;
 949         m->data.configs.configs = settings;
 950         m->data.configs.num_configs = nconfs;
 951         return 0;
 952 }
 953
 954 /**
 955  * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
 956  * @pctldev: pin controller device
 957  * @pcs: pinctrl driver instance
 958  * @np: device node of the mux entry
 959  * @map: map entry
 960  * @num_maps: number of map
 961  * @pgnames: pingroup names
 962  *
 963  * Note that this binding currently supports only sets of one register + value.
 964  *
 965  * Also note that this driver tries to avoid understanding pin and function
 966  * names because of the extra bloat they would cause especially in the case of
 967  * a large number of pins. This driver just sets what is specified for the board
 968  * in the .dts file. Further user space debugging tools can be developed to
 969  * decipher the pin and function names using debugfs.
 970  *
 971  * If you are concerned about the boot time, set up the static pins in
 972  * the bootloader, and only set up selected pins as device tree entries.
 973  */
 974 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
 975                                                 struct device_node *np,
 976                                                 struct pinctrl_map **map,
 977                                                 unsigned *num_maps,
 978                                                 const char **pgnames)
 979 {
 980         const char *name = "pinctrl-single,pins";
 981         struct pcs_func_vals *vals;
 982         int rows, *pins, found = 0, res = -ENOMEM, i;
 983         struct pcs_function *function;
 984
 985         rows = pinctrl_count_index_with_args(np, name);
 986         if (rows <= 0) {
 987                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
 988                 return -EINVAL;
 989         }
 990
 991         vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
 992         if (!vals)
 993                 return -ENOMEM;
 994
 995         pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
 996         if (!pins)
 997                 goto free_vals;
 998
 999         for (i = 0; i < rows; i++) {
1000                 struct of_phandle_args pinctrl_spec;
1001                 unsigned int offset;
1002                 int pin;
1003
1004                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1005                 if (res)
1006                         return res;
1007
1008                 if (pinctrl_spec.args_count < 2) {
1009                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1010                                 pinctrl_spec.args_count);
1011                         break;
1012                 }
1013
1014                 /* Index plus one value cell */
1015                 offset = pinctrl_spec.args[0];
1016                 vals[found].reg = pcs->base + offset;
1017                 vals[found].val = pinctrl_spec.args[1];
1018
1019                 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
1020                         pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
1021
1022                 pin = pcs_get_pin_by_offset(pcs, offset);
1023                 if (pin < 0) {
1024                         dev_err(pcs->dev,
1025                                 "could not add functions for %s %ux\n",
1026                                 np->name, offset);
1027                         break;
1028                 }
1029                 pins[found++] = pin;
1030         }
1031
1032         pgnames[0] = np->name;
1033         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1034         if (!function) {
1035                 res = -ENOMEM;
1036                 goto free_pins;
1037         }
1038
1039         res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1040         if (res < 0)
1041                 goto free_function;
1042
1043         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1044         (*map)->data.mux.group = np->name;
1045         (*map)->data.mux.function = np->name;
1046
1047         if (PCS_HAS_PINCONF) {
1048                 res = pcs_parse_pinconf(pcs, np, function, map);
1049                 if (res)
1050                         goto free_pingroups;
1051                 *num_maps = 2;
1052         } else {
1053                 *num_maps = 1;
1054         }
1055         return 0;
1056
1057 free_pingroups:
1058         pinctrl_generic_remove_last_group(pcs->pctl);
1059         *num_maps = 1;
1060 free_function:
1061         pinmux_generic_remove_last_function(pcs->pctl);
1062
1063 free_pins:
1064         devm_kfree(pcs->dev, pins);
1065
1066 free_vals:
1067         devm_kfree(pcs->dev, vals);
1068
1069         return res;
1070 }
1071
1072 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1073                                                 struct device_node *np,
1074                                                 struct pinctrl_map **map,
1075                                                 unsigned *num_maps,
1076                                                 const char **pgnames)
1077 {
1078         const char *name = "pinctrl-single,bits";
1079         struct pcs_func_vals *vals;
1080         int rows, *pins, found = 0, res = -ENOMEM, i;
1081         int npins_in_row;
1082         struct pcs_function *function;
1083
1084         rows = pinctrl_count_index_with_args(np, name);
1085         if (rows <= 0) {
1086                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1087                 return -EINVAL;
1088         }
1089
1090         npins_in_row = pcs->width / pcs->bits_per_pin;
1091
1092         vals = devm_kzalloc(pcs->dev,
1093                             array3_size(rows, npins_in_row, sizeof(*vals)),
1094                             GFP_KERNEL);
1095         if (!vals)
1096                 return -ENOMEM;
1097
1098         pins = devm_kzalloc(pcs->dev,
1099                             array3_size(rows, npins_in_row, sizeof(*pins)),
1100                             GFP_KERNEL);
1101         if (!pins)
1102                 goto free_vals;
1103
1104         for (i = 0; i < rows; i++) {
1105                 struct of_phandle_args pinctrl_spec;
1106                 unsigned offset, val;
1107                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1108                 unsigned pin_num_from_lsb;
1109                 int pin;
1110
1111                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1112                 if (res)
1113                         return res;
1114
1115                 if (pinctrl_spec.args_count < 3) {
1116                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1117                                 pinctrl_spec.args_count);
1118                         break;
1119                 }
1120
1121                 /* Index plus two value cells */
1122                 offset = pinctrl_spec.args[0];
1123                 val = pinctrl_spec.args[1];
1124                 mask = pinctrl_spec.args[2];
1125
1126                 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1127                         pinctrl_spec.np->name, offset, val, mask);
1128
1129                 /* Parse pins in each row from LSB */
1130                 while (mask) {
1131                         bit_pos = __ffs(mask);
1132                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1133                         mask_pos = ((pcs->fmask) << bit_pos);
1134                         val_pos = val & mask_pos;
1135                         submask = mask & mask_pos;
1136
1137                         if ((mask & mask_pos) == 0) {
1138                                 dev_err(pcs->dev,
1139                                         "Invalid mask for %s at 0x%x\n",
1140                                         np->name, offset);
1141                                 break;
1142                         }
1143
1144                         mask &= ~mask_pos;
1145
1146                         if (submask != mask_pos) {
1147                                 dev_warn(pcs->dev,
1148                                                 "Invalid submask 0x%x for %s at 0x%x\n",
1149                                                 submask, np->name, offset);
1150                                 continue;
1151                         }
1152
1153                         vals[found].mask = submask;
1154                         vals[found].reg = pcs->base + offset;
1155                         vals[found].val = val_pos;
1156
1157                         pin = pcs_get_pin_by_offset(pcs, offset);
1158                         if (pin < 0) {
1159                                 dev_err(pcs->dev,
1160                                         "could not add functions for %s %ux\n",
1161                                         np->name, offset);
1162                                 break;
1163                         }
1164                         pins[found++] = pin + pin_num_from_lsb;
1165                 }
1166         }
1167
1168         pgnames[0] = np->name;
1169         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1170         if (!function) {
1171                 res = -ENOMEM;
1172                 goto free_pins;
1173         }
1174
1175         res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1176         if (res < 0)
1177                 goto free_function;
1178
1179         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1180         (*map)->data.mux.group = np->name;
1181         (*map)->data.mux.function = np->name;
1182
1183         if (PCS_HAS_PINCONF) {
1184                 dev_err(pcs->dev, "pinconf not supported\n");
1185                 goto free_pingroups;
1186         }
1187
1188         *num_maps = 1;
1189         return 0;
1190
1191 free_pingroups:
1192         pinctrl_generic_remove_last_group(pcs->pctl);
1193         *num_maps = 1;
1194 free_function:
1195         pinmux_generic_remove_last_function(pcs->pctl);
1196 free_pins:
1197         devm_kfree(pcs->dev, pins);
1198
1199 free_vals:
1200         devm_kfree(pcs->dev, vals);
1201
1202         return res;
1203 }
1204 /**
1205  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1206  * @pctldev: pinctrl instance
1207  * @np_config: device tree pinmux entry
1208  * @map: array of map entries
1209  * @num_maps: number of maps
1210  */
1211 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1212                                 struct device_node *np_config,
1213                                 struct pinctrl_map **map, unsigned *num_maps)
1214 {
1215         struct pcs_device *pcs;
1216         const char **pgnames;
1217         int ret;
1218
1219         pcs = pinctrl_dev_get_drvdata(pctldev);
1220
1221         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1222         *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1223         if (!*map)
1224                 return -ENOMEM;
1225
1226         *num_maps = 0;
1227
1228         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1229         if (!pgnames) {
1230                 ret = -ENOMEM;
1231                 goto free_map;
1232         }
1233
1234         if (pcs->bits_per_mux) {
1235                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1236                                 num_maps, pgnames);
1237                 if (ret < 0) {
1238                         dev_err(pcs->dev, "no pins entries for %s\n",
1239                                 np_config->name);
1240                         goto free_pgnames;
1241                 }
1242         } else {
1243                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1244                                 num_maps, pgnames);
1245                 if (ret < 0) {
1246                         dev_err(pcs->dev, "no pins entries for %s\n",
1247                                 np_config->name);
1248                         goto free_pgnames;
1249                 }
1250         }
1251
1252         return 0;
1253
1254 free_pgnames:
1255         devm_kfree(pcs->dev, pgnames);
1256 free_map:
1257         devm_kfree(pcs->dev, *map);
1258
1259         return ret;
1260 }
1261
1262 /**
1263  * pcs_irq_free() - free interrupt
1264  * @pcs: pcs driver instance
1265  */
1266 static void pcs_irq_free(struct pcs_device *pcs)
1267 {
1268         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1269
1270         if (pcs_soc->irq < 0)
1271                 return;
1272
1273         if (pcs->domain)
1274                 irq_domain_remove(pcs->domain);
1275
1276         if (PCS_QUIRK_HAS_SHARED_IRQ)
1277                 free_irq(pcs_soc->irq, pcs_soc);
1278         else
1279                 irq_set_chained_handler(pcs_soc->irq, NULL);
1280 }
1281
1282 /**
1283  * pcs_free_resources() - free memory used by this driver
1284  * @pcs: pcs driver instance
1285  */
1286 static void pcs_free_resources(struct pcs_device *pcs)
1287 {
1288         pcs_irq_free(pcs);
1289         pinctrl_unregister(pcs->pctl);
1290
1291 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1292         if (pcs->missing_nr_pinctrl_cells)
1293                 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1294 #endif
1295 }
1296
1297 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1298 {
1299         const char *propname = "pinctrl-single,gpio-range";
1300         const char *cellname = "#pinctrl-single,gpio-range-cells";
1301         struct of_phandle_args gpiospec;
1302         struct pcs_gpiofunc_range *range;
1303         int ret, i;
1304
1305         for (i = 0; ; i++) {
1306                 ret = of_parse_phandle_with_args(node, propname, cellname,
1307                                                  i, &gpiospec);
1308                 /* Do not treat it as error. Only treat it as end condition. */
1309                 if (ret) {
1310                         ret = 0;
1311                         break;
1312                 }
1313                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1314                 if (!range) {
1315                         ret = -ENOMEM;
1316                         break;
1317                 }
1318                 range->offset = gpiospec.args[0];
1319                 range->npins = gpiospec.args[1];
1320                 range->gpiofunc = gpiospec.args[2];
1321                 mutex_lock(&pcs->mutex);
1322                 list_add_tail(&range->node, &pcs->gpiofuncs);
1323                 mutex_unlock(&pcs->mutex);
1324         }
1325         return ret;
1326 }
1327 /**
1328  * @reg:        virtual address of interrupt register
1329  * @hwirq:      hardware irq number
1330  * @irq:        virtual irq number
1331  * @node:       list node
1332  */
1333 struct pcs_interrupt {
1334         void __iomem *reg;
1335         irq_hw_number_t hwirq;
1336         unsigned int irq;
1337         struct list_head node;
1338 };
1339
1340 /**
1341  * pcs_irq_set() - enables or disables an interrupt
1342  *
1343  * Note that this currently assumes one interrupt per pinctrl
1344  * register that is typically used for wake-up events.
1345  */
1346 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1347                                int irq, const bool enable)
1348 {
1349         struct pcs_device *pcs;
1350         struct list_head *pos;
1351         unsigned mask;
1352
1353         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1354         list_for_each(pos, &pcs->irqs) {
1355                 struct pcs_interrupt *pcswi;
1356                 unsigned soc_mask;
1357
1358                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1359                 if (irq != pcswi->irq)
1360                         continue;
1361
1362                 soc_mask = pcs_soc->irq_enable_mask;
1363                 raw_spin_lock(&pcs->lock);
1364                 mask = pcs->read(pcswi->reg);
1365                 if (enable)
1366                         mask |= soc_mask;
1367                 else
1368                         mask &= ~soc_mask;
1369                 pcs->write(mask, pcswi->reg);
1370
1371                 /* flush posted write */
1372                 mask = pcs->read(pcswi->reg);
1373                 raw_spin_unlock(&pcs->lock);
1374         }
1375
1376         if (pcs_soc->rearm)
1377                 pcs_soc->rearm();
1378 }
1379
1380 /**
1381  * pcs_irq_mask() - mask pinctrl interrupt
1382  * @d: interrupt data
1383  */
1384 static void pcs_irq_mask(struct irq_data *d)
1385 {
1386         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1387
1388         pcs_irq_set(pcs_soc, d->irq, false);
1389 }
1390
1391 /**
1392  * pcs_irq_unmask() - unmask pinctrl interrupt
1393  * @d: interrupt data
1394  */
1395 static void pcs_irq_unmask(struct irq_data *d)
1396 {
1397         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1398
1399         pcs_irq_set(pcs_soc, d->irq, true);
1400 }
1401
1402 /**
1403  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1404  * @d: interrupt data
1405  * @state: wake-up state
1406  *
1407  * Note that this should be called only for suspend and resume.
1408  * For runtime PM, the wake-up events should be enabled by default.
1409  */
1410 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1411 {
1412         if (state)
1413                 pcs_irq_unmask(d);
1414         else
1415                 pcs_irq_mask(d);
1416
1417         return 0;
1418 }
1419
1420 /**
1421  * pcs_irq_handle() - common interrupt handler
1422  * @pcs_irq: interrupt data
1423  *
1424  * Note that this currently assumes we have one interrupt bit per
1425  * mux register. This interrupt is typically used for wake-up events.
1426  * For more complex interrupts different handlers can be specified.
1427  */
1428 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1429 {
1430         struct pcs_device *pcs;
1431         struct list_head *pos;
1432         int count = 0;
1433
1434         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1435         list_for_each(pos, &pcs->irqs) {
1436                 struct pcs_interrupt *pcswi;
1437                 unsigned mask;
1438
1439                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1440                 raw_spin_lock(&pcs->lock);
1441                 mask = pcs->read(pcswi->reg);
1442                 raw_spin_unlock(&pcs->lock);
1443                 if (mask & pcs_soc->irq_status_mask) {
1444                         generic_handle_irq(irq_find_mapping(pcs->domain,
1445                                                             pcswi->hwirq));
1446                         count++;
1447                 }
1448         }
1449
1450         return count;
1451 }
1452
1453 /**
1454  * pcs_irq_handler() - handler for the shared interrupt case
1455  * @irq: interrupt
1456  * @d: data
1457  *
1458  * Use this for cases where multiple instances of
1459  * pinctrl-single share a single interrupt like on omaps.
1460  */
1461 static irqreturn_t pcs_irq_handler(int irq, void *d)
1462 {
1463         struct pcs_soc_data *pcs_soc = d;
1464
1465         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1466 }
1467
1468 /**
1469  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1470  * @irq: interrupt
1471  * @desc: interrupt descriptor
1472  *
1473  * Use this if you have a separate interrupt for each
1474  * pinctrl-single instance.
1475  */
1476 static void pcs_irq_chain_handler(struct irq_desc *desc)
1477 {
1478         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1479         struct irq_chip *chip;
1480
1481         chip = irq_desc_get_chip(desc);
1482         chained_irq_enter(chip, desc);
1483         pcs_irq_handle(pcs_soc);
1484         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1485         chained_irq_exit(chip, desc);
1486 }
1487
1488 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1489                              irq_hw_number_t hwirq)
1490 {
1491         struct pcs_soc_data *pcs_soc = d->host_data;
1492         struct pcs_device *pcs;
1493         struct pcs_interrupt *pcswi;
1494
1495         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1496         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1497         if (!pcswi)
1498                 return -ENOMEM;
1499
1500         pcswi->reg = pcs->base + hwirq;
1501         pcswi->hwirq = hwirq;
1502         pcswi->irq = irq;
1503
1504         mutex_lock(&pcs->mutex);
1505         list_add_tail(&pcswi->node, &pcs->irqs);
1506         mutex_unlock(&pcs->mutex);
1507
1508         irq_set_chip_data(irq, pcs_soc);
1509         irq_set_chip_and_handler(irq, &pcs->chip,
1510                                  handle_level_irq);
1511         irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1512         irq_set_noprobe(irq);
1513
1514         return 0;
1515 }
1516
1517 static const struct irq_domain_ops pcs_irqdomain_ops = {
1518         .map = pcs_irqdomain_map,
1519         .xlate = irq_domain_xlate_onecell,
1520 };
1521
1522 /**
1523  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1524  * @pcs: pcs driver instance
1525  * @np: device node pointer
1526  */
1527 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1528                                         struct device_node *np)
1529 {
1530         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1531         const char *name = "pinctrl";
1532         int num_irqs;
1533
1534         if (!pcs_soc->irq_enable_mask ||
1535             !pcs_soc->irq_status_mask) {
1536                 pcs_soc->irq = -1;
1537                 return -EINVAL;
1538         }
1539
1540         INIT_LIST_HEAD(&pcs->irqs);
1541         pcs->chip.name = name;
1542         pcs->chip.irq_ack = pcs_irq_mask;
1543         pcs->chip.irq_mask = pcs_irq_mask;
1544         pcs->chip.irq_unmask = pcs_irq_unmask;
1545         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1546
1547         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1548                 int res;
1549
1550                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1551                                   IRQF_SHARED | IRQF_NO_SUSPEND |
1552                                   IRQF_NO_THREAD,
1553                                   name, pcs_soc);
1554                 if (res) {
1555                         pcs_soc->irq = -1;
1556                         return res;
1557                 }
1558         } else {
1559                 irq_set_chained_handler_and_data(pcs_soc->irq,
1560                                                  pcs_irq_chain_handler,
1561                                                  pcs_soc);
1562         }
1563
1564         /*
1565          * We can use the register offset as the hardirq
1566          * number as irq_domain_add_simple maps them lazily.
1567          * This way we can easily support more than one
1568          * interrupt per function if needed.
1569          */
1570         num_irqs = pcs->size;
1571
1572         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1573                                             &pcs_irqdomain_ops,
1574                                             pcs_soc);
1575         if (!pcs->domain) {
1576                 irq_set_chained_handler(pcs_soc->irq, NULL);
1577                 return -EINVAL;
1578         }
1579
1580         return 0;
1581 }
1582
1583 #ifdef CONFIG_PM
1584 static int pcs_save_context(struct pcs_device *pcs)
1585 {
1586         int i, mux_bytes;
1587         u64 *regsl;
1588         u32 *regsw;
1589         u16 *regshw;
1590
1591         mux_bytes = pcs->width / BITS_PER_BYTE;
1592
1593         if (!pcs->saved_vals)
1594                 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1595
1596         switch (pcs->width) {
1597         case 64:
1598                 regsl = (u64 *)pcs->saved_vals;
1599                 for (i = 0; i < pcs->size / mux_bytes; i++)
1600                         regsl[i] = pcs->read(pcs->base + i * mux_bytes);
1601                 break;
1602         case 32:
1603                 regsw = (u32 *)pcs->saved_vals;
1604                 for (i = 0; i < pcs->size / mux_bytes; i++)
1605                         regsw[i] = pcs->read(pcs->base + i * mux_bytes);
1606                 break;
1607         case 16:
1608                 regshw = (u16 *)pcs->saved_vals;
1609                 for (i = 0; i < pcs->size / mux_bytes; i++)
1610                         regshw[i] = pcs->read(pcs->base + i * mux_bytes);
1611                 break;
1612         }
1613
1614         return 0;
1615 }
1616
1617 static void pcs_restore_context(struct pcs_device *pcs)
1618 {
1619         int i, mux_bytes;
1620         u64 *regsl;
1621         u32 *regsw;
1622         u16 *regshw;
1623
1624         mux_bytes = pcs->width / BITS_PER_BYTE;
1625
1626         switch (pcs->width) {
1627         case 64:
1628                 regsl = (u64 *)pcs->saved_vals;
1629                 for (i = 0; i < pcs->size / mux_bytes; i++)
1630                         pcs->write(regsl[i], pcs->base + i * mux_bytes);
1631                 break;
1632         case 32:
1633                 regsw = (u32 *)pcs->saved_vals;
1634                 for (i = 0; i < pcs->size / mux_bytes; i++)
1635                         pcs->write(regsw[i], pcs->base + i * mux_bytes);
1636                 break;
1637         case 16:
1638                 regshw = (u16 *)pcs->saved_vals;
1639                 for (i = 0; i < pcs->size / mux_bytes; i++)
1640                         pcs->write(regshw[i], pcs->base + i * mux_bytes);
1641                 break;
1642         }
1643 }
1644
1645 static int pinctrl_single_suspend(struct platform_device *pdev,
1646                                         pm_message_t state)
1647 {
1648         struct pcs_device *pcs;
1649
1650         pcs = platform_get_drvdata(pdev);
1651         if (!pcs)
1652                 return -EINVAL;
1653
1654         if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1655                 pcs_save_context(pcs);
1656
1657         return pinctrl_force_sleep(pcs->pctl);
1658 }
1659
1660 static int pinctrl_single_resume(struct platform_device *pdev)
1661 {
1662         struct pcs_device *pcs;
1663
1664         pcs = platform_get_drvdata(pdev);
1665         if (!pcs)
1666                 return -EINVAL;
1667
1668         if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1669                 pcs_restore_context(pcs);
1670
1671         return pinctrl_force_default(pcs->pctl);
1672 }
1673 #endif
1674
1675 /**
1676  * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1677  * @pcs: pinctrl driver instance
1678  * @np: device tree node
1679  * @cells: number of cells
1680  *
1681  * Handle legacy binding with no #pinctrl-cells. This should be
1682  * always two pinctrl-single,bit-per-mux and one for others.
1683  * At some point we may want to consider removing this.
1684  */
1685 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1686                                            struct device_node *np,
1687                                            int cells)
1688 {
1689         struct property *p;
1690         const char *name = "#pinctrl-cells";
1691         int error;
1692         u32 val;
1693
1694         error = of_property_read_u32(np, name, &val);
1695         if (!error)
1696                 return 0;
1697
1698         dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1699                  name, cells);
1700
1701         p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1702         if (!p)
1703                 return -ENOMEM;
1704
1705         p->length = sizeof(__be32);
1706         p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1707         if (!p->value)
1708                 return -ENOMEM;
1709         *(__be32 *)p->value = cpu_to_be32(cells);
1710
1711         p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1712         if (!p->name)
1713                 return -ENOMEM;
1714
1715         pcs->missing_nr_pinctrl_cells = p;
1716
1717 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1718         error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1719 #endif
1720
1721         return error;
1722 }
1723
1724 static int pcs_probe(struct platform_device *pdev)
1725 {
1726         struct device_node *np = pdev->dev.of_node;
1727         struct pcs_pdata *pdata;
1728         struct resource *res;
1729         struct pcs_device *pcs;
1730         const struct pcs_soc_data *soc;
1731         int ret;
1732
1733         soc = of_device_get_match_data(&pdev->dev);
1734         if (WARN_ON(!soc))
1735                 return -EINVAL;
1736
1737         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1738         if (!pcs)
1739                 return -ENOMEM;
1740
1741         pcs->dev = &pdev->dev;
1742         pcs->np = np;
1743         raw_spin_lock_init(&pcs->lock);
1744         mutex_init(&pcs->mutex);
1745         INIT_LIST_HEAD(&pcs->gpiofuncs);
1746         pcs->flags = soc->flags;
1747         memcpy(&pcs->socdata, soc, sizeof(*soc));
1748
1749         ret = of_property_read_u32(np, "pinctrl-single,register-width",
1750                                    &pcs->width);
1751         if (ret) {
1752                 dev_err(pcs->dev, "register width not specified\n");
1753
1754                 return ret;
1755         }
1756
1757         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1758                                    &pcs->fmask);
1759         if (!ret) {
1760                 pcs->fshift = __ffs(pcs->fmask);
1761                 pcs->fmax = pcs->fmask >> pcs->fshift;
1762         } else {
1763                 /* If mask property doesn't exist, function mux is invalid. */
1764                 pcs->fmask = 0;
1765                 pcs->fshift = 0;
1766                 pcs->fmax = 0;
1767         }
1768
1769         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1770                                         &pcs->foff);
1771         if (ret)
1772                 pcs->foff = PCS_OFF_DISABLED;
1773
1774         pcs->bits_per_mux = of_property_read_bool(np,
1775                                                   "pinctrl-single,bit-per-mux");
1776         ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1777                                               pcs->bits_per_mux ? 2 : 1);
1778         if (ret) {
1779                 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1780
1781                 return ret;
1782         }
1783
1784         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1785         if (!res) {
1786                 dev_err(pcs->dev, "could not get resource\n");
1787                 return -ENODEV;
1788         }
1789
1790         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1791                         resource_size(res), DRIVER_NAME);
1792         if (!pcs->res) {
1793                 dev_err(pcs->dev, "could not get mem_region\n");
1794                 return -EBUSY;
1795         }
1796
1797         pcs->size = resource_size(pcs->res);
1798         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1799         if (!pcs->base) {
1800                 dev_err(pcs->dev, "could not ioremap\n");
1801                 return -ENODEV;
1802         }
1803
1804         platform_set_drvdata(pdev, pcs);
1805
1806         switch (pcs->width) {
1807         case 8:
1808                 pcs->read = pcs_readb;
1809                 pcs->write = pcs_writeb;
1810                 break;
1811         case 16:
1812                 pcs->read = pcs_readw;
1813                 pcs->write = pcs_writew;
1814                 break;
1815         case 32:
1816                 pcs->read = pcs_readl;
1817                 pcs->write = pcs_writel;
1818                 break;
1819         default:
1820                 break;
1821         }
1822
1823         pcs->desc.name = DRIVER_NAME;
1824         pcs->desc.pctlops = &pcs_pinctrl_ops;
1825         pcs->desc.pmxops = &pcs_pinmux_ops;
1826         if (PCS_HAS_PINCONF)
1827                 pcs->desc.confops = &pcs_pinconf_ops;
1828         pcs->desc.owner = THIS_MODULE;
1829
1830         ret = pcs_allocate_pin_table(pcs);
1831         if (ret < 0)
1832                 goto free;
1833
1834         ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1835         if (ret) {
1836                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1837                 goto free;
1838         }
1839
1840         ret = pcs_add_gpio_func(np, pcs);
1841         if (ret < 0)
1842                 goto free;
1843
1844         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1845         if (pcs->socdata.irq)
1846                 pcs->flags |= PCS_FEAT_IRQ;
1847
1848         /* We still need auxdata for some omaps for PRM interrupts */
1849         pdata = dev_get_platdata(&pdev->dev);
1850         if (pdata) {
1851                 if (pdata->rearm)
1852                         pcs->socdata.rearm = pdata->rearm;
1853                 if (pdata->irq) {
1854                         pcs->socdata.irq = pdata->irq;
1855                         pcs->flags |= PCS_FEAT_IRQ;
1856                 }
1857         }
1858
1859         if (PCS_HAS_IRQ) {
1860                 ret = pcs_irq_init_chained_handler(pcs, np);
1861                 if (ret < 0)
1862                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1863         }
1864
1865         dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1866
1867         return pinctrl_enable(pcs->pctl);
1868
1869 free:
1870         pcs_free_resources(pcs);
1871
1872         return ret;
1873 }
1874
1875 static int pcs_remove(struct platform_device *pdev)
1876 {
1877         struct pcs_device *pcs = platform_get_drvdata(pdev);
1878
1879         if (!pcs)
1880                 return 0;
1881
1882         pcs_free_resources(pcs);
1883
1884         return 0;
1885 }
1886
1887 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1888         .flags = PCS_QUIRK_SHARED_IRQ,
1889         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
1890         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
1891 };
1892
1893 static const struct pcs_soc_data pinctrl_single_dra7 = {
1894         .irq_enable_mask = (1 << 24),   /* WAKEUPENABLE */
1895         .irq_status_mask = (1 << 25),   /* WAKEUPEVENT */
1896 };
1897
1898 static const struct pcs_soc_data pinctrl_single_am437x = {
1899         .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1900         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1901         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1902 };
1903
1904 static const struct pcs_soc_data pinctrl_single = {
1905 };
1906
1907 static const struct pcs_soc_data pinconf_single = {
1908         .flags = PCS_FEAT_PINCONF,
1909 };
1910
1911 static const struct of_device_id pcs_of_match[] = {
1912         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1913         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1914         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1915         { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1916         { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1917         { .compatible = "pinctrl-single", .data = &pinctrl_single },
1918         { .compatible = "pinconf-single", .data = &pinconf_single },
1919         { },
1920 };
1921 MODULE_DEVICE_TABLE(of, pcs_of_match);
1922
1923 static struct platform_driver pcs_driver = {
1924         .probe          = pcs_probe,
1925         .remove         = pcs_remove,
1926         .driver = {
1927                 .name           = DRIVER_NAME,
1928                 .of_match_table = pcs_of_match,
1929         },
1930 #ifdef CONFIG_PM
1931         .suspend = pinctrl_single_suspend,
1932         .resume = pinctrl_single_resume,
1933 #endif
1934 };
1935
1936 module_platform_driver(pcs_driver);
1937
1938 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1939 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1940 MODULE_LICENSE("GPL v2");