drivers/pinctrl/pinctrl-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Pinctrl driver for Rockchip SoCs
   4  *
   5  * Copyright (c) 2013 MundoReader S.L.
   6  * Author: Heiko Stuebner <heiko@sntech.de>
   7  *
   8  * With some ideas taken from pinctrl-samsung:
   9  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  10  *              http://www.samsung.com
  11  * Copyright (c) 2012 Linaro Ltd
  12  *              https://www.linaro.org
  13  *
  14  * and pinctrl-at91:
  15  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/io.h>
  21 #include <linux/bitops.h>
  22 #include <linux/gpio/driver.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/pinctrl/machine.h>
  26 #include <linux/pinctrl/pinconf.h>
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30 #include <linux/irqchip/chained_irq.h>
  31 #include <linux/clk.h>
  32 #include <linux/regmap.h>
  33 #include <linux/mfd/syscon.h>
  34 #include <dt-bindings/pinctrl/rockchip.h>
  35
  36 #include "core.h"
  37 #include "pinconf.h"
  38
  39 /* GPIO control registers */
  40 #define GPIO_SWPORT_DR          0x00
  41 #define GPIO_SWPORT_DDR         0x04
  42 #define GPIO_INTEN              0x30
  43 #define GPIO_INTMASK            0x34
  44 #define GPIO_INTTYPE_LEVEL      0x38
  45 #define GPIO_INT_POLARITY       0x3c
  46 #define GPIO_INT_STATUS         0x40
  47 #define GPIO_INT_RAWSTATUS      0x44
  48 #define GPIO_DEBOUNCE           0x48
  49 #define GPIO_PORTS_EOI          0x4c
  50 #define GPIO_EXT_PORT           0x50
  51 #define GPIO_LS_SYNC            0x60
  52
  53 enum rockchip_pinctrl_type {
  54         PX30,
  55         RV1108,
  56         RK2928,
  57         RK3066B,
  58         RK3128,
  59         RK3188,
  60         RK3288,
  61         RK3308,
  62         RK3368,
  63         RK3399,
  64 };
  65
  66 /*
  67  * Encode variants of iomux registers into a type variable
  68  */
  69 #define IOMUX_GPIO_ONLY         BIT(0)
  70 #define IOMUX_WIDTH_4BIT        BIT(1)
  71 #define IOMUX_SOURCE_PMU        BIT(2)
  72 #define IOMUX_UNROUTED          BIT(3)
  73 #define IOMUX_WIDTH_3BIT        BIT(4)
  74 #define IOMUX_WIDTH_2BIT        BIT(5)
  75
  76 /**
  77  * struct rockchip_iomux
  78  * @type: iomux variant using IOMUX_* constants
  79  * @offset: if initialized to -1 it will be autocalculated, by specifying
  80  *          an initial offset value the relevant source offset can be reset
  81  *          to a new value for autocalculating the following iomux registers.
  82  */
  83 struct rockchip_iomux {
  84         int                             type;
  85         int                             offset;
  86 };
  87
  88 /*
  89  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  90  */
  91 enum rockchip_pin_drv_type {
  92         DRV_TYPE_IO_DEFAULT = 0,
  93         DRV_TYPE_IO_1V8_OR_3V0,
  94         DRV_TYPE_IO_1V8_ONLY,
  95         DRV_TYPE_IO_1V8_3V0_AUTO,
  96         DRV_TYPE_IO_3V3_ONLY,
  97         DRV_TYPE_MAX
  98 };
  99
 100 /*
 101  * enum type index corresponding to rockchip_pull_list arrays index.
 102  */
 103 enum rockchip_pin_pull_type {
 104         PULL_TYPE_IO_DEFAULT = 0,
 105         PULL_TYPE_IO_1V8_ONLY,
 106         PULL_TYPE_MAX
 107 };
 108
 109 /**
 110  * struct rockchip_drv
 111  * @drv_type: drive strength variant using rockchip_perpin_drv_type
 112  * @offset: if initialized to -1 it will be autocalculated, by specifying
 113  *          an initial offset value the relevant source offset can be reset
 114  *          to a new value for autocalculating the following drive strength
 115  *          registers. if used chips own cal_drv func instead to calculate
 116  *          registers offset, the variant could be ignored.
 117  */
 118 struct rockchip_drv {
 119         enum rockchip_pin_drv_type      drv_type;
 120         int                             offset;
 121 };
 122
 123 /**
 124  * struct rockchip_pin_bank
 125  * @reg_base: register base of the gpio bank
 126  * @regmap_pull: optional separate register for additional pull settings
 127  * @clk: clock of the gpio bank
 128  * @irq: interrupt of the gpio bank
 129  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 130  * @pin_base: first pin number
 131  * @nr_pins: number of pins in this bank
 132  * @name: name of the bank
 133  * @bank_num: number of the bank, to account for holes
 134  * @iomux: array describing the 4 iomux sources of the bank
 135  * @drv: array describing the 4 drive strength sources of the bank
 136  * @pull_type: array describing the 4 pull type sources of the bank
 137  * @valid: is all necessary information present
 138  * @of_node: dt node of this bank
 139  * @drvdata: common pinctrl basedata
 140  * @domain: irqdomain of the gpio bank
 141  * @gpio_chip: gpiolib chip
 142  * @grange: gpio range
 143  * @slock: spinlock for the gpio bank
 144  * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
 145  * @recalced_mask: bit mask to indicate a need to recalulate the mask
 146  * @route_mask: bits describing the routing pins of per bank
 147  */
 148 struct rockchip_pin_bank {
 149         void __iomem                    *reg_base;
 150         struct regmap                   *regmap_pull;
 151         struct clk                      *clk;
 152         int                             irq;
 153         u32                             saved_masks;
 154         u32                             pin_base;
 155         u8                              nr_pins;
 156         char                            *name;
 157         u8                              bank_num;
 158         struct rockchip_iomux           iomux[4];
 159         struct rockchip_drv             drv[4];
 160         enum rockchip_pin_pull_type     pull_type[4];
 161         bool                            valid;
 162         struct device_node              *of_node;
 163         struct rockchip_pinctrl         *drvdata;
 164         struct irq_domain               *domain;
 165         struct gpio_chip                gpio_chip;
 166         struct pinctrl_gpio_range       grange;
 167         raw_spinlock_t                  slock;
 168         u32                             toggle_edge_mode;
 169         u32                             recalced_mask;
 170         u32                             route_mask;
 171 };
 172
 173 #define PIN_BANK(id, pins, label)                       \
 174         {                                               \
 175                 .bank_num       = id,                   \
 176                 .nr_pins        = pins,                 \
 177                 .name           = label,                \
 178                 .iomux          = {                     \
 179                         { .offset = -1 },               \
 180                         { .offset = -1 },               \
 181                         { .offset = -1 },               \
 182                         { .offset = -1 },               \
 183                 },                                      \
 184         }
 185
 186 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 187         {                                                               \
 188                 .bank_num       = id,                                   \
 189                 .nr_pins        = pins,                                 \
 190                 .name           = label,                                \
 191                 .iomux          = {                                     \
 192                         { .type = iom0, .offset = -1 },                 \
 193                         { .type = iom1, .offset = -1 },                 \
 194                         { .type = iom2, .offset = -1 },                 \
 195                         { .type = iom3, .offset = -1 },                 \
 196                 },                                                      \
 197         }
 198
 199 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 200         {                                                               \
 201                 .bank_num       = id,                                   \
 202                 .nr_pins        = pins,                                 \
 203                 .name           = label,                                \
 204                 .iomux          = {                                     \
 205                         { .offset = -1 },                               \
 206                         { .offset = -1 },                               \
 207                         { .offset = -1 },                               \
 208                         { .offset = -1 },                               \
 209                 },                                                      \
 210                 .drv            = {                                     \
 211                         { .drv_type = type0, .offset = -1 },            \
 212                         { .drv_type = type1, .offset = -1 },            \
 213                         { .drv_type = type2, .offset = -1 },            \
 214                         { .drv_type = type3, .offset = -1 },            \
 215                 },                                                      \
 216         }
 217
 218 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 219                                       drv2, drv3, pull0, pull1,         \
 220                                       pull2, pull3)                     \
 221         {                                                               \
 222                 .bank_num       = id,                                   \
 223                 .nr_pins        = pins,                                 \
 224                 .name           = label,                                \
 225                 .iomux          = {                                     \
 226                         { .offset = -1 },                               \
 227                         { .offset = -1 },                               \
 228                         { .offset = -1 },                               \
 229                         { .offset = -1 },                               \
 230                 },                                                      \
 231                 .drv            = {                                     \
 232                         { .drv_type = drv0, .offset = -1 },             \
 233                         { .drv_type = drv1, .offset = -1 },             \
 234                         { .drv_type = drv2, .offset = -1 },             \
 235                         { .drv_type = drv3, .offset = -1 },             \
 236                 },                                                      \
 237                 .pull_type[0] = pull0,                                  \
 238                 .pull_type[1] = pull1,                                  \
 239                 .pull_type[2] = pull2,                                  \
 240                 .pull_type[3] = pull3,                                  \
 241         }
 242
 243 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 244                                         iom2, iom3, drv0, drv1, drv2,   \
 245                                         drv3, offset0, offset1,         \
 246                                         offset2, offset3)               \
 247         {                                                               \
 248                 .bank_num       = id,                                   \
 249                 .nr_pins        = pins,                                 \
 250                 .name           = label,                                \
 251                 .iomux          = {                                     \
 252                         { .type = iom0, .offset = -1 },                 \
 253                         { .type = iom1, .offset = -1 },                 \
 254                         { .type = iom2, .offset = -1 },                 \
 255                         { .type = iom3, .offset = -1 },                 \
 256                 },                                                      \
 257                 .drv            = {                                     \
 258                         { .drv_type = drv0, .offset = offset0 },        \
 259                         { .drv_type = drv1, .offset = offset1 },        \
 260                         { .drv_type = drv2, .offset = offset2 },        \
 261                         { .drv_type = drv3, .offset = offset3 },        \
 262                 },                                                      \
 263         }
 264
 265 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 266                                               label, iom0, iom1, iom2,  \
 267                                               iom3, drv0, drv1, drv2,   \
 268                                               drv3, offset0, offset1,   \
 269                                               offset2, offset3, pull0,  \
 270                                               pull1, pull2, pull3)      \
 271         {                                                               \
 272                 .bank_num       = id,                                   \
 273                 .nr_pins        = pins,                                 \
 274                 .name           = label,                                \
 275                 .iomux          = {                                     \
 276                         { .type = iom0, .offset = -1 },                 \
 277                         { .type = iom1, .offset = -1 },                 \
 278                         { .type = iom2, .offset = -1 },                 \
 279                         { .type = iom3, .offset = -1 },                 \
 280                 },                                                      \
 281                 .drv            = {                                     \
 282                         { .drv_type = drv0, .offset = offset0 },        \
 283                         { .drv_type = drv1, .offset = offset1 },        \
 284                         { .drv_type = drv2, .offset = offset2 },        \
 285                         { .drv_type = drv3, .offset = offset3 },        \
 286                 },                                                      \
 287                 .pull_type[0] = pull0,                                  \
 288                 .pull_type[1] = pull1,                                  \
 289                 .pull_type[2] = pull2,                                  \
 290                 .pull_type[3] = pull3,                                  \
 291         }
 292
 293 /**
 294  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 295  * @num: bank number.
 296  * @pin: pin number.
 297  * @bit: index at register.
 298  * @reg: register offset.
 299  * @mask: mask bit
 300  */
 301 struct rockchip_mux_recalced_data {
 302         u8 num;
 303         u8 pin;
 304         u32 reg;
 305         u8 bit;
 306         u8 mask;
 307 };
 308
 309 enum rockchip_mux_route_location {
 310         ROCKCHIP_ROUTE_SAME = 0,
 311         ROCKCHIP_ROUTE_PMU,
 312         ROCKCHIP_ROUTE_GRF,
 313 };
 314
 315 /**
 316  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 317  * @bank_num: bank number.
 318  * @pin: index at register or used to calc index.
 319  * @func: the min pin.
 320  * @route_location: the mux route location (same, pmu, grf).
 321  * @route_offset: the max pin.
 322  * @route_val: the register offset.
 323  */
 324 struct rockchip_mux_route_data {
 325         u8 bank_num;
 326         u8 pin;
 327         u8 func;
 328         enum rockchip_mux_route_location route_location;
 329         u32 route_offset;
 330         u32 route_val;
 331 };
 332
 333 struct rockchip_pin_ctrl {
 334         struct rockchip_pin_bank        *pin_banks;
 335         u32                             nr_banks;
 336         u32                             nr_pins;
 337         char                            *label;
 338         enum rockchip_pinctrl_type      type;
 339         int                             grf_mux_offset;
 340         int                             pmu_mux_offset;
 341         int                             grf_drv_offset;
 342         int                             pmu_drv_offset;
 343         struct rockchip_mux_recalced_data *iomux_recalced;
 344         u32                             niomux_recalced;
 345         struct rockchip_mux_route_data *iomux_routes;
 346         u32                             niomux_routes;
 347
 348         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 349                                     int pin_num, struct regmap **regmap,
 350                                     int *reg, u8 *bit);
 351         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 352                                     int pin_num, struct regmap **regmap,
 353                                     int *reg, u8 *bit);
 354         int     (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
 355                                     int pin_num, struct regmap **regmap,
 356                                     int *reg, u8 *bit);
 357 };
 358
 359 struct rockchip_pin_config {
 360         unsigned int            func;
 361         unsigned long           *configs;
 362         unsigned int            nconfigs;
 363 };
 364
 365 /**
 366  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 367  * @name: name of the pin group, used to lookup the group.
 368  * @pins: the pins included in this group.
 369  * @npins: number of pins included in this group.
 370  * @data: local pin configuration
 371  */
 372 struct rockchip_pin_group {
 373         const char                      *name;
 374         unsigned int                    npins;
 375         unsigned int                    *pins;
 376         struct rockchip_pin_config      *data;
 377 };
 378
 379 /**
 380  * struct rockchip_pmx_func: represent a pin function.
 381  * @name: name of the pin function, used to lookup the function.
 382  * @groups: one or more names of pin groups that provide this function.
 383  * @ngroups: number of groups included in @groups.
 384  */
 385 struct rockchip_pmx_func {
 386         const char              *name;
 387         const char              **groups;
 388         u8                      ngroups;
 389 };
 390
 391 struct rockchip_pinctrl {
 392         struct regmap                   *regmap_base;
 393         int                             reg_size;
 394         struct regmap                   *regmap_pull;
 395         struct regmap                   *regmap_pmu;
 396         struct device                   *dev;
 397         struct rockchip_pin_ctrl        *ctrl;
 398         struct pinctrl_desc             pctl;
 399         struct pinctrl_dev              *pctl_dev;
 400         struct rockchip_pin_group       *groups;
 401         unsigned int                    ngroups;
 402         struct rockchip_pmx_func        *functions;
 403         unsigned int                    nfunctions;
 404 };
 405
 406 static struct regmap_config rockchip_regmap_config = {
 407         .reg_bits = 32,
 408         .val_bits = 32,
 409         .reg_stride = 4,
 410 };
 411
 412 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 413                                         const struct rockchip_pinctrl *info,
 414                                         const char *name)
 415 {
 416         int i;
 417
 418         for (i = 0; i < info->ngroups; i++) {
 419                 if (!strcmp(info->groups[i].name, name))
 420                         return &info->groups[i];
 421         }
 422
 423         return NULL;
 424 }
 425
 426 /*
 427  * given a pin number that is local to a pin controller, find out the pin bank
 428  * and the register base of the pin bank.
 429  */
 430 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 431                                                                 unsigned pin)
 432 {
 433         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 434
 435         while (pin >= (b->pin_base + b->nr_pins))
 436                 b++;
 437
 438         return b;
 439 }
 440
 441 static struct rockchip_pin_bank *bank_num_to_bank(
 442                                         struct rockchip_pinctrl *info,
 443                                         unsigned num)
 444 {
 445         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 446         int i;
 447
 448         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 449                 if (b->bank_num == num)
 450                         return b;
 451         }
 452
 453         return ERR_PTR(-EINVAL);
 454 }
 455
 456 /*
 457  * Pinctrl_ops handling
 458  */
 459
 460 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 461 {
 462         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 463
 464         return info->ngroups;
 465 }
 466
 467 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 468                                                         unsigned selector)
 469 {
 470         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 471
 472         return info->groups[selector].name;
 473 }
 474
 475 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 476                                       unsigned selector, const unsigned **pins,
 477                                       unsigned *npins)
 478 {
 479         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 480
 481         if (selector >= info->ngroups)
 482                 return -EINVAL;
 483
 484         *pins = info->groups[selector].pins;
 485         *npins = info->groups[selector].npins;
 486
 487         return 0;
 488 }
 489
 490 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 491                                  struct device_node *np,
 492                                  struct pinctrl_map **map, unsigned *num_maps)
 493 {
 494         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 495         const struct rockchip_pin_group *grp;
 496         struct pinctrl_map *new_map;
 497         struct device_node *parent;
 498         int map_num = 1;
 499         int i;
 500
 501         /*
 502          * first find the group of this node and check if we need to create
 503          * config maps for pins
 504          */
 505         grp = pinctrl_name_to_group(info, np->name);
 506         if (!grp) {
 507                 dev_err(info->dev, "unable to find group for node %pOFn\n",
 508                         np);
 509                 return -EINVAL;
 510         }
 511
 512         map_num += grp->npins;
 513
 514         new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 515         if (!new_map)
 516                 return -ENOMEM;
 517
 518         *map = new_map;
 519         *num_maps = map_num;
 520
 521         /* create mux map */
 522         parent = of_get_parent(np);
 523         if (!parent) {
 524                 kfree(new_map);
 525                 return -EINVAL;
 526         }
 527         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 528         new_map[0].data.mux.function = parent->name;
 529         new_map[0].data.mux.group = np->name;
 530         of_node_put(parent);
 531
 532         /* create config map */
 533         new_map++;
 534         for (i = 0; i < grp->npins; i++) {
 535                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 536                 new_map[i].data.configs.group_or_pin =
 537                                 pin_get_name(pctldev, grp->pins[i]);
 538                 new_map[i].data.configs.configs = grp->data[i].configs;
 539                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 540         }
 541
 542         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 543                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 544
 545         return 0;
 546 }
 547
 548 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 549                                     struct pinctrl_map *map, unsigned num_maps)
 550 {
 551         kfree(map);
 552 }
 553
 554 static const struct pinctrl_ops rockchip_pctrl_ops = {
 555         .get_groups_count       = rockchip_get_groups_count,
 556         .get_group_name         = rockchip_get_group_name,
 557         .get_group_pins         = rockchip_get_group_pins,
 558         .dt_node_to_map         = rockchip_dt_node_to_map,
 559         .dt_free_map            = rockchip_dt_free_map,
 560 };
 561
 562 /*
 563  * Hardware access
 564  */
 565
 566 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 567         {
 568                 .num = 1,
 569                 .pin = 0,
 570                 .reg = 0x418,
 571                 .bit = 0,
 572                 .mask = 0x3
 573         }, {
 574                 .num = 1,
 575                 .pin = 1,
 576                 .reg = 0x418,
 577                 .bit = 2,
 578                 .mask = 0x3
 579         }, {
 580                 .num = 1,
 581                 .pin = 2,
 582                 .reg = 0x418,
 583                 .bit = 4,
 584                 .mask = 0x3
 585         }, {
 586                 .num = 1,
 587                 .pin = 3,
 588                 .reg = 0x418,
 589                 .bit = 6,
 590                 .mask = 0x3
 591         }, {
 592                 .num = 1,
 593                 .pin = 4,
 594                 .reg = 0x418,
 595                 .bit = 8,
 596                 .mask = 0x3
 597         }, {
 598                 .num = 1,
 599                 .pin = 5,
 600                 .reg = 0x418,
 601                 .bit = 10,
 602                 .mask = 0x3
 603         }, {
 604                 .num = 1,
 605                 .pin = 6,
 606                 .reg = 0x418,
 607                 .bit = 12,
 608                 .mask = 0x3
 609         }, {
 610                 .num = 1,
 611                 .pin = 7,
 612                 .reg = 0x418,
 613                 .bit = 14,
 614                 .mask = 0x3
 615         }, {
 616                 .num = 1,
 617                 .pin = 8,
 618                 .reg = 0x41c,
 619                 .bit = 0,
 620                 .mask = 0x3
 621         }, {
 622                 .num = 1,
 623                 .pin = 9,
 624                 .reg = 0x41c,
 625                 .bit = 2,
 626                 .mask = 0x3
 627         },
 628 };
 629
 630 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 631         {
 632                 .num = 2,
 633                 .pin = 20,
 634                 .reg = 0xe8,
 635                 .bit = 0,
 636                 .mask = 0x7
 637         }, {
 638                 .num = 2,
 639                 .pin = 21,
 640                 .reg = 0xe8,
 641                 .bit = 4,
 642                 .mask = 0x7
 643         }, {
 644                 .num = 2,
 645                 .pin = 22,
 646                 .reg = 0xe8,
 647                 .bit = 8,
 648                 .mask = 0x7
 649         }, {
 650                 .num = 2,
 651                 .pin = 23,
 652                 .reg = 0xe8,
 653                 .bit = 12,
 654                 .mask = 0x7
 655         }, {
 656                 .num = 2,
 657                 .pin = 24,
 658                 .reg = 0xd4,
 659                 .bit = 12,
 660                 .mask = 0x7
 661         },
 662 };
 663
 664 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
 665         {
 666                 .num = 1,
 667                 .pin = 14,
 668                 .reg = 0x28,
 669                 .bit = 12,
 670                 .mask = 0xf
 671         }, {
 672                 .num = 1,
 673                 .pin = 15,
 674                 .reg = 0x2c,
 675                 .bit = 0,
 676                 .mask = 0x3
 677         }, {
 678                 .num = 1,
 679                 .pin = 18,
 680                 .reg = 0x30,
 681                 .bit = 4,
 682                 .mask = 0xf
 683         }, {
 684                 .num = 1,
 685                 .pin = 19,
 686                 .reg = 0x30,
 687                 .bit = 8,
 688                 .mask = 0xf
 689         }, {
 690                 .num = 1,
 691                 .pin = 20,
 692                 .reg = 0x30,
 693                 .bit = 12,
 694                 .mask = 0xf
 695         }, {
 696                 .num = 1,
 697                 .pin = 21,
 698                 .reg = 0x34,
 699                 .bit = 0,
 700                 .mask = 0xf
 701         }, {
 702                 .num = 1,
 703                 .pin = 22,
 704                 .reg = 0x34,
 705                 .bit = 4,
 706                 .mask = 0xf
 707         }, {
 708                 .num = 1,
 709                 .pin = 23,
 710                 .reg = 0x34,
 711                 .bit = 8,
 712                 .mask = 0xf
 713         }, {
 714                 .num = 3,
 715                 .pin = 12,
 716                 .reg = 0x68,
 717                 .bit = 8,
 718                 .mask = 0xf
 719         }, {
 720                 .num = 3,
 721                 .pin = 13,
 722                 .reg = 0x68,
 723                 .bit = 12,
 724                 .mask = 0xf
 725         }, {
 726                 .num = 2,
 727                 .pin = 2,
 728                 .reg = 0x608,
 729                 .bit = 0,
 730                 .mask = 0x7
 731         }, {
 732                 .num = 2,
 733                 .pin = 3,
 734                 .reg = 0x608,
 735                 .bit = 4,
 736                 .mask = 0x7
 737         }, {
 738                 .num = 2,
 739                 .pin = 16,
 740                 .reg = 0x610,
 741                 .bit = 8,
 742                 .mask = 0x7
 743         }, {
 744                 .num = 3,
 745                 .pin = 10,
 746                 .reg = 0x610,
 747                 .bit = 0,
 748                 .mask = 0x7
 749         }, {
 750                 .num = 3,
 751                 .pin = 11,
 752                 .reg = 0x610,
 753                 .bit = 4,
 754                 .mask = 0x7
 755         },
 756 };
 757
 758 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 759         {
 760                 .num = 2,
 761                 .pin = 12,
 762                 .reg = 0x24,
 763                 .bit = 8,
 764                 .mask = 0x3
 765         }, {
 766                 .num = 2,
 767                 .pin = 15,
 768                 .reg = 0x28,
 769                 .bit = 0,
 770                 .mask = 0x7
 771         }, {
 772                 .num = 2,
 773                 .pin = 23,
 774                 .reg = 0x30,
 775                 .bit = 14,
 776                 .mask = 0x3
 777         },
 778 };
 779
 780 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 781                                       int *reg, u8 *bit, int *mask)
 782 {
 783         struct rockchip_pinctrl *info = bank->drvdata;
 784         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 785         struct rockchip_mux_recalced_data *data;
 786         int i;
 787
 788         for (i = 0; i < ctrl->niomux_recalced; i++) {
 789                 data = &ctrl->iomux_recalced[i];
 790                 if (data->num == bank->bank_num &&
 791                     data->pin == pin)
 792                         break;
 793         }
 794
 795         if (i >= ctrl->niomux_recalced)
 796                 return;
 797
 798         *reg = data->reg;
 799         *mask = data->mask;
 800         *bit = data->bit;
 801 }
 802
 803 static struct rockchip_mux_route_data px30_mux_route_data[] = {
 804         {
 805                 /* cif-d2m0 */
 806                 .bank_num = 2,
 807                 .pin = 0,
 808                 .func = 1,
 809                 .route_offset = 0x184,
 810                 .route_val = BIT(16 + 7),
 811         }, {
 812                 /* cif-d2m1 */
 813                 .bank_num = 3,
 814                 .pin = 3,
 815                 .func = 3,
 816                 .route_offset = 0x184,
 817                 .route_val = BIT(16 + 7) | BIT(7),
 818         }, {
 819                 /* pdm-m0 */
 820                 .bank_num = 3,
 821                 .pin = 22,
 822                 .func = 2,
 823                 .route_offset = 0x184,
 824                 .route_val = BIT(16 + 8),
 825         }, {
 826                 /* pdm-m1 */
 827                 .bank_num = 2,
 828                 .pin = 22,
 829                 .func = 1,
 830                 .route_offset = 0x184,
 831                 .route_val = BIT(16 + 8) | BIT(8),
 832         }, {
 833                 /* uart2-rxm0 */
 834                 .bank_num = 1,
 835                 .pin = 27,
 836                 .func = 2,
 837                 .route_offset = 0x184,
 838                 .route_val = BIT(16 + 10),
 839         }, {
 840                 /* uart2-rxm1 */
 841                 .bank_num = 2,
 842                 .pin = 14,
 843                 .func = 2,
 844                 .route_offset = 0x184,
 845                 .route_val = BIT(16 + 10) | BIT(10),
 846         }, {
 847                 /* uart3-rxm0 */
 848                 .bank_num = 0,
 849                 .pin = 17,
 850                 .func = 2,
 851                 .route_offset = 0x184,
 852                 .route_val = BIT(16 + 9),
 853         }, {
 854                 /* uart3-rxm1 */
 855                 .bank_num = 1,
 856                 .pin = 15,
 857                 .func = 2,
 858                 .route_offset = 0x184,
 859                 .route_val = BIT(16 + 9) | BIT(9),
 860         },
 861 };
 862
 863 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 864         {
 865                 /* spi-0 */
 866                 .bank_num = 1,
 867                 .pin = 10,
 868                 .func = 1,
 869                 .route_offset = 0x144,
 870                 .route_val = BIT(16 + 3) | BIT(16 + 4),
 871         }, {
 872                 /* spi-1 */
 873                 .bank_num = 1,
 874                 .pin = 27,
 875                 .func = 3,
 876                 .route_offset = 0x144,
 877                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
 878         }, {
 879                 /* spi-2 */
 880                 .bank_num = 0,
 881                 .pin = 13,
 882                 .func = 2,
 883                 .route_offset = 0x144,
 884                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
 885         }, {
 886                 /* i2s-0 */
 887                 .bank_num = 1,
 888                 .pin = 5,
 889                 .func = 1,
 890                 .route_offset = 0x144,
 891                 .route_val = BIT(16 + 5),
 892         }, {
 893                 /* i2s-1 */
 894                 .bank_num = 0,
 895                 .pin = 14,
 896                 .func = 1,
 897                 .route_offset = 0x144,
 898                 .route_val = BIT(16 + 5) | BIT(5),
 899         }, {
 900                 /* emmc-0 */
 901                 .bank_num = 1,
 902                 .pin = 22,
 903                 .func = 2,
 904                 .route_offset = 0x144,
 905                 .route_val = BIT(16 + 6),
 906         }, {
 907                 /* emmc-1 */
 908                 .bank_num = 2,
 909                 .pin = 4,
 910                 .func = 2,
 911                 .route_offset = 0x144,
 912                 .route_val = BIT(16 + 6) | BIT(6),
 913         },
 914 };
 915
 916 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
 917         {
 918                 /* non-iomuxed emmc/flash pins on flash-dqs */
 919                 .bank_num = 0,
 920                 .pin = 24,
 921                 .func = 1,
 922                 .route_location = ROCKCHIP_ROUTE_GRF,
 923                 .route_offset = 0xa0,
 924                 .route_val = BIT(16 + 11),
 925         }, {
 926                 /* non-iomuxed emmc/flash pins on emmc-clk */
 927                 .bank_num = 0,
 928                 .pin = 24,
 929                 .func = 2,
 930                 .route_location = ROCKCHIP_ROUTE_GRF,
 931                 .route_offset = 0xa0,
 932                 .route_val = BIT(16 + 11) | BIT(11),
 933         },
 934 };
 935
 936 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 937         {
 938                 /* pwm0-0 */
 939                 .bank_num = 0,
 940                 .pin = 26,
 941                 .func = 1,
 942                 .route_offset = 0x50,
 943                 .route_val = BIT(16),
 944         }, {
 945                 /* pwm0-1 */
 946                 .bank_num = 3,
 947                 .pin = 21,
 948                 .func = 1,
 949                 .route_offset = 0x50,
 950                 .route_val = BIT(16) | BIT(0),
 951         }, {
 952                 /* pwm1-0 */
 953                 .bank_num = 0,
 954                 .pin = 27,
 955                 .func = 1,
 956                 .route_offset = 0x50,
 957                 .route_val = BIT(16 + 1),
 958         }, {
 959                 /* pwm1-1 */
 960                 .bank_num = 0,
 961                 .pin = 30,
 962                 .func = 2,
 963                 .route_offset = 0x50,
 964                 .route_val = BIT(16 + 1) | BIT(1),
 965         }, {
 966                 /* pwm2-0 */
 967                 .bank_num = 0,
 968                 .pin = 28,
 969                 .func = 1,
 970                 .route_offset = 0x50,
 971                 .route_val = BIT(16 + 2),
 972         }, {
 973                 /* pwm2-1 */
 974                 .bank_num = 1,
 975                 .pin = 12,
 976                 .func = 2,
 977                 .route_offset = 0x50,
 978                 .route_val = BIT(16 + 2) | BIT(2),
 979         }, {
 980                 /* pwm3-0 */
 981                 .bank_num = 3,
 982                 .pin = 26,
 983                 .func = 1,
 984                 .route_offset = 0x50,
 985                 .route_val = BIT(16 + 3),
 986         }, {
 987                 /* pwm3-1 */
 988                 .bank_num = 1,
 989                 .pin = 11,
 990                 .func = 2,
 991                 .route_offset = 0x50,
 992                 .route_val = BIT(16 + 3) | BIT(3),
 993         }, {
 994                 /* sdio-0_d0 */
 995                 .bank_num = 1,
 996                 .pin = 1,
 997                 .func = 1,
 998                 .route_offset = 0x50,
 999                 .route_val = BIT(16 + 4),
1000         }, {
1001                 /* sdio-1_d0 */
1002                 .bank_num = 3,
1003                 .pin = 2,
1004                 .func = 1,
1005                 .route_offset = 0x50,
1006                 .route_val = BIT(16 + 4) | BIT(4),
1007         }, {
1008                 /* spi-0_rx */
1009                 .bank_num = 0,
1010                 .pin = 13,
1011                 .func = 2,
1012                 .route_offset = 0x50,
1013                 .route_val = BIT(16 + 5),
1014         }, {
1015                 /* spi-1_rx */
1016                 .bank_num = 2,
1017                 .pin = 0,
1018                 .func = 2,
1019                 .route_offset = 0x50,
1020                 .route_val = BIT(16 + 5) | BIT(5),
1021         }, {
1022                 /* emmc-0_cmd */
1023                 .bank_num = 1,
1024                 .pin = 22,
1025                 .func = 2,
1026                 .route_offset = 0x50,
1027                 .route_val = BIT(16 + 7),
1028         }, {
1029                 /* emmc-1_cmd */
1030                 .bank_num = 2,
1031                 .pin = 4,
1032                 .func = 2,
1033                 .route_offset = 0x50,
1034                 .route_val = BIT(16 + 7) | BIT(7),
1035         }, {
1036                 /* uart2-0_rx */
1037                 .bank_num = 1,
1038                 .pin = 19,
1039                 .func = 2,
1040                 .route_offset = 0x50,
1041                 .route_val = BIT(16 + 8),
1042         }, {
1043                 /* uart2-1_rx */
1044                 .bank_num = 1,
1045                 .pin = 10,
1046                 .func = 2,
1047                 .route_offset = 0x50,
1048                 .route_val = BIT(16 + 8) | BIT(8),
1049         }, {
1050                 /* uart1-0_rx */
1051                 .bank_num = 1,
1052                 .pin = 10,
1053                 .func = 1,
1054                 .route_offset = 0x50,
1055                 .route_val = BIT(16 + 11),
1056         }, {
1057                 /* uart1-1_rx */
1058                 .bank_num = 3,
1059                 .pin = 13,
1060                 .func = 1,
1061                 .route_offset = 0x50,
1062                 .route_val = BIT(16 + 11) | BIT(11),
1063         },
1064 };
1065
1066 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
1067         {
1068                 /* edphdmi_cecinoutt1 */
1069                 .bank_num = 7,
1070                 .pin = 16,
1071                 .func = 2,
1072                 .route_offset = 0x264,
1073                 .route_val = BIT(16 + 12) | BIT(12),
1074         }, {
1075                 /* edphdmi_cecinout */
1076                 .bank_num = 7,
1077                 .pin = 23,
1078                 .func = 4,
1079                 .route_offset = 0x264,
1080                 .route_val = BIT(16 + 12),
1081         },
1082 };
1083
1084 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
1085         {
1086                 /* rtc_clk */
1087                 .bank_num = 0,
1088                 .pin = 19,
1089                 .func = 1,
1090                 .route_offset = 0x314,
1091                 .route_val = BIT(16 + 0) | BIT(0),
1092         }, {
1093                 /* uart2_rxm0 */
1094                 .bank_num = 1,
1095                 .pin = 22,
1096                 .func = 2,
1097                 .route_offset = 0x314,
1098                 .route_val = BIT(16 + 2) | BIT(16 + 3),
1099         }, {
1100                 /* uart2_rxm1 */
1101                 .bank_num = 4,
1102                 .pin = 26,
1103                 .func = 2,
1104                 .route_offset = 0x314,
1105                 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
1106         }, {
1107                 /* i2c3_sdam0 */
1108                 .bank_num = 0,
1109                 .pin = 15,
1110                 .func = 2,
1111                 .route_offset = 0x608,
1112                 .route_val = BIT(16 + 8) | BIT(16 + 9),
1113         }, {
1114                 /* i2c3_sdam1 */
1115                 .bank_num = 3,
1116                 .pin = 12,
1117                 .func = 2,
1118                 .route_offset = 0x608,
1119                 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
1120         }, {
1121                 /* i2c3_sdam2 */
1122                 .bank_num = 2,
1123                 .pin = 0,
1124                 .func = 3,
1125                 .route_offset = 0x608,
1126                 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
1127         }, {
1128                 /* i2s-8ch-1-sclktxm0 */
1129                 .bank_num = 1,
1130                 .pin = 3,
1131                 .func = 2,
1132                 .route_offset = 0x308,
1133                 .route_val = BIT(16 + 3),
1134         }, {
1135                 /* i2s-8ch-1-sclkrxm0 */
1136                 .bank_num = 1,
1137                 .pin = 4,
1138                 .func = 2,
1139                 .route_offset = 0x308,
1140                 .route_val = BIT(16 + 3),
1141         }, {
1142                 /* i2s-8ch-1-sclktxm1 */
1143                 .bank_num = 1,
1144                 .pin = 13,
1145                 .func = 2,
1146                 .route_offset = 0x308,
1147                 .route_val = BIT(16 + 3) | BIT(3),
1148         }, {
1149                 /* i2s-8ch-1-sclkrxm1 */
1150                 .bank_num = 1,
1151                 .pin = 14,
1152                 .func = 2,
1153                 .route_offset = 0x308,
1154                 .route_val = BIT(16 + 3) | BIT(3),
1155         }, {
1156                 /* pdm-clkm0 */
1157                 .bank_num = 1,
1158                 .pin = 4,
1159                 .func = 3,
1160                 .route_offset = 0x308,
1161                 .route_val =  BIT(16 + 12) | BIT(16 + 13),
1162         }, {
1163                 /* pdm-clkm1 */
1164                 .bank_num = 1,
1165                 .pin = 14,
1166                 .func = 4,
1167                 .route_offset = 0x308,
1168                 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1169         }, {
1170                 /* pdm-clkm2 */
1171                 .bank_num = 2,
1172                 .pin = 6,
1173                 .func = 2,
1174                 .route_offset = 0x308,
1175                 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1176         }, {
1177                 /* pdm-clkm-m2 */
1178                 .bank_num = 2,
1179                 .pin = 4,
1180                 .func = 3,
1181                 .route_offset = 0x600,
1182                 .route_val = BIT(16 + 2) | BIT(2),
1183         }, {
1184                 /* spi1_miso */
1185                 .bank_num = 3,
1186                 .pin = 10,
1187                 .func = 3,
1188                 .route_offset = 0x314,
1189                 .route_val = BIT(16 + 9),
1190         }, {
1191                 /* spi1_miso_m1 */
1192                 .bank_num = 2,
1193                 .pin = 4,
1194                 .func = 2,
1195                 .route_offset = 0x314,
1196                 .route_val = BIT(16 + 9) | BIT(9),
1197         }, {
1198                 /* owire_m0 */
1199                 .bank_num = 0,
1200                 .pin = 11,
1201                 .func = 3,
1202                 .route_offset = 0x314,
1203                 .route_val = BIT(16 + 10) | BIT(16 + 11),
1204         }, {
1205                 /* owire_m1 */
1206                 .bank_num = 1,
1207                 .pin = 22,
1208                 .func = 7,
1209                 .route_offset = 0x314,
1210                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1211         }, {
1212                 /* owire_m2 */
1213                 .bank_num = 2,
1214                 .pin = 2,
1215                 .func = 5,
1216                 .route_offset = 0x314,
1217                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1218         }, {
1219                 /* can_rxd_m0 */
1220                 .bank_num = 0,
1221                 .pin = 11,
1222                 .func = 2,
1223                 .route_offset = 0x314,
1224                 .route_val = BIT(16 + 12) | BIT(16 + 13),
1225         }, {
1226                 /* can_rxd_m1 */
1227                 .bank_num = 1,
1228                 .pin = 22,
1229                 .func = 5,
1230                 .route_offset = 0x314,
1231                 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1232         }, {
1233                 /* can_rxd_m2 */
1234                 .bank_num = 2,
1235                 .pin = 2,
1236                 .func = 4,
1237                 .route_offset = 0x314,
1238                 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1239         }, {
1240                 /* mac_rxd0_m0 */
1241                 .bank_num = 1,
1242                 .pin = 20,
1243                 .func = 3,
1244                 .route_offset = 0x314,
1245                 .route_val = BIT(16 + 14),
1246         }, {
1247                 /* mac_rxd0_m1 */
1248                 .bank_num = 4,
1249                 .pin = 2,
1250                 .func = 2,
1251                 .route_offset = 0x314,
1252                 .route_val = BIT(16 + 14) | BIT(14),
1253         }, {
1254                 /* uart3_rx */
1255                 .bank_num = 3,
1256                 .pin = 12,
1257                 .func = 4,
1258                 .route_offset = 0x314,
1259                 .route_val = BIT(16 + 15),
1260         }, {
1261                 /* uart3_rx_m1 */
1262                 .bank_num = 0,
1263                 .pin = 17,
1264                 .func = 3,
1265                 .route_offset = 0x314,
1266                 .route_val = BIT(16 + 15) | BIT(15),
1267         },
1268 };
1269
1270 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
1271         {
1272                 /* uart2dbg_rxm0 */
1273                 .bank_num = 1,
1274                 .pin = 1,
1275                 .func = 2,
1276                 .route_offset = 0x50,
1277                 .route_val = BIT(16) | BIT(16 + 1),
1278         }, {
1279                 /* uart2dbg_rxm1 */
1280                 .bank_num = 2,
1281                 .pin = 1,
1282                 .func = 1,
1283                 .route_offset = 0x50,
1284                 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1285         }, {
1286                 /* gmac-m1_rxd0 */
1287                 .bank_num = 1,
1288                 .pin = 11,
1289                 .func = 2,
1290                 .route_offset = 0x50,
1291                 .route_val = BIT(16 + 2) | BIT(2),
1292         }, {
1293                 /* gmac-m1-optimized_rxd3 */
1294                 .bank_num = 1,
1295                 .pin = 14,
1296                 .func = 2,
1297                 .route_offset = 0x50,
1298                 .route_val = BIT(16 + 10) | BIT(10),
1299         }, {
1300                 /* pdm_sdi0m0 */
1301                 .bank_num = 2,
1302                 .pin = 19,
1303                 .func = 2,
1304                 .route_offset = 0x50,
1305                 .route_val = BIT(16 + 3),
1306         }, {
1307                 /* pdm_sdi0m1 */
1308                 .bank_num = 1,
1309                 .pin = 23,
1310                 .func = 3,
1311                 .route_offset = 0x50,
1312                 .route_val =  BIT(16 + 3) | BIT(3),
1313         }, {
1314                 /* spi_rxdm2 */
1315                 .bank_num = 3,
1316                 .pin = 2,
1317                 .func = 4,
1318                 .route_offset = 0x50,
1319                 .route_val =  BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1320         }, {
1321                 /* i2s2_sdim0 */
1322                 .bank_num = 1,
1323                 .pin = 24,
1324                 .func = 1,
1325                 .route_offset = 0x50,
1326                 .route_val = BIT(16 + 6),
1327         }, {
1328                 /* i2s2_sdim1 */
1329                 .bank_num = 3,
1330                 .pin = 2,
1331                 .func = 6,
1332                 .route_offset = 0x50,
1333                 .route_val =  BIT(16 + 6) | BIT(6),
1334         }, {
1335                 /* card_iom1 */
1336                 .bank_num = 2,
1337                 .pin = 22,
1338                 .func = 3,
1339                 .route_offset = 0x50,
1340                 .route_val =  BIT(16 + 7) | BIT(7),
1341         }, {
1342                 /* tsp_d5m1 */
1343                 .bank_num = 2,
1344                 .pin = 16,
1345                 .func = 3,
1346                 .route_offset = 0x50,
1347                 .route_val =  BIT(16 + 8) | BIT(8),
1348         }, {
1349                 /* cif_data5m1 */
1350                 .bank_num = 2,
1351                 .pin = 16,
1352                 .func = 4,
1353                 .route_offset = 0x50,
1354                 .route_val =  BIT(16 + 9) | BIT(9),
1355         },
1356 };
1357
1358 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1359         {
1360                 /* uart2dbga_rx */
1361                 .bank_num = 4,
1362                 .pin = 8,
1363                 .func = 2,
1364                 .route_offset = 0xe21c,
1365                 .route_val = BIT(16 + 10) | BIT(16 + 11),
1366         }, {
1367                 /* uart2dbgb_rx */
1368                 .bank_num = 4,
1369                 .pin = 16,
1370                 .func = 2,
1371                 .route_offset = 0xe21c,
1372                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1373         }, {
1374                 /* uart2dbgc_rx */
1375                 .bank_num = 4,
1376                 .pin = 19,
1377                 .func = 1,
1378                 .route_offset = 0xe21c,
1379                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1380         }, {
1381                 /* pcie_clkreqn */
1382                 .bank_num = 2,
1383                 .pin = 26,
1384                 .func = 2,
1385                 .route_offset = 0xe21c,
1386                 .route_val = BIT(16 + 14),
1387         }, {
1388                 /* pcie_clkreqnb */
1389                 .bank_num = 4,
1390                 .pin = 24,
1391                 .func = 1,
1392                 .route_offset = 0xe21c,
1393                 .route_val = BIT(16 + 14) | BIT(14),
1394         },
1395 };
1396
1397 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1398                                    int mux, u32 *loc, u32 *reg, u32 *value)
1399 {
1400         struct rockchip_pinctrl *info = bank->drvdata;
1401         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1402         struct rockchip_mux_route_data *data;
1403         int i;
1404
1405         for (i = 0; i < ctrl->niomux_routes; i++) {
1406                 data = &ctrl->iomux_routes[i];
1407                 if ((data->bank_num == bank->bank_num) &&
1408                     (data->pin == pin) && (data->func == mux))
1409                         break;
1410         }
1411
1412         if (i >= ctrl->niomux_routes)
1413                 return false;
1414
1415         *loc = data->route_location;
1416         *reg = data->route_offset;
1417         *value = data->route_val;
1418
1419         return true;
1420 }
1421
1422 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1423 {
1424         struct rockchip_pinctrl *info = bank->drvdata;
1425         int iomux_num = (pin / 8);
1426         struct regmap *regmap;
1427         unsigned int val;
1428         int reg, ret, mask, mux_type;
1429         u8 bit;
1430
1431         if (iomux_num > 3)
1432                 return -EINVAL;
1433
1434         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1435                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1436                 return -EINVAL;
1437         }
1438
1439         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1440                 return RK_FUNC_GPIO;
1441
1442         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1443                                 ? info->regmap_pmu : info->regmap_base;
1444
1445         /* get basic quadrupel of mux registers and the correct reg inside */
1446         mux_type = bank->iomux[iomux_num].type;
1447         reg = bank->iomux[iomux_num].offset;
1448         if (mux_type & IOMUX_WIDTH_4BIT) {
1449                 if ((pin % 8) >= 4)
1450                         reg += 0x4;
1451                 bit = (pin % 4) * 4;
1452                 mask = 0xf;
1453         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1454                 if ((pin % 8) >= 5)
1455                         reg += 0x4;
1456                 bit = (pin % 8 % 5) * 3;
1457                 mask = 0x7;
1458         } else {
1459                 bit = (pin % 8) * 2;
1460                 mask = 0x3;
1461         }
1462
1463         if (bank->recalced_mask & BIT(pin))
1464                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1465
1466         ret = regmap_read(regmap, reg, &val);
1467         if (ret)
1468                 return ret;
1469
1470         return ((val >> bit) & mask);
1471 }
1472
1473 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1474                                int pin, int mux)
1475 {
1476         struct rockchip_pinctrl *info = bank->drvdata;
1477         int iomux_num = (pin / 8);
1478
1479         if (iomux_num > 3)
1480                 return -EINVAL;
1481
1482         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1483                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1484                 return -EINVAL;
1485         }
1486
1487         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1488                 if (mux != RK_FUNC_GPIO) {
1489                         dev_err(info->dev,
1490                                 "pin %d only supports a gpio mux\n", pin);
1491                         return -ENOTSUPP;
1492                 }
1493         }
1494
1495         return 0;
1496 }
1497
1498 /*
1499  * Set a new mux function for a pin.
1500  *
1501  * The register is divided into the upper and lower 16 bit. When changing
1502  * a value, the previous register value is not read and changed. Instead
1503  * it seems the changed bits are marked in the upper 16 bit, while the
1504  * changed value gets set in the same offset in the lower 16 bit.
1505  * All pin settings seem to be 2 bit wide in both the upper and lower
1506  * parts.
1507  * @bank: pin bank to change
1508  * @pin: pin to change
1509  * @mux: new mux function to set
1510  */
1511 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1512 {
1513         struct rockchip_pinctrl *info = bank->drvdata;
1514         int iomux_num = (pin / 8);
1515         struct regmap *regmap;
1516         int reg, ret, mask, mux_type;
1517         u8 bit;
1518         u32 data, rmask, route_location, route_reg, route_val;
1519
1520         ret = rockchip_verify_mux(bank, pin, mux);
1521         if (ret < 0)
1522                 return ret;
1523
1524         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1525                 return 0;
1526
1527         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1528                                                 bank->bank_num, pin, mux);
1529
1530         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1531                                 ? info->regmap_pmu : info->regmap_base;
1532
1533         /* get basic quadrupel of mux registers and the correct reg inside */
1534         mux_type = bank->iomux[iomux_num].type;
1535         reg = bank->iomux[iomux_num].offset;
1536         if (mux_type & IOMUX_WIDTH_4BIT) {
1537                 if ((pin % 8) >= 4)
1538                         reg += 0x4;
1539                 bit = (pin % 4) * 4;
1540                 mask = 0xf;
1541         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1542                 if ((pin % 8) >= 5)
1543                         reg += 0x4;
1544                 bit = (pin % 8 % 5) * 3;
1545                 mask = 0x7;
1546         } else {
1547                 bit = (pin % 8) * 2;
1548                 mask = 0x3;
1549         }
1550
1551         if (bank->recalced_mask & BIT(pin))
1552                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1553
1554         if (bank->route_mask & BIT(pin)) {
1555                 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1556                                            &route_reg, &route_val)) {
1557                         struct regmap *route_regmap = regmap;
1558
1559                         /* handle special locations */
1560                         switch (route_location) {
1561                         case ROCKCHIP_ROUTE_PMU:
1562                                 route_regmap = info->regmap_pmu;
1563                                 break;
1564                         case ROCKCHIP_ROUTE_GRF:
1565                                 route_regmap = info->regmap_base;
1566                                 break;
1567                         }
1568
1569                         ret = regmap_write(route_regmap, route_reg, route_val);
1570                         if (ret)
1571                                 return ret;
1572                 }
1573         }
1574
1575         data = (mask << (bit + 16));
1576         rmask = data | (data >> 16);
1577         data |= (mux & mask) << bit;
1578         ret = regmap_update_bits(regmap, reg, rmask, data);
1579
1580         return ret;
1581 }
1582
1583 #define PX30_PULL_PMU_OFFSET            0x10
1584 #define PX30_PULL_GRF_OFFSET            0x60
1585 #define PX30_PULL_BITS_PER_PIN          2
1586 #define PX30_PULL_PINS_PER_REG          8
1587 #define PX30_PULL_BANK_STRIDE           16
1588
1589 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1590                                        int pin_num, struct regmap **regmap,
1591                                        int *reg, u8 *bit)
1592 {
1593         struct rockchip_pinctrl *info = bank->drvdata;
1594
1595         /* The first 32 pins of the first bank are located in PMU */
1596         if (bank->bank_num == 0) {
1597                 *regmap = info->regmap_pmu;
1598                 *reg = PX30_PULL_PMU_OFFSET;
1599         } else {
1600                 *regmap = info->regmap_base;
1601                 *reg = PX30_PULL_GRF_OFFSET;
1602
1603                 /* correct the offset, as we're starting with the 2nd bank */
1604                 *reg -= 0x10;
1605                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1606         }
1607
1608         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1609         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1610         *bit *= PX30_PULL_BITS_PER_PIN;
1611 }
1612
1613 #define PX30_DRV_PMU_OFFSET             0x20
1614 #define PX30_DRV_GRF_OFFSET             0xf0
1615 #define PX30_DRV_BITS_PER_PIN           2
1616 #define PX30_DRV_PINS_PER_REG           8
1617 #define PX30_DRV_BANK_STRIDE            16
1618
1619 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1620                                       int pin_num, struct regmap **regmap,
1621                                       int *reg, u8 *bit)
1622 {
1623         struct rockchip_pinctrl *info = bank->drvdata;
1624
1625         /* The first 32 pins of the first bank are located in PMU */
1626         if (bank->bank_num == 0) {
1627                 *regmap = info->regmap_pmu;
1628                 *reg = PX30_DRV_PMU_OFFSET;
1629         } else {
1630                 *regmap = info->regmap_base;
1631                 *reg = PX30_DRV_GRF_OFFSET;
1632
1633                 /* correct the offset, as we're starting with the 2nd bank */
1634                 *reg -= 0x10;
1635                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1636         }
1637
1638         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1639         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1640         *bit *= PX30_DRV_BITS_PER_PIN;
1641 }
1642
1643 #define PX30_SCHMITT_PMU_OFFSET                 0x38
1644 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
1645 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
1646 #define PX30_SCHMITT_BANK_STRIDE                16
1647 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
1648
1649 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1650                                          int pin_num,
1651                                          struct regmap **regmap,
1652                                          int *reg, u8 *bit)
1653 {
1654         struct rockchip_pinctrl *info = bank->drvdata;
1655         int pins_per_reg;
1656
1657         if (bank->bank_num == 0) {
1658                 *regmap = info->regmap_pmu;
1659                 *reg = PX30_SCHMITT_PMU_OFFSET;
1660                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1661         } else {
1662                 *regmap = info->regmap_base;
1663                 *reg = PX30_SCHMITT_GRF_OFFSET;
1664                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1665                 *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1666         }
1667
1668         *reg += ((pin_num / pins_per_reg) * 4);
1669         *bit = pin_num % pins_per_reg;
1670
1671         return 0;
1672 }
1673
1674 #define RV1108_PULL_PMU_OFFSET          0x10
1675 #define RV1108_PULL_OFFSET              0x110
1676 #define RV1108_PULL_PINS_PER_REG        8
1677 #define RV1108_PULL_BITS_PER_PIN        2
1678 #define RV1108_PULL_BANK_STRIDE         16
1679
1680 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1681                                          int pin_num, struct regmap **regmap,
1682                                          int *reg, u8 *bit)
1683 {
1684         struct rockchip_pinctrl *info = bank->drvdata;
1685
1686         /* The first 24 pins of the first bank are located in PMU */
1687         if (bank->bank_num == 0) {
1688                 *regmap = info->regmap_pmu;
1689                 *reg = RV1108_PULL_PMU_OFFSET;
1690         } else {
1691                 *reg = RV1108_PULL_OFFSET;
1692                 *regmap = info->regmap_base;
1693                 /* correct the offset, as we're starting with the 2nd bank */
1694                 *reg -= 0x10;
1695                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1696         }
1697
1698         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1699         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1700         *bit *= RV1108_PULL_BITS_PER_PIN;
1701 }
1702
1703 #define RV1108_DRV_PMU_OFFSET           0x20
1704 #define RV1108_DRV_GRF_OFFSET           0x210
1705 #define RV1108_DRV_BITS_PER_PIN         2
1706 #define RV1108_DRV_PINS_PER_REG         8
1707 #define RV1108_DRV_BANK_STRIDE          16
1708
1709 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1710                                         int pin_num, struct regmap **regmap,
1711                                         int *reg, u8 *bit)
1712 {
1713         struct rockchip_pinctrl *info = bank->drvdata;
1714
1715         /* The first 24 pins of the first bank are located in PMU */
1716         if (bank->bank_num == 0) {
1717                 *regmap = info->regmap_pmu;
1718                 *reg = RV1108_DRV_PMU_OFFSET;
1719         } else {
1720                 *regmap = info->regmap_base;
1721                 *reg = RV1108_DRV_GRF_OFFSET;
1722
1723                 /* correct the offset, as we're starting with the 2nd bank */
1724                 *reg -= 0x10;
1725                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1726         }
1727
1728         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1729         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1730         *bit *= RV1108_DRV_BITS_PER_PIN;
1731 }
1732
1733 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1734 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1735 #define RV1108_SCHMITT_BANK_STRIDE              8
1736 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1737 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1738
1739 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1740                                            int pin_num,
1741                                            struct regmap **regmap,
1742                                            int *reg, u8 *bit)
1743 {
1744         struct rockchip_pinctrl *info = bank->drvdata;
1745         int pins_per_reg;
1746
1747         if (bank->bank_num == 0) {
1748                 *regmap = info->regmap_pmu;
1749                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1750                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1751         } else {
1752                 *regmap = info->regmap_base;
1753                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1754                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1755                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1756         }
1757         *reg += ((pin_num / pins_per_reg) * 4);
1758         *bit = pin_num % pins_per_reg;
1759
1760         return 0;
1761 }
1762
1763 #define RK3308_SCHMITT_PINS_PER_REG             8
1764 #define RK3308_SCHMITT_BANK_STRIDE              16
1765 #define RK3308_SCHMITT_GRF_OFFSET               0x1a0
1766
1767 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1768                                     int pin_num, struct regmap **regmap,
1769                                     int *reg, u8 *bit)
1770 {
1771         struct rockchip_pinctrl *info = bank->drvdata;
1772
1773         *regmap = info->regmap_base;
1774         *reg = RK3308_SCHMITT_GRF_OFFSET;
1775
1776         *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1777         *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1778         *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1779
1780         return 0;
1781 }
1782
1783 #define RK2928_PULL_OFFSET              0x118
1784 #define RK2928_PULL_PINS_PER_REG        16
1785 #define RK2928_PULL_BANK_STRIDE         8
1786
1787 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1788                                     int pin_num, struct regmap **regmap,
1789                                     int *reg, u8 *bit)
1790 {
1791         struct rockchip_pinctrl *info = bank->drvdata;
1792
1793         *regmap = info->regmap_base;
1794         *reg = RK2928_PULL_OFFSET;
1795         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1796         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1797
1798         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1799 };
1800
1801 #define RK3128_PULL_OFFSET      0x118
1802
1803 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1804                                          int pin_num, struct regmap **regmap,
1805                                          int *reg, u8 *bit)
1806 {
1807         struct rockchip_pinctrl *info = bank->drvdata;
1808
1809         *regmap = info->regmap_base;
1810         *reg = RK3128_PULL_OFFSET;
1811         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1812         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1813
1814         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1815 }
1816
1817 #define RK3188_PULL_OFFSET              0x164
1818 #define RK3188_PULL_BITS_PER_PIN        2
1819 #define RK3188_PULL_PINS_PER_REG        8
1820 #define RK3188_PULL_BANK_STRIDE         16
1821 #define RK3188_PULL_PMU_OFFSET          0x64
1822
1823 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1824                                     int pin_num, struct regmap **regmap,
1825                                     int *reg, u8 *bit)
1826 {
1827         struct rockchip_pinctrl *info = bank->drvdata;
1828
1829         /* The first 12 pins of the first bank are located elsewhere */
1830         if (bank->bank_num == 0 && pin_num < 12) {
1831                 *regmap = info->regmap_pmu ? info->regmap_pmu
1832                                            : bank->regmap_pull;
1833                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1834                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1835                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1836                 *bit *= RK3188_PULL_BITS_PER_PIN;
1837         } else {
1838                 *regmap = info->regmap_pull ? info->regmap_pull
1839                                             : info->regmap_base;
1840                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1841
1842                 /* correct the offset, as it is the 2nd pull register */
1843                 *reg -= 4;
1844                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1845                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1846
1847                 /*
1848                  * The bits in these registers have an inverse ordering
1849                  * with the lowest pin being in bits 15:14 and the highest
1850                  * pin in bits 1:0
1851                  */
1852                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1853                 *bit *= RK3188_PULL_BITS_PER_PIN;
1854         }
1855 }
1856
1857 #define RK3288_PULL_OFFSET              0x140
1858 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1859                                     int pin_num, struct regmap **regmap,
1860                                     int *reg, u8 *bit)
1861 {
1862         struct rockchip_pinctrl *info = bank->drvdata;
1863
1864         /* The first 24 pins of the first bank are located in PMU */
1865         if (bank->bank_num == 0) {
1866                 *regmap = info->regmap_pmu;
1867                 *reg = RK3188_PULL_PMU_OFFSET;
1868
1869                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1870                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1871                 *bit *= RK3188_PULL_BITS_PER_PIN;
1872         } else {
1873                 *regmap = info->regmap_base;
1874                 *reg = RK3288_PULL_OFFSET;
1875
1876                 /* correct the offset, as we're starting with the 2nd bank */
1877                 *reg -= 0x10;
1878                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1879                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1880
1881                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1882                 *bit *= RK3188_PULL_BITS_PER_PIN;
1883         }
1884 }
1885
1886 #define RK3288_DRV_PMU_OFFSET           0x70
1887 #define RK3288_DRV_GRF_OFFSET           0x1c0
1888 #define RK3288_DRV_BITS_PER_PIN         2
1889 #define RK3288_DRV_PINS_PER_REG         8
1890 #define RK3288_DRV_BANK_STRIDE          16
1891
1892 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1893                                     int pin_num, struct regmap **regmap,
1894                                     int *reg, u8 *bit)
1895 {
1896         struct rockchip_pinctrl *info = bank->drvdata;
1897
1898         /* The first 24 pins of the first bank are located in PMU */
1899         if (bank->bank_num == 0) {
1900                 *regmap = info->regmap_pmu;
1901                 *reg = RK3288_DRV_PMU_OFFSET;
1902
1903                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1904                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1905                 *bit *= RK3288_DRV_BITS_PER_PIN;
1906         } else {
1907                 *regmap = info->regmap_base;
1908                 *reg = RK3288_DRV_GRF_OFFSET;
1909
1910                 /* correct the offset, as we're starting with the 2nd bank */
1911                 *reg -= 0x10;
1912                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1913                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1914
1915                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1916                 *bit *= RK3288_DRV_BITS_PER_PIN;
1917         }
1918 }
1919
1920 #define RK3228_PULL_OFFSET              0x100
1921
1922 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1923                                     int pin_num, struct regmap **regmap,
1924                                     int *reg, u8 *bit)
1925 {
1926         struct rockchip_pinctrl *info = bank->drvdata;
1927
1928         *regmap = info->regmap_base;
1929         *reg = RK3228_PULL_OFFSET;
1930         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1931         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1932
1933         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1934         *bit *= RK3188_PULL_BITS_PER_PIN;
1935 }
1936
1937 #define RK3228_DRV_GRF_OFFSET           0x200
1938
1939 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1940                                     int pin_num, struct regmap **regmap,
1941                                     int *reg, u8 *bit)
1942 {
1943         struct rockchip_pinctrl *info = bank->drvdata;
1944
1945         *regmap = info->regmap_base;
1946         *reg = RK3228_DRV_GRF_OFFSET;
1947         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1948         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1949
1950         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1951         *bit *= RK3288_DRV_BITS_PER_PIN;
1952 }
1953
1954 #define RK3308_PULL_OFFSET              0xa0
1955
1956 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1957                                     int pin_num, struct regmap **regmap,
1958                                     int *reg, u8 *bit)
1959 {
1960         struct rockchip_pinctrl *info = bank->drvdata;
1961
1962         *regmap = info->regmap_base;
1963         *reg = RK3308_PULL_OFFSET;
1964         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1965         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1966
1967         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1968         *bit *= RK3188_PULL_BITS_PER_PIN;
1969 }
1970
1971 #define RK3308_DRV_GRF_OFFSET           0x100
1972
1973 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1974                                     int pin_num, struct regmap **regmap,
1975                                     int *reg, u8 *bit)
1976 {
1977         struct rockchip_pinctrl *info = bank->drvdata;
1978
1979         *regmap = info->regmap_base;
1980         *reg = RK3308_DRV_GRF_OFFSET;
1981         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1982         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1983
1984         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1985         *bit *= RK3288_DRV_BITS_PER_PIN;
1986 }
1987
1988 #define RK3368_PULL_GRF_OFFSET          0x100
1989 #define RK3368_PULL_PMU_OFFSET          0x10
1990
1991 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1992                                     int pin_num, struct regmap **regmap,
1993                                     int *reg, u8 *bit)
1994 {
1995         struct rockchip_pinctrl *info = bank->drvdata;
1996
1997         /* The first 32 pins of the first bank are located in PMU */
1998         if (bank->bank_num == 0) {
1999                 *regmap = info->regmap_pmu;
2000                 *reg = RK3368_PULL_PMU_OFFSET;
2001
2002                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2003                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2004                 *bit *= RK3188_PULL_BITS_PER_PIN;
2005         } else {
2006                 *regmap = info->regmap_base;
2007                 *reg = RK3368_PULL_GRF_OFFSET;
2008
2009                 /* correct the offset, as we're starting with the 2nd bank */
2010                 *reg -= 0x10;
2011                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2012                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2013
2014                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2015                 *bit *= RK3188_PULL_BITS_PER_PIN;
2016         }
2017 }
2018
2019 #define RK3368_DRV_PMU_OFFSET           0x20
2020 #define RK3368_DRV_GRF_OFFSET           0x200
2021
2022 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2023                                     int pin_num, struct regmap **regmap,
2024                                     int *reg, u8 *bit)
2025 {
2026         struct rockchip_pinctrl *info = bank->drvdata;
2027
2028         /* The first 32 pins of the first bank are located in PMU */
2029         if (bank->bank_num == 0) {
2030                 *regmap = info->regmap_pmu;
2031                 *reg = RK3368_DRV_PMU_OFFSET;
2032
2033                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2034                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2035                 *bit *= RK3288_DRV_BITS_PER_PIN;
2036         } else {
2037                 *regmap = info->regmap_base;
2038                 *reg = RK3368_DRV_GRF_OFFSET;
2039
2040                 /* correct the offset, as we're starting with the 2nd bank */
2041                 *reg -= 0x10;
2042                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2043                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2044
2045                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2046                 *bit *= RK3288_DRV_BITS_PER_PIN;
2047         }
2048 }
2049
2050 #define RK3399_PULL_GRF_OFFSET          0xe040
2051 #define RK3399_PULL_PMU_OFFSET          0x40
2052 #define RK3399_DRV_3BITS_PER_PIN        3
2053
2054 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2055                                          int pin_num, struct regmap **regmap,
2056                                          int *reg, u8 *bit)
2057 {
2058         struct rockchip_pinctrl *info = bank->drvdata;
2059
2060         /* The bank0:16 and bank1:32 pins are located in PMU */
2061         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
2062                 *regmap = info->regmap_pmu;
2063                 *reg = RK3399_PULL_PMU_OFFSET;
2064
2065                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2066
2067                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2068                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2069                 *bit *= RK3188_PULL_BITS_PER_PIN;
2070         } else {
2071                 *regmap = info->regmap_base;
2072                 *reg = RK3399_PULL_GRF_OFFSET;
2073
2074                 /* correct the offset, as we're starting with the 3rd bank */
2075                 *reg -= 0x20;
2076                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2077                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2078
2079                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2080                 *bit *= RK3188_PULL_BITS_PER_PIN;
2081         }
2082 }
2083
2084 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2085                                         int pin_num, struct regmap **regmap,
2086                                         int *reg, u8 *bit)
2087 {
2088         struct rockchip_pinctrl *info = bank->drvdata;
2089         int drv_num = (pin_num / 8);
2090
2091         /*  The bank0:16 and bank1:32 pins are located in PMU */
2092         if ((bank->bank_num == 0) || (bank->bank_num == 1))
2093                 *regmap = info->regmap_pmu;
2094         else
2095                 *regmap = info->regmap_base;
2096
2097         *reg = bank->drv[drv_num].offset;
2098         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2099             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
2100                 *bit = (pin_num % 8) * 3;
2101         else
2102                 *bit = (pin_num % 8) * 2;
2103 }
2104
2105 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2106         { 2, 4, 8, 12, -1, -1, -1, -1 },
2107         { 3, 6, 9, 12, -1, -1, -1, -1 },
2108         { 5, 10, 15, 20, -1, -1, -1, -1 },
2109         { 4, 6, 8, 10, 12, 14, 16, 18 },
2110         { 4, 7, 10, 13, 16, 19, 22, 26 }
2111 };
2112
2113 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
2114                                      int pin_num)
2115 {
2116         struct rockchip_pinctrl *info = bank->drvdata;
2117         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2118         struct regmap *regmap;
2119         int reg, ret;
2120         u32 data, temp, rmask_bits;
2121         u8 bit;
2122         int drv_type = bank->drv[pin_num / 8].drv_type;
2123
2124         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2125
2126         switch (drv_type) {
2127         case DRV_TYPE_IO_1V8_3V0_AUTO:
2128         case DRV_TYPE_IO_3V3_ONLY:
2129                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2130                 switch (bit) {
2131                 case 0 ... 12:
2132                         /* regular case, nothing to do */
2133                         break;
2134                 case 15:
2135                         /*
2136                          * drive-strength offset is special, as it is
2137                          * spread over 2 registers
2138                          */
2139                         ret = regmap_read(regmap, reg, &data);
2140                         if (ret)
2141                                 return ret;
2142
2143                         ret = regmap_read(regmap, reg + 0x4, &temp);
2144                         if (ret)
2145                                 return ret;
2146
2147                         /*
2148                          * the bit data[15] contains bit 0 of the value
2149                          * while temp[1:0] contains bits 2 and 1
2150                          */
2151                         data >>= 15;
2152                         temp &= 0x3;
2153                         temp <<= 1;
2154                         data |= temp;
2155
2156                         return rockchip_perpin_drv_list[drv_type][data];
2157                 case 18 ... 21:
2158                         /* setting fully enclosed in the second register */
2159                         reg += 4;
2160                         bit -= 16;
2161                         break;
2162                 default:
2163                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2164                                 bit, drv_type);
2165                         return -EINVAL;
2166                 }
2167
2168                 break;
2169         case DRV_TYPE_IO_DEFAULT:
2170         case DRV_TYPE_IO_1V8_OR_3V0:
2171         case DRV_TYPE_IO_1V8_ONLY:
2172                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2173                 break;
2174         default:
2175                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2176                         drv_type);
2177                 return -EINVAL;
2178         }
2179
2180         ret = regmap_read(regmap, reg, &data);
2181         if (ret)
2182                 return ret;
2183
2184         data >>= bit;
2185         data &= (1 << rmask_bits) - 1;
2186
2187         return rockchip_perpin_drv_list[drv_type][data];
2188 }
2189
2190 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2191                                      int pin_num, int strength)
2192 {
2193         struct rockchip_pinctrl *info = bank->drvdata;
2194         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2195         struct regmap *regmap;
2196         int reg, ret, i;
2197         u32 data, rmask, rmask_bits, temp;
2198         u8 bit;
2199         int drv_type = bank->drv[pin_num / 8].drv_type;
2200
2201         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
2202                 bank->bank_num, pin_num, strength);
2203
2204         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2205
2206         ret = -EINVAL;
2207         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2208                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2209                         ret = i;
2210                         break;
2211                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2212                         ret = rockchip_perpin_drv_list[drv_type][i];
2213                         break;
2214                 }
2215         }
2216
2217         if (ret < 0) {
2218                 dev_err(info->dev, "unsupported driver strength %d\n",
2219                         strength);
2220                 return ret;
2221         }
2222
2223         switch (drv_type) {
2224         case DRV_TYPE_IO_1V8_3V0_AUTO:
2225         case DRV_TYPE_IO_3V3_ONLY:
2226                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2227                 switch (bit) {
2228                 case 0 ... 12:
2229                         /* regular case, nothing to do */
2230                         break;
2231                 case 15:
2232                         /*
2233                          * drive-strength offset is special, as it is spread
2234                          * over 2 registers, the bit data[15] contains bit 0
2235                          * of the value while temp[1:0] contains bits 2 and 1
2236                          */
2237                         data = (ret & 0x1) << 15;
2238                         temp = (ret >> 0x1) & 0x3;
2239
2240                         rmask = BIT(15) | BIT(31);
2241                         data |= BIT(31);
2242                         ret = regmap_update_bits(regmap, reg, rmask, data);
2243                         if (ret)
2244                                 return ret;
2245
2246                         rmask = 0x3 | (0x3 << 16);
2247                         temp |= (0x3 << 16);
2248                         reg += 0x4;
2249                         ret = regmap_update_bits(regmap, reg, rmask, temp);
2250
2251                         return ret;
2252                 case 18 ... 21:
2253                         /* setting fully enclosed in the second register */
2254                         reg += 4;
2255                         bit -= 16;
2256                         break;
2257                 default:
2258                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2259                                 bit, drv_type);
2260                         return -EINVAL;
2261                 }
2262                 break;
2263         case DRV_TYPE_IO_DEFAULT:
2264         case DRV_TYPE_IO_1V8_OR_3V0:
2265         case DRV_TYPE_IO_1V8_ONLY:
2266                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2267                 break;
2268         default:
2269                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2270                         drv_type);
2271                 return -EINVAL;
2272         }
2273
2274         /* enable the write to the equivalent lower bits */
2275         data = ((1 << rmask_bits) - 1) << (bit + 16);
2276         rmask = data | (data >> 16);
2277         data |= (ret << bit);
2278
2279         ret = regmap_update_bits(regmap, reg, rmask, data);
2280
2281         return ret;
2282 }
2283
2284 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2285         {
2286                 PIN_CONFIG_BIAS_DISABLE,
2287                 PIN_CONFIG_BIAS_PULL_UP,
2288                 PIN_CONFIG_BIAS_PULL_DOWN,
2289                 PIN_CONFIG_BIAS_BUS_HOLD
2290         },
2291         {
2292                 PIN_CONFIG_BIAS_DISABLE,
2293                 PIN_CONFIG_BIAS_PULL_DOWN,
2294                 PIN_CONFIG_BIAS_DISABLE,
2295                 PIN_CONFIG_BIAS_PULL_UP
2296         },
2297 };
2298
2299 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2300 {
2301         struct rockchip_pinctrl *info = bank->drvdata;
2302         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2303         struct regmap *regmap;
2304         int reg, ret, pull_type;
2305         u8 bit;
2306         u32 data;
2307
2308         /* rk3066b does support any pulls */
2309         if (ctrl->type == RK3066B)
2310                 return PIN_CONFIG_BIAS_DISABLE;
2311
2312         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2313
2314         ret = regmap_read(regmap, reg, &data);
2315         if (ret)
2316                 return ret;
2317
2318         switch (ctrl->type) {
2319         case RK2928:
2320         case RK3128:
2321                 return !(data & BIT(bit))
2322                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2323                                 : PIN_CONFIG_BIAS_DISABLE;
2324         case PX30:
2325         case RV1108:
2326         case RK3188:
2327         case RK3288:
2328         case RK3308:
2329         case RK3368:
2330         case RK3399:
2331                 pull_type = bank->pull_type[pin_num / 8];
2332                 data >>= bit;
2333                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2334
2335                 return rockchip_pull_list[pull_type][data];
2336         default:
2337                 dev_err(info->dev, "unsupported pinctrl type\n");
2338                 return -EINVAL;
2339         };
2340 }
2341
2342 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2343                                         int pin_num, int pull)
2344 {
2345         struct rockchip_pinctrl *info = bank->drvdata;
2346         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2347         struct regmap *regmap;
2348         int reg, ret, i, pull_type;
2349         u8 bit;
2350         u32 data, rmask;
2351
2352         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2353                  bank->bank_num, pin_num, pull);
2354
2355         /* rk3066b does support any pulls */
2356         if (ctrl->type == RK3066B)
2357                 return pull ? -EINVAL : 0;
2358
2359         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2360
2361         switch (ctrl->type) {
2362         case RK2928:
2363         case RK3128:
2364                 data = BIT(bit + 16);
2365                 if (pull == PIN_CONFIG_BIAS_DISABLE)
2366                         data |= BIT(bit);
2367                 ret = regmap_write(regmap, reg, data);
2368                 break;
2369         case PX30:
2370         case RV1108:
2371         case RK3188:
2372         case RK3288:
2373         case RK3308:
2374         case RK3368:
2375         case RK3399:
2376                 pull_type = bank->pull_type[pin_num / 8];
2377                 ret = -EINVAL;
2378                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2379                         i++) {
2380                         if (rockchip_pull_list[pull_type][i] == pull) {
2381                                 ret = i;
2382                                 break;
2383                         }
2384                 }
2385
2386                 if (ret < 0) {
2387                         dev_err(info->dev, "unsupported pull setting %d\n",
2388                                 pull);
2389                         return ret;
2390                 }
2391
2392                 /* enable the write to the equivalent lower bits */
2393                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2394                 rmask = data | (data >> 16);
2395                 data |= (ret << bit);
2396
2397                 ret = regmap_update_bits(regmap, reg, rmask, data);
2398                 break;
2399         default:
2400                 dev_err(info->dev, "unsupported pinctrl type\n");
2401                 return -EINVAL;
2402         }
2403
2404         return ret;
2405 }
2406
2407 #define RK3328_SCHMITT_BITS_PER_PIN             1
2408 #define RK3328_SCHMITT_PINS_PER_REG             16
2409 #define RK3328_SCHMITT_BANK_STRIDE              8
2410 #define RK3328_SCHMITT_GRF_OFFSET               0x380
2411
2412 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2413                                            int pin_num,
2414                                            struct regmap **regmap,
2415                                            int *reg, u8 *bit)
2416 {
2417         struct rockchip_pinctrl *info = bank->drvdata;
2418
2419         *regmap = info->regmap_base;
2420         *reg = RK3328_SCHMITT_GRF_OFFSET;
2421
2422         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2423         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2424         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2425
2426         return 0;
2427 }
2428
2429 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2430 {
2431         struct rockchip_pinctrl *info = bank->drvdata;
2432         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2433         struct regmap *regmap;
2434         int reg, ret;
2435         u8 bit;
2436         u32 data;
2437
2438         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2439         if (ret)
2440                 return ret;
2441
2442         ret = regmap_read(regmap, reg, &data);
2443         if (ret)
2444                 return ret;
2445
2446         data >>= bit;
2447         return data & 0x1;
2448 }
2449
2450 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2451                                 int pin_num, int enable)
2452 {
2453         struct rockchip_pinctrl *info = bank->drvdata;
2454         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2455         struct regmap *regmap;
2456         int reg, ret;
2457         u8 bit;
2458         u32 data, rmask;
2459
2460         dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2461                 bank->bank_num, pin_num, enable);
2462
2463         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2464         if (ret)
2465                 return ret;
2466
2467         /* enable the write to the equivalent lower bits */
2468         data = BIT(bit + 16) | (enable << bit);
2469         rmask = BIT(bit + 16) | BIT(bit);
2470
2471         return regmap_update_bits(regmap, reg, rmask, data);
2472 }
2473
2474 /*
2475  * Pinmux_ops handling
2476  */
2477
2478 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2479 {
2480         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2481
2482         return info->nfunctions;
2483 }
2484
2485 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2486                                           unsigned selector)
2487 {
2488         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2489
2490         return info->functions[selector].name;
2491 }
2492
2493 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2494                                 unsigned selector, const char * const **groups,
2495                                 unsigned * const num_groups)
2496 {
2497         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2498
2499         *groups = info->functions[selector].groups;
2500         *num_groups = info->functions[selector].ngroups;
2501
2502         return 0;
2503 }
2504
2505 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2506                             unsigned group)
2507 {
2508         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2509         const unsigned int *pins = info->groups[group].pins;
2510         const struct rockchip_pin_config *data = info->groups[group].data;
2511         struct rockchip_pin_bank *bank;
2512         int cnt, ret = 0;
2513
2514         dev_dbg(info->dev, "enable function %s group %s\n",
2515                 info->functions[selector].name, info->groups[group].name);
2516
2517         /*
2518          * for each pin in the pin group selected, program the corresponding
2519          * pin function number in the config register.
2520          */
2521         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2522                 bank = pin_to_bank(info, pins[cnt]);
2523                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2524                                        data[cnt].func);
2525                 if (ret)
2526                         break;
2527         }
2528
2529         if (ret) {
2530                 /* revert the already done pin settings */
2531                 for (cnt--; cnt >= 0; cnt--)
2532                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2533
2534                 return ret;
2535         }
2536
2537         return 0;
2538 }
2539
2540 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2541 {
2542         struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2543         u32 data;
2544         int ret;
2545
2546         ret = clk_enable(bank->clk);
2547         if (ret < 0) {
2548                 dev_err(bank->drvdata->dev,
2549                         "failed to enable clock for bank %s\n", bank->name);
2550                 return ret;
2551         }
2552         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2553         clk_disable(bank->clk);
2554
2555         if (data & BIT(offset))
2556                 return GPIO_LINE_DIRECTION_OUT;
2557
2558         return GPIO_LINE_DIRECTION_IN;
2559 }
2560
2561 /*
2562  * The calls to gpio_direction_output() and gpio_direction_input()
2563  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2564  * function called from the gpiolib interface).
2565  */
2566 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2567                                             int pin, bool input)
2568 {
2569         struct rockchip_pin_bank *bank;
2570         int ret;
2571         unsigned long flags;
2572         u32 data;
2573
2574         bank = gpiochip_get_data(chip);
2575
2576         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2577         if (ret < 0)
2578                 return ret;
2579
2580         clk_enable(bank->clk);
2581         raw_spin_lock_irqsave(&bank->slock, flags);
2582
2583         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2584         /* set bit to 1 for output, 0 for input */
2585         if (!input)
2586                 data |= BIT(pin);
2587         else
2588                 data &= ~BIT(pin);
2589         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2590
2591         raw_spin_unlock_irqrestore(&bank->slock, flags);
2592         clk_disable(bank->clk);
2593
2594         return 0;
2595 }
2596
2597 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2598                                               struct pinctrl_gpio_range *range,
2599                                               unsigned offset, bool input)
2600 {
2601         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2602         struct gpio_chip *chip;
2603         int pin;
2604
2605         chip = range->gc;
2606         pin = offset - chip->base;
2607         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2608                  offset, range->name, pin, input ? "input" : "output");
2609
2610         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2611                                                 input);
2612 }
2613
2614 static const struct pinmux_ops rockchip_pmx_ops = {
2615         .get_functions_count    = rockchip_pmx_get_funcs_count,
2616         .get_function_name      = rockchip_pmx_get_func_name,
2617         .get_function_groups    = rockchip_pmx_get_groups,
2618         .set_mux                = rockchip_pmx_set,
2619         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
2620 };
2621
2622 /*
2623  * Pinconf_ops handling
2624  */
2625
2626 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2627                                         enum pin_config_param pull)
2628 {
2629         switch (ctrl->type) {
2630         case RK2928:
2631         case RK3128:
2632                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2633                                         pull == PIN_CONFIG_BIAS_DISABLE);
2634         case RK3066B:
2635                 return pull ? false : true;
2636         case PX30:
2637         case RV1108:
2638         case RK3188:
2639         case RK3288:
2640         case RK3308:
2641         case RK3368:
2642         case RK3399:
2643                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2644         }
2645
2646         return false;
2647 }
2648
2649 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2650 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2651
2652 /* set the pin config settings for a specified pin */
2653 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2654                                 unsigned long *configs, unsigned num_configs)
2655 {
2656         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2657         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2658         enum pin_config_param param;
2659         u32 arg;
2660         int i;
2661         int rc;
2662
2663         for (i = 0; i < num_configs; i++) {
2664                 param = pinconf_to_config_param(configs[i]);
2665                 arg = pinconf_to_config_argument(configs[i]);
2666
2667                 switch (param) {
2668                 case PIN_CONFIG_BIAS_DISABLE:
2669                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2670                                 param);
2671                         if (rc)
2672                                 return rc;
2673                         break;
2674                 case PIN_CONFIG_BIAS_PULL_UP:
2675                 case PIN_CONFIG_BIAS_PULL_DOWN:
2676                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2677                 case PIN_CONFIG_BIAS_BUS_HOLD:
2678                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2679                                 return -ENOTSUPP;
2680
2681                         if (!arg)
2682                                 return -EINVAL;
2683
2684                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2685                                 param);
2686                         if (rc)
2687                                 return rc;
2688                         break;
2689                 case PIN_CONFIG_OUTPUT:
2690                         rockchip_gpio_set(&bank->gpio_chip,
2691                                           pin - bank->pin_base, arg);
2692                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2693                                           pin - bank->pin_base, false);
2694                         if (rc)
2695                                 return rc;
2696                         break;
2697                 case PIN_CONFIG_DRIVE_STRENGTH:
2698                         /* rk3288 is the first with per-pin drive-strength */
2699                         if (!info->ctrl->drv_calc_reg)
2700                                 return -ENOTSUPP;
2701
2702                         rc = rockchip_set_drive_perpin(bank,
2703                                                 pin - bank->pin_base, arg);
2704                         if (rc < 0)
2705                                 return rc;
2706                         break;
2707                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2708                         if (!info->ctrl->schmitt_calc_reg)
2709                                 return -ENOTSUPP;
2710
2711                         rc = rockchip_set_schmitt(bank,
2712                                                   pin - bank->pin_base, arg);
2713                         if (rc < 0)
2714                                 return rc;
2715                         break;
2716                 default:
2717                         return -ENOTSUPP;
2718                         break;
2719                 }
2720         } /* for each config */
2721
2722         return 0;
2723 }
2724
2725 /* get the pin config settings for a specified pin */
2726 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2727                                                         unsigned long *config)
2728 {
2729         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2730         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2731         enum pin_config_param param = pinconf_to_config_param(*config);
2732         u16 arg;
2733         int rc;
2734
2735         switch (param) {
2736         case PIN_CONFIG_BIAS_DISABLE:
2737                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2738                         return -EINVAL;
2739
2740                 arg = 0;
2741                 break;
2742         case PIN_CONFIG_BIAS_PULL_UP:
2743         case PIN_CONFIG_BIAS_PULL_DOWN:
2744         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2745         case PIN_CONFIG_BIAS_BUS_HOLD:
2746                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2747                         return -ENOTSUPP;
2748
2749                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2750                         return -EINVAL;
2751
2752                 arg = 1;
2753                 break;
2754         case PIN_CONFIG_OUTPUT:
2755                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2756                 if (rc != RK_FUNC_GPIO)
2757                         return -EINVAL;
2758
2759                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2760                 if (rc < 0)
2761                         return rc;
2762
2763                 arg = rc ? 1 : 0;
2764                 break;
2765         case PIN_CONFIG_DRIVE_STRENGTH:
2766                 /* rk3288 is the first with per-pin drive-strength */
2767                 if (!info->ctrl->drv_calc_reg)
2768                         return -ENOTSUPP;
2769
2770                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2771                 if (rc < 0)
2772                         return rc;
2773
2774                 arg = rc;
2775                 break;
2776         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2777                 if (!info->ctrl->schmitt_calc_reg)
2778                         return -ENOTSUPP;
2779
2780                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2781                 if (rc < 0)
2782                         return rc;
2783
2784                 arg = rc;
2785                 break;
2786         default:
2787                 return -ENOTSUPP;
2788                 break;
2789         }
2790
2791         *config = pinconf_to_config_packed(param, arg);
2792
2793         return 0;
2794 }
2795
2796 static const struct pinconf_ops rockchip_pinconf_ops = {
2797         .pin_config_get                 = rockchip_pinconf_get,
2798         .pin_config_set                 = rockchip_pinconf_set,
2799         .is_generic                     = true,
2800 };
2801
2802 static const struct of_device_id rockchip_bank_match[] = {
2803         { .compatible = "rockchip,gpio-bank" },
2804         { .compatible = "rockchip,rk3188-gpio-bank0" },
2805         {},
2806 };
2807
2808 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2809                                                 struct device_node *np)
2810 {
2811         struct device_node *child;
2812
2813         for_each_child_of_node(np, child) {
2814                 if (of_match_node(rockchip_bank_match, child))
2815                         continue;
2816
2817                 info->nfunctions++;
2818                 info->ngroups += of_get_child_count(child);
2819         }
2820 }
2821
2822 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2823                                               struct rockchip_pin_group *grp,
2824                                               struct rockchip_pinctrl *info,
2825                                               u32 index)
2826 {
2827         struct rockchip_pin_bank *bank;
2828         int size;
2829         const __be32 *list;
2830         int num;
2831         int i, j;
2832         int ret;
2833
2834         dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2835
2836         /* Initialise group */
2837         grp->name = np->name;
2838
2839         /*
2840          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2841          * do sanity check and calculate pins number
2842          */
2843         list = of_get_property(np, "rockchip,pins", &size);
2844         /* we do not check return since it's safe node passed down */
2845         size /= sizeof(*list);
2846         if (!size || size % 4) {
2847                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2848                 return -EINVAL;
2849         }
2850
2851         grp->npins = size / 4;
2852
2853         grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2854                                                 GFP_KERNEL);
2855         grp->data = devm_kcalloc(info->dev,
2856                                         grp->npins,
2857                                         sizeof(struct rockchip_pin_config),
2858                                         GFP_KERNEL);
2859         if (!grp->pins || !grp->data)
2860                 return -ENOMEM;
2861
2862         for (i = 0, j = 0; i < size; i += 4, j++) {
2863                 const __be32 *phandle;
2864                 struct device_node *np_config;
2865
2866                 num = be32_to_cpu(*list++);
2867                 bank = bank_num_to_bank(info, num);
2868                 if (IS_ERR(bank))
2869                         return PTR_ERR(bank);
2870
2871                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2872                 grp->data[j].func = be32_to_cpu(*list++);
2873
2874                 phandle = list++;
2875                 if (!phandle)
2876                         return -EINVAL;
2877
2878                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2879                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2880                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2881                 if (ret)
2882                         return ret;
2883         }
2884
2885         return 0;
2886 }
2887
2888 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2889                                                 struct rockchip_pinctrl *info,
2890                                                 u32 index)
2891 {
2892         struct device_node *child;
2893         struct rockchip_pmx_func *func;
2894         struct rockchip_pin_group *grp;
2895         int ret;
2896         static u32 grp_index;
2897         u32 i = 0;
2898
2899         dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2900
2901         func = &info->functions[index];
2902
2903         /* Initialise function */
2904         func->name = np->name;
2905         func->ngroups = of_get_child_count(np);
2906         if (func->ngroups <= 0)
2907                 return 0;
2908
2909         func->groups = devm_kcalloc(info->dev,
2910                         func->ngroups, sizeof(char *), GFP_KERNEL);
2911         if (!func->groups)
2912                 return -ENOMEM;
2913
2914         for_each_child_of_node(np, child) {
2915                 func->groups[i] = child->name;
2916                 grp = &info->groups[grp_index++];
2917                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2918                 if (ret) {
2919                         of_node_put(child);
2920                         return ret;
2921                 }
2922         }
2923
2924         return 0;
2925 }
2926
2927 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2928                                               struct rockchip_pinctrl *info)
2929 {
2930         struct device *dev = &pdev->dev;
2931         struct device_node *np = dev->of_node;
2932         struct device_node *child;
2933         int ret;
2934         int i;
2935
2936         rockchip_pinctrl_child_count(info, np);
2937
2938         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2939         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2940
2941         info->functions = devm_kcalloc(dev,
2942                                               info->nfunctions,
2943                                               sizeof(struct rockchip_pmx_func),
2944                                               GFP_KERNEL);
2945         if (!info->functions)
2946                 return -ENOMEM;
2947
2948         info->groups = devm_kcalloc(dev,
2949                                             info->ngroups,
2950                                             sizeof(struct rockchip_pin_group),
2951                                             GFP_KERNEL);
2952         if (!info->groups)
2953                 return -ENOMEM;
2954
2955         i = 0;
2956
2957         for_each_child_of_node(np, child) {
2958                 if (of_match_node(rockchip_bank_match, child))
2959                         continue;
2960
2961                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2962                 if (ret) {
2963                         dev_err(&pdev->dev, "failed to parse function\n");
2964                         of_node_put(child);
2965                         return ret;
2966                 }
2967         }
2968
2969         return 0;
2970 }
2971
2972 static int rockchip_pinctrl_register(struct platform_device *pdev,
2973                                         struct rockchip_pinctrl *info)
2974 {
2975         struct pinctrl_desc *ctrldesc = &info->pctl;
2976         struct pinctrl_pin_desc *pindesc, *pdesc;
2977         struct rockchip_pin_bank *pin_bank;
2978         int pin, bank, ret;
2979         int k;
2980
2981         ctrldesc->name = "rockchip-pinctrl";
2982         ctrldesc->owner = THIS_MODULE;
2983         ctrldesc->pctlops = &rockchip_pctrl_ops;
2984         ctrldesc->pmxops = &rockchip_pmx_ops;
2985         ctrldesc->confops = &rockchip_pinconf_ops;
2986
2987         pindesc = devm_kcalloc(&pdev->dev,
2988                                info->ctrl->nr_pins, sizeof(*pindesc),
2989                                GFP_KERNEL);
2990         if (!pindesc)
2991                 return -ENOMEM;
2992
2993         ctrldesc->pins = pindesc;
2994         ctrldesc->npins = info->ctrl->nr_pins;
2995
2996         pdesc = pindesc;
2997         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2998                 pin_bank = &info->ctrl->pin_banks[bank];
2999                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3000                         pdesc->number = k;
3001                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
3002                                                 pin_bank->name, pin);
3003                         pdesc++;
3004                 }
3005         }
3006
3007         ret = rockchip_pinctrl_parse_dt(pdev, info);
3008         if (ret)
3009                 return ret;
3010
3011         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
3012         if (IS_ERR(info->pctl_dev)) {
3013                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
3014                 return PTR_ERR(info->pctl_dev);
3015         }
3016
3017         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
3018                 pin_bank = &info->ctrl->pin_banks[bank];
3019                 pin_bank->grange.name = pin_bank->name;
3020                 pin_bank->grange.id = bank;
3021                 pin_bank->grange.pin_base = pin_bank->pin_base;
3022                 pin_bank->grange.base = pin_bank->gpio_chip.base;
3023                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
3024                 pin_bank->grange.gc = &pin_bank->gpio_chip;
3025                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
3026         }
3027
3028         return 0;
3029 }
3030
3031 /*
3032  * GPIO handling
3033  */
3034
3035 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
3036 {
3037         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3038         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
3039         unsigned long flags;
3040         u32 data;
3041
3042         clk_enable(bank->clk);
3043         raw_spin_lock_irqsave(&bank->slock, flags);
3044
3045         data = readl(reg);
3046         data &= ~BIT(offset);
3047         if (value)
3048                 data |= BIT(offset);
3049         writel(data, reg);
3050
3051         raw_spin_unlock_irqrestore(&bank->slock, flags);
3052         clk_disable(bank->clk);
3053 }
3054
3055 /*
3056  * Returns the level of the pin for input direction and setting of the DR
3057  * register for output gpios.
3058  */
3059 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
3060 {
3061         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3062         u32 data;
3063
3064         clk_enable(bank->clk);
3065         data = readl(bank->reg_base + GPIO_EXT_PORT);
3066         clk_disable(bank->clk);
3067         data >>= offset;
3068         data &= 1;
3069         return data;
3070 }
3071
3072 /*
3073  * gpiolib gpio_direction_input callback function. The setting of the pin
3074  * mux function as 'gpio input' will be handled by the pinctrl subsystem
3075  * interface.
3076  */
3077 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
3078 {
3079         return pinctrl_gpio_direction_input(gc->base + offset);
3080 }
3081
3082 /*
3083  * gpiolib gpio_direction_output callback function. The setting of the pin
3084  * mux function as 'gpio output' will be handled by the pinctrl subsystem
3085  * interface.
3086  */
3087 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
3088                                           unsigned offset, int value)
3089 {
3090         rockchip_gpio_set(gc, offset, value);
3091         return pinctrl_gpio_direction_output(gc->base + offset);
3092 }
3093
3094 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
3095                                        unsigned int offset, bool enable)
3096 {
3097         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3098         void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
3099         unsigned long flags;
3100         u32 data;
3101
3102         clk_enable(bank->clk);
3103         raw_spin_lock_irqsave(&bank->slock, flags);
3104
3105         data = readl(reg);
3106         if (enable)
3107                 data |= BIT(offset);
3108         else
3109                 data &= ~BIT(offset);
3110         writel(data, reg);
3111
3112         raw_spin_unlock_irqrestore(&bank->slock, flags);
3113         clk_disable(bank->clk);
3114 }
3115
3116 /*
3117  * gpiolib set_config callback function. The setting of the pin
3118  * mux function as 'gpio output' will be handled by the pinctrl subsystem
3119  * interface.
3120  */
3121 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
3122                                   unsigned long config)
3123 {
3124         enum pin_config_param param = pinconf_to_config_param(config);
3125
3126         switch (param) {
3127         case PIN_CONFIG_INPUT_DEBOUNCE:
3128                 rockchip_gpio_set_debounce(gc, offset, true);
3129                 /*
3130                  * Rockchip's gpio could only support up to one period
3131                  * of the debounce clock(pclk), which is far away from
3132                  * satisftying the requirement, as pclk is usually near
3133                  * 100MHz shared by all peripherals. So the fact is it
3134                  * has crippled debounce capability could only be useful
3135                  * to prevent any spurious glitches from waking up the system
3136                  * if the gpio is conguired as wakeup interrupt source. Let's
3137                  * still return -ENOTSUPP as before, to make sure the caller
3138                  * of gpiod_set_debounce won't change its behaviour.
3139                  */
3140                 return -ENOTSUPP;
3141         default:
3142                 return -ENOTSUPP;
3143         }
3144 }
3145
3146 /*
3147  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
3148  * and a virtual IRQ, if not already present.
3149  */
3150 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
3151 {
3152         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3153         unsigned int virq;
3154
3155         if (!bank->domain)
3156                 return -ENXIO;
3157
3158         clk_enable(bank->clk);
3159         virq = irq_create_mapping(bank->domain, offset);
3160         clk_disable(bank->clk);
3161
3162         return (virq) ? : -ENXIO;
3163 }
3164
3165 static const struct gpio_chip rockchip_gpiolib_chip = {
3166         .request = gpiochip_generic_request,
3167         .free = gpiochip_generic_free,
3168         .set = rockchip_gpio_set,
3169         .get = rockchip_gpio_get,
3170         .get_direction  = rockchip_gpio_get_direction,
3171         .direction_input = rockchip_gpio_direction_input,
3172         .direction_output = rockchip_gpio_direction_output,
3173         .set_config = rockchip_gpio_set_config,
3174         .to_irq = rockchip_gpio_to_irq,
3175         .owner = THIS_MODULE,
3176 };
3177
3178 /*
3179  * Interrupt handling
3180  */
3181
3182 static void rockchip_irq_demux(struct irq_desc *desc)
3183 {
3184         struct irq_chip *chip = irq_desc_get_chip(desc);
3185         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
3186         u32 pend;
3187
3188         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
3189
3190         chained_irq_enter(chip, desc);
3191
3192         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
3193
3194         while (pend) {
3195                 unsigned int irq, virq;
3196
3197                 irq = __ffs(pend);
3198                 pend &= ~BIT(irq);
3199                 virq = irq_find_mapping(bank->domain, irq);
3200
3201                 if (!virq) {
3202                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
3203                         continue;
3204                 }
3205
3206                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
3207
3208                 /*
3209                  * Triggering IRQ on both rising and falling edge
3210                  * needs manual intervention.
3211                  */
3212                 if (bank->toggle_edge_mode & BIT(irq)) {
3213                         u32 data, data_old, polarity;
3214                         unsigned long flags;
3215
3216                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
3217                         do {
3218                                 raw_spin_lock_irqsave(&bank->slock, flags);
3219
3220                                 polarity = readl_relaxed(bank->reg_base +
3221                                                          GPIO_INT_POLARITY);
3222                                 if (data & BIT(irq))
3223                                         polarity &= ~BIT(irq);
3224                                 else
3225                                         polarity |= BIT(irq);
3226                                 writel(polarity,
3227                                        bank->reg_base + GPIO_INT_POLARITY);
3228
3229                                 raw_spin_unlock_irqrestore(&bank->slock, flags);
3230
3231                                 data_old = data;
3232                                 data = readl_relaxed(bank->reg_base +
3233                                                      GPIO_EXT_PORT);
3234                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
3235                 }
3236
3237                 generic_handle_irq(virq);
3238         }
3239
3240         chained_irq_exit(chip, desc);
3241 }
3242
3243 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
3244 {
3245         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3246         struct rockchip_pin_bank *bank = gc->private;
3247         u32 mask = BIT(d->hwirq);
3248         u32 polarity;
3249         u32 level;
3250         u32 data;
3251         unsigned long flags;
3252         int ret;
3253
3254         /* make sure the pin is configured as gpio input */
3255         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
3256         if (ret < 0)
3257                 return ret;
3258
3259         clk_enable(bank->clk);
3260         raw_spin_lock_irqsave(&bank->slock, flags);
3261
3262         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
3263         data &= ~mask;
3264         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
3265
3266         raw_spin_unlock_irqrestore(&bank->slock, flags);
3267
3268         if (type & IRQ_TYPE_EDGE_BOTH)
3269                 irq_set_handler_locked(d, handle_edge_irq);
3270         else
3271                 irq_set_handler_locked(d, handle_level_irq);
3272
3273         raw_spin_lock_irqsave(&bank->slock, flags);
3274         irq_gc_lock(gc);
3275
3276         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
3277         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
3278
3279         switch (type) {
3280         case IRQ_TYPE_EDGE_BOTH:
3281                 bank->toggle_edge_mode |= mask;
3282                 level |= mask;
3283
3284                 /*
3285                  * Determine gpio state. If 1 next interrupt should be falling
3286                  * otherwise rising.
3287                  */
3288                 data = readl(bank->reg_base + GPIO_EXT_PORT);
3289                 if (data & mask)
3290                         polarity &= ~mask;
3291                 else
3292                         polarity |= mask;
3293                 break;
3294         case IRQ_TYPE_EDGE_RISING:
3295                 bank->toggle_edge_mode &= ~mask;
3296                 level |= mask;
3297                 polarity |= mask;
3298                 break;
3299         case IRQ_TYPE_EDGE_FALLING:
3300                 bank->toggle_edge_mode &= ~mask;
3301                 level |= mask;
3302                 polarity &= ~mask;
3303                 break;
3304         case IRQ_TYPE_LEVEL_HIGH:
3305                 bank->toggle_edge_mode &= ~mask;
3306                 level &= ~mask;
3307                 polarity |= mask;
3308                 break;
3309         case IRQ_TYPE_LEVEL_LOW:
3310                 bank->toggle_edge_mode &= ~mask;
3311                 level &= ~mask;
3312                 polarity &= ~mask;
3313                 break;
3314         default:
3315                 irq_gc_unlock(gc);
3316                 raw_spin_unlock_irqrestore(&bank->slock, flags);
3317                 clk_disable(bank->clk);
3318                 return -EINVAL;
3319         }
3320
3321         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
3322         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
3323
3324         irq_gc_unlock(gc);
3325         raw_spin_unlock_irqrestore(&bank->slock, flags);
3326         clk_disable(bank->clk);
3327
3328         return 0;
3329 }
3330
3331 static void rockchip_irq_suspend(struct irq_data *d)
3332 {
3333         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3334         struct rockchip_pin_bank *bank = gc->private;
3335
3336         clk_enable(bank->clk);
3337         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
3338         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
3339         clk_disable(bank->clk);
3340 }
3341
3342 static void rockchip_irq_resume(struct irq_data *d)
3343 {
3344         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3345         struct rockchip_pin_bank *bank = gc->private;
3346
3347         clk_enable(bank->clk);
3348         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3349         clk_disable(bank->clk);
3350 }
3351
3352 static void rockchip_irq_enable(struct irq_data *d)
3353 {
3354         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3355         struct rockchip_pin_bank *bank = gc->private;
3356
3357         clk_enable(bank->clk);
3358         irq_gc_mask_clr_bit(d);
3359 }
3360
3361 static void rockchip_irq_disable(struct irq_data *d)
3362 {
3363         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3364         struct rockchip_pin_bank *bank = gc->private;
3365
3366         irq_gc_mask_set_bit(d);
3367         clk_disable(bank->clk);
3368 }
3369
3370 static int rockchip_interrupts_register(struct platform_device *pdev,
3371                                                 struct rockchip_pinctrl *info)
3372 {
3373         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3374         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3375         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3376         struct irq_chip_generic *gc;
3377         int ret;
3378         int i;
3379
3380         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3381                 if (!bank->valid) {
3382                         dev_warn(&pdev->dev, "bank %s is not valid\n",
3383                                  bank->name);
3384                         continue;
3385                 }
3386
3387                 ret = clk_enable(bank->clk);
3388                 if (ret) {
3389                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3390                                 bank->name);
3391                         continue;
3392                 }
3393
3394                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3395                                                 &irq_generic_chip_ops, NULL);
3396                 if (!bank->domain) {
3397                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3398                                  bank->name);
3399                         clk_disable(bank->clk);
3400                         continue;
3401                 }
3402
3403                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3404                                          "rockchip_gpio_irq", handle_level_irq,
3405                                          clr, 0, 0);
3406                 if (ret) {
3407                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3408                                 bank->name);
3409                         irq_domain_remove(bank->domain);
3410                         clk_disable(bank->clk);
3411                         continue;
3412                 }
3413
3414                 gc = irq_get_domain_generic_chip(bank->domain, 0);
3415                 gc->reg_base = bank->reg_base;
3416                 gc->private = bank;
3417                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3418                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3419                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3420                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3421                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3422                 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3423                 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3424                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3425                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3426                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3427                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3428                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3429
3430                 /*
3431                  * Linux assumes that all interrupts start out disabled/masked.
3432                  * Our driver only uses the concept of masked and always keeps
3433                  * things enabled, so for us that's all masked and all enabled.
3434                  */
3435                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3436                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3437                 gc->mask_cache = 0xffffffff;
3438
3439                 irq_set_chained_handler_and_data(bank->irq,
3440                                                  rockchip_irq_demux, bank);
3441                 clk_disable(bank->clk);
3442         }
3443
3444         return 0;
3445 }
3446
3447 static int rockchip_gpiolib_register(struct platform_device *pdev,
3448                                                 struct rockchip_pinctrl *info)
3449 {
3450         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3451         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3452         struct gpio_chip *gc;
3453         int ret;
3454         int i;
3455
3456         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3457                 if (!bank->valid) {
3458                         dev_warn(&pdev->dev, "bank %s is not valid\n",
3459                                  bank->name);
3460                         continue;
3461                 }
3462
3463                 bank->gpio_chip = rockchip_gpiolib_chip;
3464
3465                 gc = &bank->gpio_chip;
3466                 gc->base = bank->pin_base;
3467                 gc->ngpio = bank->nr_pins;
3468                 gc->parent = &pdev->dev;
3469                 gc->of_node = bank->of_node;
3470                 gc->label = bank->name;
3471
3472                 ret = gpiochip_add_data(gc, bank);
3473                 if (ret) {
3474                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3475                                                         gc->label, ret);
3476                         goto fail;
3477                 }
3478         }
3479
3480         rockchip_interrupts_register(pdev, info);
3481
3482         return 0;
3483
3484 fail:
3485         for (--i, --bank; i >= 0; --i, --bank) {
3486                 if (!bank->valid)
3487                         continue;
3488                 gpiochip_remove(&bank->gpio_chip);
3489         }
3490         return ret;
3491 }
3492
3493 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3494                                                 struct rockchip_pinctrl *info)
3495 {
3496         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3497         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3498         int i;
3499
3500         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3501                 if (!bank->valid)
3502                         continue;
3503                 gpiochip_remove(&bank->gpio_chip);
3504         }
3505
3506         return 0;
3507 }
3508
3509 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3510                                   struct rockchip_pinctrl *info)
3511 {
3512         struct resource res;
3513         void __iomem *base;
3514
3515         if (of_address_to_resource(bank->of_node, 0, &res)) {
3516                 dev_err(info->dev, "cannot find IO resource for bank\n");
3517                 return -ENOENT;
3518         }
3519
3520         bank->reg_base = devm_ioremap_resource(info->dev, &res);
3521         if (IS_ERR(bank->reg_base))
3522                 return PTR_ERR(bank->reg_base);
3523
3524         /*
3525          * special case, where parts of the pull setting-registers are
3526          * part of the PMU register space
3527          */
3528         if (of_device_is_compatible(bank->of_node,
3529                                     "rockchip,rk3188-gpio-bank0")) {
3530                 struct device_node *node;
3531
3532                 node = of_parse_phandle(bank->of_node->parent,
3533                                         "rockchip,pmu", 0);
3534                 if (!node) {
3535                         if (of_address_to_resource(bank->of_node, 1, &res)) {
3536                                 dev_err(info->dev, "cannot find IO resource for bank\n");
3537                                 return -ENOENT;
3538                         }
3539
3540                         base = devm_ioremap_resource(info->dev, &res);
3541                         if (IS_ERR(base))
3542                                 return PTR_ERR(base);
3543                         rockchip_regmap_config.max_register =
3544                                                     resource_size(&res) - 4;
3545                         rockchip_regmap_config.name =
3546                                             "rockchip,rk3188-gpio-bank0-pull";
3547                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3548                                                     base,
3549                                                     &rockchip_regmap_config);
3550                 }
3551                 of_node_put(node);
3552         }
3553
3554         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3555
3556         bank->clk = of_clk_get(bank->of_node, 0);
3557         if (IS_ERR(bank->clk))
3558                 return PTR_ERR(bank->clk);
3559
3560         return clk_prepare(bank->clk);
3561 }
3562
3563 static const struct of_device_id rockchip_pinctrl_dt_match[];
3564
3565 /* retrieve the soc specific data */
3566 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3567                                                 struct rockchip_pinctrl *d,
3568                                                 struct platform_device *pdev)
3569 {
3570         const struct of_device_id *match;
3571         struct device_node *node = pdev->dev.of_node;
3572         struct device_node *np;
3573         struct rockchip_pin_ctrl *ctrl;
3574         struct rockchip_pin_bank *bank;
3575         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3576
3577         match = of_match_node(rockchip_pinctrl_dt_match, node);
3578         ctrl = (struct rockchip_pin_ctrl *)match->data;
3579
3580         for_each_child_of_node(node, np) {
3581                 if (!of_find_property(np, "gpio-controller", NULL))
3582                         continue;
3583
3584                 bank = ctrl->pin_banks;
3585                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3586                         if (!strcmp(bank->name, np->name)) {
3587                                 bank->of_node = np;
3588
3589                                 if (!rockchip_get_bank_data(bank, d))
3590                                         bank->valid = true;
3591
3592                                 break;
3593                         }
3594                 }
3595         }
3596
3597         grf_offs = ctrl->grf_mux_offset;
3598         pmu_offs = ctrl->pmu_mux_offset;
3599         drv_pmu_offs = ctrl->pmu_drv_offset;
3600         drv_grf_offs = ctrl->grf_drv_offset;
3601         bank = ctrl->pin_banks;
3602         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3603                 int bank_pins = 0;
3604
3605                 raw_spin_lock_init(&bank->slock);
3606                 bank->drvdata = d;
3607                 bank->pin_base = ctrl->nr_pins;
3608                 ctrl->nr_pins += bank->nr_pins;
3609
3610                 /* calculate iomux and drv offsets */
3611                 for (j = 0; j < 4; j++) {
3612                         struct rockchip_iomux *iom = &bank->iomux[j];
3613                         struct rockchip_drv *drv = &bank->drv[j];
3614                         int inc;
3615
3616                         if (bank_pins >= bank->nr_pins)
3617                                 break;
3618
3619                         /* preset iomux offset value, set new start value */
3620                         if (iom->offset >= 0) {
3621                                 if (iom->type & IOMUX_SOURCE_PMU)
3622                                         pmu_offs = iom->offset;
3623                                 else
3624                                         grf_offs = iom->offset;
3625                         } else { /* set current iomux offset */
3626                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3627                                                         pmu_offs : grf_offs;
3628                         }
3629
3630                         /* preset drv offset value, set new start value */
3631                         if (drv->offset >= 0) {
3632                                 if (iom->type & IOMUX_SOURCE_PMU)
3633                                         drv_pmu_offs = drv->offset;
3634                                 else
3635                                         drv_grf_offs = drv->offset;
3636                         } else { /* set current drv offset */
3637                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3638                                                 drv_pmu_offs : drv_grf_offs;
3639                         }
3640
3641                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3642                                 i, j, iom->offset, drv->offset);
3643
3644                         /*
3645                          * Increase offset according to iomux width.
3646                          * 4bit iomux'es are spread over two registers.
3647                          */
3648                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
3649                                             IOMUX_WIDTH_3BIT |
3650                                             IOMUX_WIDTH_2BIT)) ? 8 : 4;
3651                         if (iom->type & IOMUX_SOURCE_PMU)
3652                                 pmu_offs += inc;
3653                         else
3654                                 grf_offs += inc;
3655
3656                         /*
3657                          * Increase offset according to drv width.
3658                          * 3bit drive-strenth'es are spread over two registers.
3659                          */
3660                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3661                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3662                                 inc = 8;
3663                         else
3664                                 inc = 4;
3665
3666                         if (iom->type & IOMUX_SOURCE_PMU)
3667                                 drv_pmu_offs += inc;
3668                         else
3669                                 drv_grf_offs += inc;
3670
3671                         bank_pins += 8;
3672                 }
3673
3674                 /* calculate the per-bank recalced_mask */
3675                 for (j = 0; j < ctrl->niomux_recalced; j++) {
3676                         int pin = 0;
3677
3678                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3679                                 pin = ctrl->iomux_recalced[j].pin;
3680                                 bank->recalced_mask |= BIT(pin);
3681                         }
3682                 }
3683
3684                 /* calculate the per-bank route_mask */
3685                 for (j = 0; j < ctrl->niomux_routes; j++) {
3686                         int pin = 0;
3687
3688                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3689                                 pin = ctrl->iomux_routes[j].pin;
3690                                 bank->route_mask |= BIT(pin);
3691                         }
3692                 }
3693         }
3694
3695         return ctrl;
3696 }
3697
3698 #define RK3288_GRF_GPIO6C_IOMUX         0x64
3699 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
3700
3701 static u32 rk3288_grf_gpio6c_iomux;
3702
3703 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3704 {
3705         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3706         int ret = pinctrl_force_sleep(info->pctl_dev);
3707
3708         if (ret)
3709                 return ret;
3710
3711         /*
3712          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3713          * the setting here, and restore it at resume.
3714          */
3715         if (info->ctrl->type == RK3288) {
3716                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3717                                   &rk3288_grf_gpio6c_iomux);
3718                 if (ret) {
3719                         pinctrl_force_default(info->pctl_dev);
3720                         return ret;
3721                 }
3722         }
3723
3724         return 0;
3725 }
3726
3727 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3728 {
3729         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3730         int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3731                                rk3288_grf_gpio6c_iomux |
3732                                GPIO6C6_SEL_WRITE_ENABLE);
3733
3734         if (ret)
3735                 return ret;
3736
3737         return pinctrl_force_default(info->pctl_dev);
3738 }
3739
3740 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3741                          rockchip_pinctrl_resume);
3742
3743 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3744 {
3745         struct rockchip_pinctrl *info;
3746         struct device *dev = &pdev->dev;
3747         struct rockchip_pin_ctrl *ctrl;
3748         struct device_node *np = pdev->dev.of_node, *node;
3749         struct resource *res;
3750         void __iomem *base;
3751         int ret;
3752
3753         if (!dev->of_node) {
3754                 dev_err(dev, "device tree node not found\n");
3755                 return -ENODEV;
3756         }
3757
3758         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3759         if (!info)
3760                 return -ENOMEM;
3761
3762         info->dev = dev;
3763
3764         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3765         if (!ctrl) {
3766                 dev_err(dev, "driver data not available\n");
3767                 return -EINVAL;
3768         }
3769         info->ctrl = ctrl;
3770
3771         node = of_parse_phandle(np, "rockchip,grf", 0);
3772         if (node) {
3773                 info->regmap_base = syscon_node_to_regmap(node);
3774                 if (IS_ERR(info->regmap_base))
3775                         return PTR_ERR(info->regmap_base);
3776         } else {
3777                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3778                 base = devm_ioremap_resource(&pdev->dev, res);
3779                 if (IS_ERR(base))
3780                         return PTR_ERR(base);
3781
3782                 rockchip_regmap_config.max_register = resource_size(res) - 4;
3783                 rockchip_regmap_config.name = "rockchip,pinctrl";
3784                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3785                                                     &rockchip_regmap_config);
3786
3787                 /* to check for the old dt-bindings */
3788                 info->reg_size = resource_size(res);
3789
3790                 /* Honor the old binding, with pull registers as 2nd resource */
3791                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3792                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3793                         base = devm_ioremap_resource(&pdev->dev, res);
3794                         if (IS_ERR(base))
3795                                 return PTR_ERR(base);
3796
3797                         rockchip_regmap_config.max_register =
3798                                                         resource_size(res) - 4;
3799                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3800                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3801                                                     base,
3802                                                     &rockchip_regmap_config);
3803                 }
3804         }
3805
3806         /* try to find the optional reference to the pmu syscon */
3807         node = of_parse_phandle(np, "rockchip,pmu", 0);
3808         if (node) {
3809                 info->regmap_pmu = syscon_node_to_regmap(node);
3810                 if (IS_ERR(info->regmap_pmu))
3811                         return PTR_ERR(info->regmap_pmu);
3812         }
3813
3814         ret = rockchip_gpiolib_register(pdev, info);
3815         if (ret)
3816                 return ret;
3817
3818         ret = rockchip_pinctrl_register(pdev, info);
3819         if (ret) {
3820                 rockchip_gpiolib_unregister(pdev, info);
3821                 return ret;
3822         }
3823
3824         platform_set_drvdata(pdev, info);
3825
3826         return 0;
3827 }
3828
3829 static struct rockchip_pin_bank px30_pin_banks[] = {
3830         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3831                                              IOMUX_SOURCE_PMU,
3832                                              IOMUX_SOURCE_PMU,
3833                                              IOMUX_SOURCE_PMU
3834                             ),
3835         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3836                                              IOMUX_WIDTH_4BIT,
3837                                              IOMUX_WIDTH_4BIT,
3838                                              IOMUX_WIDTH_4BIT
3839                             ),
3840         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3841                                              IOMUX_WIDTH_4BIT,
3842                                              IOMUX_WIDTH_4BIT,
3843                                              IOMUX_WIDTH_4BIT
3844                             ),
3845         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3846                                              IOMUX_WIDTH_4BIT,
3847                                              IOMUX_WIDTH_4BIT,
3848                                              IOMUX_WIDTH_4BIT
3849                             ),
3850 };
3851
3852 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3853                 .pin_banks              = px30_pin_banks,
3854                 .nr_banks               = ARRAY_SIZE(px30_pin_banks),
3855                 .label                  = "PX30-GPIO",
3856                 .type                   = PX30,
3857                 .grf_mux_offset         = 0x0,
3858                 .pmu_mux_offset         = 0x0,
3859                 .iomux_routes           = px30_mux_route_data,
3860                 .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
3861                 .pull_calc_reg          = px30_calc_pull_reg_and_bit,
3862                 .drv_calc_reg           = px30_calc_drv_reg_and_bit,
3863                 .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
3864 };
3865
3866 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3867         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3868                                              IOMUX_SOURCE_PMU,
3869                                              IOMUX_SOURCE_PMU,
3870                                              IOMUX_SOURCE_PMU),
3871         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3872         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3873         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3874 };
3875
3876 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3877         .pin_banks              = rv1108_pin_banks,
3878         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
3879         .label                  = "RV1108-GPIO",
3880         .type                   = RV1108,
3881         .grf_mux_offset         = 0x10,
3882         .pmu_mux_offset         = 0x0,
3883         .iomux_recalced         = rv1108_mux_recalced_data,
3884         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
3885         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
3886         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
3887         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
3888 };
3889
3890 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3891         PIN_BANK(0, 32, "gpio0"),
3892         PIN_BANK(1, 32, "gpio1"),
3893         PIN_BANK(2, 32, "gpio2"),
3894         PIN_BANK(3, 32, "gpio3"),
3895 };
3896
3897 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3898                 .pin_banks              = rk2928_pin_banks,
3899                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3900                 .label                  = "RK2928-GPIO",
3901                 .type                   = RK2928,
3902                 .grf_mux_offset         = 0xa8,
3903                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3904 };
3905
3906 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3907         PIN_BANK(0, 32, "gpio0"),
3908         PIN_BANK(1, 32, "gpio1"),
3909         PIN_BANK(2, 32, "gpio2"),
3910 };
3911
3912 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3913                 .pin_banks              = rk3036_pin_banks,
3914                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3915                 .label                  = "RK3036-GPIO",
3916                 .type                   = RK2928,
3917                 .grf_mux_offset         = 0xa8,
3918                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3919 };
3920
3921 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3922         PIN_BANK(0, 32, "gpio0"),
3923         PIN_BANK(1, 32, "gpio1"),
3924         PIN_BANK(2, 32, "gpio2"),
3925         PIN_BANK(3, 32, "gpio3"),
3926         PIN_BANK(4, 32, "gpio4"),
3927         PIN_BANK(6, 16, "gpio6"),
3928 };
3929
3930 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3931                 .pin_banks              = rk3066a_pin_banks,
3932                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3933                 .label                  = "RK3066a-GPIO",
3934                 .type                   = RK2928,
3935                 .grf_mux_offset         = 0xa8,
3936                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3937 };
3938
3939 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3940         PIN_BANK(0, 32, "gpio0"),
3941         PIN_BANK(1, 32, "gpio1"),
3942         PIN_BANK(2, 32, "gpio2"),
3943         PIN_BANK(3, 32, "gpio3"),
3944 };
3945
3946 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3947                 .pin_banks      = rk3066b_pin_banks,
3948                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3949                 .label          = "RK3066b-GPIO",
3950                 .type           = RK3066B,
3951                 .grf_mux_offset = 0x60,
3952 };
3953
3954 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3955         PIN_BANK(0, 32, "gpio0"),
3956         PIN_BANK(1, 32, "gpio1"),
3957         PIN_BANK(2, 32, "gpio2"),
3958         PIN_BANK(3, 32, "gpio3"),
3959 };
3960
3961 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3962                 .pin_banks              = rk3128_pin_banks,
3963                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
3964                 .label                  = "RK3128-GPIO",
3965                 .type                   = RK3128,
3966                 .grf_mux_offset         = 0xa8,
3967                 .iomux_recalced         = rk3128_mux_recalced_data,
3968                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
3969                 .iomux_routes           = rk3128_mux_route_data,
3970                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
3971                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
3972 };
3973
3974 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3975         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3976         PIN_BANK(1, 32, "gpio1"),
3977         PIN_BANK(2, 32, "gpio2"),
3978         PIN_BANK(3, 32, "gpio3"),
3979 };
3980
3981 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3982                 .pin_banks              = rk3188_pin_banks,
3983                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3984                 .label                  = "RK3188-GPIO",
3985                 .type                   = RK3188,
3986                 .grf_mux_offset         = 0x60,
3987                 .iomux_routes           = rk3188_mux_route_data,
3988                 .niomux_routes          = ARRAY_SIZE(rk3188_mux_route_data),
3989                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
3990 };
3991
3992 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3993         PIN_BANK(0, 32, "gpio0"),
3994         PIN_BANK(1, 32, "gpio1"),
3995         PIN_BANK(2, 32, "gpio2"),
3996         PIN_BANK(3, 32, "gpio3"),
3997 };
3998
3999 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
4000                 .pin_banks              = rk3228_pin_banks,
4001                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
4002                 .label                  = "RK3228-GPIO",
4003                 .type                   = RK3288,
4004                 .grf_mux_offset         = 0x0,
4005                 .iomux_routes           = rk3228_mux_route_data,
4006                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
4007                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
4008                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
4009 };
4010
4011 static struct rockchip_pin_bank rk3288_pin_banks[] = {
4012         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
4013                                              IOMUX_SOURCE_PMU,
4014                                              IOMUX_SOURCE_PMU,
4015                                              IOMUX_UNROUTED
4016                             ),
4017         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
4018                                              IOMUX_UNROUTED,
4019                                              IOMUX_UNROUTED,
4020                                              0
4021                             ),
4022         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
4023         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
4024         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4025                                              IOMUX_WIDTH_4BIT,
4026                                              0,
4027                                              0
4028                             ),
4029         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
4030                                              0,
4031                                              0,
4032                                              IOMUX_UNROUTED
4033                             ),
4034         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
4035         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
4036                                              0,
4037                                              IOMUX_WIDTH_4BIT,
4038                                              IOMUX_UNROUTED
4039                             ),
4040         PIN_BANK(8, 16, "gpio8"),
4041 };
4042
4043 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
4044                 .pin_banks              = rk3288_pin_banks,
4045                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
4046                 .label                  = "RK3288-GPIO",
4047                 .type                   = RK3288,
4048                 .grf_mux_offset         = 0x0,
4049                 .pmu_mux_offset         = 0x84,
4050                 .iomux_routes           = rk3288_mux_route_data,
4051                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
4052                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
4053                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
4054 };
4055
4056 static struct rockchip_pin_bank rk3308_pin_banks[] = {
4057         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
4058                                              IOMUX_WIDTH_2BIT,
4059                                              IOMUX_WIDTH_2BIT,
4060                                              IOMUX_WIDTH_2BIT),
4061         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
4062                                              IOMUX_WIDTH_2BIT,
4063                                              IOMUX_WIDTH_2BIT,
4064                                              IOMUX_WIDTH_2BIT),
4065         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
4066                                              IOMUX_WIDTH_2BIT,
4067                                              IOMUX_WIDTH_2BIT,
4068                                              IOMUX_WIDTH_2BIT),
4069         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
4070                                              IOMUX_WIDTH_2BIT,
4071                                              IOMUX_WIDTH_2BIT,
4072                                              IOMUX_WIDTH_2BIT),
4073         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
4074                                              IOMUX_WIDTH_2BIT,
4075                                              IOMUX_WIDTH_2BIT,
4076                                              IOMUX_WIDTH_2BIT),
4077 };
4078
4079 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
4080                 .pin_banks              = rk3308_pin_banks,
4081                 .nr_banks               = ARRAY_SIZE(rk3308_pin_banks),
4082                 .label                  = "RK3308-GPIO",
4083                 .type                   = RK3308,
4084                 .grf_mux_offset         = 0x0,
4085                 .iomux_recalced         = rk3308_mux_recalced_data,
4086                 .niomux_recalced        = ARRAY_SIZE(rk3308_mux_recalced_data),
4087                 .iomux_routes           = rk3308_mux_route_data,
4088                 .niomux_routes          = ARRAY_SIZE(rk3308_mux_route_data),
4089                 .pull_calc_reg          = rk3308_calc_pull_reg_and_bit,
4090                 .drv_calc_reg           = rk3308_calc_drv_reg_and_bit,
4091                 .schmitt_calc_reg       = rk3308_calc_schmitt_reg_and_bit,
4092 };
4093
4094 static struct rockchip_pin_bank rk3328_pin_banks[] = {
4095         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
4096         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
4097         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
4098                              IOMUX_WIDTH_3BIT,
4099                              IOMUX_WIDTH_3BIT,
4100                              0),
4101         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4102                              IOMUX_WIDTH_3BIT,
4103                              IOMUX_WIDTH_3BIT,
4104                              0,
4105                              0),
4106 };
4107
4108 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
4109                 .pin_banks              = rk3328_pin_banks,
4110                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
4111                 .label                  = "RK3328-GPIO",
4112                 .type                   = RK3288,
4113                 .grf_mux_offset         = 0x0,
4114                 .iomux_recalced         = rk3328_mux_recalced_data,
4115                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
4116                 .iomux_routes           = rk3328_mux_route_data,
4117                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
4118                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
4119                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
4120                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
4121 };
4122
4123 static struct rockchip_pin_bank rk3368_pin_banks[] = {
4124         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4125                                              IOMUX_SOURCE_PMU,
4126                                              IOMUX_SOURCE_PMU,
4127                                              IOMUX_SOURCE_PMU
4128                             ),
4129         PIN_BANK(1, 32, "gpio1"),
4130         PIN_BANK(2, 32, "gpio2"),
4131         PIN_BANK(3, 32, "gpio3"),
4132 };
4133
4134 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
4135                 .pin_banks              = rk3368_pin_banks,
4136                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
4137                 .label                  = "RK3368-GPIO",
4138                 .type                   = RK3368,
4139                 .grf_mux_offset         = 0x0,
4140                 .pmu_mux_offset         = 0x0,
4141                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
4142                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
4143 };
4144
4145 static struct rockchip_pin_bank rk3399_pin_banks[] = {
4146         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
4147                                                          IOMUX_SOURCE_PMU,
4148                                                          IOMUX_SOURCE_PMU,
4149                                                          IOMUX_SOURCE_PMU,
4150                                                          IOMUX_SOURCE_PMU,
4151                                                          DRV_TYPE_IO_1V8_ONLY,
4152                                                          DRV_TYPE_IO_1V8_ONLY,
4153                                                          DRV_TYPE_IO_DEFAULT,
4154                                                          DRV_TYPE_IO_DEFAULT,
4155                                                          0x80,
4156                                                          0x88,
4157                                                          -1,
4158                                                          -1,
4159                                                          PULL_TYPE_IO_1V8_ONLY,
4160                                                          PULL_TYPE_IO_1V8_ONLY,
4161                                                          PULL_TYPE_IO_DEFAULT,
4162                                                          PULL_TYPE_IO_DEFAULT
4163                                                         ),
4164         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
4165                                         IOMUX_SOURCE_PMU,
4166                                         IOMUX_SOURCE_PMU,
4167                                         IOMUX_SOURCE_PMU,
4168                                         DRV_TYPE_IO_1V8_OR_3V0,
4169                                         DRV_TYPE_IO_1V8_OR_3V0,
4170                                         DRV_TYPE_IO_1V8_OR_3V0,
4171                                         DRV_TYPE_IO_1V8_OR_3V0,
4172                                         0xa0,
4173                                         0xa8,
4174                                         0xb0,
4175                                         0xb8
4176                                         ),
4177         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4178                                       DRV_TYPE_IO_1V8_OR_3V0,
4179                                       DRV_TYPE_IO_1V8_ONLY,
4180                                       DRV_TYPE_IO_1V8_ONLY,
4181                                       PULL_TYPE_IO_DEFAULT,
4182                                       PULL_TYPE_IO_DEFAULT,
4183                                       PULL_TYPE_IO_1V8_ONLY,
4184                                       PULL_TYPE_IO_1V8_ONLY
4185                                       ),
4186         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
4187                            DRV_TYPE_IO_3V3_ONLY,
4188                            DRV_TYPE_IO_3V3_ONLY,
4189                            DRV_TYPE_IO_1V8_OR_3V0
4190                            ),
4191         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
4192                            DRV_TYPE_IO_1V8_3V0_AUTO,
4193                            DRV_TYPE_IO_1V8_OR_3V0,
4194                            DRV_TYPE_IO_1V8_OR_3V0
4195                            ),
4196 };
4197
4198 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
4199                 .pin_banks              = rk3399_pin_banks,
4200                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
4201                 .label                  = "RK3399-GPIO",
4202                 .type                   = RK3399,
4203                 .grf_mux_offset         = 0xe000,
4204                 .pmu_mux_offset         = 0x0,
4205                 .grf_drv_offset         = 0xe100,
4206                 .pmu_drv_offset         = 0x80,
4207                 .iomux_routes           = rk3399_mux_route_data,
4208                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
4209                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
4210                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
4211 };
4212
4213 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4214         { .compatible = "rockchip,px30-pinctrl",
4215                 .data = &px30_pin_ctrl },
4216         { .compatible = "rockchip,rv1108-pinctrl",
4217                 .data = &rv1108_pin_ctrl },
4218         { .compatible = "rockchip,rk2928-pinctrl",
4219                 .data = &rk2928_pin_ctrl },
4220         { .compatible = "rockchip,rk3036-pinctrl",
4221                 .data = &rk3036_pin_ctrl },
4222         { .compatible = "rockchip,rk3066a-pinctrl",
4223                 .data = &rk3066a_pin_ctrl },
4224         { .compatible = "rockchip,rk3066b-pinctrl",
4225                 .data = &rk3066b_pin_ctrl },
4226         { .compatible = "rockchip,rk3128-pinctrl",
4227                 .data = (void *)&rk3128_pin_ctrl },
4228         { .compatible = "rockchip,rk3188-pinctrl",
4229                 .data = &rk3188_pin_ctrl },
4230         { .compatible = "rockchip,rk3228-pinctrl",
4231                 .data = &rk3228_pin_ctrl },
4232         { .compatible = "rockchip,rk3288-pinctrl",
4233                 .data = &rk3288_pin_ctrl },
4234         { .compatible = "rockchip,rk3308-pinctrl",
4235                 .data = &rk3308_pin_ctrl },
4236         { .compatible = "rockchip,rk3328-pinctrl",
4237                 .data = &rk3328_pin_ctrl },
4238         { .compatible = "rockchip,rk3368-pinctrl",
4239                 .data = &rk3368_pin_ctrl },
4240         { .compatible = "rockchip,rk3399-pinctrl",
4241                 .data = &rk3399_pin_ctrl },
4242         {},
4243 };
4244
4245 static struct platform_driver rockchip_pinctrl_driver = {
4246         .probe          = rockchip_pinctrl_probe,
4247         .driver = {
4248                 .name   = "rockchip-pinctrl",
4249                 .pm = &rockchip_pinctrl_dev_pm_ops,
4250                 .of_match_table = rockchip_pinctrl_dt_match,
4251         },
4252 };
4253
4254 static int __init rockchip_pinctrl_drv_register(void)
4255 {
4256         return platform_driver_register(&rockchip_pinctrl_driver);
4257 }
4258 postcore_initcall(rockchip_pinctrl_drv_register);