drivers/pinctrl/pinctrl-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Pinctrl driver for Rockchip SoCs
   4  *
   5  * Copyright (c) 2013 MundoReader S.L.
   6  * Author: Heiko Stuebner <heiko@sntech.de>
   7  *
   8  * With some ideas taken from pinctrl-samsung:
   9  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  10  *              http://www.samsung.com
  11  * Copyright (c) 2012 Linaro Ltd
  12  *              https://www.linaro.org
  13  *
  14  * and pinctrl-at91:
  15  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/io.h>
  22 #include <linux/bitops.h>
  23 #include <linux/gpio/driver.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/pinctrl/machine.h>
  28 #include <linux/pinctrl/pinconf.h>
  29 #include <linux/pinctrl/pinctrl.h>
  30 #include <linux/pinctrl/pinmux.h>
  31 #include <linux/pinctrl/pinconf-generic.h>
  32 #include <linux/irqchip/chained_irq.h>
  33 #include <linux/clk.h>
  34 #include <linux/regmap.h>
  35 #include <linux/mfd/syscon.h>
  36 #include <linux/string_helpers.h>
  37
  38 #include <dt-bindings/pinctrl/rockchip.h>
  39
  40 #include "core.h"
  41 #include "pinconf.h"
  42 #include "pinctrl-rockchip.h"
  43
  44 /*
  45  * Generate a bitmask for setting a value (v) with a write mask bit in hiword
  46  * register 31:16 area.
  47  */
  48 #define WRITE_MASK_VAL(h, l, v) \
  49         (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
  50
  51 /*
  52  * Encode variants of iomux registers into a type variable
  53  */
  54 #define IOMUX_GPIO_ONLY         BIT(0)
  55 #define IOMUX_WIDTH_4BIT        BIT(1)
  56 #define IOMUX_SOURCE_PMU        BIT(2)
  57 #define IOMUX_UNROUTED          BIT(3)
  58 #define IOMUX_WIDTH_3BIT        BIT(4)
  59 #define IOMUX_WIDTH_2BIT        BIT(5)
  60
  61 #define PIN_BANK(id, pins, label)                       \
  62         {                                               \
  63                 .bank_num       = id,                   \
  64                 .nr_pins        = pins,                 \
  65                 .name           = label,                \
  66                 .iomux          = {                     \
  67                         { .offset = -1 },               \
  68                         { .offset = -1 },               \
  69                         { .offset = -1 },               \
  70                         { .offset = -1 },               \
  71                 },                                      \
  72         }
  73
  74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  75         {                                                               \
  76                 .bank_num       = id,                                   \
  77                 .nr_pins        = pins,                                 \
  78                 .name           = label,                                \
  79                 .iomux          = {                                     \
  80                         { .type = iom0, .offset = -1 },                 \
  81                         { .type = iom1, .offset = -1 },                 \
  82                         { .type = iom2, .offset = -1 },                 \
  83                         { .type = iom3, .offset = -1 },                 \
  84                 },                                                      \
  85         }
  86
  87 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
  88         {                                                               \
  89                 .bank_num       = id,                                   \
  90                 .nr_pins        = pins,                                 \
  91                 .name           = label,                                \
  92                 .iomux          = {                                     \
  93                         { .offset = -1 },                               \
  94                         { .offset = -1 },                               \
  95                         { .offset = -1 },                               \
  96                         { .offset = -1 },                               \
  97                 },                                                      \
  98                 .drv            = {                                     \
  99                         { .drv_type = type0, .offset = -1 },            \
 100                         { .drv_type = type1, .offset = -1 },            \
 101                         { .drv_type = type2, .offset = -1 },            \
 102                         { .drv_type = type3, .offset = -1 },            \
 103                 },                                                      \
 104         }
 105
 106 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 107                                       drv2, drv3, pull0, pull1,         \
 108                                       pull2, pull3)                     \
 109         {                                                               \
 110                 .bank_num       = id,                                   \
 111                 .nr_pins        = pins,                                 \
 112                 .name           = label,                                \
 113                 .iomux          = {                                     \
 114                         { .offset = -1 },                               \
 115                         { .offset = -1 },                               \
 116                         { .offset = -1 },                               \
 117                         { .offset = -1 },                               \
 118                 },                                                      \
 119                 .drv            = {                                     \
 120                         { .drv_type = drv0, .offset = -1 },             \
 121                         { .drv_type = drv1, .offset = -1 },             \
 122                         { .drv_type = drv2, .offset = -1 },             \
 123                         { .drv_type = drv3, .offset = -1 },             \
 124                 },                                                      \
 125                 .pull_type[0] = pull0,                                  \
 126                 .pull_type[1] = pull1,                                  \
 127                 .pull_type[2] = pull2,                                  \
 128                 .pull_type[3] = pull3,                                  \
 129         }
 130
 131 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 132                                         iom2, iom3, drv0, drv1, drv2,   \
 133                                         drv3, offset0, offset1,         \
 134                                         offset2, offset3)               \
 135         {                                                               \
 136                 .bank_num       = id,                                   \
 137                 .nr_pins        = pins,                                 \
 138                 .name           = label,                                \
 139                 .iomux          = {                                     \
 140                         { .type = iom0, .offset = -1 },                 \
 141                         { .type = iom1, .offset = -1 },                 \
 142                         { .type = iom2, .offset = -1 },                 \
 143                         { .type = iom3, .offset = -1 },                 \
 144                 },                                                      \
 145                 .drv            = {                                     \
 146                         { .drv_type = drv0, .offset = offset0 },        \
 147                         { .drv_type = drv1, .offset = offset1 },        \
 148                         { .drv_type = drv2, .offset = offset2 },        \
 149                         { .drv_type = drv3, .offset = offset3 },        \
 150                 },                                                      \
 151         }
 152
 153 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 154                                               label, iom0, iom1, iom2,  \
 155                                               iom3, drv0, drv1, drv2,   \
 156                                               drv3, offset0, offset1,   \
 157                                               offset2, offset3, pull0,  \
 158                                               pull1, pull2, pull3)      \
 159         {                                                               \
 160                 .bank_num       = id,                                   \
 161                 .nr_pins        = pins,                                 \
 162                 .name           = label,                                \
 163                 .iomux          = {                                     \
 164                         { .type = iom0, .offset = -1 },                 \
 165                         { .type = iom1, .offset = -1 },                 \
 166                         { .type = iom2, .offset = -1 },                 \
 167                         { .type = iom3, .offset = -1 },                 \
 168                 },                                                      \
 169                 .drv            = {                                     \
 170                         { .drv_type = drv0, .offset = offset0 },        \
 171                         { .drv_type = drv1, .offset = offset1 },        \
 172                         { .drv_type = drv2, .offset = offset2 },        \
 173                         { .drv_type = drv3, .offset = offset3 },        \
 174                 },                                                      \
 175                 .pull_type[0] = pull0,                                  \
 176                 .pull_type[1] = pull1,                                  \
 177                 .pull_type[2] = pull2,                                  \
 178                 .pull_type[3] = pull3,                                  \
 179         }
 180
 181 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG)         \
 182         {                                                               \
 183                 .bank_num       = ID,                                   \
 184                 .pin            = PIN,                                  \
 185                 .func           = FUNC,                                 \
 186                 .route_offset   = REG,                                  \
 187                 .route_val      = VAL,                                  \
 188                 .route_location = FLAG,                                 \
 189         }
 190
 191 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL)       \
 192         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
 193
 194 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL)        \
 195         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
 196
 197 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL)        \
 198         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
 199
 200 static struct regmap_config rockchip_regmap_config = {
 201         .reg_bits = 32,
 202         .val_bits = 32,
 203         .reg_stride = 4,
 204 };
 205
 206 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 207                                         const struct rockchip_pinctrl *info,
 208                                         const char *name)
 209 {
 210         int i;
 211
 212         for (i = 0; i < info->ngroups; i++) {
 213                 if (!strcmp(info->groups[i].name, name))
 214                         return &info->groups[i];
 215         }
 216
 217         return NULL;
 218 }
 219
 220 /*
 221  * given a pin number that is local to a pin controller, find out the pin bank
 222  * and the register base of the pin bank.
 223  */
 224 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 225                                                                 unsigned pin)
 226 {
 227         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 228
 229         while (pin >= (b->pin_base + b->nr_pins))
 230                 b++;
 231
 232         return b;
 233 }
 234
 235 static struct rockchip_pin_bank *bank_num_to_bank(
 236                                         struct rockchip_pinctrl *info,
 237                                         unsigned num)
 238 {
 239         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 240         int i;
 241
 242         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 243                 if (b->bank_num == num)
 244                         return b;
 245         }
 246
 247         return ERR_PTR(-EINVAL);
 248 }
 249
 250 /*
 251  * Pinctrl_ops handling
 252  */
 253
 254 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 255 {
 256         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 257
 258         return info->ngroups;
 259 }
 260
 261 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 262                                                         unsigned selector)
 263 {
 264         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 265
 266         return info->groups[selector].name;
 267 }
 268
 269 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 270                                       unsigned selector, const unsigned **pins,
 271                                       unsigned *npins)
 272 {
 273         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 274
 275         if (selector >= info->ngroups)
 276                 return -EINVAL;
 277
 278         *pins = info->groups[selector].pins;
 279         *npins = info->groups[selector].npins;
 280
 281         return 0;
 282 }
 283
 284 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 285                                  struct device_node *np,
 286                                  struct pinctrl_map **map, unsigned *num_maps)
 287 {
 288         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 289         const struct rockchip_pin_group *grp;
 290         struct device *dev = info->dev;
 291         struct pinctrl_map *new_map;
 292         struct device_node *parent;
 293         int map_num = 1;
 294         int i;
 295
 296         /*
 297          * first find the group of this node and check if we need to create
 298          * config maps for pins
 299          */
 300         grp = pinctrl_name_to_group(info, np->name);
 301         if (!grp) {
 302                 dev_err(dev, "unable to find group for node %pOFn\n", np);
 303                 return -EINVAL;
 304         }
 305
 306         map_num += grp->npins;
 307
 308         new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 309         if (!new_map)
 310                 return -ENOMEM;
 311
 312         *map = new_map;
 313         *num_maps = map_num;
 314
 315         /* create mux map */
 316         parent = of_get_parent(np);
 317         if (!parent) {
 318                 kfree(new_map);
 319                 return -EINVAL;
 320         }
 321         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 322         new_map[0].data.mux.function = parent->name;
 323         new_map[0].data.mux.group = np->name;
 324         of_node_put(parent);
 325
 326         /* create config map */
 327         new_map++;
 328         for (i = 0; i < grp->npins; i++) {
 329                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 330                 new_map[i].data.configs.group_or_pin =
 331                                 pin_get_name(pctldev, grp->pins[i]);
 332                 new_map[i].data.configs.configs = grp->data[i].configs;
 333                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 334         }
 335
 336         dev_dbg(dev, "maps: function %s group %s num %d\n",
 337                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 338
 339         return 0;
 340 }
 341
 342 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 343                                     struct pinctrl_map *map, unsigned num_maps)
 344 {
 345         kfree(map);
 346 }
 347
 348 static const struct pinctrl_ops rockchip_pctrl_ops = {
 349         .get_groups_count       = rockchip_get_groups_count,
 350         .get_group_name         = rockchip_get_group_name,
 351         .get_group_pins         = rockchip_get_group_pins,
 352         .dt_node_to_map         = rockchip_dt_node_to_map,
 353         .dt_free_map            = rockchip_dt_free_map,
 354 };
 355
 356 /*
 357  * Hardware access
 358  */
 359
 360 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 361         {
 362                 .num = 1,
 363                 .pin = 0,
 364                 .reg = 0x418,
 365                 .bit = 0,
 366                 .mask = 0x3
 367         }, {
 368                 .num = 1,
 369                 .pin = 1,
 370                 .reg = 0x418,
 371                 .bit = 2,
 372                 .mask = 0x3
 373         }, {
 374                 .num = 1,
 375                 .pin = 2,
 376                 .reg = 0x418,
 377                 .bit = 4,
 378                 .mask = 0x3
 379         }, {
 380                 .num = 1,
 381                 .pin = 3,
 382                 .reg = 0x418,
 383                 .bit = 6,
 384                 .mask = 0x3
 385         }, {
 386                 .num = 1,
 387                 .pin = 4,
 388                 .reg = 0x418,
 389                 .bit = 8,
 390                 .mask = 0x3
 391         }, {
 392                 .num = 1,
 393                 .pin = 5,
 394                 .reg = 0x418,
 395                 .bit = 10,
 396                 .mask = 0x3
 397         }, {
 398                 .num = 1,
 399                 .pin = 6,
 400                 .reg = 0x418,
 401                 .bit = 12,
 402                 .mask = 0x3
 403         }, {
 404                 .num = 1,
 405                 .pin = 7,
 406                 .reg = 0x418,
 407                 .bit = 14,
 408                 .mask = 0x3
 409         }, {
 410                 .num = 1,
 411                 .pin = 8,
 412                 .reg = 0x41c,
 413                 .bit = 0,
 414                 .mask = 0x3
 415         }, {
 416                 .num = 1,
 417                 .pin = 9,
 418                 .reg = 0x41c,
 419                 .bit = 2,
 420                 .mask = 0x3
 421         },
 422 };
 423
 424 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 425         {
 426                 .num = 2,
 427                 .pin = 20,
 428                 .reg = 0xe8,
 429                 .bit = 0,
 430                 .mask = 0x7
 431         }, {
 432                 .num = 2,
 433                 .pin = 21,
 434                 .reg = 0xe8,
 435                 .bit = 4,
 436                 .mask = 0x7
 437         }, {
 438                 .num = 2,
 439                 .pin = 22,
 440                 .reg = 0xe8,
 441                 .bit = 8,
 442                 .mask = 0x7
 443         }, {
 444                 .num = 2,
 445                 .pin = 23,
 446                 .reg = 0xe8,
 447                 .bit = 12,
 448                 .mask = 0x7
 449         }, {
 450                 .num = 2,
 451                 .pin = 24,
 452                 .reg = 0xd4,
 453                 .bit = 12,
 454                 .mask = 0x7
 455         },
 456 };
 457
 458 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
 459         {
 460                 /* gpio1b6_sel */
 461                 .num = 1,
 462                 .pin = 14,
 463                 .reg = 0x28,
 464                 .bit = 12,
 465                 .mask = 0xf
 466         }, {
 467                 /* gpio1b7_sel */
 468                 .num = 1,
 469                 .pin = 15,
 470                 .reg = 0x2c,
 471                 .bit = 0,
 472                 .mask = 0x3
 473         }, {
 474                 /* gpio1c2_sel */
 475                 .num = 1,
 476                 .pin = 18,
 477                 .reg = 0x30,
 478                 .bit = 4,
 479                 .mask = 0xf
 480         }, {
 481                 /* gpio1c3_sel */
 482                 .num = 1,
 483                 .pin = 19,
 484                 .reg = 0x30,
 485                 .bit = 8,
 486                 .mask = 0xf
 487         }, {
 488                 /* gpio1c4_sel */
 489                 .num = 1,
 490                 .pin = 20,
 491                 .reg = 0x30,
 492                 .bit = 12,
 493                 .mask = 0xf
 494         }, {
 495                 /* gpio1c5_sel */
 496                 .num = 1,
 497                 .pin = 21,
 498                 .reg = 0x34,
 499                 .bit = 0,
 500                 .mask = 0xf
 501         }, {
 502                 /* gpio1c6_sel */
 503                 .num = 1,
 504                 .pin = 22,
 505                 .reg = 0x34,
 506                 .bit = 4,
 507                 .mask = 0xf
 508         }, {
 509                 /* gpio1c7_sel */
 510                 .num = 1,
 511                 .pin = 23,
 512                 .reg = 0x34,
 513                 .bit = 8,
 514                 .mask = 0xf
 515         }, {
 516                 /* gpio2a2_sel */
 517                 .num = 2,
 518                 .pin = 2,
 519                 .reg = 0x40,
 520                 .bit = 4,
 521                 .mask = 0x3
 522         }, {
 523                 /* gpio2a3_sel */
 524                 .num = 2,
 525                 .pin = 3,
 526                 .reg = 0x40,
 527                 .bit = 6,
 528                 .mask = 0x3
 529         }, {
 530                 /* gpio2c0_sel */
 531                 .num = 2,
 532                 .pin = 16,
 533                 .reg = 0x50,
 534                 .bit = 0,
 535                 .mask = 0x3
 536         }, {
 537                 /* gpio3b2_sel */
 538                 .num = 3,
 539                 .pin = 10,
 540                 .reg = 0x68,
 541                 .bit = 4,
 542                 .mask = 0x3
 543         }, {
 544                 /* gpio3b3_sel */
 545                 .num = 3,
 546                 .pin = 11,
 547                 .reg = 0x68,
 548                 .bit = 6,
 549                 .mask = 0x3
 550         }, {
 551                 /* gpio3b4_sel */
 552                 .num = 3,
 553                 .pin = 12,
 554                 .reg = 0x68,
 555                 .bit = 8,
 556                 .mask = 0xf
 557         }, {
 558                 /* gpio3b5_sel */
 559                 .num = 3,
 560                 .pin = 13,
 561                 .reg = 0x68,
 562                 .bit = 12,
 563                 .mask = 0xf
 564         },
 565 };
 566
 567 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 568         {
 569                 .num = 2,
 570                 .pin = 12,
 571                 .reg = 0x24,
 572                 .bit = 8,
 573                 .mask = 0x3
 574         }, {
 575                 .num = 2,
 576                 .pin = 15,
 577                 .reg = 0x28,
 578                 .bit = 0,
 579                 .mask = 0x7
 580         }, {
 581                 .num = 2,
 582                 .pin = 23,
 583                 .reg = 0x30,
 584                 .bit = 14,
 585                 .mask = 0x3
 586         },
 587 };
 588
 589 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 590                                       int *reg, u8 *bit, int *mask)
 591 {
 592         struct rockchip_pinctrl *info = bank->drvdata;
 593         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 594         struct rockchip_mux_recalced_data *data;
 595         int i;
 596
 597         for (i = 0; i < ctrl->niomux_recalced; i++) {
 598                 data = &ctrl->iomux_recalced[i];
 599                 if (data->num == bank->bank_num &&
 600                     data->pin == pin)
 601                         break;
 602         }
 603
 604         if (i >= ctrl->niomux_recalced)
 605                 return;
 606
 607         *reg = data->reg;
 608         *mask = data->mask;
 609         *bit = data->bit;
 610 }
 611
 612 static struct rockchip_mux_route_data px30_mux_route_data[] = {
 613         RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
 614         RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
 615         RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
 616         RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
 617         RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
 618         RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
 619         RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
 620         RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
 621 };
 622
 623 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 624         RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
 625         RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
 626         RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
 627         RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
 628         RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
 629         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
 630         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
 631 };
 632
 633 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
 634         RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
 635         RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
 636 };
 637
 638 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 639         RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
 640         RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
 641         RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
 642         RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
 643         RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
 644         RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
 645         RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
 646         RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
 647         RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
 648         RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
 649         RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
 650         RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
 651         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
 652         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
 653         RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
 654         RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
 655         RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
 656         RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
 657 };
 658
 659 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
 660         RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
 661         RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
 662 };
 663
 664 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
 665         RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
 666         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
 667         RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
 668         RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
 669         RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
 670         RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
 671         RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
 672         RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
 673         RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
 674         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
 675         RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
 676         RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
 677         RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
 678         RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
 679         RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
 680         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
 681         RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
 682         RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
 683         RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
 684         RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
 685         RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
 686         RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
 687         RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
 688         RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
 689         RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
 690         RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
 691 };
 692
 693 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 694         RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
 695         RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
 696         RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
 697         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
 698         RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
 699         RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
 700         RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
 701         RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
 702         RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
 703         RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
 704         RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
 705         RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
 706 };
 707
 708 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
 709         RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
 710         RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
 711         RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
 712         RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
 713         RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
 714 };
 715
 716 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
 717         RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
 718         RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
 719         RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
 720         RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
 721         RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
 722         RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
 723         RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
 724         RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
 725         RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
 726         RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
 727         RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
 728         RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
 729         RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
 730         RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
 731         RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
 732         RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
 733         RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
 734         RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
 735         RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
 736         RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
 737         RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
 738         RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
 739         RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
 740         RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
 741         RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
 742         RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
 743         RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
 744         RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
 745         RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
 746         RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
 747         RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
 748         RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
 749         RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
 750         RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
 751         RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
 752         RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
 753         RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
 754         RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
 755         RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
 756         RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
 757         RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
 758         RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
 759         RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
 760         RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
 761         RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
 762         RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
 763         RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
 764         RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
 765         RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
 766         RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
 767         RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
 768         RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
 769         RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
 770         RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
 771         RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
 772         RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
 773         RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
 774         RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
 775         RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
 776         RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
 777         RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
 778         RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
 779         RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
 780         RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
 781         RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
 782         RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
 783         RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
 784         RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
 785         RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
 786         RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
 787         RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
 788         RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
 789         RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
 790         RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
 791         RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
 792         RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
 793         RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
 794         RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
 795         RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
 796         RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
 797         RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
 798         RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
 799         RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
 800         RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
 801         RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
 802         RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
 803         RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
 804         RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
 805         RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
 806         RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
 807         RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
 808         RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
 809         RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
 810 };
 811
 812 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
 813                                    int mux, u32 *loc, u32 *reg, u32 *value)
 814 {
 815         struct rockchip_pinctrl *info = bank->drvdata;
 816         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 817         struct rockchip_mux_route_data *data;
 818         int i;
 819
 820         for (i = 0; i < ctrl->niomux_routes; i++) {
 821                 data = &ctrl->iomux_routes[i];
 822                 if ((data->bank_num == bank->bank_num) &&
 823                     (data->pin == pin) && (data->func == mux))
 824                         break;
 825         }
 826
 827         if (i >= ctrl->niomux_routes)
 828                 return false;
 829
 830         *loc = data->route_location;
 831         *reg = data->route_offset;
 832         *value = data->route_val;
 833
 834         return true;
 835 }
 836
 837 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 838 {
 839         struct rockchip_pinctrl *info = bank->drvdata;
 840         int iomux_num = (pin / 8);
 841         struct regmap *regmap;
 842         unsigned int val;
 843         int reg, ret, mask, mux_type;
 844         u8 bit;
 845
 846         if (iomux_num > 3)
 847                 return -EINVAL;
 848
 849         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 850                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 851                 return -EINVAL;
 852         }
 853
 854         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 855                 return RK_FUNC_GPIO;
 856
 857         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 858                                 ? info->regmap_pmu : info->regmap_base;
 859
 860         /* get basic quadrupel of mux registers and the correct reg inside */
 861         mux_type = bank->iomux[iomux_num].type;
 862         reg = bank->iomux[iomux_num].offset;
 863         if (mux_type & IOMUX_WIDTH_4BIT) {
 864                 if ((pin % 8) >= 4)
 865                         reg += 0x4;
 866                 bit = (pin % 4) * 4;
 867                 mask = 0xf;
 868         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 869                 if ((pin % 8) >= 5)
 870                         reg += 0x4;
 871                 bit = (pin % 8 % 5) * 3;
 872                 mask = 0x7;
 873         } else {
 874                 bit = (pin % 8) * 2;
 875                 mask = 0x3;
 876         }
 877
 878         if (bank->recalced_mask & BIT(pin))
 879                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
 880
 881         ret = regmap_read(regmap, reg, &val);
 882         if (ret)
 883                 return ret;
 884
 885         return ((val >> bit) & mask);
 886 }
 887
 888 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
 889                                int pin, int mux)
 890 {
 891         struct rockchip_pinctrl *info = bank->drvdata;
 892         struct device *dev = info->dev;
 893         int iomux_num = (pin / 8);
 894
 895         if (iomux_num > 3)
 896                 return -EINVAL;
 897
 898         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 899                 dev_err(dev, "pin %d is unrouted\n", pin);
 900                 return -EINVAL;
 901         }
 902
 903         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 904                 if (mux != RK_FUNC_GPIO) {
 905                         dev_err(dev, "pin %d only supports a gpio mux\n", pin);
 906                         return -ENOTSUPP;
 907                 }
 908         }
 909
 910         return 0;
 911 }
 912
 913 /*
 914  * Set a new mux function for a pin.
 915  *
 916  * The register is divided into the upper and lower 16 bit. When changing
 917  * a value, the previous register value is not read and changed. Instead
 918  * it seems the changed bits are marked in the upper 16 bit, while the
 919  * changed value gets set in the same offset in the lower 16 bit.
 920  * All pin settings seem to be 2 bit wide in both the upper and lower
 921  * parts.
 922  * @bank: pin bank to change
 923  * @pin: pin to change
 924  * @mux: new mux function to set
 925  */
 926 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 927 {
 928         struct rockchip_pinctrl *info = bank->drvdata;
 929         struct device *dev = info->dev;
 930         int iomux_num = (pin / 8);
 931         struct regmap *regmap;
 932         int reg, ret, mask, mux_type;
 933         u8 bit;
 934         u32 data, rmask, route_location, route_reg, route_val;
 935
 936         ret = rockchip_verify_mux(bank, pin, mux);
 937         if (ret < 0)
 938                 return ret;
 939
 940         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 941                 return 0;
 942
 943         dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
 944
 945         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 946                                 ? info->regmap_pmu : info->regmap_base;
 947
 948         /* get basic quadrupel of mux registers and the correct reg inside */
 949         mux_type = bank->iomux[iomux_num].type;
 950         reg = bank->iomux[iomux_num].offset;
 951         if (mux_type & IOMUX_WIDTH_4BIT) {
 952                 if ((pin % 8) >= 4)
 953                         reg += 0x4;
 954                 bit = (pin % 4) * 4;
 955                 mask = 0xf;
 956         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 957                 if ((pin % 8) >= 5)
 958                         reg += 0x4;
 959                 bit = (pin % 8 % 5) * 3;
 960                 mask = 0x7;
 961         } else {
 962                 bit = (pin % 8) * 2;
 963                 mask = 0x3;
 964         }
 965
 966         if (bank->recalced_mask & BIT(pin))
 967                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
 968
 969         if (bank->route_mask & BIT(pin)) {
 970                 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
 971                                            &route_reg, &route_val)) {
 972                         struct regmap *route_regmap = regmap;
 973
 974                         /* handle special locations */
 975                         switch (route_location) {
 976                         case ROCKCHIP_ROUTE_PMU:
 977                                 route_regmap = info->regmap_pmu;
 978                                 break;
 979                         case ROCKCHIP_ROUTE_GRF:
 980                                 route_regmap = info->regmap_base;
 981                                 break;
 982                         }
 983
 984                         ret = regmap_write(route_regmap, route_reg, route_val);
 985                         if (ret)
 986                                 return ret;
 987                 }
 988         }
 989
 990         data = (mask << (bit + 16));
 991         rmask = data | (data >> 16);
 992         data |= (mux & mask) << bit;
 993         ret = regmap_update_bits(regmap, reg, rmask, data);
 994
 995         return ret;
 996 }
 997
 998 #define PX30_PULL_PMU_OFFSET            0x10
 999 #define PX30_PULL_GRF_OFFSET            0x60
1000 #define PX30_PULL_BITS_PER_PIN          2
1001 #define PX30_PULL_PINS_PER_REG          8
1002 #define PX30_PULL_BANK_STRIDE           16
1003
1004 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1005                                        int pin_num, struct regmap **regmap,
1006                                        int *reg, u8 *bit)
1007 {
1008         struct rockchip_pinctrl *info = bank->drvdata;
1009
1010         /* The first 32 pins of the first bank are located in PMU */
1011         if (bank->bank_num == 0) {
1012                 *regmap = info->regmap_pmu;
1013                 *reg = PX30_PULL_PMU_OFFSET;
1014         } else {
1015                 *regmap = info->regmap_base;
1016                 *reg = PX30_PULL_GRF_OFFSET;
1017
1018                 /* correct the offset, as we're starting with the 2nd bank */
1019                 *reg -= 0x10;
1020                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1021         }
1022
1023         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1024         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1025         *bit *= PX30_PULL_BITS_PER_PIN;
1026 }
1027
1028 #define PX30_DRV_PMU_OFFSET             0x20
1029 #define PX30_DRV_GRF_OFFSET             0xf0
1030 #define PX30_DRV_BITS_PER_PIN           2
1031 #define PX30_DRV_PINS_PER_REG           8
1032 #define PX30_DRV_BANK_STRIDE            16
1033
1034 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1035                                       int pin_num, struct regmap **regmap,
1036                                       int *reg, u8 *bit)
1037 {
1038         struct rockchip_pinctrl *info = bank->drvdata;
1039
1040         /* The first 32 pins of the first bank are located in PMU */
1041         if (bank->bank_num == 0) {
1042                 *regmap = info->regmap_pmu;
1043                 *reg = PX30_DRV_PMU_OFFSET;
1044         } else {
1045                 *regmap = info->regmap_base;
1046                 *reg = PX30_DRV_GRF_OFFSET;
1047
1048                 /* correct the offset, as we're starting with the 2nd bank */
1049                 *reg -= 0x10;
1050                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1051         }
1052
1053         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1054         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1055         *bit *= PX30_DRV_BITS_PER_PIN;
1056 }
1057
1058 #define PX30_SCHMITT_PMU_OFFSET                 0x38
1059 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
1060 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
1061 #define PX30_SCHMITT_BANK_STRIDE                16
1062 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
1063
1064 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1065                                          int pin_num,
1066                                          struct regmap **regmap,
1067                                          int *reg, u8 *bit)
1068 {
1069         struct rockchip_pinctrl *info = bank->drvdata;
1070         int pins_per_reg;
1071
1072         if (bank->bank_num == 0) {
1073                 *regmap = info->regmap_pmu;
1074                 *reg = PX30_SCHMITT_PMU_OFFSET;
1075                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1076         } else {
1077                 *regmap = info->regmap_base;
1078                 *reg = PX30_SCHMITT_GRF_OFFSET;
1079                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1080                 *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1081         }
1082
1083         *reg += ((pin_num / pins_per_reg) * 4);
1084         *bit = pin_num % pins_per_reg;
1085
1086         return 0;
1087 }
1088
1089 #define RV1108_PULL_PMU_OFFSET          0x10
1090 #define RV1108_PULL_OFFSET              0x110
1091 #define RV1108_PULL_PINS_PER_REG        8
1092 #define RV1108_PULL_BITS_PER_PIN        2
1093 #define RV1108_PULL_BANK_STRIDE         16
1094
1095 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1096                                          int pin_num, struct regmap **regmap,
1097                                          int *reg, u8 *bit)
1098 {
1099         struct rockchip_pinctrl *info = bank->drvdata;
1100
1101         /* The first 24 pins of the first bank are located in PMU */
1102         if (bank->bank_num == 0) {
1103                 *regmap = info->regmap_pmu;
1104                 *reg = RV1108_PULL_PMU_OFFSET;
1105         } else {
1106                 *reg = RV1108_PULL_OFFSET;
1107                 *regmap = info->regmap_base;
1108                 /* correct the offset, as we're starting with the 2nd bank */
1109                 *reg -= 0x10;
1110                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1111         }
1112
1113         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1114         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1115         *bit *= RV1108_PULL_BITS_PER_PIN;
1116 }
1117
1118 #define RV1108_DRV_PMU_OFFSET           0x20
1119 #define RV1108_DRV_GRF_OFFSET           0x210
1120 #define RV1108_DRV_BITS_PER_PIN         2
1121 #define RV1108_DRV_PINS_PER_REG         8
1122 #define RV1108_DRV_BANK_STRIDE          16
1123
1124 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1125                                         int pin_num, struct regmap **regmap,
1126                                         int *reg, u8 *bit)
1127 {
1128         struct rockchip_pinctrl *info = bank->drvdata;
1129
1130         /* The first 24 pins of the first bank are located in PMU */
1131         if (bank->bank_num == 0) {
1132                 *regmap = info->regmap_pmu;
1133                 *reg = RV1108_DRV_PMU_OFFSET;
1134         } else {
1135                 *regmap = info->regmap_base;
1136                 *reg = RV1108_DRV_GRF_OFFSET;
1137
1138                 /* correct the offset, as we're starting with the 2nd bank */
1139                 *reg -= 0x10;
1140                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1141         }
1142
1143         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1144         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1145         *bit *= RV1108_DRV_BITS_PER_PIN;
1146 }
1147
1148 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1149 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1150 #define RV1108_SCHMITT_BANK_STRIDE              8
1151 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1152 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1153
1154 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1155                                            int pin_num,
1156                                            struct regmap **regmap,
1157                                            int *reg, u8 *bit)
1158 {
1159         struct rockchip_pinctrl *info = bank->drvdata;
1160         int pins_per_reg;
1161
1162         if (bank->bank_num == 0) {
1163                 *regmap = info->regmap_pmu;
1164                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1165                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1166         } else {
1167                 *regmap = info->regmap_base;
1168                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1169                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1170                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1171         }
1172         *reg += ((pin_num / pins_per_reg) * 4);
1173         *bit = pin_num % pins_per_reg;
1174
1175         return 0;
1176 }
1177
1178 #define RK3308_SCHMITT_PINS_PER_REG             8
1179 #define RK3308_SCHMITT_BANK_STRIDE              16
1180 #define RK3308_SCHMITT_GRF_OFFSET               0x1a0
1181
1182 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1183                                     int pin_num, struct regmap **regmap,
1184                                     int *reg, u8 *bit)
1185 {
1186         struct rockchip_pinctrl *info = bank->drvdata;
1187
1188         *regmap = info->regmap_base;
1189         *reg = RK3308_SCHMITT_GRF_OFFSET;
1190
1191         *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1192         *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1193         *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1194
1195         return 0;
1196 }
1197
1198 #define RK2928_PULL_OFFSET              0x118
1199 #define RK2928_PULL_PINS_PER_REG        16
1200 #define RK2928_PULL_BANK_STRIDE         8
1201
1202 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1203                                     int pin_num, struct regmap **regmap,
1204                                     int *reg, u8 *bit)
1205 {
1206         struct rockchip_pinctrl *info = bank->drvdata;
1207
1208         *regmap = info->regmap_base;
1209         *reg = RK2928_PULL_OFFSET;
1210         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1211         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1212
1213         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1214 };
1215
1216 #define RK3128_PULL_OFFSET      0x118
1217
1218 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1219                                          int pin_num, struct regmap **regmap,
1220                                          int *reg, u8 *bit)
1221 {
1222         struct rockchip_pinctrl *info = bank->drvdata;
1223
1224         *regmap = info->regmap_base;
1225         *reg = RK3128_PULL_OFFSET;
1226         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1227         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1228
1229         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1230 }
1231
1232 #define RK3188_PULL_OFFSET              0x164
1233 #define RK3188_PULL_BITS_PER_PIN        2
1234 #define RK3188_PULL_PINS_PER_REG        8
1235 #define RK3188_PULL_BANK_STRIDE         16
1236 #define RK3188_PULL_PMU_OFFSET          0x64
1237
1238 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1239                                     int pin_num, struct regmap **regmap,
1240                                     int *reg, u8 *bit)
1241 {
1242         struct rockchip_pinctrl *info = bank->drvdata;
1243
1244         /* The first 12 pins of the first bank are located elsewhere */
1245         if (bank->bank_num == 0 && pin_num < 12) {
1246                 *regmap = info->regmap_pmu ? info->regmap_pmu
1247                                            : bank->regmap_pull;
1248                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1249                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1250                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1251                 *bit *= RK3188_PULL_BITS_PER_PIN;
1252         } else {
1253                 *regmap = info->regmap_pull ? info->regmap_pull
1254                                             : info->regmap_base;
1255                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1256
1257                 /* correct the offset, as it is the 2nd pull register */
1258                 *reg -= 4;
1259                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1260                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1261
1262                 /*
1263                  * The bits in these registers have an inverse ordering
1264                  * with the lowest pin being in bits 15:14 and the highest
1265                  * pin in bits 1:0
1266                  */
1267                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1268                 *bit *= RK3188_PULL_BITS_PER_PIN;
1269         }
1270 }
1271
1272 #define RK3288_PULL_OFFSET              0x140
1273 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1274                                     int pin_num, struct regmap **regmap,
1275                                     int *reg, u8 *bit)
1276 {
1277         struct rockchip_pinctrl *info = bank->drvdata;
1278
1279         /* The first 24 pins of the first bank are located in PMU */
1280         if (bank->bank_num == 0) {
1281                 *regmap = info->regmap_pmu;
1282                 *reg = RK3188_PULL_PMU_OFFSET;
1283
1284                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1285                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1286                 *bit *= RK3188_PULL_BITS_PER_PIN;
1287         } else {
1288                 *regmap = info->regmap_base;
1289                 *reg = RK3288_PULL_OFFSET;
1290
1291                 /* correct the offset, as we're starting with the 2nd bank */
1292                 *reg -= 0x10;
1293                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1294                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1295
1296                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1297                 *bit *= RK3188_PULL_BITS_PER_PIN;
1298         }
1299 }
1300
1301 #define RK3288_DRV_PMU_OFFSET           0x70
1302 #define RK3288_DRV_GRF_OFFSET           0x1c0
1303 #define RK3288_DRV_BITS_PER_PIN         2
1304 #define RK3288_DRV_PINS_PER_REG         8
1305 #define RK3288_DRV_BANK_STRIDE          16
1306
1307 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1308                                     int pin_num, struct regmap **regmap,
1309                                     int *reg, u8 *bit)
1310 {
1311         struct rockchip_pinctrl *info = bank->drvdata;
1312
1313         /* The first 24 pins of the first bank are located in PMU */
1314         if (bank->bank_num == 0) {
1315                 *regmap = info->regmap_pmu;
1316                 *reg = RK3288_DRV_PMU_OFFSET;
1317
1318                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1319                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1320                 *bit *= RK3288_DRV_BITS_PER_PIN;
1321         } else {
1322                 *regmap = info->regmap_base;
1323                 *reg = RK3288_DRV_GRF_OFFSET;
1324
1325                 /* correct the offset, as we're starting with the 2nd bank */
1326                 *reg -= 0x10;
1327                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1328                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1329
1330                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1331                 *bit *= RK3288_DRV_BITS_PER_PIN;
1332         }
1333 }
1334
1335 #define RK3228_PULL_OFFSET              0x100
1336
1337 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1338                                     int pin_num, struct regmap **regmap,
1339                                     int *reg, u8 *bit)
1340 {
1341         struct rockchip_pinctrl *info = bank->drvdata;
1342
1343         *regmap = info->regmap_base;
1344         *reg = RK3228_PULL_OFFSET;
1345         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1346         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1347
1348         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1349         *bit *= RK3188_PULL_BITS_PER_PIN;
1350 }
1351
1352 #define RK3228_DRV_GRF_OFFSET           0x200
1353
1354 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1355                                     int pin_num, struct regmap **regmap,
1356                                     int *reg, u8 *bit)
1357 {
1358         struct rockchip_pinctrl *info = bank->drvdata;
1359
1360         *regmap = info->regmap_base;
1361         *reg = RK3228_DRV_GRF_OFFSET;
1362         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1363         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1364
1365         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1366         *bit *= RK3288_DRV_BITS_PER_PIN;
1367 }
1368
1369 #define RK3308_PULL_OFFSET              0xa0
1370
1371 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1372                                     int pin_num, struct regmap **regmap,
1373                                     int *reg, u8 *bit)
1374 {
1375         struct rockchip_pinctrl *info = bank->drvdata;
1376
1377         *regmap = info->regmap_base;
1378         *reg = RK3308_PULL_OFFSET;
1379         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1380         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1381
1382         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1383         *bit *= RK3188_PULL_BITS_PER_PIN;
1384 }
1385
1386 #define RK3308_DRV_GRF_OFFSET           0x100
1387
1388 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1389                                     int pin_num, struct regmap **regmap,
1390                                     int *reg, u8 *bit)
1391 {
1392         struct rockchip_pinctrl *info = bank->drvdata;
1393
1394         *regmap = info->regmap_base;
1395         *reg = RK3308_DRV_GRF_OFFSET;
1396         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1397         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1398
1399         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1400         *bit *= RK3288_DRV_BITS_PER_PIN;
1401 }
1402
1403 #define RK3368_PULL_GRF_OFFSET          0x100
1404 #define RK3368_PULL_PMU_OFFSET          0x10
1405
1406 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1407                                     int pin_num, struct regmap **regmap,
1408                                     int *reg, u8 *bit)
1409 {
1410         struct rockchip_pinctrl *info = bank->drvdata;
1411
1412         /* The first 32 pins of the first bank are located in PMU */
1413         if (bank->bank_num == 0) {
1414                 *regmap = info->regmap_pmu;
1415                 *reg = RK3368_PULL_PMU_OFFSET;
1416
1417                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1418                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1419                 *bit *= RK3188_PULL_BITS_PER_PIN;
1420         } else {
1421                 *regmap = info->regmap_base;
1422                 *reg = RK3368_PULL_GRF_OFFSET;
1423
1424                 /* correct the offset, as we're starting with the 2nd bank */
1425                 *reg -= 0x10;
1426                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1427                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1428
1429                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1430                 *bit *= RK3188_PULL_BITS_PER_PIN;
1431         }
1432 }
1433
1434 #define RK3368_DRV_PMU_OFFSET           0x20
1435 #define RK3368_DRV_GRF_OFFSET           0x200
1436
1437 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1438                                     int pin_num, struct regmap **regmap,
1439                                     int *reg, u8 *bit)
1440 {
1441         struct rockchip_pinctrl *info = bank->drvdata;
1442
1443         /* The first 32 pins of the first bank are located in PMU */
1444         if (bank->bank_num == 0) {
1445                 *regmap = info->regmap_pmu;
1446                 *reg = RK3368_DRV_PMU_OFFSET;
1447
1448                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1449                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1450                 *bit *= RK3288_DRV_BITS_PER_PIN;
1451         } else {
1452                 *regmap = info->regmap_base;
1453                 *reg = RK3368_DRV_GRF_OFFSET;
1454
1455                 /* correct the offset, as we're starting with the 2nd bank */
1456                 *reg -= 0x10;
1457                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1458                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1459
1460                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1461                 *bit *= RK3288_DRV_BITS_PER_PIN;
1462         }
1463 }
1464
1465 #define RK3399_PULL_GRF_OFFSET          0xe040
1466 #define RK3399_PULL_PMU_OFFSET          0x40
1467 #define RK3399_DRV_3BITS_PER_PIN        3
1468
1469 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1470                                          int pin_num, struct regmap **regmap,
1471                                          int *reg, u8 *bit)
1472 {
1473         struct rockchip_pinctrl *info = bank->drvdata;
1474
1475         /* The bank0:16 and bank1:32 pins are located in PMU */
1476         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1477                 *regmap = info->regmap_pmu;
1478                 *reg = RK3399_PULL_PMU_OFFSET;
1479
1480                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1481
1482                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1483                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1484                 *bit *= RK3188_PULL_BITS_PER_PIN;
1485         } else {
1486                 *regmap = info->regmap_base;
1487                 *reg = RK3399_PULL_GRF_OFFSET;
1488
1489                 /* correct the offset, as we're starting with the 3rd bank */
1490                 *reg -= 0x20;
1491                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1492                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1493
1494                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1495                 *bit *= RK3188_PULL_BITS_PER_PIN;
1496         }
1497 }
1498
1499 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1500                                         int pin_num, struct regmap **regmap,
1501                                         int *reg, u8 *bit)
1502 {
1503         struct rockchip_pinctrl *info = bank->drvdata;
1504         int drv_num = (pin_num / 8);
1505
1506         /*  The bank0:16 and bank1:32 pins are located in PMU */
1507         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1508                 *regmap = info->regmap_pmu;
1509         else
1510                 *regmap = info->regmap_base;
1511
1512         *reg = bank->drv[drv_num].offset;
1513         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1514             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1515                 *bit = (pin_num % 8) * 3;
1516         else
1517                 *bit = (pin_num % 8) * 2;
1518 }
1519
1520 #define RK3568_PULL_PMU_OFFSET          0x20
1521 #define RK3568_PULL_GRF_OFFSET          0x80
1522 #define RK3568_PULL_BITS_PER_PIN        2
1523 #define RK3568_PULL_PINS_PER_REG        8
1524 #define RK3568_PULL_BANK_STRIDE         0x10
1525
1526 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1527                                          int pin_num, struct regmap **regmap,
1528                                          int *reg, u8 *bit)
1529 {
1530         struct rockchip_pinctrl *info = bank->drvdata;
1531
1532         if (bank->bank_num == 0) {
1533                 *regmap = info->regmap_pmu;
1534                 *reg = RK3568_PULL_PMU_OFFSET;
1535                 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1536                 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1537
1538                 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
1539                 *bit *= RK3568_PULL_BITS_PER_PIN;
1540         } else {
1541                 *regmap = info->regmap_base;
1542                 *reg = RK3568_PULL_GRF_OFFSET;
1543                 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1544                 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1545
1546                 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
1547                 *bit *= RK3568_PULL_BITS_PER_PIN;
1548         }
1549 }
1550
1551 #define RK3568_DRV_PMU_OFFSET           0x70
1552 #define RK3568_DRV_GRF_OFFSET           0x200
1553 #define RK3568_DRV_BITS_PER_PIN         8
1554 #define RK3568_DRV_PINS_PER_REG         2
1555 #define RK3568_DRV_BANK_STRIDE          0x40
1556
1557 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1558                                         int pin_num, struct regmap **regmap,
1559                                         int *reg, u8 *bit)
1560 {
1561         struct rockchip_pinctrl *info = bank->drvdata;
1562
1563         /* The first 32 pins of the first bank are located in PMU */
1564         if (bank->bank_num == 0) {
1565                 *regmap = info->regmap_pmu;
1566                 *reg = RK3568_DRV_PMU_OFFSET;
1567                 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1568
1569                 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
1570                 *bit *= RK3568_DRV_BITS_PER_PIN;
1571         } else {
1572                 *regmap = info->regmap_base;
1573                 *reg = RK3568_DRV_GRF_OFFSET;
1574                 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
1575                 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1576
1577                 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
1578                 *bit *= RK3568_DRV_BITS_PER_PIN;
1579         }
1580 }
1581
1582 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1583         { 2, 4, 8, 12, -1, -1, -1, -1 },
1584         { 3, 6, 9, 12, -1, -1, -1, -1 },
1585         { 5, 10, 15, 20, -1, -1, -1, -1 },
1586         { 4, 6, 8, 10, 12, 14, 16, 18 },
1587         { 4, 7, 10, 13, 16, 19, 22, 26 }
1588 };
1589
1590 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1591                                      int pin_num)
1592 {
1593         struct rockchip_pinctrl *info = bank->drvdata;
1594         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1595         struct device *dev = info->dev;
1596         struct regmap *regmap;
1597         int reg, ret;
1598         u32 data, temp, rmask_bits;
1599         u8 bit;
1600         int drv_type = bank->drv[pin_num / 8].drv_type;
1601
1602         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1603
1604         switch (drv_type) {
1605         case DRV_TYPE_IO_1V8_3V0_AUTO:
1606         case DRV_TYPE_IO_3V3_ONLY:
1607                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1608                 switch (bit) {
1609                 case 0 ... 12:
1610                         /* regular case, nothing to do */
1611                         break;
1612                 case 15:
1613                         /*
1614                          * drive-strength offset is special, as it is
1615                          * spread over 2 registers
1616                          */
1617                         ret = regmap_read(regmap, reg, &data);
1618                         if (ret)
1619                                 return ret;
1620
1621                         ret = regmap_read(regmap, reg + 0x4, &temp);
1622                         if (ret)
1623                                 return ret;
1624
1625                         /*
1626                          * the bit data[15] contains bit 0 of the value
1627                          * while temp[1:0] contains bits 2 and 1
1628                          */
1629                         data >>= 15;
1630                         temp &= 0x3;
1631                         temp <<= 1;
1632                         data |= temp;
1633
1634                         return rockchip_perpin_drv_list[drv_type][data];
1635                 case 18 ... 21:
1636                         /* setting fully enclosed in the second register */
1637                         reg += 4;
1638                         bit -= 16;
1639                         break;
1640                 default:
1641                         dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1642                                 bit, drv_type);
1643                         return -EINVAL;
1644                 }
1645
1646                 break;
1647         case DRV_TYPE_IO_DEFAULT:
1648         case DRV_TYPE_IO_1V8_OR_3V0:
1649         case DRV_TYPE_IO_1V8_ONLY:
1650                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1651                 break;
1652         default:
1653                 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
1654                 return -EINVAL;
1655         }
1656
1657         ret = regmap_read(regmap, reg, &data);
1658         if (ret)
1659                 return ret;
1660
1661         data >>= bit;
1662         data &= (1 << rmask_bits) - 1;
1663
1664         return rockchip_perpin_drv_list[drv_type][data];
1665 }
1666
1667 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1668                                      int pin_num, int strength)
1669 {
1670         struct rockchip_pinctrl *info = bank->drvdata;
1671         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1672         struct device *dev = info->dev;
1673         struct regmap *regmap;
1674         int reg, ret, i;
1675         u32 data, rmask, rmask_bits, temp;
1676         u8 bit;
1677         int drv_type = bank->drv[pin_num / 8].drv_type;
1678
1679         dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
1680                 bank->bank_num, pin_num, strength);
1681
1682         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1683         if (ctrl->type == RK3568) {
1684                 rmask_bits = RK3568_DRV_BITS_PER_PIN;
1685                 ret = (1 << (strength + 1)) - 1;
1686                 goto config;
1687         }
1688
1689         ret = -EINVAL;
1690         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1691                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1692                         ret = i;
1693                         break;
1694                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1695                         ret = rockchip_perpin_drv_list[drv_type][i];
1696                         break;
1697                 }
1698         }
1699
1700         if (ret < 0) {
1701                 dev_err(dev, "unsupported driver strength %d\n", strength);
1702                 return ret;
1703         }
1704
1705         switch (drv_type) {
1706         case DRV_TYPE_IO_1V8_3V0_AUTO:
1707         case DRV_TYPE_IO_3V3_ONLY:
1708                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1709                 switch (bit) {
1710                 case 0 ... 12:
1711                         /* regular case, nothing to do */
1712                         break;
1713                 case 15:
1714                         /*
1715                          * drive-strength offset is special, as it is spread
1716                          * over 2 registers, the bit data[15] contains bit 0
1717                          * of the value while temp[1:0] contains bits 2 and 1
1718                          */
1719                         data = (ret & 0x1) << 15;
1720                         temp = (ret >> 0x1) & 0x3;
1721
1722                         rmask = BIT(15) | BIT(31);
1723                         data |= BIT(31);
1724                         ret = regmap_update_bits(regmap, reg, rmask, data);
1725                         if (ret)
1726                                 return ret;
1727
1728                         rmask = 0x3 | (0x3 << 16);
1729                         temp |= (0x3 << 16);
1730                         reg += 0x4;
1731                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1732
1733                         return ret;
1734                 case 18 ... 21:
1735                         /* setting fully enclosed in the second register */
1736                         reg += 4;
1737                         bit -= 16;
1738                         break;
1739                 default:
1740                         dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1741                                 bit, drv_type);
1742                         return -EINVAL;
1743                 }
1744                 break;
1745         case DRV_TYPE_IO_DEFAULT:
1746         case DRV_TYPE_IO_1V8_OR_3V0:
1747         case DRV_TYPE_IO_1V8_ONLY:
1748                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1749                 break;
1750         default:
1751                 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
1752                 return -EINVAL;
1753         }
1754
1755 config:
1756         /* enable the write to the equivalent lower bits */
1757         data = ((1 << rmask_bits) - 1) << (bit + 16);
1758         rmask = data | (data >> 16);
1759         data |= (ret << bit);
1760
1761         ret = regmap_update_bits(regmap, reg, rmask, data);
1762
1763         return ret;
1764 }
1765
1766 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1767         {
1768                 PIN_CONFIG_BIAS_DISABLE,
1769                 PIN_CONFIG_BIAS_PULL_UP,
1770                 PIN_CONFIG_BIAS_PULL_DOWN,
1771                 PIN_CONFIG_BIAS_BUS_HOLD
1772         },
1773         {
1774                 PIN_CONFIG_BIAS_DISABLE,
1775                 PIN_CONFIG_BIAS_PULL_DOWN,
1776                 PIN_CONFIG_BIAS_DISABLE,
1777                 PIN_CONFIG_BIAS_PULL_UP
1778         },
1779 };
1780
1781 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1782 {
1783         struct rockchip_pinctrl *info = bank->drvdata;
1784         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1785         struct device *dev = info->dev;
1786         struct regmap *regmap;
1787         int reg, ret, pull_type;
1788         u8 bit;
1789         u32 data;
1790
1791         /* rk3066b does support any pulls */
1792         if (ctrl->type == RK3066B)
1793                 return PIN_CONFIG_BIAS_DISABLE;
1794
1795         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1796
1797         ret = regmap_read(regmap, reg, &data);
1798         if (ret)
1799                 return ret;
1800
1801         switch (ctrl->type) {
1802         case RK2928:
1803         case RK3128:
1804                 return !(data & BIT(bit))
1805                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1806                                 : PIN_CONFIG_BIAS_DISABLE;
1807         case PX30:
1808         case RV1108:
1809         case RK3188:
1810         case RK3288:
1811         case RK3308:
1812         case RK3368:
1813         case RK3399:
1814                 pull_type = bank->pull_type[pin_num / 8];
1815                 data >>= bit;
1816                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1817
1818                 return rockchip_pull_list[pull_type][data];
1819         default:
1820                 dev_err(dev, "unsupported pinctrl type\n");
1821                 return -EINVAL;
1822         };
1823 }
1824
1825 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1826                                         int pin_num, int pull)
1827 {
1828         struct rockchip_pinctrl *info = bank->drvdata;
1829         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1830         struct device *dev = info->dev;
1831         struct regmap *regmap;
1832         int reg, ret, i, pull_type;
1833         u8 bit;
1834         u32 data, rmask;
1835
1836         dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
1837
1838         /* rk3066b does support any pulls */
1839         if (ctrl->type == RK3066B)
1840                 return pull ? -EINVAL : 0;
1841
1842         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1843
1844         switch (ctrl->type) {
1845         case RK2928:
1846         case RK3128:
1847                 data = BIT(bit + 16);
1848                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1849                         data |= BIT(bit);
1850                 ret = regmap_write(regmap, reg, data);
1851                 break;
1852         case PX30:
1853         case RV1108:
1854         case RK3188:
1855         case RK3288:
1856         case RK3308:
1857         case RK3368:
1858         case RK3399:
1859         case RK3568:
1860                 pull_type = bank->pull_type[pin_num / 8];
1861                 ret = -EINVAL;
1862                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1863                         i++) {
1864                         if (rockchip_pull_list[pull_type][i] == pull) {
1865                                 ret = i;
1866                                 break;
1867                         }
1868                 }
1869                 /*
1870                  * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
1871                  * where that pull up value becomes 3.
1872                  */
1873                 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
1874                         if (ret == 1)
1875                                 ret = 3;
1876                 }
1877
1878                 if (ret < 0) {
1879                         dev_err(dev, "unsupported pull setting %d\n", pull);
1880                         return ret;
1881                 }
1882
1883                 /* enable the write to the equivalent lower bits */
1884                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1885                 rmask = data | (data >> 16);
1886                 data |= (ret << bit);
1887
1888                 ret = regmap_update_bits(regmap, reg, rmask, data);
1889                 break;
1890         default:
1891                 dev_err(dev, "unsupported pinctrl type\n");
1892                 return -EINVAL;
1893         }
1894
1895         return ret;
1896 }
1897
1898 #define RK3328_SCHMITT_BITS_PER_PIN             1
1899 #define RK3328_SCHMITT_PINS_PER_REG             16
1900 #define RK3328_SCHMITT_BANK_STRIDE              8
1901 #define RK3328_SCHMITT_GRF_OFFSET               0x380
1902
1903 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1904                                            int pin_num,
1905                                            struct regmap **regmap,
1906                                            int *reg, u8 *bit)
1907 {
1908         struct rockchip_pinctrl *info = bank->drvdata;
1909
1910         *regmap = info->regmap_base;
1911         *reg = RK3328_SCHMITT_GRF_OFFSET;
1912
1913         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1914         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1915         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1916
1917         return 0;
1918 }
1919
1920 #define RK3568_SCHMITT_BITS_PER_PIN             2
1921 #define RK3568_SCHMITT_PINS_PER_REG             8
1922 #define RK3568_SCHMITT_BANK_STRIDE              0x10
1923 #define RK3568_SCHMITT_GRF_OFFSET               0xc0
1924 #define RK3568_SCHMITT_PMUGRF_OFFSET            0x30
1925
1926 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1927                                            int pin_num,
1928                                            struct regmap **regmap,
1929                                            int *reg, u8 *bit)
1930 {
1931         struct rockchip_pinctrl *info = bank->drvdata;
1932
1933         if (bank->bank_num == 0) {
1934                 *regmap = info->regmap_pmu;
1935                 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
1936         } else {
1937                 *regmap = info->regmap_base;
1938                 *reg = RK3568_SCHMITT_GRF_OFFSET;
1939                 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
1940         }
1941
1942         *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
1943         *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
1944         *bit *= RK3568_SCHMITT_BITS_PER_PIN;
1945
1946         return 0;
1947 }
1948
1949 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1950 {
1951         struct rockchip_pinctrl *info = bank->drvdata;
1952         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1953         struct regmap *regmap;
1954         int reg, ret;
1955         u8 bit;
1956         u32 data;
1957
1958         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1959         if (ret)
1960                 return ret;
1961
1962         ret = regmap_read(regmap, reg, &data);
1963         if (ret)
1964                 return ret;
1965
1966         data >>= bit;
1967         switch (ctrl->type) {
1968         case RK3568:
1969                 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
1970         default:
1971                 break;
1972         }
1973
1974         return data & 0x1;
1975 }
1976
1977 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1978                                 int pin_num, int enable)
1979 {
1980         struct rockchip_pinctrl *info = bank->drvdata;
1981         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1982         struct device *dev = info->dev;
1983         struct regmap *regmap;
1984         int reg, ret;
1985         u8 bit;
1986         u32 data, rmask;
1987
1988         dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
1989                 bank->bank_num, pin_num, enable);
1990
1991         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1992         if (ret)
1993                 return ret;
1994
1995         /* enable the write to the equivalent lower bits */
1996         switch (ctrl->type) {
1997         case RK3568:
1998                 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
1999                 rmask = data | (data >> 16);
2000                 data |= ((enable ? 0x2 : 0x1) << bit);
2001                 break;
2002         default:
2003                 data = BIT(bit + 16) | (enable << bit);
2004                 rmask = BIT(bit + 16) | BIT(bit);
2005                 break;
2006         }
2007
2008         return regmap_update_bits(regmap, reg, rmask, data);
2009 }
2010
2011 /*
2012  * Pinmux_ops handling
2013  */
2014
2015 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2016 {
2017         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2018
2019         return info->nfunctions;
2020 }
2021
2022 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2023                                           unsigned selector)
2024 {
2025         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2026
2027         return info->functions[selector].name;
2028 }
2029
2030 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2031                                 unsigned selector, const char * const **groups,
2032                                 unsigned * const num_groups)
2033 {
2034         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2035
2036         *groups = info->functions[selector].groups;
2037         *num_groups = info->functions[selector].ngroups;
2038
2039         return 0;
2040 }
2041
2042 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2043                             unsigned group)
2044 {
2045         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2046         const unsigned int *pins = info->groups[group].pins;
2047         const struct rockchip_pin_config *data = info->groups[group].data;
2048         struct device *dev = info->dev;
2049         struct rockchip_pin_bank *bank;
2050         int cnt, ret = 0;
2051
2052         dev_dbg(dev, "enable function %s group %s\n",
2053                 info->functions[selector].name, info->groups[group].name);
2054
2055         /*
2056          * for each pin in the pin group selected, program the corresponding
2057          * pin function number in the config register.
2058          */
2059         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2060                 bank = pin_to_bank(info, pins[cnt]);
2061                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2062                                        data[cnt].func);
2063                 if (ret)
2064                         break;
2065         }
2066
2067         if (ret) {
2068                 /* revert the already done pin settings */
2069                 for (cnt--; cnt >= 0; cnt--)
2070                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2071
2072                 return ret;
2073         }
2074
2075         return 0;
2076 }
2077
2078 static const struct pinmux_ops rockchip_pmx_ops = {
2079         .get_functions_count    = rockchip_pmx_get_funcs_count,
2080         .get_function_name      = rockchip_pmx_get_func_name,
2081         .get_function_groups    = rockchip_pmx_get_groups,
2082         .set_mux                = rockchip_pmx_set,
2083 };
2084
2085 /*
2086  * Pinconf_ops handling
2087  */
2088
2089 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2090                                         enum pin_config_param pull)
2091 {
2092         switch (ctrl->type) {
2093         case RK2928:
2094         case RK3128:
2095                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2096                                         pull == PIN_CONFIG_BIAS_DISABLE);
2097         case RK3066B:
2098                 return pull ? false : true;
2099         case PX30:
2100         case RV1108:
2101         case RK3188:
2102         case RK3288:
2103         case RK3308:
2104         case RK3368:
2105         case RK3399:
2106         case RK3568:
2107                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2108         }
2109
2110         return false;
2111 }
2112
2113 static int rockchip_pinconf_defer_output(struct rockchip_pin_bank *bank,
2114                                          unsigned int pin, u32 arg)
2115 {
2116         struct rockchip_pin_output_deferred *cfg;
2117
2118         cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2119         if (!cfg)
2120                 return -ENOMEM;
2121
2122         cfg->pin = pin;
2123         cfg->arg = arg;
2124
2125         list_add_tail(&cfg->head, &bank->deferred_output);
2126
2127         return 0;
2128 }
2129
2130 /* set the pin config settings for a specified pin */
2131 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2132                                 unsigned long *configs, unsigned num_configs)
2133 {
2134         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2135         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2136         struct gpio_chip *gpio = &bank->gpio_chip;
2137         enum pin_config_param param;
2138         u32 arg;
2139         int i;
2140         int rc;
2141
2142         for (i = 0; i < num_configs; i++) {
2143                 param = pinconf_to_config_param(configs[i]);
2144                 arg = pinconf_to_config_argument(configs[i]);
2145
2146                 switch (param) {
2147                 case PIN_CONFIG_BIAS_DISABLE:
2148                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2149                                 param);
2150                         if (rc)
2151                                 return rc;
2152                         break;
2153                 case PIN_CONFIG_BIAS_PULL_UP:
2154                 case PIN_CONFIG_BIAS_PULL_DOWN:
2155                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2156                 case PIN_CONFIG_BIAS_BUS_HOLD:
2157                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2158                                 return -ENOTSUPP;
2159
2160                         if (!arg)
2161                                 return -EINVAL;
2162
2163                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2164                                 param);
2165                         if (rc)
2166                                 return rc;
2167                         break;
2168                 case PIN_CONFIG_OUTPUT:
2169                         rc = rockchip_set_mux(bank, pin - bank->pin_base,
2170                                               RK_FUNC_GPIO);
2171                         if (rc != RK_FUNC_GPIO)
2172                                 return -EINVAL;
2173
2174                         /*
2175                          * Check for gpio driver not being probed yet.
2176                          * The lock makes sure that either gpio-probe has completed
2177                          * or the gpio driver hasn't probed yet.
2178                          */
2179                         mutex_lock(&bank->deferred_lock);
2180                         if (!gpio || !gpio->direction_output) {
2181                                 rc = rockchip_pinconf_defer_output(bank, pin - bank->pin_base, arg);
2182                                 mutex_unlock(&bank->deferred_lock);
2183                                 if (rc)
2184                                         return rc;
2185
2186                                 break;
2187                         }
2188                         mutex_unlock(&bank->deferred_lock);
2189
2190                         rc = gpio->direction_output(gpio, pin - bank->pin_base,
2191                                                     arg);
2192                         if (rc)
2193                                 return rc;
2194                         break;
2195                 case PIN_CONFIG_DRIVE_STRENGTH:
2196                         /* rk3288 is the first with per-pin drive-strength */
2197                         if (!info->ctrl->drv_calc_reg)
2198                                 return -ENOTSUPP;
2199
2200                         rc = rockchip_set_drive_perpin(bank,
2201                                                 pin - bank->pin_base, arg);
2202                         if (rc < 0)
2203                                 return rc;
2204                         break;
2205                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2206                         if (!info->ctrl->schmitt_calc_reg)
2207                                 return -ENOTSUPP;
2208
2209                         rc = rockchip_set_schmitt(bank,
2210                                                   pin - bank->pin_base, arg);
2211                         if (rc < 0)
2212                                 return rc;
2213                         break;
2214                 default:
2215                         return -ENOTSUPP;
2216                         break;
2217                 }
2218         } /* for each config */
2219
2220         return 0;
2221 }
2222
2223 /* get the pin config settings for a specified pin */
2224 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2225                                                         unsigned long *config)
2226 {
2227         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2228         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2229         struct gpio_chip *gpio = &bank->gpio_chip;
2230         enum pin_config_param param = pinconf_to_config_param(*config);
2231         u16 arg;
2232         int rc;
2233
2234         switch (param) {
2235         case PIN_CONFIG_BIAS_DISABLE:
2236                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2237                         return -EINVAL;
2238
2239                 arg = 0;
2240                 break;
2241         case PIN_CONFIG_BIAS_PULL_UP:
2242         case PIN_CONFIG_BIAS_PULL_DOWN:
2243         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2244         case PIN_CONFIG_BIAS_BUS_HOLD:
2245                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2246                         return -ENOTSUPP;
2247
2248                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2249                         return -EINVAL;
2250
2251                 arg = 1;
2252                 break;
2253         case PIN_CONFIG_OUTPUT:
2254                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2255                 if (rc != RK_FUNC_GPIO)
2256                         return -EINVAL;
2257
2258                 if (!gpio || !gpio->get) {
2259                         arg = 0;
2260                         break;
2261                 }
2262
2263                 rc = gpio->get(gpio, pin - bank->pin_base);
2264                 if (rc < 0)
2265                         return rc;
2266
2267                 arg = rc ? 1 : 0;
2268                 break;
2269         case PIN_CONFIG_DRIVE_STRENGTH:
2270                 /* rk3288 is the first with per-pin drive-strength */
2271                 if (!info->ctrl->drv_calc_reg)
2272                         return -ENOTSUPP;
2273
2274                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2275                 if (rc < 0)
2276                         return rc;
2277
2278                 arg = rc;
2279                 break;
2280         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2281                 if (!info->ctrl->schmitt_calc_reg)
2282                         return -ENOTSUPP;
2283
2284                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2285                 if (rc < 0)
2286                         return rc;
2287
2288                 arg = rc;
2289                 break;
2290         default:
2291                 return -ENOTSUPP;
2292                 break;
2293         }
2294
2295         *config = pinconf_to_config_packed(param, arg);
2296
2297         return 0;
2298 }
2299
2300 static const struct pinconf_ops rockchip_pinconf_ops = {
2301         .pin_config_get                 = rockchip_pinconf_get,
2302         .pin_config_set                 = rockchip_pinconf_set,
2303         .is_generic                     = true,
2304 };
2305
2306 static const struct of_device_id rockchip_bank_match[] = {
2307         { .compatible = "rockchip,gpio-bank" },
2308         { .compatible = "rockchip,rk3188-gpio-bank0" },
2309         {},
2310 };
2311
2312 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2313                                                 struct device_node *np)
2314 {
2315         struct device_node *child;
2316
2317         for_each_child_of_node(np, child) {
2318                 if (of_match_node(rockchip_bank_match, child))
2319                         continue;
2320
2321                 info->nfunctions++;
2322                 info->ngroups += of_get_child_count(child);
2323         }
2324 }
2325
2326 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2327                                               struct rockchip_pin_group *grp,
2328                                               struct rockchip_pinctrl *info,
2329                                               u32 index)
2330 {
2331         struct device *dev = info->dev;
2332         struct rockchip_pin_bank *bank;
2333         int size;
2334         const __be32 *list;
2335         int num;
2336         int i, j;
2337         int ret;
2338
2339         dev_dbg(dev, "group(%d): %pOFn\n", index, np);
2340
2341         /* Initialise group */
2342         grp->name = np->name;
2343
2344         /*
2345          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2346          * do sanity check and calculate pins number
2347          */
2348         list = of_get_property(np, "rockchip,pins", &size);
2349         /* we do not check return since it's safe node passed down */
2350         size /= sizeof(*list);
2351         if (!size || size % 4)
2352                 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
2353
2354         grp->npins = size / 4;
2355
2356         grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
2357         grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
2358         if (!grp->pins || !grp->data)
2359                 return -ENOMEM;
2360
2361         for (i = 0, j = 0; i < size; i += 4, j++) {
2362                 const __be32 *phandle;
2363                 struct device_node *np_config;
2364
2365                 num = be32_to_cpu(*list++);
2366                 bank = bank_num_to_bank(info, num);
2367                 if (IS_ERR(bank))
2368                         return PTR_ERR(bank);
2369
2370                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2371                 grp->data[j].func = be32_to_cpu(*list++);
2372
2373                 phandle = list++;
2374                 if (!phandle)
2375                         return -EINVAL;
2376
2377                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2378                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2379                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2380                 if (ret)
2381                         return ret;
2382         }
2383
2384         return 0;
2385 }
2386
2387 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2388                                                 struct rockchip_pinctrl *info,
2389                                                 u32 index)
2390 {
2391         struct device *dev = info->dev;
2392         struct device_node *child;
2393         struct rockchip_pmx_func *func;
2394         struct rockchip_pin_group *grp;
2395         int ret;
2396         static u32 grp_index;
2397         u32 i = 0;
2398
2399         dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
2400
2401         func = &info->functions[index];
2402
2403         /* Initialise function */
2404         func->name = np->name;
2405         func->ngroups = of_get_child_count(np);
2406         if (func->ngroups <= 0)
2407                 return 0;
2408
2409         func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
2410         if (!func->groups)
2411                 return -ENOMEM;
2412
2413         for_each_child_of_node(np, child) {
2414                 func->groups[i] = child->name;
2415                 grp = &info->groups[grp_index++];
2416                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2417                 if (ret) {
2418                         of_node_put(child);
2419                         return ret;
2420                 }
2421         }
2422
2423         return 0;
2424 }
2425
2426 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2427                                               struct rockchip_pinctrl *info)
2428 {
2429         struct device *dev = &pdev->dev;
2430         struct device_node *np = dev->of_node;
2431         struct device_node *child;
2432         int ret;
2433         int i;
2434
2435         rockchip_pinctrl_child_count(info, np);
2436
2437         dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
2438         dev_dbg(dev, "ngroups = %d\n", info->ngroups);
2439
2440         info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
2441         if (!info->functions)
2442                 return -ENOMEM;
2443
2444         info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
2445         if (!info->groups)
2446                 return -ENOMEM;
2447
2448         i = 0;
2449
2450         for_each_child_of_node(np, child) {
2451                 if (of_match_node(rockchip_bank_match, child))
2452                         continue;
2453
2454                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2455                 if (ret) {
2456                         dev_err(dev, "failed to parse function\n");
2457                         of_node_put(child);
2458                         return ret;
2459                 }
2460         }
2461
2462         return 0;
2463 }
2464
2465 static int rockchip_pinctrl_register(struct platform_device *pdev,
2466                                         struct rockchip_pinctrl *info)
2467 {
2468         struct pinctrl_desc *ctrldesc = &info->pctl;
2469         struct pinctrl_pin_desc *pindesc, *pdesc;
2470         struct rockchip_pin_bank *pin_bank;
2471         struct device *dev = &pdev->dev;
2472         char **pin_names;
2473         int pin, bank, ret;
2474         int k;
2475
2476         ctrldesc->name = "rockchip-pinctrl";
2477         ctrldesc->owner = THIS_MODULE;
2478         ctrldesc->pctlops = &rockchip_pctrl_ops;
2479         ctrldesc->pmxops = &rockchip_pmx_ops;
2480         ctrldesc->confops = &rockchip_pinconf_ops;
2481
2482         pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
2483         if (!pindesc)
2484                 return -ENOMEM;
2485
2486         ctrldesc->pins = pindesc;
2487         ctrldesc->npins = info->ctrl->nr_pins;
2488
2489         pdesc = pindesc;
2490         for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
2491                 pin_bank = &info->ctrl->pin_banks[bank];
2492
2493                 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins);
2494                 if (IS_ERR(pin_names))
2495                         return PTR_ERR(pin_names);
2496
2497                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2498                         pdesc->number = k;
2499                         pdesc->name = pin_names[pin];
2500                         pdesc++;
2501                 }
2502
2503                 INIT_LIST_HEAD(&pin_bank->deferred_output);
2504                 mutex_init(&pin_bank->deferred_lock);
2505         }
2506
2507         ret = rockchip_pinctrl_parse_dt(pdev, info);
2508         if (ret)
2509                 return ret;
2510
2511         info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
2512         if (IS_ERR(info->pctl_dev))
2513                 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
2514
2515         return 0;
2516 }
2517
2518 static const struct of_device_id rockchip_pinctrl_dt_match[];
2519
2520 /* retrieve the soc specific data */
2521 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2522                                                 struct rockchip_pinctrl *d,
2523                                                 struct platform_device *pdev)
2524 {
2525         struct device *dev = &pdev->dev;
2526         struct device_node *node = dev->of_node;
2527         const struct of_device_id *match;
2528         struct rockchip_pin_ctrl *ctrl;
2529         struct rockchip_pin_bank *bank;
2530         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2531
2532         match = of_match_node(rockchip_pinctrl_dt_match, node);
2533         ctrl = (struct rockchip_pin_ctrl *)match->data;
2534
2535         grf_offs = ctrl->grf_mux_offset;
2536         pmu_offs = ctrl->pmu_mux_offset;
2537         drv_pmu_offs = ctrl->pmu_drv_offset;
2538         drv_grf_offs = ctrl->grf_drv_offset;
2539         bank = ctrl->pin_banks;
2540         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2541                 int bank_pins = 0;
2542
2543                 raw_spin_lock_init(&bank->slock);
2544                 bank->drvdata = d;
2545                 bank->pin_base = ctrl->nr_pins;
2546                 ctrl->nr_pins += bank->nr_pins;
2547
2548                 /* calculate iomux and drv offsets */
2549                 for (j = 0; j < 4; j++) {
2550                         struct rockchip_iomux *iom = &bank->iomux[j];
2551                         struct rockchip_drv *drv = &bank->drv[j];
2552                         int inc;
2553
2554                         if (bank_pins >= bank->nr_pins)
2555                                 break;
2556
2557                         /* preset iomux offset value, set new start value */
2558                         if (iom->offset >= 0) {
2559                                 if (iom->type & IOMUX_SOURCE_PMU)
2560                                         pmu_offs = iom->offset;
2561                                 else
2562                                         grf_offs = iom->offset;
2563                         } else { /* set current iomux offset */
2564                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2565                                                         pmu_offs : grf_offs;
2566                         }
2567
2568                         /* preset drv offset value, set new start value */
2569                         if (drv->offset >= 0) {
2570                                 if (iom->type & IOMUX_SOURCE_PMU)
2571                                         drv_pmu_offs = drv->offset;
2572                                 else
2573                                         drv_grf_offs = drv->offset;
2574                         } else { /* set current drv offset */
2575                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2576                                                 drv_pmu_offs : drv_grf_offs;
2577                         }
2578
2579                         dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2580                                 i, j, iom->offset, drv->offset);
2581
2582                         /*
2583                          * Increase offset according to iomux width.
2584                          * 4bit iomux'es are spread over two registers.
2585                          */
2586                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
2587                                             IOMUX_WIDTH_3BIT |
2588                                             IOMUX_WIDTH_2BIT)) ? 8 : 4;
2589                         if (iom->type & IOMUX_SOURCE_PMU)
2590                                 pmu_offs += inc;
2591                         else
2592                                 grf_offs += inc;
2593
2594                         /*
2595                          * Increase offset according to drv width.
2596                          * 3bit drive-strenth'es are spread over two registers.
2597                          */
2598                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2599                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2600                                 inc = 8;
2601                         else
2602                                 inc = 4;
2603
2604                         if (iom->type & IOMUX_SOURCE_PMU)
2605                                 drv_pmu_offs += inc;
2606                         else
2607                                 drv_grf_offs += inc;
2608
2609                         bank_pins += 8;
2610                 }
2611
2612                 /* calculate the per-bank recalced_mask */
2613                 for (j = 0; j < ctrl->niomux_recalced; j++) {
2614                         int pin = 0;
2615
2616                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
2617                                 pin = ctrl->iomux_recalced[j].pin;
2618                                 bank->recalced_mask |= BIT(pin);
2619                         }
2620                 }
2621
2622                 /* calculate the per-bank route_mask */
2623                 for (j = 0; j < ctrl->niomux_routes; j++) {
2624                         int pin = 0;
2625
2626                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
2627                                 pin = ctrl->iomux_routes[j].pin;
2628                                 bank->route_mask |= BIT(pin);
2629                         }
2630                 }
2631         }
2632
2633         return ctrl;
2634 }
2635
2636 #define RK3288_GRF_GPIO6C_IOMUX         0x64
2637 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
2638
2639 static u32 rk3288_grf_gpio6c_iomux;
2640
2641 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2642 {
2643         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2644         int ret = pinctrl_force_sleep(info->pctl_dev);
2645
2646         if (ret)
2647                 return ret;
2648
2649         /*
2650          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2651          * the setting here, and restore it at resume.
2652          */
2653         if (info->ctrl->type == RK3288) {
2654                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2655                                   &rk3288_grf_gpio6c_iomux);
2656                 if (ret) {
2657                         pinctrl_force_default(info->pctl_dev);
2658                         return ret;
2659                 }
2660         }
2661
2662         return 0;
2663 }
2664
2665 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2666 {
2667         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2668         int ret;
2669
2670         if (info->ctrl->type == RK3288) {
2671                 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2672                                    rk3288_grf_gpio6c_iomux |
2673                                    GPIO6C6_SEL_WRITE_ENABLE);
2674                 if (ret)
2675                         return ret;
2676         }
2677
2678         return pinctrl_force_default(info->pctl_dev);
2679 }
2680
2681 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2682                          rockchip_pinctrl_resume);
2683
2684 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2685 {
2686         struct rockchip_pinctrl *info;
2687         struct device *dev = &pdev->dev;
2688         struct device_node *np = dev->of_node, *node;
2689         struct rockchip_pin_ctrl *ctrl;
2690         struct resource *res;
2691         void __iomem *base;
2692         int ret;
2693
2694         if (!dev->of_node)
2695                 return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
2696
2697         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2698         if (!info)
2699                 return -ENOMEM;
2700
2701         info->dev = dev;
2702
2703         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2704         if (!ctrl)
2705                 return dev_err_probe(dev, -EINVAL, "driver data not available\n");
2706         info->ctrl = ctrl;
2707
2708         node = of_parse_phandle(np, "rockchip,grf", 0);
2709         if (node) {
2710                 info->regmap_base = syscon_node_to_regmap(node);
2711                 of_node_put(node);
2712                 if (IS_ERR(info->regmap_base))
2713                         return PTR_ERR(info->regmap_base);
2714         } else {
2715                 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2716                 if (IS_ERR(base))
2717                         return PTR_ERR(base);
2718
2719                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2720                 rockchip_regmap_config.name = "rockchip,pinctrl";
2721                 info->regmap_base =
2722                         devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
2723
2724                 /* to check for the old dt-bindings */
2725                 info->reg_size = resource_size(res);
2726
2727                 /* Honor the old binding, with pull registers as 2nd resource */
2728                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2729                         base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
2730                         if (IS_ERR(base))
2731                                 return PTR_ERR(base);
2732
2733                         rockchip_regmap_config.max_register = resource_size(res) - 4;
2734                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2735                         info->regmap_pull =
2736                                 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
2737                 }
2738         }
2739
2740         /* try to find the optional reference to the pmu syscon */
2741         node = of_parse_phandle(np, "rockchip,pmu", 0);
2742         if (node) {
2743                 info->regmap_pmu = syscon_node_to_regmap(node);
2744                 of_node_put(node);
2745                 if (IS_ERR(info->regmap_pmu))
2746                         return PTR_ERR(info->regmap_pmu);
2747         }
2748
2749         ret = rockchip_pinctrl_register(pdev, info);
2750         if (ret)
2751                 return ret;
2752
2753         platform_set_drvdata(pdev, info);
2754
2755         ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
2756         if (ret)
2757                 return dev_err_probe(dev, ret, "failed to register gpio device\n");
2758
2759         return 0;
2760 }
2761
2762 static int rockchip_pinctrl_remove(struct platform_device *pdev)
2763 {
2764         struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
2765         struct rockchip_pin_bank *bank;
2766         struct rockchip_pin_output_deferred *cfg;
2767         int i;
2768
2769         of_platform_depopulate(&pdev->dev);
2770
2771         for (i = 0; i < info->ctrl->nr_banks; i++) {
2772                 bank = &info->ctrl->pin_banks[i];
2773
2774                 mutex_lock(&bank->deferred_lock);
2775                 while (!list_empty(&bank->deferred_output)) {
2776                         cfg = list_first_entry(&bank->deferred_output,
2777                                                struct rockchip_pin_output_deferred, head);
2778                         list_del(&cfg->head);
2779                         kfree(cfg);
2780                 }
2781                 mutex_unlock(&bank->deferred_lock);
2782         }
2783
2784         return 0;
2785 }
2786
2787 static struct rockchip_pin_bank px30_pin_banks[] = {
2788         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2789                                              IOMUX_SOURCE_PMU,
2790                                              IOMUX_SOURCE_PMU,
2791                                              IOMUX_SOURCE_PMU
2792                             ),
2793         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
2794                                              IOMUX_WIDTH_4BIT,
2795                                              IOMUX_WIDTH_4BIT,
2796                                              IOMUX_WIDTH_4BIT
2797                             ),
2798         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
2799                                              IOMUX_WIDTH_4BIT,
2800                                              IOMUX_WIDTH_4BIT,
2801                                              IOMUX_WIDTH_4BIT
2802                             ),
2803         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
2804                                              IOMUX_WIDTH_4BIT,
2805                                              IOMUX_WIDTH_4BIT,
2806                                              IOMUX_WIDTH_4BIT
2807                             ),
2808 };
2809
2810 static struct rockchip_pin_ctrl px30_pin_ctrl = {
2811                 .pin_banks              = px30_pin_banks,
2812                 .nr_banks               = ARRAY_SIZE(px30_pin_banks),
2813                 .label                  = "PX30-GPIO",
2814                 .type                   = PX30,
2815                 .grf_mux_offset         = 0x0,
2816                 .pmu_mux_offset         = 0x0,
2817                 .iomux_routes           = px30_mux_route_data,
2818                 .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
2819                 .pull_calc_reg          = px30_calc_pull_reg_and_bit,
2820                 .drv_calc_reg           = px30_calc_drv_reg_and_bit,
2821                 .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
2822 };
2823
2824 static struct rockchip_pin_bank rv1108_pin_banks[] = {
2825         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2826                                              IOMUX_SOURCE_PMU,
2827                                              IOMUX_SOURCE_PMU,
2828                                              IOMUX_SOURCE_PMU),
2829         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2830         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2831         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2832 };
2833
2834 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
2835         .pin_banks              = rv1108_pin_banks,
2836         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
2837         .label                  = "RV1108-GPIO",
2838         .type                   = RV1108,
2839         .grf_mux_offset         = 0x10,
2840         .pmu_mux_offset         = 0x0,
2841         .iomux_recalced         = rv1108_mux_recalced_data,
2842         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
2843         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
2844         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
2845         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
2846 };
2847
2848 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2849         PIN_BANK(0, 32, "gpio0"),
2850         PIN_BANK(1, 32, "gpio1"),
2851         PIN_BANK(2, 32, "gpio2"),
2852         PIN_BANK(3, 32, "gpio3"),
2853 };
2854
2855 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2856                 .pin_banks              = rk2928_pin_banks,
2857                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2858                 .label                  = "RK2928-GPIO",
2859                 .type                   = RK2928,
2860                 .grf_mux_offset         = 0xa8,
2861                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2862 };
2863
2864 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2865         PIN_BANK(0, 32, "gpio0"),
2866         PIN_BANK(1, 32, "gpio1"),
2867         PIN_BANK(2, 32, "gpio2"),
2868 };
2869
2870 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2871                 .pin_banks              = rk3036_pin_banks,
2872                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
2873                 .label                  = "RK3036-GPIO",
2874                 .type                   = RK2928,
2875                 .grf_mux_offset         = 0xa8,
2876                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2877 };
2878
2879 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2880         PIN_BANK(0, 32, "gpio0"),
2881         PIN_BANK(1, 32, "gpio1"),
2882         PIN_BANK(2, 32, "gpio2"),
2883         PIN_BANK(3, 32, "gpio3"),
2884         PIN_BANK(4, 32, "gpio4"),
2885         PIN_BANK(6, 16, "gpio6"),
2886 };
2887
2888 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2889                 .pin_banks              = rk3066a_pin_banks,
2890                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2891                 .label                  = "RK3066a-GPIO",
2892                 .type                   = RK2928,
2893                 .grf_mux_offset         = 0xa8,
2894                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2895 };
2896
2897 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2898         PIN_BANK(0, 32, "gpio0"),
2899         PIN_BANK(1, 32, "gpio1"),
2900         PIN_BANK(2, 32, "gpio2"),
2901         PIN_BANK(3, 32, "gpio3"),
2902 };
2903
2904 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2905                 .pin_banks      = rk3066b_pin_banks,
2906                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2907                 .label          = "RK3066b-GPIO",
2908                 .type           = RK3066B,
2909                 .grf_mux_offset = 0x60,
2910 };
2911
2912 static struct rockchip_pin_bank rk3128_pin_banks[] = {
2913         PIN_BANK(0, 32, "gpio0"),
2914         PIN_BANK(1, 32, "gpio1"),
2915         PIN_BANK(2, 32, "gpio2"),
2916         PIN_BANK(3, 32, "gpio3"),
2917 };
2918
2919 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
2920                 .pin_banks              = rk3128_pin_banks,
2921                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
2922                 .label                  = "RK3128-GPIO",
2923                 .type                   = RK3128,
2924                 .grf_mux_offset         = 0xa8,
2925                 .iomux_recalced         = rk3128_mux_recalced_data,
2926                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
2927                 .iomux_routes           = rk3128_mux_route_data,
2928                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
2929                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
2930 };
2931
2932 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2933         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2934         PIN_BANK(1, 32, "gpio1"),
2935         PIN_BANK(2, 32, "gpio2"),
2936         PIN_BANK(3, 32, "gpio3"),
2937 };
2938
2939 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2940                 .pin_banks              = rk3188_pin_banks,
2941                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2942                 .label                  = "RK3188-GPIO",
2943                 .type                   = RK3188,
2944                 .grf_mux_offset         = 0x60,
2945                 .iomux_routes           = rk3188_mux_route_data,
2946                 .niomux_routes          = ARRAY_SIZE(rk3188_mux_route_data),
2947                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2948 };
2949
2950 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2951         PIN_BANK(0, 32, "gpio0"),
2952         PIN_BANK(1, 32, "gpio1"),
2953         PIN_BANK(2, 32, "gpio2"),
2954         PIN_BANK(3, 32, "gpio3"),
2955 };
2956
2957 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2958                 .pin_banks              = rk3228_pin_banks,
2959                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
2960                 .label                  = "RK3228-GPIO",
2961                 .type                   = RK3288,
2962                 .grf_mux_offset         = 0x0,
2963                 .iomux_routes           = rk3228_mux_route_data,
2964                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
2965                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
2966                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
2967 };
2968
2969 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2970         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2971                                              IOMUX_SOURCE_PMU,
2972                                              IOMUX_SOURCE_PMU,
2973                                              IOMUX_UNROUTED
2974                             ),
2975         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2976                                              IOMUX_UNROUTED,
2977                                              IOMUX_UNROUTED,
2978                                              0
2979                             ),
2980         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2981         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2982         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2983                                              IOMUX_WIDTH_4BIT,
2984                                              0,
2985                                              0
2986                             ),
2987         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2988                                              0,
2989                                              0,
2990                                              IOMUX_UNROUTED
2991                             ),
2992         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2993         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2994                                              0,
2995                                              IOMUX_WIDTH_4BIT,
2996                                              IOMUX_UNROUTED
2997                             ),
2998         PIN_BANK(8, 16, "gpio8"),
2999 };
3000
3001 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3002                 .pin_banks              = rk3288_pin_banks,
3003                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3004                 .label                  = "RK3288-GPIO",
3005                 .type                   = RK3288,
3006                 .grf_mux_offset         = 0x0,
3007                 .pmu_mux_offset         = 0x84,
3008                 .iomux_routes           = rk3288_mux_route_data,
3009                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
3010                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3011                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3012 };
3013
3014 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3015         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3016                                              IOMUX_WIDTH_2BIT,
3017                                              IOMUX_WIDTH_2BIT,
3018                                              IOMUX_WIDTH_2BIT),
3019         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3020                                              IOMUX_WIDTH_2BIT,
3021                                              IOMUX_WIDTH_2BIT,
3022                                              IOMUX_WIDTH_2BIT),
3023         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3024                                              IOMUX_WIDTH_2BIT,
3025                                              IOMUX_WIDTH_2BIT,
3026                                              IOMUX_WIDTH_2BIT),
3027         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3028                                              IOMUX_WIDTH_2BIT,
3029                                              IOMUX_WIDTH_2BIT,
3030                                              IOMUX_WIDTH_2BIT),
3031         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3032                                              IOMUX_WIDTH_2BIT,
3033                                              IOMUX_WIDTH_2BIT,
3034                                              IOMUX_WIDTH_2BIT),
3035 };
3036
3037 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3038                 .pin_banks              = rk3308_pin_banks,
3039                 .nr_banks               = ARRAY_SIZE(rk3308_pin_banks),
3040                 .label                  = "RK3308-GPIO",
3041                 .type                   = RK3308,
3042                 .grf_mux_offset         = 0x0,
3043                 .iomux_recalced         = rk3308_mux_recalced_data,
3044                 .niomux_recalced        = ARRAY_SIZE(rk3308_mux_recalced_data),
3045                 .iomux_routes           = rk3308_mux_route_data,
3046                 .niomux_routes          = ARRAY_SIZE(rk3308_mux_route_data),
3047                 .pull_calc_reg          = rk3308_calc_pull_reg_and_bit,
3048                 .drv_calc_reg           = rk3308_calc_drv_reg_and_bit,
3049                 .schmitt_calc_reg       = rk3308_calc_schmitt_reg_and_bit,
3050 };
3051
3052 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3053         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3054         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3055         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3056                              IOMUX_WIDTH_3BIT,
3057                              IOMUX_WIDTH_3BIT,
3058                              0),
3059         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3060                              IOMUX_WIDTH_3BIT,
3061                              IOMUX_WIDTH_3BIT,
3062                              0,
3063                              0),
3064 };
3065
3066 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3067                 .pin_banks              = rk3328_pin_banks,
3068                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3069                 .label                  = "RK3328-GPIO",
3070                 .type                   = RK3288,
3071                 .grf_mux_offset         = 0x0,
3072                 .iomux_recalced         = rk3328_mux_recalced_data,
3073                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
3074                 .iomux_routes           = rk3328_mux_route_data,
3075                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
3076                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3077                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3078                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
3079 };
3080
3081 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3082         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3083                                              IOMUX_SOURCE_PMU,
3084                                              IOMUX_SOURCE_PMU,
3085                                              IOMUX_SOURCE_PMU
3086                             ),
3087         PIN_BANK(1, 32, "gpio1"),
3088         PIN_BANK(2, 32, "gpio2"),
3089         PIN_BANK(3, 32, "gpio3"),
3090 };
3091
3092 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3093                 .pin_banks              = rk3368_pin_banks,
3094                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3095                 .label                  = "RK3368-GPIO",
3096                 .type                   = RK3368,
3097                 .grf_mux_offset         = 0x0,
3098                 .pmu_mux_offset         = 0x0,
3099                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3100                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3101 };
3102
3103 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3104         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3105                                                          IOMUX_SOURCE_PMU,
3106                                                          IOMUX_SOURCE_PMU,
3107                                                          IOMUX_SOURCE_PMU,
3108                                                          IOMUX_SOURCE_PMU,
3109                                                          DRV_TYPE_IO_1V8_ONLY,
3110                                                          DRV_TYPE_IO_1V8_ONLY,
3111                                                          DRV_TYPE_IO_DEFAULT,
3112                                                          DRV_TYPE_IO_DEFAULT,
3113                                                          0x80,
3114                                                          0x88,
3115                                                          -1,
3116                                                          -1,
3117                                                          PULL_TYPE_IO_1V8_ONLY,
3118                                                          PULL_TYPE_IO_1V8_ONLY,
3119                                                          PULL_TYPE_IO_DEFAULT,
3120                                                          PULL_TYPE_IO_DEFAULT
3121                                                         ),
3122         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3123                                         IOMUX_SOURCE_PMU,
3124                                         IOMUX_SOURCE_PMU,
3125                                         IOMUX_SOURCE_PMU,
3126                                         DRV_TYPE_IO_1V8_OR_3V0,
3127                                         DRV_TYPE_IO_1V8_OR_3V0,
3128                                         DRV_TYPE_IO_1V8_OR_3V0,
3129                                         DRV_TYPE_IO_1V8_OR_3V0,
3130                                         0xa0,
3131                                         0xa8,
3132                                         0xb0,
3133                                         0xb8
3134                                         ),
3135         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3136                                       DRV_TYPE_IO_1V8_OR_3V0,
3137                                       DRV_TYPE_IO_1V8_ONLY,
3138                                       DRV_TYPE_IO_1V8_ONLY,
3139                                       PULL_TYPE_IO_DEFAULT,
3140                                       PULL_TYPE_IO_DEFAULT,
3141                                       PULL_TYPE_IO_1V8_ONLY,
3142                                       PULL_TYPE_IO_1V8_ONLY
3143                                       ),
3144         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3145                            DRV_TYPE_IO_3V3_ONLY,
3146                            DRV_TYPE_IO_3V3_ONLY,
3147                            DRV_TYPE_IO_1V8_OR_3V0
3148                            ),
3149         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3150                            DRV_TYPE_IO_1V8_3V0_AUTO,
3151                            DRV_TYPE_IO_1V8_OR_3V0,
3152                            DRV_TYPE_IO_1V8_OR_3V0
3153                            ),
3154 };
3155
3156 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3157                 .pin_banks              = rk3399_pin_banks,
3158                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3159                 .label                  = "RK3399-GPIO",
3160                 .type                   = RK3399,
3161                 .grf_mux_offset         = 0xe000,
3162                 .pmu_mux_offset         = 0x0,
3163                 .grf_drv_offset         = 0xe100,
3164                 .pmu_drv_offset         = 0x80,
3165                 .iomux_routes           = rk3399_mux_route_data,
3166                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
3167                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3168                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3169 };
3170
3171 static struct rockchip_pin_bank rk3568_pin_banks[] = {
3172         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3173                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3174                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3175                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
3176         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3177                                              IOMUX_WIDTH_4BIT,
3178                                              IOMUX_WIDTH_4BIT,
3179                                              IOMUX_WIDTH_4BIT),
3180         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3181                                              IOMUX_WIDTH_4BIT,
3182                                              IOMUX_WIDTH_4BIT,
3183                                              IOMUX_WIDTH_4BIT),
3184         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3185                                              IOMUX_WIDTH_4BIT,
3186                                              IOMUX_WIDTH_4BIT,
3187                                              IOMUX_WIDTH_4BIT),
3188         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3189                                              IOMUX_WIDTH_4BIT,
3190                                              IOMUX_WIDTH_4BIT,
3191                                              IOMUX_WIDTH_4BIT),
3192 };
3193
3194 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
3195         .pin_banks              = rk3568_pin_banks,
3196         .nr_banks               = ARRAY_SIZE(rk3568_pin_banks),
3197         .label                  = "RK3568-GPIO",
3198         .type                   = RK3568,
3199         .grf_mux_offset         = 0x0,
3200         .pmu_mux_offset         = 0x0,
3201         .grf_drv_offset         = 0x0200,
3202         .pmu_drv_offset         = 0x0070,
3203         .iomux_routes           = rk3568_mux_route_data,
3204         .niomux_routes          = ARRAY_SIZE(rk3568_mux_route_data),
3205         .pull_calc_reg          = rk3568_calc_pull_reg_and_bit,
3206         .drv_calc_reg           = rk3568_calc_drv_reg_and_bit,
3207         .schmitt_calc_reg       = rk3568_calc_schmitt_reg_and_bit,
3208 };
3209
3210 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3211         { .compatible = "rockchip,px30-pinctrl",
3212                 .data = &px30_pin_ctrl },
3213         { .compatible = "rockchip,rv1108-pinctrl",
3214                 .data = &rv1108_pin_ctrl },
3215         { .compatible = "rockchip,rk2928-pinctrl",
3216                 .data = &rk2928_pin_ctrl },
3217         { .compatible = "rockchip,rk3036-pinctrl",
3218                 .data = &rk3036_pin_ctrl },
3219         { .compatible = "rockchip,rk3066a-pinctrl",
3220                 .data = &rk3066a_pin_ctrl },
3221         { .compatible = "rockchip,rk3066b-pinctrl",
3222                 .data = &rk3066b_pin_ctrl },
3223         { .compatible = "rockchip,rk3128-pinctrl",
3224                 .data = (void *)&rk3128_pin_ctrl },
3225         { .compatible = "rockchip,rk3188-pinctrl",
3226                 .data = &rk3188_pin_ctrl },
3227         { .compatible = "rockchip,rk3228-pinctrl",
3228                 .data = &rk3228_pin_ctrl },
3229         { .compatible = "rockchip,rk3288-pinctrl",
3230                 .data = &rk3288_pin_ctrl },
3231         { .compatible = "rockchip,rk3308-pinctrl",
3232                 .data = &rk3308_pin_ctrl },
3233         { .compatible = "rockchip,rk3328-pinctrl",
3234                 .data = &rk3328_pin_ctrl },
3235         { .compatible = "rockchip,rk3368-pinctrl",
3236                 .data = &rk3368_pin_ctrl },
3237         { .compatible = "rockchip,rk3399-pinctrl",
3238                 .data = &rk3399_pin_ctrl },
3239         { .compatible = "rockchip,rk3568-pinctrl",
3240                 .data = &rk3568_pin_ctrl },
3241         {},
3242 };
3243
3244 static struct platform_driver rockchip_pinctrl_driver = {
3245         .probe          = rockchip_pinctrl_probe,
3246         .remove         = rockchip_pinctrl_remove,
3247         .driver = {
3248                 .name   = "rockchip-pinctrl",
3249                 .pm = &rockchip_pinctrl_dev_pm_ops,
3250                 .of_match_table = rockchip_pinctrl_dt_match,
3251         },
3252 };
3253
3254 static int __init rockchip_pinctrl_drv_register(void)
3255 {
3256         return platform_driver_register(&rockchip_pinctrl_driver);
3257 }
3258 postcore_initcall(rockchip_pinctrl_drv_register);
3259
3260 static void __exit rockchip_pinctrl_drv_unregister(void)
3261 {
3262         platform_driver_unregister(&rockchip_pinctrl_driver);
3263 }
3264 module_exit(rockchip_pinctrl_drv_unregister);
3265
3266 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
3267 MODULE_LICENSE("GPL");
3268 MODULE_ALIAS("platform:pinctrl-rockchip");
3269 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);