drivers/pinctrl/pinctrl-bm1880.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Bitmain BM1880 SoC Pinctrl driver
   4  *
   5  * Copyright (c) 2019 Linaro Ltd.
   6  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  */
   8
   9 #include <linux/io.h>
  10 #include <linux/of.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/pinctrl/pinctrl.h>
  13 #include <linux/pinctrl/pinmux.h>
  14 #include <linux/pinctrl/pinconf-generic.h>
  15 #include <linux/slab.h>
  16
  17 #include "core.h"
  18 #include "pinctrl-utils.h"
  19
  20 #define BM1880_REG_MUX 0x20
  21
  22 /**
  23  * struct bm1880_pinctrl - driver data
  24  * @base:       Pinctrl base address
  25  * @pctrldev:   Pinctrl device
  26  * @groups:     Pingroups
  27  * @ngroups:    Number of @groups
  28  * @funcs:      Pinmux functions
  29  * @nfuncs:     Number of @funcs
  30  * @pinconf:    Pinconf data
  31  */
  32 struct bm1880_pinctrl {
  33         void __iomem *base;
  34         struct pinctrl_dev *pctrldev;
  35         const struct bm1880_pctrl_group *groups;
  36         unsigned int ngroups;
  37         const struct bm1880_pinmux_function *funcs;
  38         unsigned int nfuncs;
  39         const struct bm1880_pinconf_data *pinconf;
  40 };
  41
  42 /**
  43  * struct bm1880_pctrl_group - pinctrl group
  44  * @name:       Name of the group
  45  * @pins:       Array of pins belonging to this group
  46  * @npins:      Number of @pins
  47  */
  48 struct bm1880_pctrl_group {
  49         const char *name;
  50         const unsigned int *pins;
  51         const unsigned int npins;
  52 };
  53
  54 /**
  55  * struct bm1880_pinmux_function - a pinmux function
  56  * @name:       Name of the pinmux function.
  57  * @groups:     List of pingroups for this function.
  58  * @ngroups:    Number of entries in @groups.
  59  * @mux_val:    Selector for this function
  60  * @mux:        Offset of function specific mux
  61  * @mux_shift:  Shift for function specific selector
  62  */
  63 struct bm1880_pinmux_function {
  64         const char *name;
  65         const char * const *groups;
  66         unsigned int ngroups;
  67         u32 mux_val;
  68         u32 mux;
  69         u8 mux_shift;
  70 };
  71
  72 /**
  73  * struct bm1880_pinconf_data - pinconf data
  74  * @drv_bits:   Drive strength bit width
  75  */
  76 struct bm1880_pinconf_data {
  77         u32 drv_bits;
  78 };
  79
  80 static const struct pinctrl_pin_desc bm1880_pins[] = {
  81         PINCTRL_PIN(0,   "MIO0"),
  82         PINCTRL_PIN(1,   "MIO1"),
  83         PINCTRL_PIN(2,   "MIO2"),
  84         PINCTRL_PIN(3,   "MIO3"),
  85         PINCTRL_PIN(4,   "MIO4"),
  86         PINCTRL_PIN(5,   "MIO5"),
  87         PINCTRL_PIN(6,   "MIO6"),
  88         PINCTRL_PIN(7,   "MIO7"),
  89         PINCTRL_PIN(8,   "MIO8"),
  90         PINCTRL_PIN(9,   "MIO9"),
  91         PINCTRL_PIN(10,   "MIO10"),
  92         PINCTRL_PIN(11,   "MIO11"),
  93         PINCTRL_PIN(12,   "MIO12"),
  94         PINCTRL_PIN(13,   "MIO13"),
  95         PINCTRL_PIN(14,   "MIO14"),
  96         PINCTRL_PIN(15,   "MIO15"),
  97         PINCTRL_PIN(16,   "MIO16"),
  98         PINCTRL_PIN(17,   "MIO17"),
  99         PINCTRL_PIN(18,   "MIO18"),
 100         PINCTRL_PIN(19,   "MIO19"),
 101         PINCTRL_PIN(20,   "MIO20"),
 102         PINCTRL_PIN(21,   "MIO21"),
 103         PINCTRL_PIN(22,   "MIO22"),
 104         PINCTRL_PIN(23,   "MIO23"),
 105         PINCTRL_PIN(24,   "MIO24"),
 106         PINCTRL_PIN(25,   "MIO25"),
 107         PINCTRL_PIN(26,   "MIO26"),
 108         PINCTRL_PIN(27,   "MIO27"),
 109         PINCTRL_PIN(28,   "MIO28"),
 110         PINCTRL_PIN(29,   "MIO29"),
 111         PINCTRL_PIN(30,   "MIO30"),
 112         PINCTRL_PIN(31,   "MIO31"),
 113         PINCTRL_PIN(32,   "MIO32"),
 114         PINCTRL_PIN(33,   "MIO33"),
 115         PINCTRL_PIN(34,   "MIO34"),
 116         PINCTRL_PIN(35,   "MIO35"),
 117         PINCTRL_PIN(36,   "MIO36"),
 118         PINCTRL_PIN(37,   "MIO37"),
 119         PINCTRL_PIN(38,   "MIO38"),
 120         PINCTRL_PIN(39,   "MIO39"),
 121         PINCTRL_PIN(40,   "MIO40"),
 122         PINCTRL_PIN(41,   "MIO41"),
 123         PINCTRL_PIN(42,   "MIO42"),
 124         PINCTRL_PIN(43,   "MIO43"),
 125         PINCTRL_PIN(44,   "MIO44"),
 126         PINCTRL_PIN(45,   "MIO45"),
 127         PINCTRL_PIN(46,   "MIO46"),
 128         PINCTRL_PIN(47,   "MIO47"),
 129         PINCTRL_PIN(48,   "MIO48"),
 130         PINCTRL_PIN(49,   "MIO49"),
 131         PINCTRL_PIN(50,   "MIO50"),
 132         PINCTRL_PIN(51,   "MIO51"),
 133         PINCTRL_PIN(52,   "MIO52"),
 134         PINCTRL_PIN(53,   "MIO53"),
 135         PINCTRL_PIN(54,   "MIO54"),
 136         PINCTRL_PIN(55,   "MIO55"),
 137         PINCTRL_PIN(56,   "MIO56"),
 138         PINCTRL_PIN(57,   "MIO57"),
 139         PINCTRL_PIN(58,   "MIO58"),
 140         PINCTRL_PIN(59,   "MIO59"),
 141         PINCTRL_PIN(60,   "MIO60"),
 142         PINCTRL_PIN(61,   "MIO61"),
 143         PINCTRL_PIN(62,   "MIO62"),
 144         PINCTRL_PIN(63,   "MIO63"),
 145         PINCTRL_PIN(64,   "MIO64"),
 146         PINCTRL_PIN(65,   "MIO65"),
 147         PINCTRL_PIN(66,   "MIO66"),
 148         PINCTRL_PIN(67,   "MIO67"),
 149         PINCTRL_PIN(68,   "MIO68"),
 150         PINCTRL_PIN(69,   "MIO69"),
 151         PINCTRL_PIN(70,   "MIO70"),
 152         PINCTRL_PIN(71,   "MIO71"),
 153         PINCTRL_PIN(72,   "MIO72"),
 154         PINCTRL_PIN(73,   "MIO73"),
 155         PINCTRL_PIN(74,   "MIO74"),
 156         PINCTRL_PIN(75,   "MIO75"),
 157         PINCTRL_PIN(76,   "MIO76"),
 158         PINCTRL_PIN(77,   "MIO77"),
 159         PINCTRL_PIN(78,   "MIO78"),
 160         PINCTRL_PIN(79,   "MIO79"),
 161         PINCTRL_PIN(80,   "MIO80"),
 162         PINCTRL_PIN(81,   "MIO81"),
 163         PINCTRL_PIN(82,   "MIO82"),
 164         PINCTRL_PIN(83,   "MIO83"),
 165         PINCTRL_PIN(84,   "MIO84"),
 166         PINCTRL_PIN(85,   "MIO85"),
 167         PINCTRL_PIN(86,   "MIO86"),
 168         PINCTRL_PIN(87,   "MIO87"),
 169         PINCTRL_PIN(88,   "MIO88"),
 170         PINCTRL_PIN(89,   "MIO89"),
 171         PINCTRL_PIN(90,   "MIO90"),
 172         PINCTRL_PIN(91,   "MIO91"),
 173         PINCTRL_PIN(92,   "MIO92"),
 174         PINCTRL_PIN(93,   "MIO93"),
 175         PINCTRL_PIN(94,   "MIO94"),
 176         PINCTRL_PIN(95,   "MIO95"),
 177         PINCTRL_PIN(96,   "MIO96"),
 178         PINCTRL_PIN(97,   "MIO97"),
 179         PINCTRL_PIN(98,   "MIO98"),
 180         PINCTRL_PIN(99,   "MIO99"),
 181         PINCTRL_PIN(100,   "MIO100"),
 182         PINCTRL_PIN(101,   "MIO101"),
 183         PINCTRL_PIN(102,   "MIO102"),
 184         PINCTRL_PIN(103,   "MIO103"),
 185         PINCTRL_PIN(104,   "MIO104"),
 186         PINCTRL_PIN(105,   "MIO105"),
 187         PINCTRL_PIN(106,   "MIO106"),
 188         PINCTRL_PIN(107,   "MIO107"),
 189         PINCTRL_PIN(108,   "MIO108"),
 190         PINCTRL_PIN(109,   "MIO109"),
 191         PINCTRL_PIN(110,   "MIO110"),
 192         PINCTRL_PIN(111,   "MIO111"),
 193 };
 194
 195 enum bm1880_pinmux_functions {
 196         F_nand, F_spi, F_emmc, F_sdio, F_eth0, F_pwm0, F_pwm1, F_pwm2,
 197         F_pwm3, F_pwm4, F_pwm5, F_pwm6, F_pwm7, F_pwm8, F_pwm9, F_pwm10,
 198         F_pwm11, F_pwm12, F_pwm13, F_pwm14, F_pwm15, F_pwm16, F_pwm17,
 199         F_pwm18, F_pwm19, F_pwm20, F_pwm21, F_pwm22, F_pwm23, F_pwm24,
 200         F_pwm25, F_pwm26, F_pwm27, F_pwm28, F_pwm29, F_pwm30, F_pwm31,
 201         F_pwm32, F_pwm33, F_pwm34, F_pwm35, F_pwm36, F_pwm37, F_i2c0, F_i2c1,
 202         F_i2c2, F_i2c3, F_i2c4, F_uart0, F_uart1, F_uart2, F_uart3, F_uart4,
 203         F_uart5, F_uart6, F_uart7, F_uart8, F_uart9, F_uart10, F_uart11,
 204         F_uart12, F_uart13, F_uart14, F_uart15, F_gpio0, F_gpio1, F_gpio2,
 205         F_gpio3, F_gpio4, F_gpio5, F_gpio6, F_gpio7, F_gpio8, F_gpio9, F_gpio10,
 206         F_gpio11, F_gpio12, F_gpio13, F_gpio14, F_gpio15, F_gpio16, F_gpio17,
 207         F_gpio18, F_gpio19, F_gpio20, F_gpio21, F_gpio22, F_gpio23, F_gpio24,
 208         F_gpio25, F_gpio26, F_gpio27, F_gpio28, F_gpio29, F_gpio30, F_gpio31,
 209         F_gpio32, F_gpio33, F_gpio34, F_gpio35, F_gpio36, F_gpio37, F_gpio38,
 210         F_gpio39, F_gpio40, F_gpio41, F_gpio42, F_gpio43, F_gpio44, F_gpio45,
 211         F_gpio46, F_gpio47, F_gpio48, F_gpio49, F_gpio50, F_gpio51, F_gpio52,
 212         F_gpio53, F_gpio54, F_gpio55, F_gpio56, F_gpio57, F_gpio58, F_gpio59,
 213         F_gpio60, F_gpio61, F_gpio62, F_gpio63, F_gpio64, F_gpio65, F_gpio66,
 214         F_gpio67, F_eth1, F_i2s0, F_i2s0_mclkin, F_i2s1, F_i2s1_mclkin, F_spi0,
 215         F_max
 216 };
 217
 218 static const unsigned int nand_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
 219                                           10, 11, 12, 13, 14, 15, 16 };
 220 static const unsigned int spi_pins[] = { 0, 1, 8, 10, 11, 12, 13 };
 221 static const unsigned int emmc_pins[] = { 2, 3, 4, 5, 6, 7, 9, 14, 15, 16 };
 222 static const unsigned int sdio_pins[] = { 17, 18, 19, 20, 21, 22, 23, 24,
 223                                           25, 26 };
 224 static const unsigned int eth0_pins[] = { 27, 28, 29, 30, 31, 32, 33, 34, 35,
 225                                           36, 37, 38, 39, 40, 41, 42 };
 226 static const unsigned int pwm0_pins[] = { 29 };
 227 static const unsigned int pwm1_pins[] = { 30 };
 228 static const unsigned int pwm2_pins[] = { 34 };
 229 static const unsigned int pwm3_pins[] = { 35 };
 230 static const unsigned int pwm4_pins[] = { 43 };
 231 static const unsigned int pwm5_pins[] = { 44 };
 232 static const unsigned int pwm6_pins[] = { 45 };
 233 static const unsigned int pwm7_pins[] = { 46 };
 234 static const unsigned int pwm8_pins[] = { 47 };
 235 static const unsigned int pwm9_pins[] = { 48 };
 236 static const unsigned int pwm10_pins[] = { 49 };
 237 static const unsigned int pwm11_pins[] = { 50 };
 238 static const unsigned int pwm12_pins[] = { 51 };
 239 static const unsigned int pwm13_pins[] = { 52 };
 240 static const unsigned int pwm14_pins[] = { 53 };
 241 static const unsigned int pwm15_pins[] = { 54 };
 242 static const unsigned int pwm16_pins[] = { 55 };
 243 static const unsigned int pwm17_pins[] = { 56 };
 244 static const unsigned int pwm18_pins[] = { 57 };
 245 static const unsigned int pwm19_pins[] = { 58 };
 246 static const unsigned int pwm20_pins[] = { 59 };
 247 static const unsigned int pwm21_pins[] = { 60 };
 248 static const unsigned int pwm22_pins[] = { 61 };
 249 static const unsigned int pwm23_pins[] = { 62 };
 250 static const unsigned int pwm24_pins[] = { 97 };
 251 static const unsigned int pwm25_pins[] = { 98 };
 252 static const unsigned int pwm26_pins[] = { 99 };
 253 static const unsigned int pwm27_pins[] = { 100 };
 254 static const unsigned int pwm28_pins[] = { 101 };
 255 static const unsigned int pwm29_pins[] = { 102 };
 256 static const unsigned int pwm30_pins[] = { 103 };
 257 static const unsigned int pwm31_pins[] = { 104 };
 258 static const unsigned int pwm32_pins[] = { 105 };
 259 static const unsigned int pwm33_pins[] = { 106 };
 260 static const unsigned int pwm34_pins[] = { 107 };
 261 static const unsigned int pwm35_pins[] = { 108 };
 262 static const unsigned int pwm36_pins[] = { 109 };
 263 static const unsigned int pwm37_pins[] = { 110 };
 264 static const unsigned int i2c0_pins[] = { 63, 64 };
 265 static const unsigned int i2c1_pins[] = { 65, 66 };
 266 static const unsigned int i2c2_pins[] = { 67, 68 };
 267 static const unsigned int i2c3_pins[] = { 69, 70 };
 268 static const unsigned int i2c4_pins[] = { 71, 72 };
 269 static const unsigned int uart0_pins[] = { 73, 74 };
 270 static const unsigned int uart1_pins[] = { 75, 76 };
 271 static const unsigned int uart2_pins[] = { 77, 78 };
 272 static const unsigned int uart3_pins[] = { 79, 80 };
 273 static const unsigned int uart4_pins[] = { 81, 82 };
 274 static const unsigned int uart5_pins[] = { 83, 84 };
 275 static const unsigned int uart6_pins[] = { 85, 86 };
 276 static const unsigned int uart7_pins[] = { 87, 88 };
 277 static const unsigned int uart8_pins[] = { 89, 90 };
 278 static const unsigned int uart9_pins[] = { 91, 92 };
 279 static const unsigned int uart10_pins[] = { 93, 94 };
 280 static const unsigned int uart11_pins[] = { 95, 96 };
 281 static const unsigned int uart12_pins[] = { 73, 74, 75, 76 };
 282 static const unsigned int uart13_pins[] = { 77, 78, 83, 84 };
 283 static const unsigned int uart14_pins[] = { 79, 80, 85, 86 };
 284 static const unsigned int uart15_pins[] = { 81, 82, 87, 88 };
 285 static const unsigned int gpio0_pins[] = { 97 };
 286 static const unsigned int gpio1_pins[] = { 98 };
 287 static const unsigned int gpio2_pins[] = { 99 };
 288 static const unsigned int gpio3_pins[] = { 100 };
 289 static const unsigned int gpio4_pins[] = { 101 };
 290 static const unsigned int gpio5_pins[] = { 102 };
 291 static const unsigned int gpio6_pins[] = { 103 };
 292 static const unsigned int gpio7_pins[] = { 104 };
 293 static const unsigned int gpio8_pins[] = { 105 };
 294 static const unsigned int gpio9_pins[] = { 106 };
 295 static const unsigned int gpio10_pins[] = { 107 };
 296 static const unsigned int gpio11_pins[] = { 108 };
 297 static const unsigned int gpio12_pins[] = { 109 };
 298 static const unsigned int gpio13_pins[] = { 110 };
 299 static const unsigned int gpio14_pins[] = { 43 };
 300 static const unsigned int gpio15_pins[] = { 44 };
 301 static const unsigned int gpio16_pins[] = { 45 };
 302 static const unsigned int gpio17_pins[] = { 46 };
 303 static const unsigned int gpio18_pins[] = { 47 };
 304 static const unsigned int gpio19_pins[] = { 48 };
 305 static const unsigned int gpio20_pins[] = { 49 };
 306 static const unsigned int gpio21_pins[] = { 50 };
 307 static const unsigned int gpio22_pins[] = { 51 };
 308 static const unsigned int gpio23_pins[] = { 52 };
 309 static const unsigned int gpio24_pins[] = { 53 };
 310 static const unsigned int gpio25_pins[] = { 54 };
 311 static const unsigned int gpio26_pins[] = { 55 };
 312 static const unsigned int gpio27_pins[] = { 56 };
 313 static const unsigned int gpio28_pins[] = { 57 };
 314 static const unsigned int gpio29_pins[] = { 58 };
 315 static const unsigned int gpio30_pins[] = { 59 };
 316 static const unsigned int gpio31_pins[] = { 60 };
 317 static const unsigned int gpio32_pins[] = { 61 };
 318 static const unsigned int gpio33_pins[] = { 62 };
 319 static const unsigned int gpio34_pins[] = { 63 };
 320 static const unsigned int gpio35_pins[] = { 64 };
 321 static const unsigned int gpio36_pins[] = { 65 };
 322 static const unsigned int gpio37_pins[] = { 66 };
 323 static const unsigned int gpio38_pins[] = { 67 };
 324 static const unsigned int gpio39_pins[] = { 68 };
 325 static const unsigned int gpio40_pins[] = { 69 };
 326 static const unsigned int gpio41_pins[] = { 70 };
 327 static const unsigned int gpio42_pins[] = { 71 };
 328 static const unsigned int gpio43_pins[] = { 72 };
 329 static const unsigned int gpio44_pins[] = { 73 };
 330 static const unsigned int gpio45_pins[] = { 74 };
 331 static const unsigned int gpio46_pins[] = { 75 };
 332 static const unsigned int gpio47_pins[] = { 76 };
 333 static const unsigned int gpio48_pins[] = { 77 };
 334 static const unsigned int gpio49_pins[] = { 78 };
 335 static const unsigned int gpio50_pins[] = { 79 };
 336 static const unsigned int gpio51_pins[] = { 80 };
 337 static const unsigned int gpio52_pins[] = { 81 };
 338 static const unsigned int gpio53_pins[] = { 82 };
 339 static const unsigned int gpio54_pins[] = { 83 };
 340 static const unsigned int gpio55_pins[] = { 84 };
 341 static const unsigned int gpio56_pins[] = { 85 };
 342 static const unsigned int gpio57_pins[] = { 86 };
 343 static const unsigned int gpio58_pins[] = { 87 };
 344 static const unsigned int gpio59_pins[] = { 88 };
 345 static const unsigned int gpio60_pins[] = { 89 };
 346 static const unsigned int gpio61_pins[] = { 90 };
 347 static const unsigned int gpio62_pins[] = { 91 };
 348 static const unsigned int gpio63_pins[] = { 92 };
 349 static const unsigned int gpio64_pins[] = { 93 };
 350 static const unsigned int gpio65_pins[] = { 94 };
 351 static const unsigned int gpio66_pins[] = { 95 };
 352 static const unsigned int gpio67_pins[] = { 96 };
 353 static const unsigned int eth1_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51,
 354                                           52, 53, 54, 55, 56, 57, 58 };
 355 static const unsigned int i2s0_pins[] = { 87, 88, 89, 90, 91 };
 356 static const unsigned int i2s0_mclkin_pins[] = { 97 };
 357 static const unsigned int i2s1_pins[] = { 92, 93, 94, 95, 96 };
 358 static const unsigned int i2s1_mclkin_pins[] = { 98 };
 359 static const unsigned int spi0_pins[] = { 59, 60, 61, 62 };
 360
 361 #define BM1880_PINCTRL_GRP(nm) \
 362         { \
 363                 .name = #nm "_grp", \
 364                 .pins = nm ## _pins, \
 365                 .npins = ARRAY_SIZE(nm ## _pins), \
 366         }
 367
 368 static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = {
 369         BM1880_PINCTRL_GRP(nand),
 370         BM1880_PINCTRL_GRP(spi),
 371         BM1880_PINCTRL_GRP(emmc),
 372         BM1880_PINCTRL_GRP(sdio),
 373         BM1880_PINCTRL_GRP(eth0),
 374         BM1880_PINCTRL_GRP(pwm0),
 375         BM1880_PINCTRL_GRP(pwm1),
 376         BM1880_PINCTRL_GRP(pwm2),
 377         BM1880_PINCTRL_GRP(pwm3),
 378         BM1880_PINCTRL_GRP(pwm4),
 379         BM1880_PINCTRL_GRP(pwm5),
 380         BM1880_PINCTRL_GRP(pwm6),
 381         BM1880_PINCTRL_GRP(pwm7),
 382         BM1880_PINCTRL_GRP(pwm8),
 383         BM1880_PINCTRL_GRP(pwm9),
 384         BM1880_PINCTRL_GRP(pwm10),
 385         BM1880_PINCTRL_GRP(pwm11),
 386         BM1880_PINCTRL_GRP(pwm12),
 387         BM1880_PINCTRL_GRP(pwm13),
 388         BM1880_PINCTRL_GRP(pwm14),
 389         BM1880_PINCTRL_GRP(pwm15),
 390         BM1880_PINCTRL_GRP(pwm16),
 391         BM1880_PINCTRL_GRP(pwm17),
 392         BM1880_PINCTRL_GRP(pwm18),
 393         BM1880_PINCTRL_GRP(pwm19),
 394         BM1880_PINCTRL_GRP(pwm20),
 395         BM1880_PINCTRL_GRP(pwm21),
 396         BM1880_PINCTRL_GRP(pwm22),
 397         BM1880_PINCTRL_GRP(pwm23),
 398         BM1880_PINCTRL_GRP(pwm24),
 399         BM1880_PINCTRL_GRP(pwm25),
 400         BM1880_PINCTRL_GRP(pwm26),
 401         BM1880_PINCTRL_GRP(pwm27),
 402         BM1880_PINCTRL_GRP(pwm28),
 403         BM1880_PINCTRL_GRP(pwm29),
 404         BM1880_PINCTRL_GRP(pwm30),
 405         BM1880_PINCTRL_GRP(pwm31),
 406         BM1880_PINCTRL_GRP(pwm32),
 407         BM1880_PINCTRL_GRP(pwm33),
 408         BM1880_PINCTRL_GRP(pwm34),
 409         BM1880_PINCTRL_GRP(pwm35),
 410         BM1880_PINCTRL_GRP(pwm36),
 411         BM1880_PINCTRL_GRP(pwm37),
 412         BM1880_PINCTRL_GRP(i2c0),
 413         BM1880_PINCTRL_GRP(i2c1),
 414         BM1880_PINCTRL_GRP(i2c2),
 415         BM1880_PINCTRL_GRP(i2c3),
 416         BM1880_PINCTRL_GRP(i2c4),
 417         BM1880_PINCTRL_GRP(uart0),
 418         BM1880_PINCTRL_GRP(uart1),
 419         BM1880_PINCTRL_GRP(uart2),
 420         BM1880_PINCTRL_GRP(uart3),
 421         BM1880_PINCTRL_GRP(uart4),
 422         BM1880_PINCTRL_GRP(uart5),
 423         BM1880_PINCTRL_GRP(uart6),
 424         BM1880_PINCTRL_GRP(uart7),
 425         BM1880_PINCTRL_GRP(uart8),
 426         BM1880_PINCTRL_GRP(uart9),
 427         BM1880_PINCTRL_GRP(uart10),
 428         BM1880_PINCTRL_GRP(uart11),
 429         BM1880_PINCTRL_GRP(uart12),
 430         BM1880_PINCTRL_GRP(uart13),
 431         BM1880_PINCTRL_GRP(uart14),
 432         BM1880_PINCTRL_GRP(uart15),
 433         BM1880_PINCTRL_GRP(gpio0),
 434         BM1880_PINCTRL_GRP(gpio1),
 435         BM1880_PINCTRL_GRP(gpio2),
 436         BM1880_PINCTRL_GRP(gpio3),
 437         BM1880_PINCTRL_GRP(gpio4),
 438         BM1880_PINCTRL_GRP(gpio5),
 439         BM1880_PINCTRL_GRP(gpio6),
 440         BM1880_PINCTRL_GRP(gpio7),
 441         BM1880_PINCTRL_GRP(gpio8),
 442         BM1880_PINCTRL_GRP(gpio9),
 443         BM1880_PINCTRL_GRP(gpio10),
 444         BM1880_PINCTRL_GRP(gpio11),
 445         BM1880_PINCTRL_GRP(gpio12),
 446         BM1880_PINCTRL_GRP(gpio13),
 447         BM1880_PINCTRL_GRP(gpio14),
 448         BM1880_PINCTRL_GRP(gpio15),
 449         BM1880_PINCTRL_GRP(gpio16),
 450         BM1880_PINCTRL_GRP(gpio17),
 451         BM1880_PINCTRL_GRP(gpio18),
 452         BM1880_PINCTRL_GRP(gpio19),
 453         BM1880_PINCTRL_GRP(gpio20),
 454         BM1880_PINCTRL_GRP(gpio21),
 455         BM1880_PINCTRL_GRP(gpio22),
 456         BM1880_PINCTRL_GRP(gpio23),
 457         BM1880_PINCTRL_GRP(gpio24),
 458         BM1880_PINCTRL_GRP(gpio25),
 459         BM1880_PINCTRL_GRP(gpio26),
 460         BM1880_PINCTRL_GRP(gpio27),
 461         BM1880_PINCTRL_GRP(gpio28),
 462         BM1880_PINCTRL_GRP(gpio29),
 463         BM1880_PINCTRL_GRP(gpio30),
 464         BM1880_PINCTRL_GRP(gpio31),
 465         BM1880_PINCTRL_GRP(gpio32),
 466         BM1880_PINCTRL_GRP(gpio33),
 467         BM1880_PINCTRL_GRP(gpio34),
 468         BM1880_PINCTRL_GRP(gpio35),
 469         BM1880_PINCTRL_GRP(gpio36),
 470         BM1880_PINCTRL_GRP(gpio37),
 471         BM1880_PINCTRL_GRP(gpio38),
 472         BM1880_PINCTRL_GRP(gpio39),
 473         BM1880_PINCTRL_GRP(gpio40),
 474         BM1880_PINCTRL_GRP(gpio41),
 475         BM1880_PINCTRL_GRP(gpio42),
 476         BM1880_PINCTRL_GRP(gpio43),
 477         BM1880_PINCTRL_GRP(gpio44),
 478         BM1880_PINCTRL_GRP(gpio45),
 479         BM1880_PINCTRL_GRP(gpio46),
 480         BM1880_PINCTRL_GRP(gpio47),
 481         BM1880_PINCTRL_GRP(gpio48),
 482         BM1880_PINCTRL_GRP(gpio49),
 483         BM1880_PINCTRL_GRP(gpio50),
 484         BM1880_PINCTRL_GRP(gpio51),
 485         BM1880_PINCTRL_GRP(gpio52),
 486         BM1880_PINCTRL_GRP(gpio53),
 487         BM1880_PINCTRL_GRP(gpio54),
 488         BM1880_PINCTRL_GRP(gpio55),
 489         BM1880_PINCTRL_GRP(gpio56),
 490         BM1880_PINCTRL_GRP(gpio57),
 491         BM1880_PINCTRL_GRP(gpio58),
 492         BM1880_PINCTRL_GRP(gpio59),
 493         BM1880_PINCTRL_GRP(gpio60),
 494         BM1880_PINCTRL_GRP(gpio61),
 495         BM1880_PINCTRL_GRP(gpio62),
 496         BM1880_PINCTRL_GRP(gpio63),
 497         BM1880_PINCTRL_GRP(gpio64),
 498         BM1880_PINCTRL_GRP(gpio65),
 499         BM1880_PINCTRL_GRP(gpio66),
 500         BM1880_PINCTRL_GRP(gpio67),
 501         BM1880_PINCTRL_GRP(eth1),
 502         BM1880_PINCTRL_GRP(i2s0),
 503         BM1880_PINCTRL_GRP(i2s0_mclkin),
 504         BM1880_PINCTRL_GRP(i2s1),
 505         BM1880_PINCTRL_GRP(i2s1_mclkin),
 506         BM1880_PINCTRL_GRP(spi0),
 507 };
 508
 509 static const char * const nand_group[] = { "nand_grp" };
 510 static const char * const spi_group[] = { "spi_grp" };
 511 static const char * const emmc_group[] = { "emmc_grp" };
 512 static const char * const sdio_group[] = { "sdio_grp" };
 513 static const char * const eth0_group[] = { "eth0_grp" };
 514 static const char * const pwm0_group[] = { "pwm0_grp" };
 515 static const char * const pwm1_group[] = { "pwm1_grp" };
 516 static const char * const pwm2_group[] = { "pwm2_grp" };
 517 static const char * const pwm3_group[] = { "pwm3_grp" };
 518 static const char * const pwm4_group[] = { "pwm4_grp" };
 519 static const char * const pwm5_group[] = { "pwm5_grp" };
 520 static const char * const pwm6_group[] = { "pwm6_grp" };
 521 static const char * const pwm7_group[] = { "pwm7_grp" };
 522 static const char * const pwm8_group[] = { "pwm8_grp" };
 523 static const char * const pwm9_group[] = { "pwm9_grp" };
 524 static const char * const pwm10_group[] = { "pwm10_grp" };
 525 static const char * const pwm11_group[] = { "pwm11_grp" };
 526 static const char * const pwm12_group[] = { "pwm12_grp" };
 527 static const char * const pwm13_group[] = { "pwm13_grp" };
 528 static const char * const pwm14_group[] = { "pwm14_grp" };
 529 static const char * const pwm15_group[] = { "pwm15_grp" };
 530 static const char * const pwm16_group[] = { "pwm16_grp" };
 531 static const char * const pwm17_group[] = { "pwm17_grp" };
 532 static const char * const pwm18_group[] = { "pwm18_grp" };
 533 static const char * const pwm19_group[] = { "pwm19_grp" };
 534 static const char * const pwm20_group[] = { "pwm20_grp" };
 535 static const char * const pwm21_group[] = { "pwm21_grp" };
 536 static const char * const pwm22_group[] = { "pwm22_grp" };
 537 static const char * const pwm23_group[] = { "pwm23_grp" };
 538 static const char * const pwm24_group[] = { "pwm24_grp" };
 539 static const char * const pwm25_group[] = { "pwm25_grp" };
 540 static const char * const pwm26_group[] = { "pwm26_grp" };
 541 static const char * const pwm27_group[] = { "pwm27_grp" };
 542 static const char * const pwm28_group[] = { "pwm28_grp" };
 543 static const char * const pwm29_group[] = { "pwm29_grp" };
 544 static const char * const pwm30_group[] = { "pwm30_grp" };
 545 static const char * const pwm31_group[] = { "pwm31_grp" };
 546 static const char * const pwm32_group[] = { "pwm32_grp" };
 547 static const char * const pwm33_group[] = { "pwm33_grp" };
 548 static const char * const pwm34_group[] = { "pwm34_grp" };
 549 static const char * const pwm35_group[] = { "pwm35_grp" };
 550 static const char * const pwm36_group[] = { "pwm36_grp" };
 551 static const char * const pwm37_group[] = { "pwm37_grp" };
 552 static const char * const i2c0_group[] = { "i2c0_grp" };
 553 static const char * const i2c1_group[] = { "i2c1_grp" };
 554 static const char * const i2c2_group[] = { "i2c2_grp" };
 555 static const char * const i2c3_group[] = { "i2c3_grp" };
 556 static const char * const i2c4_group[] = { "i2c4_grp" };
 557 static const char * const uart0_group[] = { "uart0_grp" };
 558 static const char * const uart1_group[] = { "uart1_grp" };
 559 static const char * const uart2_group[] = { "uart2_grp" };
 560 static const char * const uart3_group[] = { "uart3_grp" };
 561 static const char * const uart4_group[] = { "uart4_grp" };
 562 static const char * const uart5_group[] = { "uart5_grp" };
 563 static const char * const uart6_group[] = { "uart6_grp" };
 564 static const char * const uart7_group[] = { "uart7_grp" };
 565 static const char * const uart8_group[] = { "uart8_grp" };
 566 static const char * const uart9_group[] = { "uart9_grp" };
 567 static const char * const uart10_group[] = { "uart10_grp" };
 568 static const char * const uart11_group[] = { "uart11_grp" };
 569 static const char * const uart12_group[] = { "uart12_grp" };
 570 static const char * const uart13_group[] = { "uart13_grp" };
 571 static const char * const uart14_group[] = { "uart14_grp" };
 572 static const char * const uart15_group[] = { "uart15_grp" };
 573 static const char * const gpio0_group[] = { "gpio0_grp" };
 574 static const char * const gpio1_group[] = { "gpio1_grp" };
 575 static const char * const gpio2_group[] = { "gpio2_grp" };
 576 static const char * const gpio3_group[] = { "gpio3_grp" };
 577 static const char * const gpio4_group[] = { "gpio4_grp" };
 578 static const char * const gpio5_group[] = { "gpio5_grp" };
 579 static const char * const gpio6_group[] = { "gpio6_grp" };
 580 static const char * const gpio7_group[] = { "gpio7_grp" };
 581 static const char * const gpio8_group[] = { "gpio8_grp" };
 582 static const char * const gpio9_group[] = { "gpio9_grp" };
 583 static const char * const gpio10_group[] = { "gpio10_grp" };
 584 static const char * const gpio11_group[] = { "gpio11_grp" };
 585 static const char * const gpio12_group[] = { "gpio12_grp" };
 586 static const char * const gpio13_group[] = { "gpio13_grp" };
 587 static const char * const gpio14_group[] = { "gpio14_grp" };
 588 static const char * const gpio15_group[] = { "gpio15_grp" };
 589 static const char * const gpio16_group[] = { "gpio16_grp" };
 590 static const char * const gpio17_group[] = { "gpio17_grp" };
 591 static const char * const gpio18_group[] = { "gpio18_grp" };
 592 static const char * const gpio19_group[] = { "gpio19_grp" };
 593 static const char * const gpio20_group[] = { "gpio20_grp" };
 594 static const char * const gpio21_group[] = { "gpio21_grp" };
 595 static const char * const gpio22_group[] = { "gpio22_grp" };
 596 static const char * const gpio23_group[] = { "gpio23_grp" };
 597 static const char * const gpio24_group[] = { "gpio24_grp" };
 598 static const char * const gpio25_group[] = { "gpio25_grp" };
 599 static const char * const gpio26_group[] = { "gpio26_grp" };
 600 static const char * const gpio27_group[] = { "gpio27_grp" };
 601 static const char * const gpio28_group[] = { "gpio28_grp" };
 602 static const char * const gpio29_group[] = { "gpio29_grp" };
 603 static const char * const gpio30_group[] = { "gpio30_grp" };
 604 static const char * const gpio31_group[] = { "gpio31_grp" };
 605 static const char * const gpio32_group[] = { "gpio32_grp" };
 606 static const char * const gpio33_group[] = { "gpio33_grp" };
 607 static const char * const gpio34_group[] = { "gpio34_grp" };
 608 static const char * const gpio35_group[] = { "gpio35_grp" };
 609 static const char * const gpio36_group[] = { "gpio36_grp" };
 610 static const char * const gpio37_group[] = { "gpio37_grp" };
 611 static const char * const gpio38_group[] = { "gpio38_grp" };
 612 static const char * const gpio39_group[] = { "gpio39_grp" };
 613 static const char * const gpio40_group[] = { "gpio40_grp" };
 614 static const char * const gpio41_group[] = { "gpio41_grp" };
 615 static const char * const gpio42_group[] = { "gpio42_grp" };
 616 static const char * const gpio43_group[] = { "gpio43_grp" };
 617 static const char * const gpio44_group[] = { "gpio44_grp" };
 618 static const char * const gpio45_group[] = { "gpio45_grp" };
 619 static const char * const gpio46_group[] = { "gpio46_grp" };
 620 static const char * const gpio47_group[] = { "gpio47_grp" };
 621 static const char * const gpio48_group[] = { "gpio48_grp" };
 622 static const char * const gpio49_group[] = { "gpio49_grp" };
 623 static const char * const gpio50_group[] = { "gpio50_grp" };
 624 static const char * const gpio51_group[] = { "gpio51_grp" };
 625 static const char * const gpio52_group[] = { "gpio52_grp" };
 626 static const char * const gpio53_group[] = { "gpio53_grp" };
 627 static const char * const gpio54_group[] = { "gpio54_grp" };
 628 static const char * const gpio55_group[] = { "gpio55_grp" };
 629 static const char * const gpio56_group[] = { "gpio56_grp" };
 630 static const char * const gpio57_group[] = { "gpio57_grp" };
 631 static const char * const gpio58_group[] = { "gpio58_grp" };
 632 static const char * const gpio59_group[] = { "gpio59_grp" };
 633 static const char * const gpio60_group[] = { "gpio60_grp" };
 634 static const char * const gpio61_group[] = { "gpio61_grp" };
 635 static const char * const gpio62_group[] = { "gpio62_grp" };
 636 static const char * const gpio63_group[] = { "gpio63_grp" };
 637 static const char * const gpio64_group[] = { "gpio64_grp" };
 638 static const char * const gpio65_group[] = { "gpio65_grp" };
 639 static const char * const gpio66_group[] = { "gpio66_grp" };
 640 static const char * const gpio67_group[] = { "gpio67_grp" };
 641 static const char * const eth1_group[] = { "eth1_grp" };
 642 static const char * const i2s0_group[] = { "i2s0_grp" };
 643 static const char * const i2s0_mclkin_group[] = { "i2s0_mclkin_grp" };
 644 static const char * const i2s1_group[] = { "i2s1_grp" };
 645 static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" };
 646 static const char * const spi0_group[] = { "spi0_grp" };
 647
 648 #define BM1880_PINMUX_FUNCTION(fname, mval)             \
 649         [F_##fname] = {                                 \
 650                 .name = #fname,                         \
 651                 .groups = fname##_group,                \
 652                 .ngroups = ARRAY_SIZE(fname##_group),   \
 653                 .mux_val = mval,                        \
 654         }
 655
 656 static const struct bm1880_pinmux_function bm1880_pmux_functions[] = {
 657         BM1880_PINMUX_FUNCTION(nand, 2),
 658         BM1880_PINMUX_FUNCTION(spi, 0),
 659         BM1880_PINMUX_FUNCTION(emmc, 1),
 660         BM1880_PINMUX_FUNCTION(sdio, 0),
 661         BM1880_PINMUX_FUNCTION(eth0, 0),
 662         BM1880_PINMUX_FUNCTION(pwm0, 2),
 663         BM1880_PINMUX_FUNCTION(pwm1, 2),
 664         BM1880_PINMUX_FUNCTION(pwm2, 2),
 665         BM1880_PINMUX_FUNCTION(pwm3, 2),
 666         BM1880_PINMUX_FUNCTION(pwm4, 2),
 667         BM1880_PINMUX_FUNCTION(pwm5, 2),
 668         BM1880_PINMUX_FUNCTION(pwm6, 2),
 669         BM1880_PINMUX_FUNCTION(pwm7, 2),
 670         BM1880_PINMUX_FUNCTION(pwm8, 2),
 671         BM1880_PINMUX_FUNCTION(pwm9, 2),
 672         BM1880_PINMUX_FUNCTION(pwm10, 2),
 673         BM1880_PINMUX_FUNCTION(pwm11, 2),
 674         BM1880_PINMUX_FUNCTION(pwm12, 2),
 675         BM1880_PINMUX_FUNCTION(pwm13, 2),
 676         BM1880_PINMUX_FUNCTION(pwm14, 2),
 677         BM1880_PINMUX_FUNCTION(pwm15, 2),
 678         BM1880_PINMUX_FUNCTION(pwm16, 2),
 679         BM1880_PINMUX_FUNCTION(pwm17, 2),
 680         BM1880_PINMUX_FUNCTION(pwm18, 2),
 681         BM1880_PINMUX_FUNCTION(pwm19, 2),
 682         BM1880_PINMUX_FUNCTION(pwm20, 2),
 683         BM1880_PINMUX_FUNCTION(pwm21, 2),
 684         BM1880_PINMUX_FUNCTION(pwm22, 2),
 685         BM1880_PINMUX_FUNCTION(pwm23, 2),
 686         BM1880_PINMUX_FUNCTION(pwm24, 2),
 687         BM1880_PINMUX_FUNCTION(pwm25, 2),
 688         BM1880_PINMUX_FUNCTION(pwm26, 2),
 689         BM1880_PINMUX_FUNCTION(pwm27, 2),
 690         BM1880_PINMUX_FUNCTION(pwm28, 2),
 691         BM1880_PINMUX_FUNCTION(pwm29, 2),
 692         BM1880_PINMUX_FUNCTION(pwm30, 2),
 693         BM1880_PINMUX_FUNCTION(pwm31, 2),
 694         BM1880_PINMUX_FUNCTION(pwm32, 2),
 695         BM1880_PINMUX_FUNCTION(pwm33, 2),
 696         BM1880_PINMUX_FUNCTION(pwm34, 2),
 697         BM1880_PINMUX_FUNCTION(pwm35, 2),
 698         BM1880_PINMUX_FUNCTION(pwm36, 2),
 699         BM1880_PINMUX_FUNCTION(pwm37, 2),
 700         BM1880_PINMUX_FUNCTION(i2c0, 1),
 701         BM1880_PINMUX_FUNCTION(i2c1, 1),
 702         BM1880_PINMUX_FUNCTION(i2c2, 1),
 703         BM1880_PINMUX_FUNCTION(i2c3, 1),
 704         BM1880_PINMUX_FUNCTION(i2c4, 1),
 705         BM1880_PINMUX_FUNCTION(uart0, 3),
 706         BM1880_PINMUX_FUNCTION(uart1, 3),
 707         BM1880_PINMUX_FUNCTION(uart2, 3),
 708         BM1880_PINMUX_FUNCTION(uart3, 3),
 709         BM1880_PINMUX_FUNCTION(uart4, 1),
 710         BM1880_PINMUX_FUNCTION(uart5, 1),
 711         BM1880_PINMUX_FUNCTION(uart6, 1),
 712         BM1880_PINMUX_FUNCTION(uart7, 1),
 713         BM1880_PINMUX_FUNCTION(uart8, 1),
 714         BM1880_PINMUX_FUNCTION(uart9, 1),
 715         BM1880_PINMUX_FUNCTION(uart10, 1),
 716         BM1880_PINMUX_FUNCTION(uart11, 1),
 717         BM1880_PINMUX_FUNCTION(uart12, 3),
 718         BM1880_PINMUX_FUNCTION(uart13, 3),
 719         BM1880_PINMUX_FUNCTION(uart14, 3),
 720         BM1880_PINMUX_FUNCTION(uart15, 3),
 721         BM1880_PINMUX_FUNCTION(gpio0, 0),
 722         BM1880_PINMUX_FUNCTION(gpio1, 0),
 723         BM1880_PINMUX_FUNCTION(gpio2, 0),
 724         BM1880_PINMUX_FUNCTION(gpio3, 0),
 725         BM1880_PINMUX_FUNCTION(gpio4, 0),
 726         BM1880_PINMUX_FUNCTION(gpio5, 0),
 727         BM1880_PINMUX_FUNCTION(gpio6, 0),
 728         BM1880_PINMUX_FUNCTION(gpio7, 0),
 729         BM1880_PINMUX_FUNCTION(gpio8, 0),
 730         BM1880_PINMUX_FUNCTION(gpio9, 0),
 731         BM1880_PINMUX_FUNCTION(gpio10, 0),
 732         BM1880_PINMUX_FUNCTION(gpio11, 0),
 733         BM1880_PINMUX_FUNCTION(gpio12, 1),
 734         BM1880_PINMUX_FUNCTION(gpio13, 1),
 735         BM1880_PINMUX_FUNCTION(gpio14, 0),
 736         BM1880_PINMUX_FUNCTION(gpio15, 0),
 737         BM1880_PINMUX_FUNCTION(gpio16, 0),
 738         BM1880_PINMUX_FUNCTION(gpio17, 0),
 739         BM1880_PINMUX_FUNCTION(gpio18, 0),
 740         BM1880_PINMUX_FUNCTION(gpio19, 0),
 741         BM1880_PINMUX_FUNCTION(gpio20, 0),
 742         BM1880_PINMUX_FUNCTION(gpio21, 0),
 743         BM1880_PINMUX_FUNCTION(gpio22, 0),
 744         BM1880_PINMUX_FUNCTION(gpio23, 0),
 745         BM1880_PINMUX_FUNCTION(gpio24, 0),
 746         BM1880_PINMUX_FUNCTION(gpio25, 0),
 747         BM1880_PINMUX_FUNCTION(gpio26, 0),
 748         BM1880_PINMUX_FUNCTION(gpio27, 0),
 749         BM1880_PINMUX_FUNCTION(gpio28, 0),
 750         BM1880_PINMUX_FUNCTION(gpio29, 0),
 751         BM1880_PINMUX_FUNCTION(gpio30, 0),
 752         BM1880_PINMUX_FUNCTION(gpio31, 0),
 753         BM1880_PINMUX_FUNCTION(gpio32, 0),
 754         BM1880_PINMUX_FUNCTION(gpio33, 0),
 755         BM1880_PINMUX_FUNCTION(gpio34, 0),
 756         BM1880_PINMUX_FUNCTION(gpio35, 0),
 757         BM1880_PINMUX_FUNCTION(gpio36, 0),
 758         BM1880_PINMUX_FUNCTION(gpio37, 0),
 759         BM1880_PINMUX_FUNCTION(gpio38, 0),
 760         BM1880_PINMUX_FUNCTION(gpio39, 0),
 761         BM1880_PINMUX_FUNCTION(gpio40, 0),
 762         BM1880_PINMUX_FUNCTION(gpio41, 0),
 763         BM1880_PINMUX_FUNCTION(gpio42, 0),
 764         BM1880_PINMUX_FUNCTION(gpio43, 0),
 765         BM1880_PINMUX_FUNCTION(gpio44, 0),
 766         BM1880_PINMUX_FUNCTION(gpio45, 0),
 767         BM1880_PINMUX_FUNCTION(gpio46, 0),
 768         BM1880_PINMUX_FUNCTION(gpio47, 0),
 769         BM1880_PINMUX_FUNCTION(gpio48, 0),
 770         BM1880_PINMUX_FUNCTION(gpio49, 0),
 771         BM1880_PINMUX_FUNCTION(gpio50, 0),
 772         BM1880_PINMUX_FUNCTION(gpio51, 0),
 773         BM1880_PINMUX_FUNCTION(gpio52, 0),
 774         BM1880_PINMUX_FUNCTION(gpio53, 0),
 775         BM1880_PINMUX_FUNCTION(gpio54, 0),
 776         BM1880_PINMUX_FUNCTION(gpio55, 0),
 777         BM1880_PINMUX_FUNCTION(gpio56, 0),
 778         BM1880_PINMUX_FUNCTION(gpio57, 0),
 779         BM1880_PINMUX_FUNCTION(gpio58, 0),
 780         BM1880_PINMUX_FUNCTION(gpio59, 0),
 781         BM1880_PINMUX_FUNCTION(gpio60, 0),
 782         BM1880_PINMUX_FUNCTION(gpio61, 0),
 783         BM1880_PINMUX_FUNCTION(gpio62, 0),
 784         BM1880_PINMUX_FUNCTION(gpio63, 0),
 785         BM1880_PINMUX_FUNCTION(gpio64, 0),
 786         BM1880_PINMUX_FUNCTION(gpio65, 0),
 787         BM1880_PINMUX_FUNCTION(gpio66, 0),
 788         BM1880_PINMUX_FUNCTION(gpio67, 0),
 789         BM1880_PINMUX_FUNCTION(eth1, 1),
 790         BM1880_PINMUX_FUNCTION(i2s0, 2),
 791         BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1),
 792         BM1880_PINMUX_FUNCTION(i2s1, 2),
 793         BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1),
 794         BM1880_PINMUX_FUNCTION(spi0, 1),
 795 };
 796
 797 #define BM1880_PINCONF_DAT(_width)              \
 798         {                                       \
 799                 .drv_bits = _width,             \
 800         }
 801
 802 static const struct bm1880_pinconf_data bm1880_pinconf[] = {
 803         BM1880_PINCONF_DAT(0x03),
 804         BM1880_PINCONF_DAT(0x03),
 805         BM1880_PINCONF_DAT(0x03),
 806         BM1880_PINCONF_DAT(0x03),
 807         BM1880_PINCONF_DAT(0x03),
 808         BM1880_PINCONF_DAT(0x03),
 809         BM1880_PINCONF_DAT(0x03),
 810         BM1880_PINCONF_DAT(0x03),
 811         BM1880_PINCONF_DAT(0x03),
 812         BM1880_PINCONF_DAT(0x03),
 813         BM1880_PINCONF_DAT(0x03),
 814         BM1880_PINCONF_DAT(0x03),
 815         BM1880_PINCONF_DAT(0x03),
 816         BM1880_PINCONF_DAT(0x03),
 817         BM1880_PINCONF_DAT(0x03),
 818         BM1880_PINCONF_DAT(0x03),
 819         BM1880_PINCONF_DAT(0x03),
 820         BM1880_PINCONF_DAT(0x03),
 821         BM1880_PINCONF_DAT(0x03),
 822         BM1880_PINCONF_DAT(0x03),
 823         BM1880_PINCONF_DAT(0x03),
 824         BM1880_PINCONF_DAT(0x03),
 825         BM1880_PINCONF_DAT(0x03),
 826         BM1880_PINCONF_DAT(0x03),
 827         BM1880_PINCONF_DAT(0x03),
 828         BM1880_PINCONF_DAT(0x03),
 829         BM1880_PINCONF_DAT(0x03),
 830         BM1880_PINCONF_DAT(0x03),
 831         BM1880_PINCONF_DAT(0x03),
 832         BM1880_PINCONF_DAT(0x03),
 833         BM1880_PINCONF_DAT(0x03),
 834         BM1880_PINCONF_DAT(0x03),
 835         BM1880_PINCONF_DAT(0x03),
 836         BM1880_PINCONF_DAT(0x03),
 837         BM1880_PINCONF_DAT(0x03),
 838         BM1880_PINCONF_DAT(0x03),
 839         BM1880_PINCONF_DAT(0x03),
 840         BM1880_PINCONF_DAT(0x03),
 841         BM1880_PINCONF_DAT(0x03),
 842         BM1880_PINCONF_DAT(0x03),
 843         BM1880_PINCONF_DAT(0x03),
 844         BM1880_PINCONF_DAT(0x03),
 845         BM1880_PINCONF_DAT(0x03),
 846         BM1880_PINCONF_DAT(0x03),
 847         BM1880_PINCONF_DAT(0x03),
 848         BM1880_PINCONF_DAT(0x03),
 849         BM1880_PINCONF_DAT(0x03),
 850         BM1880_PINCONF_DAT(0x03),
 851         BM1880_PINCONF_DAT(0x03),
 852         BM1880_PINCONF_DAT(0x03),
 853         BM1880_PINCONF_DAT(0x03),
 854         BM1880_PINCONF_DAT(0x03),
 855         BM1880_PINCONF_DAT(0x03),
 856         BM1880_PINCONF_DAT(0x03),
 857         BM1880_PINCONF_DAT(0x03),
 858         BM1880_PINCONF_DAT(0x03),
 859         BM1880_PINCONF_DAT(0x03),
 860         BM1880_PINCONF_DAT(0x03),
 861         BM1880_PINCONF_DAT(0x03),
 862         BM1880_PINCONF_DAT(0x03),
 863         BM1880_PINCONF_DAT(0x02),
 864         BM1880_PINCONF_DAT(0x02),
 865         BM1880_PINCONF_DAT(0x02),
 866         BM1880_PINCONF_DAT(0x02),
 867         BM1880_PINCONF_DAT(0x02),
 868         BM1880_PINCONF_DAT(0x02),
 869         BM1880_PINCONF_DAT(0x02),
 870         BM1880_PINCONF_DAT(0x02),
 871         BM1880_PINCONF_DAT(0x02),
 872         BM1880_PINCONF_DAT(0x02),
 873         BM1880_PINCONF_DAT(0x02),
 874         BM1880_PINCONF_DAT(0x02),
 875         BM1880_PINCONF_DAT(0x02),
 876         BM1880_PINCONF_DAT(0x02),
 877         BM1880_PINCONF_DAT(0x02),
 878         BM1880_PINCONF_DAT(0x02),
 879         BM1880_PINCONF_DAT(0x02),
 880         BM1880_PINCONF_DAT(0x02),
 881         BM1880_PINCONF_DAT(0x02),
 882         BM1880_PINCONF_DAT(0x02),
 883         BM1880_PINCONF_DAT(0x02),
 884         BM1880_PINCONF_DAT(0x02),
 885         BM1880_PINCONF_DAT(0x02),
 886         BM1880_PINCONF_DAT(0x02),
 887         BM1880_PINCONF_DAT(0x02),
 888         BM1880_PINCONF_DAT(0x02),
 889         BM1880_PINCONF_DAT(0x02),
 890         BM1880_PINCONF_DAT(0x02),
 891         BM1880_PINCONF_DAT(0x02),
 892         BM1880_PINCONF_DAT(0x02),
 893         BM1880_PINCONF_DAT(0x02),
 894         BM1880_PINCONF_DAT(0x02),
 895         BM1880_PINCONF_DAT(0x02),
 896         BM1880_PINCONF_DAT(0x02),
 897         BM1880_PINCONF_DAT(0x02),
 898         BM1880_PINCONF_DAT(0x02),
 899         BM1880_PINCONF_DAT(0x02),
 900         BM1880_PINCONF_DAT(0x02),
 901         BM1880_PINCONF_DAT(0x02),
 902         BM1880_PINCONF_DAT(0x02),
 903         BM1880_PINCONF_DAT(0x02),
 904         BM1880_PINCONF_DAT(0x02),
 905         BM1880_PINCONF_DAT(0x02),
 906         BM1880_PINCONF_DAT(0x02),
 907         BM1880_PINCONF_DAT(0x02),
 908         BM1880_PINCONF_DAT(0x02),
 909         BM1880_PINCONF_DAT(0x02),
 910         BM1880_PINCONF_DAT(0x02),
 911         BM1880_PINCONF_DAT(0x02),
 912         BM1880_PINCONF_DAT(0x02),
 913         BM1880_PINCONF_DAT(0x02),
 914         BM1880_PINCONF_DAT(0x02),
 915 };
 916
 917 static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 918 {
 919         struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 920
 921         return pctrl->ngroups;
 922 }
 923
 924 static const char *bm1880_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 925                                                unsigned int selector)
 926 {
 927         struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 928
 929         return pctrl->groups[selector].name;
 930 }
 931
 932 static int bm1880_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 933                                        unsigned int selector,
 934                                        const unsigned int **pins,
 935                                        unsigned int *num_pins)
 936 {
 937         struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 938
 939         *pins = pctrl->groups[selector].pins;
 940         *num_pins = pctrl->groups[selector].npins;
 941
 942         return 0;
 943 }
 944
 945 static const struct pinctrl_ops bm1880_pctrl_ops = {
 946         .get_groups_count = bm1880_pctrl_get_groups_count,
 947         .get_group_name = bm1880_pctrl_get_group_name,
 948         .get_group_pins = bm1880_pctrl_get_group_pins,
 949         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
 950         .dt_free_map = pinctrl_utils_free_map,
 951 };
 952
 953 /* pinmux */
 954 static int bm1880_pmux_get_functions_count(struct pinctrl_dev *pctldev)
 955 {
 956         struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 957
 958         return pctrl->nfuncs;
 959 }
 960
 961 static const char *bm1880_pmux_get_function_name(struct pinctrl_dev *pctldev,
 962                                                  unsigned int selector)
 963 {
 964         struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 965
 966         return pctrl->funcs[selector].name;
 967 }
 968
 969 static int bm1880_pmux_get_function_groups(struct pinctrl_dev *pctldev,
 970                                            unsigned int selector,
 971                                            const char * const **groups,
 972                                            unsigned * const num_groups)
 973 {
 974         struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 975
 976         *groups = pctrl->funcs[selector].groups;
 977         *num_groups = pctrl->funcs[selector].ngroups;
 978         return 0;
 979 }
 980
 981 static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev,
 982                                  unsigned int function,
 983                                  unsigned int  group)
 984 {
 985         struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 986         const struct bm1880_pctrl_group *pgrp = &pctrl->groups[group];
 987         const struct bm1880_pinmux_function *func = &pctrl->funcs[function];
 988         int i;
 989
 990         for (i = 0; i < pgrp->npins; i++) {
 991                 unsigned int pin = pgrp->pins[i];
 992                 u32 offset = (pin >> 1) << 2;
 993                 u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4);
 994                 u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX +
 995                                            offset);
 996
 997                 regval &= ~(0x03 << mux_offset);
 998                 regval |= func->mux_val << mux_offset;
 999
1000                 writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
1001         }
1002
1003         return 0;
1004 }
1005
1006 #define BM1880_PINCONF(pin, idx) ((!((pin + 1) & 1) << 4) + idx)
1007 #define BM1880_PINCONF_PULLCTRL(pin)    BM1880_PINCONF(pin, 0)
1008 #define BM1880_PINCONF_PULLUP(pin)      BM1880_PINCONF(pin, 1)
1009 #define BM1880_PINCONF_PULLDOWN(pin)    BM1880_PINCONF(pin, 2)
1010 #define BM1880_PINCONF_DRV(pin)         BM1880_PINCONF(pin, 6)
1011 #define BM1880_PINCONF_SCHMITT(pin)     BM1880_PINCONF(pin, 9)
1012 #define BM1880_PINCONF_SLEW(pin)        BM1880_PINCONF(pin, 10)
1013
1014 static int bm1880_pinconf_drv_set(unsigned int mA, u32 width,
1015                                   u32 *regval, u32 bit_offset)
1016 {
1017         u32 _regval;
1018
1019         _regval = *regval;
1020
1021         /*
1022          * There are two sets of drive strength bit width exposed by the
1023          * SoC at 4mA step, hence we need to handle them separately.
1024          */
1025         if (width == 0x03) {
1026                 switch (mA) {
1027                 case 4:
1028                         _regval &= ~(width << bit_offset);
1029                         _regval |= (0 << bit_offset);
1030                         break;
1031                 case 8:
1032                         _regval &= ~(width << bit_offset);
1033                         _regval |= (1 << bit_offset);
1034                         break;
1035                 case 12:
1036                         _regval &= ~(width << bit_offset);
1037                         _regval |= (2 << bit_offset);
1038                         break;
1039                 case 16:
1040                         _regval &= ~(width << bit_offset);
1041                         _regval |= (3 << bit_offset);
1042                         break;
1043                 case 20:
1044                         _regval &= ~(width << bit_offset);
1045                         _regval |= (4 << bit_offset);
1046                         break;
1047                 case 24:
1048                         _regval &= ~(width << bit_offset);
1049                         _regval |= (5 << bit_offset);
1050                         break;
1051                 case 28:
1052                         _regval &= ~(width << bit_offset);
1053                         _regval |= (6 << bit_offset);
1054                         break;
1055                 case 32:
1056                         _regval &= ~(width << bit_offset);
1057                         _regval |= (7 << bit_offset);
1058                         break;
1059                 default:
1060                         return -EINVAL;
1061                 }
1062         } else {
1063                 switch (mA) {
1064                 case 4:
1065                         _regval &= ~(width << bit_offset);
1066                         _regval |= (0 << bit_offset);
1067                         break;
1068                 case 8:
1069                         _regval &= ~(width << bit_offset);
1070                         _regval |= (1 << bit_offset);
1071                         break;
1072                 case 12:
1073                         _regval &= ~(width << bit_offset);
1074                         _regval |= (2 << bit_offset);
1075                         break;
1076                 case 16:
1077                         _regval &= ~(width << bit_offset);
1078                         _regval |= (3 << bit_offset);
1079                         break;
1080                 default:
1081                         return -EINVAL;
1082                 }
1083         }
1084
1085         *regval = _regval;
1086
1087         return 0;
1088 }
1089
1090 static int bm1880_pinconf_drv_get(u32 width, u32 drv)
1091 {
1092         int ret = -ENOTSUPP;
1093
1094         /*
1095          * There are two sets of drive strength bit width exposed by the
1096          * SoC at 4mA step, hence we need to handle them separately.
1097          */
1098         if (width == 0x03) {
1099                 switch (drv) {
1100                 case 0:
1101                         ret  = 4;
1102                         break;
1103                 case 1:
1104                         ret  = 8;
1105                         break;
1106                 case 2:
1107                         ret  = 12;
1108                         break;
1109                 case 3:
1110                         ret  = 16;
1111                         break;
1112                 case 4:
1113                         ret  = 20;
1114                         break;
1115                 case 5:
1116                         ret  = 24;
1117                         break;
1118                 case 6:
1119                         ret  = 28;
1120                         break;
1121                 case 7:
1122                         ret  = 32;
1123                         break;
1124                 default:
1125                         break;
1126                 }
1127         } else {
1128                 switch (drv) {
1129                 case 0:
1130                         ret  = 4;
1131                         break;
1132                 case 1:
1133                         ret  = 8;
1134                         break;
1135                 case 2:
1136                         ret  = 12;
1137                         break;
1138                 case 3:
1139                         ret  = 16;
1140                         break;
1141                 default:
1142                         break;
1143                 }
1144         }
1145
1146         return ret;
1147 }
1148
1149 static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev,
1150                                   unsigned int pin,
1151                                   unsigned long *config)
1152 {
1153         struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1154         unsigned int param = pinconf_to_config_param(*config);
1155         unsigned int arg = 0;
1156         u32 regval, offset, bit_offset;
1157         int ret;
1158
1159         offset = (pin >> 1) << 2;
1160         regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
1161
1162         switch (param) {
1163         case PIN_CONFIG_BIAS_PULL_UP:
1164                 bit_offset = BM1880_PINCONF_PULLUP(pin);
1165                 arg = !!(regval & BIT(bit_offset));
1166                 break;
1167         case PIN_CONFIG_BIAS_PULL_DOWN:
1168                 bit_offset = BM1880_PINCONF_PULLDOWN(pin);
1169                 arg = !!(regval & BIT(bit_offset));
1170                 break;
1171         case PIN_CONFIG_BIAS_DISABLE:
1172                 bit_offset = BM1880_PINCONF_PULLCTRL(pin);
1173                 arg = !!(regval & BIT(bit_offset));
1174                 break;
1175         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1176                 bit_offset = BM1880_PINCONF_SCHMITT(pin);
1177                 arg = !!(regval & BIT(bit_offset));
1178                 break;
1179         case PIN_CONFIG_SLEW_RATE:
1180                 bit_offset = BM1880_PINCONF_SLEW(pin);
1181                 arg = !!(regval & BIT(bit_offset));
1182                 break;
1183         case PIN_CONFIG_DRIVE_STRENGTH:
1184                 bit_offset = BM1880_PINCONF_DRV(pin);
1185                 ret = bm1880_pinconf_drv_get(pctrl->pinconf[pin].drv_bits,
1186                                              !!(regval & BIT(bit_offset)));
1187                 if (ret < 0)
1188                         return ret;
1189
1190                 arg = ret;
1191                 break;
1192         default:
1193                 return -ENOTSUPP;
1194         }
1195
1196         *config = pinconf_to_config_packed(param, arg);
1197
1198         return 0;
1199 }
1200
1201 static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev,
1202                                   unsigned int pin,
1203                                   unsigned long *configs,
1204                                   unsigned int num_configs)
1205 {
1206         struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1207         u32 regval, offset, bit_offset;
1208         int i, ret;
1209
1210         offset = (pin >> 1) << 2;
1211         regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
1212
1213         for (i = 0; i < num_configs; i++) {
1214                 unsigned int param = pinconf_to_config_param(configs[i]);
1215                 unsigned int arg = pinconf_to_config_argument(configs[i]);
1216
1217                 switch (param) {
1218                 case PIN_CONFIG_BIAS_PULL_UP:
1219                         bit_offset = BM1880_PINCONF_PULLUP(pin);
1220                         regval |= BIT(bit_offset);
1221                         break;
1222                 case PIN_CONFIG_BIAS_PULL_DOWN:
1223                         bit_offset = BM1880_PINCONF_PULLDOWN(pin);
1224                         regval |= BIT(bit_offset);
1225                         break;
1226                 case PIN_CONFIG_BIAS_DISABLE:
1227                         bit_offset = BM1880_PINCONF_PULLCTRL(pin);
1228                         regval |= BIT(bit_offset);
1229                         break;
1230                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1231                         bit_offset = BM1880_PINCONF_SCHMITT(pin);
1232                         if (arg)
1233                                 regval |= BIT(bit_offset);
1234                         else
1235                                 regval &= ~BIT(bit_offset);
1236                         break;
1237                 case PIN_CONFIG_SLEW_RATE:
1238                         bit_offset = BM1880_PINCONF_SLEW(pin);
1239                         if (arg)
1240                                 regval |= BIT(bit_offset);
1241                         else
1242                                 regval &= ~BIT(bit_offset);
1243                         break;
1244                 case PIN_CONFIG_DRIVE_STRENGTH:
1245                         bit_offset = BM1880_PINCONF_DRV(pin);
1246                         ret = bm1880_pinconf_drv_set(arg,
1247                                                 pctrl->pinconf[pin].drv_bits,
1248                                                 &regval, bit_offset);
1249                         if (ret < 0)
1250                                 return ret;
1251
1252                         break;
1253                 default:
1254                         dev_warn(pctldev->dev,
1255                                  "unsupported configuration parameter '%u'\n",
1256                                  param);
1257                         continue;
1258                 }
1259
1260                 writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
1261         }
1262
1263         return 0;
1264 }
1265
1266 static int bm1880_pinconf_group_set(struct pinctrl_dev *pctldev,
1267                                     unsigned int selector,
1268                                     unsigned long *configs,
1269                                     unsigned int  num_configs)
1270 {
1271         int i, ret;
1272         struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1273         const struct bm1880_pctrl_group *pgrp = &pctrl->groups[selector];
1274
1275         for (i = 0; i < pgrp->npins; i++) {
1276                 ret = bm1880_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
1277                                              num_configs);
1278                 if (ret)
1279                         return ret;
1280         }
1281
1282         return 0;
1283 }
1284
1285 static const struct pinconf_ops bm1880_pinconf_ops = {
1286         .is_generic = true,
1287         .pin_config_get = bm1880_pinconf_cfg_get,
1288         .pin_config_set = bm1880_pinconf_cfg_set,
1289         .pin_config_group_set = bm1880_pinconf_group_set,
1290 };
1291
1292 static const struct pinmux_ops bm1880_pinmux_ops = {
1293         .get_functions_count = bm1880_pmux_get_functions_count,
1294         .get_function_name = bm1880_pmux_get_function_name,
1295         .get_function_groups = bm1880_pmux_get_function_groups,
1296         .set_mux = bm1880_pinmux_set_mux,
1297 };
1298
1299 static struct pinctrl_desc bm1880_desc = {
1300         .name = "bm1880_pinctrl",
1301         .pins = bm1880_pins,
1302         .npins = ARRAY_SIZE(bm1880_pins),
1303         .pctlops = &bm1880_pctrl_ops,
1304         .pmxops = &bm1880_pinmux_ops,
1305         .confops = &bm1880_pinconf_ops,
1306         .owner = THIS_MODULE,
1307 };
1308
1309 static int bm1880_pinctrl_probe(struct platform_device *pdev)
1310
1311 {
1312         struct bm1880_pinctrl *pctrl;
1313
1314         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1315         if (!pctrl)
1316                 return -ENOMEM;
1317
1318         pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1319         if (IS_ERR(pctrl->base))
1320                 return PTR_ERR(pctrl->base);
1321
1322         pctrl->groups = bm1880_pctrl_groups;
1323         pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups);
1324         pctrl->funcs = bm1880_pmux_functions;
1325         pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions);
1326         pctrl->pinconf = bm1880_pinconf;
1327
1328         pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc,
1329                                                 pctrl);
1330         if (IS_ERR(pctrl->pctrldev))
1331                 return PTR_ERR(pctrl->pctrldev);
1332
1333         platform_set_drvdata(pdev, pctrl);
1334
1335         dev_info(&pdev->dev, "BM1880 pinctrl driver initialized\n");
1336
1337         return 0;
1338 }
1339
1340 static const struct of_device_id bm1880_pinctrl_of_match[] = {
1341         { .compatible = "bitmain,bm1880-pinctrl" },
1342         { }
1343 };
1344
1345 static struct platform_driver bm1880_pinctrl_driver = {
1346         .driver = {
1347                 .name = "pinctrl-bm1880",
1348                 .of_match_table = of_match_ptr(bm1880_pinctrl_of_match),
1349         },
1350         .probe = bm1880_pinctrl_probe,
1351 };
1352
1353 static int __init bm1880_pinctrl_init(void)
1354 {
1355         return platform_driver_register(&bm1880_pinctrl_driver);
1356 }
1357 arch_initcall(bm1880_pinctrl_init);