2 * Marvell 37xx SoC pinctrl driver
4 * Copyright (C) 2017 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
27 #include "../pinctrl-utils.h"
30 #define INPUT_VAL 0x10
31 #define OUTPUT_VAL 0x18
32 #define OUTPUT_CTL 0x20
33 #define SELECTION 0x30
37 #define IRQ_STATUS 0x10
41 #define GPIO_PER_REG 32
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pin: Index of the first pin of the main range of pins belonging to
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @val: Value to write to the registers for a given function
53 * @extra_pin: Index of the first pin of the optional second range of pins
54 * belonging to the group
55 * @extra_npins:Number of pins included in the second optional range
56 * @funcs: A list of pinmux functions that can be selected for this group.
57 * @pins: List of the pins included in the group
59 struct armada_37xx_pin_group {
61 unsigned int start_pin;
65 unsigned int extra_pin;
66 unsigned int extra_npins;
67 const char *funcs[NB_FUNCS];
71 struct armada_37xx_pin_data {
74 struct armada_37xx_pin_group *groups;
78 struct armada_37xx_pmx_func {
84 struct armada_37xx_pm_state {
96 struct armada_37xx_pinctrl {
97 struct regmap *regmap;
99 const struct armada_37xx_pin_data *data;
101 struct gpio_chip gpio_chip;
102 struct irq_chip irq_chip;
104 struct pinctrl_desc pctl;
105 struct pinctrl_dev *pctl_dev;
106 struct armada_37xx_pin_group *groups;
107 unsigned int ngroups;
108 struct armada_37xx_pmx_func *funcs;
110 struct armada_37xx_pm_state pm;
113 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
116 .start_pin = _start, \
120 .funcs = {_func1, _func2} \
123 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
126 .start_pin = _start, \
130 .funcs = {_func1, "gpio"} \
133 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
136 .start_pin = _start, \
139 .val = {_val1, _val2}, \
140 .funcs = {_func1, "gpio"} \
143 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
146 .start_pin = _start, \
149 .val = {_v1, _v2, _v3}, \
150 .funcs = {_f1, _f2, "gpio"} \
153 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
157 .start_pin = _start, \
161 .extra_pin = _start2, \
162 .extra_npins = _nr2, \
163 .funcs = {_f1, _f2} \
166 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
167 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
168 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
169 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
170 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
171 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
172 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
173 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
174 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
175 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
176 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
177 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
178 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
179 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
180 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
181 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
182 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
183 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
184 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
185 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
186 18, 2, "gpio", "uart"),
187 PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"),
188 PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"),
189 PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"),
190 PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"),
194 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
195 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
196 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
197 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
198 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
199 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
200 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
201 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
202 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
203 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
204 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
205 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
206 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
210 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
213 .groups = armada_37xx_nb_groups,
214 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
217 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
220 .groups = armada_37xx_sb_groups,
221 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
224 static inline void armada_37xx_update_reg(unsigned int *reg,
225 unsigned int *offset)
227 /* We never have more than 2 registers */
228 if (*offset >= GPIO_PER_REG) {
229 *offset -= GPIO_PER_REG;
234 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
235 struct armada_37xx_pinctrl *info, int pin, int *grp)
237 while (*grp < info->ngroups) {
238 struct armada_37xx_pin_group *group = &info->groups[*grp];
242 for (j = 0; j < (group->npins + group->extra_npins); j++)
243 if (group->pins[j] == pin)
249 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
250 unsigned int selector, unsigned long *config)
255 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
256 unsigned int selector, unsigned long *configs,
257 unsigned int num_configs)
262 static const struct pinconf_ops armada_37xx_pinconf_ops = {
264 .pin_config_group_get = armada_37xx_pin_config_group_get,
265 .pin_config_group_set = armada_37xx_pin_config_group_set,
268 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
270 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
272 return info->ngroups;
275 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
278 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
280 return info->groups[group].name;
283 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
284 unsigned int selector,
285 const unsigned int **pins,
288 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
290 if (selector >= info->ngroups)
293 *pins = info->groups[selector].pins;
294 *npins = info->groups[selector].npins +
295 info->groups[selector].extra_npins;
300 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
301 .get_groups_count = armada_37xx_get_groups_count,
302 .get_group_name = armada_37xx_get_group_name,
303 .get_group_pins = armada_37xx_get_group_pins,
304 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
305 .dt_free_map = pinctrl_utils_free_map,
309 * Pinmux_ops handling
312 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
314 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
319 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
320 unsigned int selector)
322 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
324 return info->funcs[selector].name;
327 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
328 unsigned int selector,
329 const char * const **groups,
330 unsigned int * const num_groups)
332 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
334 *groups = info->funcs[selector].groups;
335 *num_groups = info->funcs[selector].ngroups;
340 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
342 struct armada_37xx_pin_group *grp)
344 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
345 unsigned int reg = SELECTION;
346 unsigned int mask = grp->reg_mask;
349 dev_dbg(info->dev, "enable function %s group %s\n",
352 func = match_string(grp->funcs, NB_FUNCS, name);
356 val = grp->val[func];
358 regmap_update_bits(info->regmap, reg, mask, val);
363 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
364 unsigned int selector,
368 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
369 struct armada_37xx_pin_group *grp = &info->groups[group];
370 const char *name = info->funcs[selector].name;
372 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
375 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
378 int offset = irqd_to_hwirq(d);
380 armada_37xx_update_reg(reg, &offset);
383 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
386 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
387 unsigned int reg = OUTPUT_EN;
390 armada_37xx_update_reg(®, &offset);
393 return regmap_update_bits(info->regmap, reg, mask, 0);
396 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
399 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
400 unsigned int reg = OUTPUT_EN;
401 unsigned int val, mask;
403 armada_37xx_update_reg(®, &offset);
405 regmap_read(info->regmap, reg, &val);
408 return GPIO_LINE_DIRECTION_OUT;
410 return GPIO_LINE_DIRECTION_IN;
413 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
414 unsigned int offset, int value)
416 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
417 unsigned int reg = OUTPUT_EN;
418 unsigned int mask, val, ret;
420 armada_37xx_update_reg(®, &offset);
423 ret = regmap_update_bits(info->regmap, reg, mask, mask);
429 val = value ? mask : 0;
430 regmap_update_bits(info->regmap, reg, mask, val);
435 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
437 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
438 unsigned int reg = INPUT_VAL;
439 unsigned int val, mask;
441 armada_37xx_update_reg(®, &offset);
444 regmap_read(info->regmap, reg, &val);
446 return (val & mask) != 0;
449 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
452 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
453 unsigned int reg = OUTPUT_VAL;
454 unsigned int mask, val;
456 armada_37xx_update_reg(®, &offset);
458 val = value ? mask : 0;
460 regmap_update_bits(info->regmap, reg, mask, val);
463 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
464 struct pinctrl_gpio_range *range,
465 unsigned int offset, bool input)
467 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
468 struct gpio_chip *chip = range->gc;
470 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
471 offset, range->name, offset, input ? "input" : "output");
474 armada_37xx_gpio_direction_input(chip, offset);
476 armada_37xx_gpio_direction_output(chip, offset, 0);
481 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
482 struct pinctrl_gpio_range *range,
485 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
486 struct armada_37xx_pin_group *group;
489 dev_dbg(info->dev, "requesting gpio %d\n", offset);
491 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
492 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
497 static const struct pinmux_ops armada_37xx_pmx_ops = {
498 .get_functions_count = armada_37xx_pmx_get_funcs_count,
499 .get_function_name = armada_37xx_pmx_get_func_name,
500 .get_function_groups = armada_37xx_pmx_get_groups,
501 .set_mux = armada_37xx_pmx_set,
502 .gpio_request_enable = armada_37xx_gpio_request_enable,
503 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
506 static const struct gpio_chip armada_37xx_gpiolib_chip = {
507 .request = gpiochip_generic_request,
508 .free = gpiochip_generic_free,
509 .set = armada_37xx_gpio_set,
510 .get = armada_37xx_gpio_get,
511 .get_direction = armada_37xx_gpio_get_direction,
512 .direction_input = armada_37xx_gpio_direction_input,
513 .direction_output = armada_37xx_gpio_direction_output,
514 .owner = THIS_MODULE,
517 static void armada_37xx_irq_ack(struct irq_data *d)
519 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
520 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
521 u32 reg = IRQ_STATUS;
524 armada_37xx_irq_update_reg(®, d);
525 spin_lock_irqsave(&info->irq_lock, flags);
526 writel(d->mask, info->base + reg);
527 spin_unlock_irqrestore(&info->irq_lock, flags);
530 static void armada_37xx_irq_mask(struct irq_data *d)
532 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
533 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
534 u32 val, reg = IRQ_EN;
537 armada_37xx_irq_update_reg(®, d);
538 spin_lock_irqsave(&info->irq_lock, flags);
539 val = readl(info->base + reg);
540 writel(val & ~d->mask, info->base + reg);
541 spin_unlock_irqrestore(&info->irq_lock, flags);
544 static void armada_37xx_irq_unmask(struct irq_data *d)
546 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
547 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
548 u32 val, reg = IRQ_EN;
551 armada_37xx_irq_update_reg(®, d);
552 spin_lock_irqsave(&info->irq_lock, flags);
553 val = readl(info->base + reg);
554 writel(val | d->mask, info->base + reg);
555 spin_unlock_irqrestore(&info->irq_lock, flags);
558 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
560 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
561 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
562 u32 val, reg = IRQ_WKUP;
565 armada_37xx_irq_update_reg(®, d);
566 spin_lock_irqsave(&info->irq_lock, flags);
567 val = readl(info->base + reg);
569 val |= (BIT(d->hwirq % GPIO_PER_REG));
571 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
572 writel(val, info->base + reg);
573 spin_unlock_irqrestore(&info->irq_lock, flags);
578 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
580 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
581 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
582 u32 val, reg = IRQ_POL;
585 spin_lock_irqsave(&info->irq_lock, flags);
586 armada_37xx_irq_update_reg(®, d);
587 val = readl(info->base + reg);
589 case IRQ_TYPE_EDGE_RISING:
590 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
592 case IRQ_TYPE_EDGE_FALLING:
593 val |= (BIT(d->hwirq % GPIO_PER_REG));
595 case IRQ_TYPE_EDGE_BOTH: {
596 u32 in_val, in_reg = INPUT_VAL;
598 armada_37xx_irq_update_reg(&in_reg, d);
599 regmap_read(info->regmap, in_reg, &in_val);
601 /* Set initial polarity based on current input level. */
602 if (in_val & BIT(d->hwirq % GPIO_PER_REG))
603 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */
605 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
609 spin_unlock_irqrestore(&info->irq_lock, flags);
612 writel(val, info->base + reg);
613 spin_unlock_irqrestore(&info->irq_lock, flags);
618 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
621 u32 reg_idx = pin_idx / GPIO_PER_REG;
622 u32 bit_num = pin_idx % GPIO_PER_REG;
626 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
628 spin_lock_irqsave(&info->irq_lock, flags);
629 p = readl(info->base + IRQ_POL + 4 * reg_idx);
630 if ((p ^ l) & (1 << bit_num)) {
632 * For the gpios which are used for both-edge irqs, when their
633 * interrupts happen, their input levels are changed,
634 * yet their interrupt polarities are kept in old values, we
635 * should synchronize their interrupt polarities; for example,
636 * at first a gpio's input level is low and its interrupt
637 * polarity control is "Detect rising edge", then the gpio has
638 * a interrupt , its level turns to high, we should change its
639 * polarity control to "Detect falling edge" correspondingly.
642 writel(p, info->base + IRQ_POL + 4 * reg_idx);
649 spin_unlock_irqrestore(&info->irq_lock, flags);
653 static void armada_37xx_irq_handler(struct irq_desc *desc)
655 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
656 struct irq_chip *chip = irq_desc_get_chip(desc);
657 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
658 struct irq_domain *d = gc->irq.domain;
661 chained_irq_enter(chip, desc);
662 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
666 spin_lock_irqsave(&info->irq_lock, flags);
667 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
668 /* Manage only the interrupt that was enabled */
669 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
670 spin_unlock_irqrestore(&info->irq_lock, flags);
672 u32 hwirq = ffs(status) - 1;
673 u32 virq = irq_find_mapping(d, hwirq +
675 u32 t = irq_get_trigger_type(virq);
677 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
678 /* Swap polarity (race with GPIO line) */
679 if (armada_37xx_edge_both_irq_swap_pol(info,
680 hwirq + i * GPIO_PER_REG)) {
682 * For spurious irq, which gpio level
683 * is not as expected after incoming
684 * edge, just ack the gpio irq.
693 generic_handle_irq(virq);
696 /* Update status in case a new IRQ appears */
697 spin_lock_irqsave(&info->irq_lock, flags);
698 status = readl_relaxed(info->base +
700 /* Manage only the interrupt that was enabled */
701 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
702 spin_unlock_irqrestore(&info->irq_lock, flags);
705 chained_irq_exit(chip, desc);
708 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
711 * The mask field is a "precomputed bitmask for accessing the
712 * chip registers" which was introduced for the generic
713 * irqchip framework. As we don't use this framework, we can
714 * reuse this field for our own usage.
716 d->mask = BIT(d->hwirq % GPIO_PER_REG);
718 armada_37xx_irq_unmask(d);
723 static int armada_37xx_irqchip_register(struct platform_device *pdev,
724 struct armada_37xx_pinctrl *info)
726 struct device_node *np = info->dev->of_node;
727 struct gpio_chip *gc = &info->gpio_chip;
728 struct irq_chip *irqchip = &info->irq_chip;
729 struct gpio_irq_chip *girq = &gc->irq;
730 struct device *dev = &pdev->dev;
732 int ret = -ENODEV, i, nr_irq_parent;
734 /* Check if we have at least one gpio-controller child node */
735 for_each_child_of_node(info->dev->of_node, np) {
736 if (of_property_read_bool(np, "gpio-controller")) {
742 dev_err(dev, "no gpio-controller child node\n");
746 nr_irq_parent = of_irq_count(np);
747 spin_lock_init(&info->irq_lock);
749 if (!nr_irq_parent) {
750 dev_err(dev, "invalid or no IRQ\n");
754 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
755 dev_err(dev, "cannot find IO resource\n");
759 info->base = devm_ioremap_resource(info->dev, &res);
760 if (IS_ERR(info->base))
761 return PTR_ERR(info->base);
763 irqchip->irq_ack = armada_37xx_irq_ack;
764 irqchip->irq_mask = armada_37xx_irq_mask;
765 irqchip->irq_unmask = armada_37xx_irq_unmask;
766 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
767 irqchip->irq_set_type = armada_37xx_irq_set_type;
768 irqchip->irq_startup = armada_37xx_irq_startup;
769 irqchip->name = info->data->name;
770 girq->chip = irqchip;
771 girq->parent_handler = armada_37xx_irq_handler;
773 * Many interrupts are connected to the parent interrupt
774 * controller. But we do not take advantage of this and use
775 * the chained irq with all of them.
777 girq->num_parents = nr_irq_parent;
778 girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent,
779 sizeof(*girq->parents), GFP_KERNEL);
782 for (i = 0; i < nr_irq_parent; i++) {
783 int irq = irq_of_parse_and_map(np, i);
787 girq->parents[i] = irq;
789 girq->default_type = IRQ_TYPE_NONE;
790 girq->handler = handle_edge_irq;
795 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
796 struct armada_37xx_pinctrl *info)
798 struct device_node *np;
799 struct gpio_chip *gc;
802 for_each_child_of_node(info->dev->of_node, np) {
803 if (of_find_property(np, "gpio-controller", NULL)) {
811 info->gpio_chip = armada_37xx_gpiolib_chip;
813 gc = &info->gpio_chip;
814 gc->ngpio = info->data->nr_pins;
815 gc->parent = &pdev->dev;
818 gc->label = info->data->name;
820 ret = armada_37xx_irqchip_register(pdev, info);
823 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
831 * armada_37xx_add_function() - Add a new function to the list
832 * @funcs: array of function to add the new one
833 * @funcsize: size of the remaining space for the function
834 * @name: name of the function to add
836 * If it is a new function then create it by adding its name else
837 * increment the number of group associated to this function.
839 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
840 int *funcsize, const char *name)
847 while (funcs->ngroups) {
848 /* function already there */
849 if (strcmp(funcs->name, name) == 0) {
858 /* append new unique function */
867 * armada_37xx_fill_group() - complete the group array
868 * @info: info driver instance
870 * Based on the data available from the armada_37xx_pin_group array
871 * completes the last member of the struct for each function: the list
872 * of the groups associated to this function.
875 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
877 int n, num = 0, funcsize = info->data->nr_pins;
879 for (n = 0; n < info->ngroups; n++) {
880 struct armada_37xx_pin_group *grp = &info->groups[n];
883 grp->pins = devm_kcalloc(info->dev,
884 grp->npins + grp->extra_npins,
890 for (i = 0; i < grp->npins; i++)
891 grp->pins[i] = grp->start_pin + i;
893 for (j = 0; j < grp->extra_npins; j++)
894 grp->pins[i+j] = grp->extra_pin + j;
896 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
898 /* check for unique functions and count groups */
899 ret = armada_37xx_add_function(info->funcs, &funcsize,
901 if (ret == -EOVERFLOW)
903 "More functions than pins(%d)\n",
904 info->data->nr_pins);
917 * armada_37xx_fill_funcs() - complete the funcs array
918 * @info: info driver instance
920 * Based on the data available from the armada_37xx_pin_group array
921 * completes the last two member of the struct for each group:
922 * - the list of the pins included in the group
923 * - the list of pinmux functions that can be selected for this group
926 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
928 struct armada_37xx_pmx_func *funcs = info->funcs;
931 for (n = 0; n < info->nfuncs; n++) {
932 const char *name = funcs[n].name;
936 funcs[n].groups = devm_kcalloc(info->dev,
938 sizeof(*(funcs[n].groups)),
940 if (!funcs[n].groups)
943 groups = funcs[n].groups;
945 for (g = 0; g < info->ngroups; g++) {
946 struct armada_37xx_pin_group *gp = &info->groups[g];
949 f = match_string(gp->funcs, NB_FUNCS, name);
960 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
961 struct armada_37xx_pinctrl *info)
963 const struct armada_37xx_pin_data *pin_data = info->data;
964 struct pinctrl_desc *ctrldesc = &info->pctl;
965 struct pinctrl_pin_desc *pindesc, *pdesc;
968 info->groups = pin_data->groups;
969 info->ngroups = pin_data->ngroups;
971 ctrldesc->name = "armada_37xx-pinctrl";
972 ctrldesc->owner = THIS_MODULE;
973 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
974 ctrldesc->pmxops = &armada_37xx_pmx_ops;
975 ctrldesc->confops = &armada_37xx_pinconf_ops;
977 pindesc = devm_kcalloc(&pdev->dev,
978 pin_data->nr_pins, sizeof(*pindesc),
983 ctrldesc->pins = pindesc;
984 ctrldesc->npins = pin_data->nr_pins;
987 for (pin = 0; pin < pin_data->nr_pins; pin++) {
989 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
990 pin_data->name, pin);
995 * we allocate functions for number of pins and hope there are
996 * fewer unique functions than pins available
998 info->funcs = devm_kcalloc(&pdev->dev,
1000 sizeof(struct armada_37xx_pmx_func),
1006 ret = armada_37xx_fill_group(info);
1010 ret = armada_37xx_fill_func(info);
1014 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1015 if (IS_ERR(info->pctl_dev)) {
1016 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1017 return PTR_ERR(info->pctl_dev);
1023 #if defined(CONFIG_PM)
1024 static int armada_3700_pinctrl_suspend(struct device *dev)
1026 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1028 /* Save GPIO state */
1029 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
1030 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
1031 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
1032 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
1033 &info->pm.out_val_h);
1035 info->pm.irq_en_l = readl(info->base + IRQ_EN);
1036 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
1037 info->pm.irq_pol_l = readl(info->base + IRQ_POL);
1038 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
1040 /* Save pinctrl state */
1041 regmap_read(info->regmap, SELECTION, &info->pm.selection);
1046 static int armada_3700_pinctrl_resume(struct device *dev)
1048 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1049 struct gpio_chip *gc;
1050 struct irq_domain *d;
1053 /* Restore GPIO state */
1054 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
1055 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
1057 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
1058 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
1059 info->pm.out_val_h);
1062 * Input levels may change during suspend, which is not monitored at
1063 * that time. GPIOs used for both-edge IRQs may not be synchronized
1064 * anymore with their polarities (rising/falling edge) and must be
1065 * re-configured manually.
1067 gc = &info->gpio_chip;
1069 for (i = 0; i < gc->ngpio; i++) {
1070 u32 irq_bit = BIT(i % GPIO_PER_REG);
1071 u32 mask, *irq_pol, input_reg, virq, type, level;
1073 if (i < GPIO_PER_REG) {
1074 mask = info->pm.irq_en_l;
1075 irq_pol = &info->pm.irq_pol_l;
1076 input_reg = INPUT_VAL;
1078 mask = info->pm.irq_en_h;
1079 irq_pol = &info->pm.irq_pol_h;
1080 input_reg = INPUT_VAL + sizeof(u32);
1083 if (!(mask & irq_bit))
1086 virq = irq_find_mapping(d, i);
1087 type = irq_get_trigger_type(virq);
1090 * Synchronize level and polarity for both-edge irqs:
1091 * - a high input level expects a falling edge,
1092 * - a low input level exepects a rising edge.
1094 if ((type & IRQ_TYPE_SENSE_MASK) ==
1095 IRQ_TYPE_EDGE_BOTH) {
1096 regmap_read(info->regmap, input_reg, &level);
1097 if ((*irq_pol ^ level) & irq_bit)
1098 *irq_pol ^= irq_bit;
1102 writel(info->pm.irq_en_l, info->base + IRQ_EN);
1103 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
1104 writel(info->pm.irq_pol_l, info->base + IRQ_POL);
1105 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
1107 /* Restore pinctrl state */
1108 regmap_write(info->regmap, SELECTION, info->pm.selection);
1114 * Since pinctrl is an infrastructure module, its resume should be issued prior
1115 * to other IO drivers.
1117 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
1118 .suspend_noirq = armada_3700_pinctrl_suspend,
1119 .resume_noirq = armada_3700_pinctrl_resume,
1122 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
1124 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
1125 #endif /* CONFIG_PM */
1127 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1129 .compatible = "marvell,armada3710-sb-pinctrl",
1130 .data = &armada_37xx_pin_sb,
1133 .compatible = "marvell,armada3710-nb-pinctrl",
1134 .data = &armada_37xx_pin_nb,
1139 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1141 struct armada_37xx_pinctrl *info;
1142 struct device *dev = &pdev->dev;
1143 struct device_node *np = dev->of_node;
1144 struct regmap *regmap;
1147 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
1154 regmap = syscon_node_to_regmap(np);
1155 if (IS_ERR(regmap)) {
1156 dev_err(&pdev->dev, "cannot get regmap\n");
1157 return PTR_ERR(regmap);
1159 info->regmap = regmap;
1161 info->data = of_device_get_match_data(dev);
1163 ret = armada_37xx_pinctrl_register(pdev, info);
1167 ret = armada_37xx_gpiochip_register(pdev, info);
1171 platform_set_drvdata(pdev, info);
1176 static struct platform_driver armada_37xx_pinctrl_driver = {
1178 .name = "armada-37xx-pinctrl",
1179 .of_match_table = armada_37xx_pinctrl_of_match,
1180 .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
1184 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1185 armada_37xx_pinctrl_probe);