drivers/pinctrl/intel/pinctrl-tigerlake.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Tiger Lake PCH pinctrl/GPIO driver
   4  *
   5  * Copyright (C) 2019 - 2020, Intel Corporation
   6  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/mod_devicetable.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13
  14 #include <linux/pinctrl/pinctrl.h>
  15
  16 #include "pinctrl-intel.h"
  17
  18 #define TGL_PAD_OWN             0x020
  19 #define TGL_LP_PADCFGLOCK       0x080
  20 #define TGL_H_PADCFGLOCK        0x090
  21 #define TGL_LP_HOSTSW_OWN       0x0b0
  22 #define TGL_H_HOSTSW_OWN        0x0c0
  23 #define TGL_GPI_IS              0x100
  24 #define TGL_GPI_IE              0x120
  25
  26 #define TGL_GPP(r, s, e, g)                             \
  27         {                                               \
  28                 .reg_num = (r),                         \
  29                 .base = (s),                            \
  30                 .size = ((e) - (s) + 1),                \
  31                 .gpio_base = (g),                       \
  32         }
  33
  34 #define TGL_COMMUNITY(b, s, e, pl, ho, g)               \
  35         {                                               \
  36                 .barno = (b),                           \
  37                 .padown_offset = TGL_PAD_OWN,           \
  38                 .padcfglock_offset = (pl),              \
  39                 .hostown_offset = (ho),                 \
  40                 .is_offset = TGL_GPI_IS,                \
  41                 .ie_offset = TGL_GPI_IE,                \
  42                 .pin_base = (s),                        \
  43                 .npins = ((e) - (s) + 1),               \
  44                 .gpps = (g),                            \
  45                 .ngpps = ARRAY_SIZE(g),                 \
  46         }
  47
  48 #define TGL_LP_COMMUNITY(b, s, e, g)                    \
  49         TGL_COMMUNITY(b, s, e, TGL_LP_PADCFGLOCK, TGL_LP_HOSTSW_OWN, g)
  50
  51 #define TGL_H_COMMUNITY(b, s, e, g)                     \
  52         TGL_COMMUNITY(b, s, e, TGL_H_PADCFGLOCK, TGL_H_HOSTSW_OWN, g)
  53
  54 /* Tiger Lake-LP */
  55 static const struct pinctrl_pin_desc tgllp_pins[] = {
  56         /* GPP_B */
  57         PINCTRL_PIN(0, "CORE_VID_0"),
  58         PINCTRL_PIN(1, "CORE_VID_1"),
  59         PINCTRL_PIN(2, "VRALERTB"),
  60         PINCTRL_PIN(3, "CPU_GP_2"),
  61         PINCTRL_PIN(4, "CPU_GP_3"),
  62         PINCTRL_PIN(5, "ISH_I2C0_SDA"),
  63         PINCTRL_PIN(6, "ISH_I2C0_SCL"),
  64         PINCTRL_PIN(7, "ISH_I2C1_SDA"),
  65         PINCTRL_PIN(8, "ISH_I2C1_SCL"),
  66         PINCTRL_PIN(9, "I2C5_SDA"),
  67         PINCTRL_PIN(10, "I2C5_SCL"),
  68         PINCTRL_PIN(11, "PMCALERTB"),
  69         PINCTRL_PIN(12, "SLP_S0B"),
  70         PINCTRL_PIN(13, "PLTRSTB"),
  71         PINCTRL_PIN(14, "SPKR"),
  72         PINCTRL_PIN(15, "GSPI0_CS0B"),
  73         PINCTRL_PIN(16, "GSPI0_CLK"),
  74         PINCTRL_PIN(17, "GSPI0_MISO"),
  75         PINCTRL_PIN(18, "GSPI0_MOSI"),
  76         PINCTRL_PIN(19, "GSPI1_CS0B"),
  77         PINCTRL_PIN(20, "GSPI1_CLK"),
  78         PINCTRL_PIN(21, "GSPI1_MISO"),
  79         PINCTRL_PIN(22, "GSPI1_MOSI"),
  80         PINCTRL_PIN(23, "SML1ALERTB"),
  81         PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
  82         PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
  83         /* GPP_T */
  84         PINCTRL_PIN(26, "I2C6_SDA"),
  85         PINCTRL_PIN(27, "I2C6_SCL"),
  86         PINCTRL_PIN(28, "I2C7_SDA"),
  87         PINCTRL_PIN(29, "I2C7_SCL"),
  88         PINCTRL_PIN(30, "UART4_RXD"),
  89         PINCTRL_PIN(31, "UART4_TXD"),
  90         PINCTRL_PIN(32, "UART4_RTSB"),
  91         PINCTRL_PIN(33, "UART4_CTSB"),
  92         PINCTRL_PIN(34, "UART5_RXD"),
  93         PINCTRL_PIN(35, "UART5_TXD"),
  94         PINCTRL_PIN(36, "UART5_RTSB"),
  95         PINCTRL_PIN(37, "UART5_CTSB"),
  96         PINCTRL_PIN(38, "UART6_RXD"),
  97         PINCTRL_PIN(39, "UART6_TXD"),
  98         PINCTRL_PIN(40, "UART6_RTSB"),
  99         PINCTRL_PIN(41, "UART6_CTSB"),
 100         /* GPP_A */
 101         PINCTRL_PIN(42, "ESPI_IO_0"),
 102         PINCTRL_PIN(43, "ESPI_IO_1"),
 103         PINCTRL_PIN(44, "ESPI_IO_2"),
 104         PINCTRL_PIN(45, "ESPI_IO_3"),
 105         PINCTRL_PIN(46, "ESPI_CSB"),
 106         PINCTRL_PIN(47, "ESPI_CLK"),
 107         PINCTRL_PIN(48, "ESPI_RESETB"),
 108         PINCTRL_PIN(49, "I2S2_SCLK"),
 109         PINCTRL_PIN(50, "I2S2_SFRM"),
 110         PINCTRL_PIN(51, "I2S2_TXD"),
 111         PINCTRL_PIN(52, "I2S2_RXD"),
 112         PINCTRL_PIN(53, "PMC_I2C_SDA"),
 113         PINCTRL_PIN(54, "SATAXPCIE_1"),
 114         PINCTRL_PIN(55, "PMC_I2C_SCL"),
 115         PINCTRL_PIN(56, "USB2_OCB_1"),
 116         PINCTRL_PIN(57, "USB2_OCB_2"),
 117         PINCTRL_PIN(58, "USB2_OCB_3"),
 118         PINCTRL_PIN(59, "DDSP_HPD_C"),
 119         PINCTRL_PIN(60, "DDSP_HPD_B"),
 120         PINCTRL_PIN(61, "DDSP_HPD_1"),
 121         PINCTRL_PIN(62, "DDSP_HPD_2"),
 122         PINCTRL_PIN(63, "GPPC_A_21"),
 123         PINCTRL_PIN(64, "GPPC_A_22"),
 124         PINCTRL_PIN(65, "I2S1_SCLK"),
 125         PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
 126         /* GPP_S */
 127         PINCTRL_PIN(67, "SNDW0_CLK"),
 128         PINCTRL_PIN(68, "SNDW0_DATA"),
 129         PINCTRL_PIN(69, "SNDW1_CLK"),
 130         PINCTRL_PIN(70, "SNDW1_DATA"),
 131         PINCTRL_PIN(71, "SNDW2_CLK"),
 132         PINCTRL_PIN(72, "SNDW2_DATA"),
 133         PINCTRL_PIN(73, "SNDW3_CLK"),
 134         PINCTRL_PIN(74, "SNDW3_DATA"),
 135         /* GPP_H */
 136         PINCTRL_PIN(75, "GPPC_H_0"),
 137         PINCTRL_PIN(76, "GPPC_H_1"),
 138         PINCTRL_PIN(77, "GPPC_H_2"),
 139         PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"),
 140         PINCTRL_PIN(79, "I2C2_SDA"),
 141         PINCTRL_PIN(80, "I2C2_SCL"),
 142         PINCTRL_PIN(81, "I2C3_SDA"),
 143         PINCTRL_PIN(82, "I2C3_SCL"),
 144         PINCTRL_PIN(83, "I2C4_SDA"),
 145         PINCTRL_PIN(84, "I2C4_SCL"),
 146         PINCTRL_PIN(85, "SRCCLKREQB_4"),
 147         PINCTRL_PIN(86, "SRCCLKREQB_5"),
 148         PINCTRL_PIN(87, "M2_SKT2_CFG_0"),
 149         PINCTRL_PIN(88, "M2_SKT2_CFG_1"),
 150         PINCTRL_PIN(89, "M2_SKT2_CFG_2"),
 151         PINCTRL_PIN(90, "M2_SKT2_CFG_3"),
 152         PINCTRL_PIN(91, "DDPB_CTRLCLK"),
 153         PINCTRL_PIN(92, "DDPB_CTRLDATA"),
 154         PINCTRL_PIN(93, "CPU_C10_GATEB"),
 155         PINCTRL_PIN(94, "TIME_SYNC_0"),
 156         PINCTRL_PIN(95, "IMGCLKOUT_1"),
 157         PINCTRL_PIN(96, "IMGCLKOUT_2"),
 158         PINCTRL_PIN(97, "IMGCLKOUT_3"),
 159         PINCTRL_PIN(98, "IMGCLKOUT_4"),
 160         /* GPP_D */
 161         PINCTRL_PIN(99, "ISH_GP_0"),
 162         PINCTRL_PIN(100, "ISH_GP_1"),
 163         PINCTRL_PIN(101, "ISH_GP_2"),
 164         PINCTRL_PIN(102, "ISH_GP_3"),
 165         PINCTRL_PIN(103, "IMGCLKOUT_0"),
 166         PINCTRL_PIN(104, "SRCCLKREQB_0"),
 167         PINCTRL_PIN(105, "SRCCLKREQB_1"),
 168         PINCTRL_PIN(106, "SRCCLKREQB_2"),
 169         PINCTRL_PIN(107, "SRCCLKREQB_3"),
 170         PINCTRL_PIN(108, "ISH_SPI_CSB"),
 171         PINCTRL_PIN(109, "ISH_SPI_CLK"),
 172         PINCTRL_PIN(110, "ISH_SPI_MISO"),
 173         PINCTRL_PIN(111, "ISH_SPI_MOSI"),
 174         PINCTRL_PIN(112, "ISH_UART0_RXD"),
 175         PINCTRL_PIN(113, "ISH_UART0_TXD"),
 176         PINCTRL_PIN(114, "ISH_UART0_RTSB"),
 177         PINCTRL_PIN(115, "ISH_UART0_CTSB"),
 178         PINCTRL_PIN(116, "ISH_GP_4"),
 179         PINCTRL_PIN(117, "ISH_GP_5"),
 180         PINCTRL_PIN(118, "I2S_MCLK1_OUT"),
 181         PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"),
 182         /* GPP_U */
 183         PINCTRL_PIN(120, "UART3_RXD"),
 184         PINCTRL_PIN(121, "UART3_TXD"),
 185         PINCTRL_PIN(122, "UART3_RTSB"),
 186         PINCTRL_PIN(123, "UART3_CTSB"),
 187         PINCTRL_PIN(124, "GSPI3_CS0B"),
 188         PINCTRL_PIN(125, "GSPI3_CLK"),
 189         PINCTRL_PIN(126, "GSPI3_MISO"),
 190         PINCTRL_PIN(127, "GSPI3_MOSI"),
 191         PINCTRL_PIN(128, "GSPI4_CS0B"),
 192         PINCTRL_PIN(129, "GSPI4_CLK"),
 193         PINCTRL_PIN(130, "GSPI4_MISO"),
 194         PINCTRL_PIN(131, "GSPI4_MOSI"),
 195         PINCTRL_PIN(132, "GSPI5_CS0B"),
 196         PINCTRL_PIN(133, "GSPI5_CLK"),
 197         PINCTRL_PIN(134, "GSPI5_MISO"),
 198         PINCTRL_PIN(135, "GSPI5_MOSI"),
 199         PINCTRL_PIN(136, "GSPI6_CS0B"),
 200         PINCTRL_PIN(137, "GSPI6_CLK"),
 201         PINCTRL_PIN(138, "GSPI6_MISO"),
 202         PINCTRL_PIN(139, "GSPI6_MOSI"),
 203         PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"),
 204         PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"),
 205         PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"),
 206         PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"),
 207         /* vGPIO */
 208         PINCTRL_PIN(144, "CNV_BTEN"),
 209         PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
 210         PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
 211         PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
 212         PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
 213         PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
 214         PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
 215         PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
 216         PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
 217         PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
 218         PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
 219         PINCTRL_PIN(155, "vUART0_TXD"),
 220         PINCTRL_PIN(156, "vUART0_RXD"),
 221         PINCTRL_PIN(157, "vUART0_CTS_B"),
 222         PINCTRL_PIN(158, "vUART0_RTS_B"),
 223         PINCTRL_PIN(159, "vISH_UART0_TXD"),
 224         PINCTRL_PIN(160, "vISH_UART0_RXD"),
 225         PINCTRL_PIN(161, "vISH_UART0_CTS_B"),
 226         PINCTRL_PIN(162, "vISH_UART0_RTS_B"),
 227         PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"),
 228         PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"),
 229         PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"),
 230         PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"),
 231         PINCTRL_PIN(167, "vI2S2_SCLK"),
 232         PINCTRL_PIN(168, "vI2S2_SFRM"),
 233         PINCTRL_PIN(169, "vI2S2_TXD"),
 234         PINCTRL_PIN(170, "vI2S2_RXD"),
 235         /* GPP_C */
 236         PINCTRL_PIN(171, "SMBCLK"),
 237         PINCTRL_PIN(172, "SMBDATA"),
 238         PINCTRL_PIN(173, "SMBALERTB"),
 239         PINCTRL_PIN(174, "SML0CLK"),
 240         PINCTRL_PIN(175, "SML0DATA"),
 241         PINCTRL_PIN(176, "SML0ALERTB"),
 242         PINCTRL_PIN(177, "SML1CLK"),
 243         PINCTRL_PIN(178, "SML1DATA"),
 244         PINCTRL_PIN(179, "UART0_RXD"),
 245         PINCTRL_PIN(180, "UART0_TXD"),
 246         PINCTRL_PIN(181, "UART0_RTSB"),
 247         PINCTRL_PIN(182, "UART0_CTSB"),
 248         PINCTRL_PIN(183, "UART1_RXD"),
 249         PINCTRL_PIN(184, "UART1_TXD"),
 250         PINCTRL_PIN(185, "UART1_RTSB"),
 251         PINCTRL_PIN(186, "UART1_CTSB"),
 252         PINCTRL_PIN(187, "I2C0_SDA"),
 253         PINCTRL_PIN(188, "I2C0_SCL"),
 254         PINCTRL_PIN(189, "I2C1_SDA"),
 255         PINCTRL_PIN(190, "I2C1_SCL"),
 256         PINCTRL_PIN(191, "UART2_RXD"),
 257         PINCTRL_PIN(192, "UART2_TXD"),
 258         PINCTRL_PIN(193, "UART2_RTSB"),
 259         PINCTRL_PIN(194, "UART2_CTSB"),
 260         /* GPP_F */
 261         PINCTRL_PIN(195, "CNV_BRI_DT"),
 262         PINCTRL_PIN(196, "CNV_BRI_RSP"),
 263         PINCTRL_PIN(197, "CNV_RGI_DT"),
 264         PINCTRL_PIN(198, "CNV_RGI_RSP"),
 265         PINCTRL_PIN(199, "CNV_RF_RESET_B"),
 266         PINCTRL_PIN(200, "GPPC_F_5"),
 267         PINCTRL_PIN(201, "CNV_PA_BLANKING"),
 268         PINCTRL_PIN(202, "GPPC_F_7"),
 269         PINCTRL_PIN(203, "I2S_MCLK2_INOUT"),
 270         PINCTRL_PIN(204, "BOOTMPC"),
 271         PINCTRL_PIN(205, "GPPC_F_10"),
 272         PINCTRL_PIN(206, "GPPC_F_11"),
 273         PINCTRL_PIN(207, "GSXDOUT"),
 274         PINCTRL_PIN(208, "GSXSLOAD"),
 275         PINCTRL_PIN(209, "GSXDIN"),
 276         PINCTRL_PIN(210, "GSXSRESETB"),
 277         PINCTRL_PIN(211, "GSXCLK"),
 278         PINCTRL_PIN(212, "GMII_MDC"),
 279         PINCTRL_PIN(213, "GMII_MDIO"),
 280         PINCTRL_PIN(214, "SRCCLKREQB_6"),
 281         PINCTRL_PIN(215, "EXT_PWR_GATEB"),
 282         PINCTRL_PIN(216, "EXT_PWR_GATE2B"),
 283         PINCTRL_PIN(217, "VNN_CTRL"),
 284         PINCTRL_PIN(218, "V1P05_CTRL"),
 285         PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"),
 286         /* HVCMOS */
 287         PINCTRL_PIN(220, "L_BKLTEN"),
 288         PINCTRL_PIN(221, "L_BKLTCTL"),
 289         PINCTRL_PIN(222, "L_VDDEN"),
 290         PINCTRL_PIN(223, "SYS_PWROK"),
 291         PINCTRL_PIN(224, "SYS_RESETB"),
 292         PINCTRL_PIN(225, "MLK_RSTB"),
 293         /* GPP_E */
 294         PINCTRL_PIN(226, "SATAXPCIE_0"),
 295         PINCTRL_PIN(227, "SPI1_IO_2"),
 296         PINCTRL_PIN(228, "SPI1_IO_3"),
 297         PINCTRL_PIN(229, "CPU_GP_0"),
 298         PINCTRL_PIN(230, "SATA_DEVSLP_0"),
 299         PINCTRL_PIN(231, "SATA_DEVSLP_1"),
 300         PINCTRL_PIN(232, "GPPC_E_6"),
 301         PINCTRL_PIN(233, "CPU_GP_1"),
 302         PINCTRL_PIN(234, "SPI1_CS1B"),
 303         PINCTRL_PIN(235, "USB2_OCB_0"),
 304         PINCTRL_PIN(236, "SPI1_CSB"),
 305         PINCTRL_PIN(237, "SPI1_CLK"),
 306         PINCTRL_PIN(238, "SPI1_MISO_IO_1"),
 307         PINCTRL_PIN(239, "SPI1_MOSI_IO_0"),
 308         PINCTRL_PIN(240, "DDSP_HPD_A"),
 309         PINCTRL_PIN(241, "ISH_GP_6"),
 310         PINCTRL_PIN(242, "ISH_GP_7"),
 311         PINCTRL_PIN(243, "GPPC_E_17"),
 312         PINCTRL_PIN(244, "DDP1_CTRLCLK"),
 313         PINCTRL_PIN(245, "DDP1_CTRLDATA"),
 314         PINCTRL_PIN(246, "DDP2_CTRLCLK"),
 315         PINCTRL_PIN(247, "DDP2_CTRLDATA"),
 316         PINCTRL_PIN(248, "DDPA_CTRLCLK"),
 317         PINCTRL_PIN(249, "DDPA_CTRLDATA"),
 318         PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"),
 319         /* JTAG */
 320         PINCTRL_PIN(251, "JTAG_TDO"),
 321         PINCTRL_PIN(252, "JTAGX"),
 322         PINCTRL_PIN(253, "PRDYB"),
 323         PINCTRL_PIN(254, "PREQB"),
 324         PINCTRL_PIN(255, "CPU_TRSTB"),
 325         PINCTRL_PIN(256, "JTAG_TDI"),
 326         PINCTRL_PIN(257, "JTAG_TMS"),
 327         PINCTRL_PIN(258, "JTAG_TCK"),
 328         PINCTRL_PIN(259, "DBG_PMODE"),
 329         /* GPP_R */
 330         PINCTRL_PIN(260, "HDA_BCLK"),
 331         PINCTRL_PIN(261, "HDA_SYNC"),
 332         PINCTRL_PIN(262, "HDA_SDO"),
 333         PINCTRL_PIN(263, "HDA_SDI_0"),
 334         PINCTRL_PIN(264, "HDA_RSTB"),
 335         PINCTRL_PIN(265, "HDA_SDI_1"),
 336         PINCTRL_PIN(266, "GPP_R_6"),
 337         PINCTRL_PIN(267, "GPP_R_7"),
 338         /* SPI */
 339         PINCTRL_PIN(268, "SPI0_IO_2"),
 340         PINCTRL_PIN(269, "SPI0_IO_3"),
 341         PINCTRL_PIN(270, "SPI0_MOSI_IO_0"),
 342         PINCTRL_PIN(271, "SPI0_MISO_IO_1"),
 343         PINCTRL_PIN(272, "SPI0_TPM_CSB"),
 344         PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"),
 345         PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"),
 346         PINCTRL_PIN(275, "SPI0_CLK"),
 347         PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"),
 348 };
 349
 350 static const struct intel_padgroup tgllp_community0_gpps[] = {
 351         TGL_GPP(0, 0, 25, 0),                           /* GPP_B */
 352         TGL_GPP(1, 26, 41, 32),                         /* GPP_T */
 353         TGL_GPP(2, 42, 66, 64),                         /* GPP_A */
 354 };
 355
 356 static const struct intel_padgroup tgllp_community1_gpps[] = {
 357         TGL_GPP(0, 67, 74, 96),                         /* GPP_S */
 358         TGL_GPP(1, 75, 98, 128),                        /* GPP_H */
 359         TGL_GPP(2, 99, 119, 160),                       /* GPP_D */
 360         TGL_GPP(3, 120, 143, 192),                      /* GPP_U */
 361         TGL_GPP(4, 144, 170, 224),                      /* vGPIO */
 362 };
 363
 364 static const struct intel_padgroup tgllp_community4_gpps[] = {
 365         TGL_GPP(0, 171, 194, 256),                      /* GPP_C */
 366         TGL_GPP(1, 195, 219, 288),                      /* GPP_F */
 367         TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP),    /* HVCMOS */
 368         TGL_GPP(3, 226, 250, 320),                      /* GPP_E */
 369         TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP),    /* JTAG */
 370 };
 371
 372 static const struct intel_padgroup tgllp_community5_gpps[] = {
 373         TGL_GPP(0, 260, 267, 352),                      /* GPP_R */
 374         TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP),    /* SPI */
 375 };
 376
 377 static const struct intel_community tgllp_communities[] = {
 378         TGL_LP_COMMUNITY(0, 0, 66, tgllp_community0_gpps),
 379         TGL_LP_COMMUNITY(1, 67, 170, tgllp_community1_gpps),
 380         TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
 381         TGL_LP_COMMUNITY(3, 260, 276, tgllp_community5_gpps),
 382 };
 383
 384 static const struct intel_pinctrl_soc_data tgllp_soc_data = {
 385         .pins = tgllp_pins,
 386         .npins = ARRAY_SIZE(tgllp_pins),
 387         .communities = tgllp_communities,
 388         .ncommunities = ARRAY_SIZE(tgllp_communities),
 389 };
 390
 391 /* Tiger Lake-H */
 392 static const struct pinctrl_pin_desc tglh_pins[] = {
 393         /* GPP_A */
 394         PINCTRL_PIN(0, "SPI0_IO_2"),
 395         PINCTRL_PIN(1, "SPI0_IO_3"),
 396         PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
 397         PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
 398         PINCTRL_PIN(4, "SPI0_TPM_CSB"),
 399         PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
 400         PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
 401         PINCTRL_PIN(7, "SPI0_CLK"),
 402         PINCTRL_PIN(8, "ESPI_IO_0"),
 403         PINCTRL_PIN(9, "ESPI_IO_1"),
 404         PINCTRL_PIN(10, "ESPI_IO_2"),
 405         PINCTRL_PIN(11, "ESPI_IO_3"),
 406         PINCTRL_PIN(12, "ESPI_CS0B"),
 407         PINCTRL_PIN(13, "ESPI_CLK"),
 408         PINCTRL_PIN(14, "ESPI_RESETB"),
 409         PINCTRL_PIN(15, "ESPI_CS1B"),
 410         PINCTRL_PIN(16, "ESPI_CS2B"),
 411         PINCTRL_PIN(17, "ESPI_CS3B"),
 412         PINCTRL_PIN(18, "ESPI_ALERT0B"),
 413         PINCTRL_PIN(19, "ESPI_ALERT1B"),
 414         PINCTRL_PIN(20, "ESPI_ALERT2B"),
 415         PINCTRL_PIN(21, "ESPI_ALERT3B"),
 416         PINCTRL_PIN(22, "GPPC_A_14"),
 417         PINCTRL_PIN(23, "SPI0_CLK_LOOPBK"),
 418         PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
 419         /* GPP_R */
 420         PINCTRL_PIN(25, "HDA_BCLK"),
 421         PINCTRL_PIN(26, "HDA_SYNC"),
 422         PINCTRL_PIN(27, "HDA_SDO"),
 423         PINCTRL_PIN(28, "HDA_SDI_0"),
 424         PINCTRL_PIN(29, "HDA_RSTB"),
 425         PINCTRL_PIN(30, "HDA_SDI_1"),
 426         PINCTRL_PIN(31, "GPP_R_6"),
 427         PINCTRL_PIN(32, "GPP_R_7"),
 428         PINCTRL_PIN(33, "GPP_R_8"),
 429         PINCTRL_PIN(34, "PCIE_LNK_DOWN"),
 430         PINCTRL_PIN(35, "ISH_UART0_RTSB"),
 431         PINCTRL_PIN(36, "SX_EXIT_HOLDOFFB"),
 432         PINCTRL_PIN(37, "CLKOUT_48"),
 433         PINCTRL_PIN(38, "ISH_GP_7"),
 434         PINCTRL_PIN(39, "ISH_GP_0"),
 435         PINCTRL_PIN(40, "ISH_GP_1"),
 436         PINCTRL_PIN(41, "ISH_GP_2"),
 437         PINCTRL_PIN(42, "ISH_GP_3"),
 438         PINCTRL_PIN(43, "ISH_GP_4"),
 439         PINCTRL_PIN(44, "ISH_GP_5"),
 440         /* GPP_B */
 441         PINCTRL_PIN(45, "GSPI0_CS1B"),
 442         PINCTRL_PIN(46, "GSPI1_CS1B"),
 443         PINCTRL_PIN(47, "VRALERTB"),
 444         PINCTRL_PIN(48, "CPU_GP_2"),
 445         PINCTRL_PIN(49, "CPU_GP_3"),
 446         PINCTRL_PIN(50, "SRCCLKREQB_0"),
 447         PINCTRL_PIN(51, "SRCCLKREQB_1"),
 448         PINCTRL_PIN(52, "SRCCLKREQB_2"),
 449         PINCTRL_PIN(53, "SRCCLKREQB_3"),
 450         PINCTRL_PIN(54, "SRCCLKREQB_4"),
 451         PINCTRL_PIN(55, "SRCCLKREQB_5"),
 452         PINCTRL_PIN(56, "I2S_MCLK"),
 453         PINCTRL_PIN(57, "SLP_S0B"),
 454         PINCTRL_PIN(58, "PLTRSTB"),
 455         PINCTRL_PIN(59, "SPKR"),
 456         PINCTRL_PIN(60, "GSPI0_CS0B"),
 457         PINCTRL_PIN(61, "GSPI0_CLK"),
 458         PINCTRL_PIN(62, "GSPI0_MISO"),
 459         PINCTRL_PIN(63, "GSPI0_MOSI"),
 460         PINCTRL_PIN(64, "GSPI1_CS0B"),
 461         PINCTRL_PIN(65, "GSPI1_CLK"),
 462         PINCTRL_PIN(66, "GSPI1_MISO"),
 463         PINCTRL_PIN(67, "GSPI1_MOSI"),
 464         PINCTRL_PIN(68, "SML1ALERTB"),
 465         PINCTRL_PIN(69, "GSPI0_CLK_LOOPBK"),
 466         PINCTRL_PIN(70, "GSPI1_CLK_LOOPBK"),
 467         /* vGPIO_0 */
 468         PINCTRL_PIN(71, "ESPI_USB_OCB_0"),
 469         PINCTRL_PIN(72, "ESPI_USB_OCB_1"),
 470         PINCTRL_PIN(73, "ESPI_USB_OCB_2"),
 471         PINCTRL_PIN(74, "ESPI_USB_OCB_3"),
 472         PINCTRL_PIN(75, "USB_CPU_OCB_0"),
 473         PINCTRL_PIN(76, "USB_CPU_OCB_1"),
 474         PINCTRL_PIN(77, "USB_CPU_OCB_2"),
 475         PINCTRL_PIN(78, "USB_CPU_OCB_3"),
 476         /* GPP_D */
 477         PINCTRL_PIN(79, "SPI1_CSB"),
 478         PINCTRL_PIN(80, "SPI1_CLK"),
 479         PINCTRL_PIN(81, "SPI1_MISO_IO_1"),
 480         PINCTRL_PIN(82, "SPI1_MOSI_IO_0"),
 481         PINCTRL_PIN(83, "SML1CLK"),
 482         PINCTRL_PIN(84, "I2S2_SFRM"),
 483         PINCTRL_PIN(85, "I2S2_TXD"),
 484         PINCTRL_PIN(86, "I2S2_RXD"),
 485         PINCTRL_PIN(87, "I2S2_SCLK"),
 486         PINCTRL_PIN(88, "SML0CLK"),
 487         PINCTRL_PIN(89, "SML0DATA"),
 488         PINCTRL_PIN(90, "GPP_D_11"),
 489         PINCTRL_PIN(91, "ISH_UART0_CTSB"),
 490         PINCTRL_PIN(92, "SPI1_IO_2"),
 491         PINCTRL_PIN(93, "SPI1_IO_3"),
 492         PINCTRL_PIN(94, "SML1DATA"),
 493         PINCTRL_PIN(95, "GSPI3_CS0B"),
 494         PINCTRL_PIN(96, "GSPI3_CLK"),
 495         PINCTRL_PIN(97, "GSPI3_MISO"),
 496         PINCTRL_PIN(98, "GSPI3_MOSI"),
 497         PINCTRL_PIN(99, "UART3_RXD"),
 498         PINCTRL_PIN(100, "UART3_TXD"),
 499         PINCTRL_PIN(101, "UART3_RTSB"),
 500         PINCTRL_PIN(102, "UART3_CTSB"),
 501         PINCTRL_PIN(103, "SPI1_CLK_LOOPBK"),
 502         PINCTRL_PIN(104, "GSPI3_CLK_LOOPBK"),
 503         /* GPP_C */
 504         PINCTRL_PIN(105, "SMBCLK"),
 505         PINCTRL_PIN(106, "SMBDATA"),
 506         PINCTRL_PIN(107, "SMBALERTB"),
 507         PINCTRL_PIN(108, "ISH_UART0_RXD"),
 508         PINCTRL_PIN(109, "ISH_UART0_TXD"),
 509         PINCTRL_PIN(110, "SML0ALERTB"),
 510         PINCTRL_PIN(111, "ISH_I2C2_SDA"),
 511         PINCTRL_PIN(112, "ISH_I2C2_SCL"),
 512         PINCTRL_PIN(113, "UART0_RXD"),
 513         PINCTRL_PIN(114, "UART0_TXD"),
 514         PINCTRL_PIN(115, "UART0_RTSB"),
 515         PINCTRL_PIN(116, "UART0_CTSB"),
 516         PINCTRL_PIN(117, "UART1_RXD"),
 517         PINCTRL_PIN(118, "UART1_TXD"),
 518         PINCTRL_PIN(119, "UART1_RTSB"),
 519         PINCTRL_PIN(120, "UART1_CTSB"),
 520         PINCTRL_PIN(121, "I2C0_SDA"),
 521         PINCTRL_PIN(122, "I2C0_SCL"),
 522         PINCTRL_PIN(123, "I2C1_SDA"),
 523         PINCTRL_PIN(124, "I2C1_SCL"),
 524         PINCTRL_PIN(125, "UART2_RXD"),
 525         PINCTRL_PIN(126, "UART2_TXD"),
 526         PINCTRL_PIN(127, "UART2_RTSB"),
 527         PINCTRL_PIN(128, "UART2_CTSB"),
 528         /* GPP_S */
 529         PINCTRL_PIN(129, "SNDW1_CLK"),
 530         PINCTRL_PIN(130, "SNDW1_DATA"),
 531         PINCTRL_PIN(131, "SNDW2_CLK"),
 532         PINCTRL_PIN(132, "SNDW2_DATA"),
 533         PINCTRL_PIN(133, "SNDW3_CLK"),
 534         PINCTRL_PIN(134, "SNDW3_DATA"),
 535         PINCTRL_PIN(135, "SNDW4_CLK"),
 536         PINCTRL_PIN(136, "SNDW4_DATA"),
 537         /* GPP_G */
 538         PINCTRL_PIN(137, "DDPA_CTRLCLK"),
 539         PINCTRL_PIN(138, "DDPA_CTRLDATA"),
 540         PINCTRL_PIN(139, "DNX_FORCE_RELOAD"),
 541         PINCTRL_PIN(140, "GMII_MDC_0"),
 542         PINCTRL_PIN(141, "GMII_MDIO_0"),
 543         PINCTRL_PIN(142, "SLP_DRAMB"),
 544         PINCTRL_PIN(143, "GPPC_G_6"),
 545         PINCTRL_PIN(144, "GPPC_G_7"),
 546         PINCTRL_PIN(145, "ISH_SPI_CSB"),
 547         PINCTRL_PIN(146, "ISH_SPI_CLK"),
 548         PINCTRL_PIN(147, "ISH_SPI_MISO"),
 549         PINCTRL_PIN(148, "ISH_SPI_MOSI"),
 550         PINCTRL_PIN(149, "DDP1_CTRLCLK"),
 551         PINCTRL_PIN(150, "DDP1_CTRLDATA"),
 552         PINCTRL_PIN(151, "DDP2_CTRLCLK"),
 553         PINCTRL_PIN(152, "DDP2_CTRLDATA"),
 554         PINCTRL_PIN(153, "GSPI2_CLK_LOOPBK"),
 555         /* vGPIO */
 556         PINCTRL_PIN(154, "CNV_BTEN"),
 557         PINCTRL_PIN(155, "CNV_BT_HOST_WAKEB"),
 558         PINCTRL_PIN(156, "CNV_BT_IF_SELECT"),
 559         PINCTRL_PIN(157, "vCNV_BT_UART_TXD"),
 560         PINCTRL_PIN(158, "vCNV_BT_UART_RXD"),
 561         PINCTRL_PIN(159, "vCNV_BT_UART_CTS_B"),
 562         PINCTRL_PIN(160, "vCNV_BT_UART_RTS_B"),
 563         PINCTRL_PIN(161, "vCNV_MFUART1_TXD"),
 564         PINCTRL_PIN(162, "vCNV_MFUART1_RXD"),
 565         PINCTRL_PIN(163, "vCNV_MFUART1_CTS_B"),
 566         PINCTRL_PIN(164, "vCNV_MFUART1_RTS_B"),
 567         PINCTRL_PIN(165, "vUART0_TXD"),
 568         PINCTRL_PIN(166, "vUART0_RXD"),
 569         PINCTRL_PIN(167, "vUART0_CTS_B"),
 570         PINCTRL_PIN(168, "vUART0_RTS_B"),
 571         PINCTRL_PIN(169, "vISH_UART0_TXD"),
 572         PINCTRL_PIN(170, "vISH_UART0_RXD"),
 573         PINCTRL_PIN(171, "vISH_UART0_CTS_B"),
 574         PINCTRL_PIN(172, "vISH_UART0_RTS_B"),
 575         PINCTRL_PIN(173, "vCNV_BT_I2S_BCLK"),
 576         PINCTRL_PIN(174, "vCNV_BT_I2S_WS_SYNC"),
 577         PINCTRL_PIN(175, "vCNV_BT_I2S_SDO"),
 578         PINCTRL_PIN(176, "vCNV_BT_I2S_SDI"),
 579         PINCTRL_PIN(177, "vI2S2_SCLK"),
 580         PINCTRL_PIN(178, "vI2S2_SFRM"),
 581         PINCTRL_PIN(179, "vI2S2_TXD"),
 582         PINCTRL_PIN(180, "vI2S2_RXD"),
 583         /* GPP_E */
 584         PINCTRL_PIN(181, "SATAXPCIE_0"),
 585         PINCTRL_PIN(182, "SATAXPCIE_1"),
 586         PINCTRL_PIN(183, "SATAXPCIE_2"),
 587         PINCTRL_PIN(184, "CPU_GP_0"),
 588         PINCTRL_PIN(185, "SATA_DEVSLP_0"),
 589         PINCTRL_PIN(186, "SATA_DEVSLP_1"),
 590         PINCTRL_PIN(187, "SATA_DEVSLP_2"),
 591         PINCTRL_PIN(188, "CPU_GP_1"),
 592         PINCTRL_PIN(189, "SATA_LEDB"),
 593         PINCTRL_PIN(190, "USB2_OCB_0"),
 594         PINCTRL_PIN(191, "USB2_OCB_1"),
 595         PINCTRL_PIN(192, "USB2_OCB_2"),
 596         PINCTRL_PIN(193, "USB2_OCB_3"),
 597         /* GPP_F */
 598         PINCTRL_PIN(194, "SATAXPCIE_3"),
 599         PINCTRL_PIN(195, "SATAXPCIE_4"),
 600         PINCTRL_PIN(196, "SATAXPCIE_5"),
 601         PINCTRL_PIN(197, "SATAXPCIE_6"),
 602         PINCTRL_PIN(198, "SATAXPCIE_7"),
 603         PINCTRL_PIN(199, "SATA_DEVSLP_3"),
 604         PINCTRL_PIN(200, "SATA_DEVSLP_4"),
 605         PINCTRL_PIN(201, "SATA_DEVSLP_5"),
 606         PINCTRL_PIN(202, "SATA_DEVSLP_6"),
 607         PINCTRL_PIN(203, "SATA_DEVSLP_7"),
 608         PINCTRL_PIN(204, "SATA_SCLOCK"),
 609         PINCTRL_PIN(205, "SATA_SLOAD"),
 610         PINCTRL_PIN(206, "SATA_SDATAOUT1"),
 611         PINCTRL_PIN(207, "SATA_SDATAOUT0"),
 612         PINCTRL_PIN(208, "PS_ONB"),
 613         PINCTRL_PIN(209, "M2_SKT2_CFG_0"),
 614         PINCTRL_PIN(210, "M2_SKT2_CFG_1"),
 615         PINCTRL_PIN(211, "M2_SKT2_CFG_2"),
 616         PINCTRL_PIN(212, "M2_SKT2_CFG_3"),
 617         PINCTRL_PIN(213, "L_VDDEN"),
 618         PINCTRL_PIN(214, "L_BKLTEN"),
 619         PINCTRL_PIN(215, "L_BKLTCTL"),
 620         PINCTRL_PIN(216, "VNN_CTRL"),
 621         PINCTRL_PIN(217, "GPP_F_23"),
 622         /* GPP_H */
 623         PINCTRL_PIN(218, "SRCCLKREQB_6"),
 624         PINCTRL_PIN(219, "SRCCLKREQB_7"),
 625         PINCTRL_PIN(220, "SRCCLKREQB_8"),
 626         PINCTRL_PIN(221, "SRCCLKREQB_9"),
 627         PINCTRL_PIN(222, "SRCCLKREQB_10"),
 628         PINCTRL_PIN(223, "SRCCLKREQB_11"),
 629         PINCTRL_PIN(224, "SRCCLKREQB_12"),
 630         PINCTRL_PIN(225, "SRCCLKREQB_13"),
 631         PINCTRL_PIN(226, "SRCCLKREQB_14"),
 632         PINCTRL_PIN(227, "SRCCLKREQB_15"),
 633         PINCTRL_PIN(228, "SML2CLK"),
 634         PINCTRL_PIN(229, "SML2DATA"),
 635         PINCTRL_PIN(230, "SML2ALERTB"),
 636         PINCTRL_PIN(231, "SML3CLK"),
 637         PINCTRL_PIN(232, "SML3DATA"),
 638         PINCTRL_PIN(233, "SML3ALERTB"),
 639         PINCTRL_PIN(234, "SML4CLK"),
 640         PINCTRL_PIN(235, "SML4DATA"),
 641         PINCTRL_PIN(236, "SML4ALERTB"),
 642         PINCTRL_PIN(237, "ISH_I2C0_SDA"),
 643         PINCTRL_PIN(238, "ISH_I2C0_SCL"),
 644         PINCTRL_PIN(239, "ISH_I2C1_SDA"),
 645         PINCTRL_PIN(240, "ISH_I2C1_SCL"),
 646         PINCTRL_PIN(241, "TIME_SYNC_0"),
 647         /* GPP_J */
 648         PINCTRL_PIN(242, "CNV_PA_BLANKING"),
 649         PINCTRL_PIN(243, "CPU_C10_GATEB"),
 650         PINCTRL_PIN(244, "CNV_BRI_DT"),
 651         PINCTRL_PIN(245, "CNV_BRI_RSP"),
 652         PINCTRL_PIN(246, "CNV_RGI_DT"),
 653         PINCTRL_PIN(247, "CNV_RGI_RSP"),
 654         PINCTRL_PIN(248, "CNV_MFUART2_RXD"),
 655         PINCTRL_PIN(249, "CNV_MFUART2_TXD"),
 656         PINCTRL_PIN(250, "GPP_J_8"),
 657         PINCTRL_PIN(251, "GPP_J_9"),
 658         /* GPP_K */
 659         PINCTRL_PIN(252, "GSXDOUT"),
 660         PINCTRL_PIN(253, "GSXSLOAD"),
 661         PINCTRL_PIN(254, "GSXDIN"),
 662         PINCTRL_PIN(255, "GSXSRESETB"),
 663         PINCTRL_PIN(256, "GSXCLK"),
 664         PINCTRL_PIN(257, "ADR_COMPLETE"),
 665         PINCTRL_PIN(258, "DDSP_HPD_A"),
 666         PINCTRL_PIN(259, "DDSP_HPD_B"),
 667         PINCTRL_PIN(260, "CORE_VID_0"),
 668         PINCTRL_PIN(261, "CORE_VID_1"),
 669         PINCTRL_PIN(262, "DDSP_HPD_C"),
 670         PINCTRL_PIN(263, "GPP_K_11"),
 671         PINCTRL_PIN(264, "SYS_PWROK"),
 672         PINCTRL_PIN(265, "SYS_RESETB"),
 673         PINCTRL_PIN(266, "MLK_RSTB"),
 674         /* GPP_I */
 675         PINCTRL_PIN(267, "PMCALERTB"),
 676         PINCTRL_PIN(268, "DDSP_HPD_1"),
 677         PINCTRL_PIN(269, "DDSP_HPD_2"),
 678         PINCTRL_PIN(270, "DDSP_HPD_3"),
 679         PINCTRL_PIN(271, "DDSP_HPD_4"),
 680         PINCTRL_PIN(272, "DDPB_CTRLCLK"),
 681         PINCTRL_PIN(273, "DDPB_CTRLDATA"),
 682         PINCTRL_PIN(274, "DDPC_CTRLCLK"),
 683         PINCTRL_PIN(275, "DDPC_CTRLDATA"),
 684         PINCTRL_PIN(276, "FUSA_DIAGTEST_EN"),
 685         PINCTRL_PIN(277, "FUSA_DIAGTEST_MODE"),
 686         PINCTRL_PIN(278, "USB2_OCB_4"),
 687         PINCTRL_PIN(279, "USB2_OCB_5"),
 688         PINCTRL_PIN(280, "USB2_OCB_6"),
 689         PINCTRL_PIN(281, "USB2_OCB_7"),
 690         /* JTAG */
 691         PINCTRL_PIN(282, "JTAG_TDO"),
 692         PINCTRL_PIN(283, "JTAGX"),
 693         PINCTRL_PIN(284, "PRDYB"),
 694         PINCTRL_PIN(285, "PREQB"),
 695         PINCTRL_PIN(286, "JTAG_TDI"),
 696         PINCTRL_PIN(287, "JTAG_TMS"),
 697         PINCTRL_PIN(288, "JTAG_TCK"),
 698         PINCTRL_PIN(289, "DBG_PMODE"),
 699         PINCTRL_PIN(290, "CPU_TRSTB"),
 700 };
 701
 702 static const struct intel_padgroup tglh_community0_gpps[] = {
 703         TGL_GPP(0, 0, 24, 0),                           /* GPP_A */
 704         TGL_GPP(1, 25, 44, 128),                        /* GPP_R */
 705         TGL_GPP(2, 45, 70, 32),                         /* GPP_B */
 706         TGL_GPP(3, 71, 78, INTEL_GPIO_BASE_NOMAP),      /* vGPIO_0 */
 707 };
 708
 709 static const struct intel_padgroup tglh_community1_gpps[] = {
 710         TGL_GPP(0, 79, 104, 96),                        /* GPP_D */
 711         TGL_GPP(1, 105, 128, 64),                       /* GPP_C */
 712         TGL_GPP(2, 129, 136, 160),                      /* GPP_S */
 713         TGL_GPP(3, 137, 153, 192),                      /* GPP_G */
 714         TGL_GPP(4, 154, 180, 224),                      /* vGPIO */
 715 };
 716
 717 static const struct intel_padgroup tglh_community3_gpps[] = {
 718         TGL_GPP(0, 181, 193, 256),                      /* GPP_E */
 719         TGL_GPP(1, 194, 217, 288),                      /* GPP_F */
 720 };
 721
 722 static const struct intel_padgroup tglh_community4_gpps[] = {
 723         TGL_GPP(0, 218, 241, 320),                      /* GPP_H */
 724         TGL_GPP(1, 242, 251, 384),                      /* GPP_J */
 725         TGL_GPP(2, 252, 266, 352),                      /* GPP_K */
 726 };
 727
 728 static const struct intel_padgroup tglh_community5_gpps[] = {
 729         TGL_GPP(0, 267, 281, 416),                      /* GPP_I */
 730         TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP),    /* JTAG */
 731 };
 732
 733 static const struct intel_community tglh_communities[] = {
 734         TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps),
 735         TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps),
 736         TGL_H_COMMUNITY(2, 181, 217, tglh_community3_gpps),
 737         TGL_H_COMMUNITY(3, 218, 266, tglh_community4_gpps),
 738         TGL_H_COMMUNITY(4, 267, 290, tglh_community5_gpps),
 739 };
 740
 741 static const struct intel_pinctrl_soc_data tglh_soc_data = {
 742         .pins = tglh_pins,
 743         .npins = ARRAY_SIZE(tglh_pins),
 744         .communities = tglh_communities,
 745         .ncommunities = ARRAY_SIZE(tglh_communities),
 746 };
 747
 748 static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
 749         { "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
 750         { "INT34C6", (kernel_ulong_t)&tglh_soc_data },
 751         { "INTC1055", (kernel_ulong_t)&tgllp_soc_data },
 752         { "INTC1057", (kernel_ulong_t)&tgllp_soc_data },
 753         { }
 754 };
 755 MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
 756
 757 static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);
 758
 759 static struct platform_driver tgl_pinctrl_driver = {
 760         .probe = intel_pinctrl_probe_by_hid,
 761         .driver = {
 762                 .name = "tigerlake-pinctrl",
 763                 .acpi_match_table = tgl_pinctrl_acpi_match,
 764                 .pm = &tgl_pinctrl_pm_ops,
 765         },
 766 };
 767
 768 module_platform_driver(tgl_pinctrl_driver);
 769
 770 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
 771 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 772 MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver");
 773 MODULE_LICENSE("GPL v2");