drivers/phy/ti/phy-j721e-wiz.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Wrapper driver for SERDES used in J721E
   4  *
   5  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
   6  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   7  */
   8
   9 #include <dt-bindings/phy/phy.h>
  10 #include <dt-bindings/phy/phy-ti.h>
  11 #include <linux/slab.h>
  12 #include <linux/clk.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/gpio.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/mux/consumer.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/reset-controller.h>
  25
  26 #define WIZ_SERDES_CTRL         0x404
  27 #define WIZ_SERDES_TOP_CTRL     0x408
  28 #define WIZ_SERDES_RST          0x40c
  29 #define WIZ_SERDES_TYPEC        0x410
  30 #define WIZ_LANECTL(n)          (0x480 + (0x40 * (n)))
  31 #define WIZ_LANEDIV(n)          (0x484 + (0x40 * (n)))
  32
  33 #define WIZ_MAX_INPUT_CLOCKS    4
  34 /* To include mux clocks, divider clocks and gate clocks */
  35 #define WIZ_MAX_OUTPUT_CLOCKS   32
  36
  37 #define WIZ_MAX_LANES           4
  38 #define WIZ_MUX_NUM_CLOCKS      3
  39 #define WIZ_DIV_NUM_CLOCKS_16G  2
  40 #define WIZ_DIV_NUM_CLOCKS_10G  1
  41
  42 #define WIZ_SERDES_TYPEC_LN10_SWAP      BIT(30)
  43
  44 enum wiz_lane_standard_mode {
  45         LANE_MODE_GEN1,
  46         LANE_MODE_GEN2,
  47         LANE_MODE_GEN3,
  48         LANE_MODE_GEN4,
  49 };
  50
  51 enum wiz_refclk_mux_sel {
  52         PLL0_REFCLK,
  53         PLL1_REFCLK,
  54         REFCLK_DIG,
  55 };
  56
  57 enum wiz_refclk_div_sel {
  58         CMN_REFCLK_DIG_DIV,
  59         CMN_REFCLK1_DIG_DIV,
  60 };
  61
  62 enum wiz_clock_input {
  63         WIZ_CORE_REFCLK,
  64         WIZ_EXT_REFCLK,
  65         WIZ_CORE_REFCLK1,
  66         WIZ_EXT_REFCLK1,
  67 };
  68
  69 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
  70 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
  71 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30);
  72 static const struct reg_field pll1_refclk_mux_sel =
  73                                         REG_FIELD(WIZ_SERDES_RST, 29, 29);
  74 static const struct reg_field pll0_refclk_mux_sel =
  75                                         REG_FIELD(WIZ_SERDES_RST, 28, 28);
  76 static const struct reg_field refclk_dig_sel_16g =
  77                                         REG_FIELD(WIZ_SERDES_RST, 24, 25);
  78 static const struct reg_field refclk_dig_sel_10g =
  79                                         REG_FIELD(WIZ_SERDES_RST, 24, 24);
  80 static const struct reg_field pma_cmn_refclk_int_mode =
  81                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
  82 static const struct reg_field pma_cmn_refclk_mode =
  83                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
  84 static const struct reg_field pma_cmn_refclk_dig_div =
  85                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
  86 static const struct reg_field pma_cmn_refclk1_dig_div =
  87                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
  88 static const char * const output_clk_names[] = {
  89         [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
  90         [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
  91         [TI_WIZ_REFCLK_DIG] = "refclk-dig",
  92         [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
  93 };
  94
  95 static const struct reg_field p_enable[WIZ_MAX_LANES] = {
  96         REG_FIELD(WIZ_LANECTL(0), 30, 31),
  97         REG_FIELD(WIZ_LANECTL(1), 30, 31),
  98         REG_FIELD(WIZ_LANECTL(2), 30, 31),
  99         REG_FIELD(WIZ_LANECTL(3), 30, 31),
 100 };
 101
 102 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
 103
 104 static const struct reg_field p_align[WIZ_MAX_LANES] = {
 105         REG_FIELD(WIZ_LANECTL(0), 29, 29),
 106         REG_FIELD(WIZ_LANECTL(1), 29, 29),
 107         REG_FIELD(WIZ_LANECTL(2), 29, 29),
 108         REG_FIELD(WIZ_LANECTL(3), 29, 29),
 109 };
 110
 111 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
 112         REG_FIELD(WIZ_LANECTL(0), 28, 28),
 113         REG_FIELD(WIZ_LANECTL(1), 28, 28),
 114         REG_FIELD(WIZ_LANECTL(2), 28, 28),
 115         REG_FIELD(WIZ_LANECTL(3), 28, 28),
 116 };
 117
 118 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
 119         REG_FIELD(WIZ_LANECTL(0), 24, 25),
 120         REG_FIELD(WIZ_LANECTL(1), 24, 25),
 121         REG_FIELD(WIZ_LANECTL(2), 24, 25),
 122         REG_FIELD(WIZ_LANECTL(3), 24, 25),
 123 };
 124
 125 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
 126         REG_FIELD(WIZ_LANECTL(0), 22, 23),
 127         REG_FIELD(WIZ_LANECTL(1), 22, 23),
 128         REG_FIELD(WIZ_LANECTL(2), 22, 23),
 129         REG_FIELD(WIZ_LANECTL(3), 22, 23),
 130 };
 131
 132 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
 133         REG_FIELD(WIZ_LANEDIV(0), 16, 22),
 134         REG_FIELD(WIZ_LANEDIV(1), 16, 22),
 135         REG_FIELD(WIZ_LANEDIV(2), 16, 22),
 136         REG_FIELD(WIZ_LANEDIV(3), 16, 22),
 137 };
 138
 139 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
 140         REG_FIELD(WIZ_LANEDIV(0), 0, 8),
 141         REG_FIELD(WIZ_LANEDIV(1), 0, 8),
 142         REG_FIELD(WIZ_LANEDIV(2), 0, 8),
 143         REG_FIELD(WIZ_LANEDIV(3), 0, 8),
 144 };
 145
 146 static const struct reg_field typec_ln10_swap =
 147                                         REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
 148
 149 struct wiz_clk_mux {
 150         struct clk_hw           hw;
 151         struct regmap_field     *field;
 152         const u32               *table;
 153         struct clk_init_data    clk_data;
 154 };
 155
 156 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw)
 157
 158 struct wiz_clk_divider {
 159         struct clk_hw           hw;
 160         struct regmap_field     *field;
 161         const struct clk_div_table      *table;
 162         struct clk_init_data    clk_data;
 163 };
 164
 165 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
 166
 167 struct wiz_clk_mux_sel {
 168         u32                     table[WIZ_MAX_INPUT_CLOCKS];
 169         const char              *node_name;
 170         u32                     num_parents;
 171         u32                     parents[WIZ_MAX_INPUT_CLOCKS];
 172 };
 173
 174 struct wiz_clk_div_sel {
 175         const struct clk_div_table *table;
 176         const char              *node_name;
 177 };
 178
 179 struct wiz_phy_en_refclk {
 180         struct clk_hw           hw;
 181         struct regmap_field     *phy_en_refclk;
 182         struct clk_init_data    clk_data;
 183 };
 184
 185 #define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw)
 186
 187 static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
 188         {
 189                 /*
 190                  * Mux value to be configured for each of the input clocks
 191                  * in the order populated in device tree
 192                  */
 193                 .table = { 1, 0 },
 194                 .node_name = "pll0-refclk",
 195         },
 196         {
 197                 .table = { 1, 0 },
 198                 .node_name = "pll1-refclk",
 199         },
 200         {
 201                 .table = { 1, 3, 0, 2 },
 202                 .node_name = "refclk-dig",
 203         },
 204 };
 205
 206 static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
 207         {
 208                 /*
 209                  * Mux value to be configured for each of the input clocks
 210                  * in the order populated in device tree
 211                  */
 212                 .num_parents = 2,
 213                 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
 214                 .table = { 1, 0 },
 215                 .node_name = "pll0-refclk",
 216         },
 217         {
 218                 .num_parents = 2,
 219                 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
 220                 .table = { 1, 0 },
 221                 .node_name = "pll1-refclk",
 222         },
 223         {
 224                 .num_parents = 2,
 225                 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
 226                 .table = { 1, 0 },
 227                 .node_name = "refclk-dig",
 228         },
 229 };
 230
 231 static const struct clk_div_table clk_div_table[] = {
 232         { .val = 0, .div = 1, },
 233         { .val = 1, .div = 2, },
 234         { .val = 2, .div = 4, },
 235         { .val = 3, .div = 8, },
 236         { /* sentinel */ },
 237 };
 238
 239 static const struct wiz_clk_div_sel clk_div_sel[] = {
 240         {
 241                 .table = clk_div_table,
 242                 .node_name = "cmn-refclk-dig-div",
 243         },
 244         {
 245                 .table = clk_div_table,
 246                 .node_name = "cmn-refclk1-dig-div",
 247         },
 248 };
 249
 250 enum wiz_type {
 251         J721E_WIZ_16G,
 252         J721E_WIZ_10G,
 253         AM64_WIZ_10G,
 254 };
 255
 256 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN      100     /* ms */
 257 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX      1000
 258
 259 struct wiz {
 260         struct regmap           *regmap;
 261         enum wiz_type           type;
 262         const struct wiz_clk_mux_sel *clk_mux_sel;
 263         const struct wiz_clk_div_sel *clk_div_sel;
 264         unsigned int            clk_div_sel_num;
 265         struct regmap_field     *por_en;
 266         struct regmap_field     *phy_reset_n;
 267         struct regmap_field     *phy_en_refclk;
 268         struct regmap_field     *p_enable[WIZ_MAX_LANES];
 269         struct regmap_field     *p_align[WIZ_MAX_LANES];
 270         struct regmap_field     *p_raw_auto_start[WIZ_MAX_LANES];
 271         struct regmap_field     *p_standard_mode[WIZ_MAX_LANES];
 272         struct regmap_field     *p_mac_div_sel0[WIZ_MAX_LANES];
 273         struct regmap_field     *p_mac_div_sel1[WIZ_MAX_LANES];
 274         struct regmap_field     *p0_fullrt_div[WIZ_MAX_LANES];
 275         struct regmap_field     *pma_cmn_refclk_int_mode;
 276         struct regmap_field     *pma_cmn_refclk_mode;
 277         struct regmap_field     *pma_cmn_refclk_dig_div;
 278         struct regmap_field     *pma_cmn_refclk1_dig_div;
 279         struct regmap_field     *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
 280         struct regmap_field     *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
 281         struct regmap_field     *typec_ln10_swap;
 282
 283         struct device           *dev;
 284         u32                     num_lanes;
 285         struct platform_device  *serdes_pdev;
 286         struct reset_controller_dev wiz_phy_reset_dev;
 287         struct gpio_desc        *gpio_typec_dir;
 288         int                     typec_dir_delay;
 289         u32 lane_phy_type[WIZ_MAX_LANES];
 290         struct clk              *input_clks[WIZ_MAX_INPUT_CLOCKS];
 291         struct clk              *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
 292         struct clk_onecell_data clk_data;
 293 };
 294
 295 static int wiz_reset(struct wiz *wiz)
 296 {
 297         int ret;
 298
 299         ret = regmap_field_write(wiz->por_en, 0x1);
 300         if (ret)
 301                 return ret;
 302
 303         mdelay(1);
 304
 305         ret = regmap_field_write(wiz->por_en, 0x0);
 306         if (ret)
 307                 return ret;
 308
 309         return 0;
 310 }
 311
 312 static int wiz_p_mac_div_sel(struct wiz *wiz)
 313 {
 314         u32 num_lanes = wiz->num_lanes;
 315         int ret;
 316         int i;
 317
 318         for (i = 0; i < num_lanes; i++) {
 319                 if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
 320                         ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
 321                         if (ret)
 322                                 return ret;
 323
 324                         ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
 325                         if (ret)
 326                                 return ret;
 327                 }
 328         }
 329
 330         return 0;
 331 }
 332
 333 static int wiz_mode_select(struct wiz *wiz)
 334 {
 335         u32 num_lanes = wiz->num_lanes;
 336         enum wiz_lane_standard_mode mode;
 337         int ret;
 338         int i;
 339
 340         for (i = 0; i < num_lanes; i++) {
 341                 if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
 342                         mode = LANE_MODE_GEN1;
 343                 else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII)
 344                         mode = LANE_MODE_GEN2;
 345                 else
 346                         continue;
 347
 348                 ret = regmap_field_write(wiz->p_standard_mode[i], mode);
 349                 if (ret)
 350                         return ret;
 351         }
 352
 353         return 0;
 354 }
 355
 356 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
 357 {
 358         u32 num_lanes = wiz->num_lanes;
 359         int i;
 360         int ret;
 361
 362         for (i = 0; i < num_lanes; i++) {
 363                 ret = regmap_field_write(wiz->p_align[i], enable);
 364                 if (ret)
 365                         return ret;
 366
 367                 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
 368                 if (ret)
 369                         return ret;
 370         }
 371
 372         return 0;
 373 }
 374
 375 static int wiz_init(struct wiz *wiz)
 376 {
 377         struct device *dev = wiz->dev;
 378         int ret;
 379
 380         ret = wiz_reset(wiz);
 381         if (ret) {
 382                 dev_err(dev, "WIZ reset failed\n");
 383                 return ret;
 384         }
 385
 386         ret = wiz_mode_select(wiz);
 387         if (ret) {
 388                 dev_err(dev, "WIZ mode select failed\n");
 389                 return ret;
 390         }
 391
 392         ret = wiz_p_mac_div_sel(wiz);
 393         if (ret) {
 394                 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n");
 395                 return ret;
 396         }
 397
 398         ret = wiz_init_raw_interface(wiz, true);
 399         if (ret) {
 400                 dev_err(dev, "WIZ interface initialization failed\n");
 401                 return ret;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static int wiz_regfield_init(struct wiz *wiz)
 408 {
 409         struct regmap *regmap = wiz->regmap;
 410         int num_lanes = wiz->num_lanes;
 411         struct device *dev = wiz->dev;
 412         int i;
 413
 414         wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
 415         if (IS_ERR(wiz->por_en)) {
 416                 dev_err(dev, "POR_EN reg field init failed\n");
 417                 return PTR_ERR(wiz->por_en);
 418         }
 419
 420         wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
 421                                                    phy_reset_n);
 422         if (IS_ERR(wiz->phy_reset_n)) {
 423                 dev_err(dev, "PHY_RESET_N reg field init failed\n");
 424                 return PTR_ERR(wiz->phy_reset_n);
 425         }
 426
 427         wiz->pma_cmn_refclk_int_mode =
 428                 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
 429         if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
 430                 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
 431                 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
 432         }
 433
 434         wiz->pma_cmn_refclk_mode =
 435                 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
 436         if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
 437                 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
 438                 return PTR_ERR(wiz->pma_cmn_refclk_mode);
 439         }
 440
 441         wiz->div_sel_field[CMN_REFCLK_DIG_DIV] =
 442                 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div);
 443         if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) {
 444                 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
 445                 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]);
 446         }
 447
 448         if (wiz->type == J721E_WIZ_16G) {
 449                 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =
 450                         devm_regmap_field_alloc(dev, regmap,
 451                                                 pma_cmn_refclk1_dig_div);
 452                 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {
 453                         dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
 454                         return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);
 455                 }
 456         }
 457
 458         wiz->mux_sel_field[PLL0_REFCLK] =
 459                 devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel);
 460         if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
 461                 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
 462                 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
 463         }
 464
 465         wiz->mux_sel_field[PLL1_REFCLK] =
 466                 devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel);
 467         if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
 468                 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
 469                 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
 470         }
 471
 472         if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
 473                 wiz->mux_sel_field[REFCLK_DIG] =
 474                         devm_regmap_field_alloc(dev, regmap,
 475                                                 refclk_dig_sel_10g);
 476         else
 477                 wiz->mux_sel_field[REFCLK_DIG] =
 478                         devm_regmap_field_alloc(dev, regmap,
 479                                                 refclk_dig_sel_16g);
 480
 481         if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
 482                 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
 483                 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
 484         }
 485
 486         for (i = 0; i < num_lanes; i++) {
 487                 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
 488                                                            p_enable[i]);
 489                 if (IS_ERR(wiz->p_enable[i])) {
 490                         dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
 491                         return PTR_ERR(wiz->p_enable[i]);
 492                 }
 493
 494                 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
 495                                                           p_align[i]);
 496                 if (IS_ERR(wiz->p_align[i])) {
 497                         dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
 498                         return PTR_ERR(wiz->p_align[i]);
 499                 }
 500
 501                 wiz->p_raw_auto_start[i] =
 502                   devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
 503                 if (IS_ERR(wiz->p_raw_auto_start[i])) {
 504                         dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
 505                                 i);
 506                         return PTR_ERR(wiz->p_raw_auto_start[i]);
 507                 }
 508
 509                 wiz->p_standard_mode[i] =
 510                   devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
 511                 if (IS_ERR(wiz->p_standard_mode[i])) {
 512                         dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
 513                                 i);
 514                         return PTR_ERR(wiz->p_standard_mode[i]);
 515                 }
 516
 517                 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
 518                 if (IS_ERR(wiz->p0_fullrt_div[i])) {
 519                         dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
 520                         return PTR_ERR(wiz->p0_fullrt_div[i]);
 521                 }
 522
 523                 wiz->p_mac_div_sel0[i] =
 524                   devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
 525                 if (IS_ERR(wiz->p_mac_div_sel0[i])) {
 526                         dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
 527                                 i);
 528                         return PTR_ERR(wiz->p_mac_div_sel0[i]);
 529                 }
 530
 531                 wiz->p_mac_div_sel1[i] =
 532                   devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]);
 533                 if (IS_ERR(wiz->p_mac_div_sel1[i])) {
 534                         dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
 535                                 i);
 536                         return PTR_ERR(wiz->p_mac_div_sel1[i]);
 537                 }
 538         }
 539
 540         wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
 541                                                        typec_ln10_swap);
 542         if (IS_ERR(wiz->typec_ln10_swap)) {
 543                 dev_err(dev, "LN10_SWAP reg field init failed\n");
 544                 return PTR_ERR(wiz->typec_ln10_swap);
 545         }
 546
 547         wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
 548         if (IS_ERR(wiz->phy_en_refclk)) {
 549                 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
 550                 return PTR_ERR(wiz->phy_en_refclk);
 551         }
 552
 553         return 0;
 554 }
 555
 556 static int wiz_phy_en_refclk_enable(struct clk_hw *hw)
 557 {
 558         struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
 559         struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
 560
 561         regmap_field_write(phy_en_refclk, 1);
 562
 563         return 0;
 564 }
 565
 566 static void wiz_phy_en_refclk_disable(struct clk_hw *hw)
 567 {
 568         struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
 569         struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
 570
 571         regmap_field_write(phy_en_refclk, 0);
 572 }
 573
 574 static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw)
 575 {
 576         struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
 577         struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
 578         int val;
 579
 580         regmap_field_read(phy_en_refclk, &val);
 581
 582         return !!val;
 583 }
 584
 585 static const struct clk_ops wiz_phy_en_refclk_ops = {
 586         .enable = wiz_phy_en_refclk_enable,
 587         .disable = wiz_phy_en_refclk_disable,
 588         .is_enabled = wiz_phy_en_refclk_is_enabled,
 589 };
 590
 591 static int wiz_phy_en_refclk_register(struct wiz *wiz)
 592 {
 593         struct wiz_phy_en_refclk *wiz_phy_en_refclk;
 594         struct device *dev = wiz->dev;
 595         struct clk_init_data *init;
 596         struct clk *clk;
 597
 598         wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL);
 599         if (!wiz_phy_en_refclk)
 600                 return -ENOMEM;
 601
 602         init = &wiz_phy_en_refclk->clk_data;
 603
 604         init->ops = &wiz_phy_en_refclk_ops;
 605         init->flags = 0;
 606         init->name = output_clk_names[TI_WIZ_PHY_EN_REFCLK];
 607
 608         wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk;
 609         wiz_phy_en_refclk->hw.init = init;
 610
 611         clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw);
 612         if (IS_ERR(clk))
 613                 return PTR_ERR(clk);
 614
 615         wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk;
 616
 617         return 0;
 618 }
 619
 620 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw)
 621 {
 622         struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
 623         struct regmap_field *field = mux->field;
 624         unsigned int val;
 625
 626         regmap_field_read(field, &val);
 627         return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val);
 628 }
 629
 630 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index)
 631 {
 632         struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
 633         struct regmap_field *field = mux->field;
 634         int val;
 635
 636         val = mux->table[index];
 637         return regmap_field_write(field, val);
 638 }
 639
 640 static const struct clk_ops wiz_clk_mux_ops = {
 641         .set_parent = wiz_clk_mux_set_parent,
 642         .get_parent = wiz_clk_mux_get_parent,
 643 };
 644
 645 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,
 646                                 const struct wiz_clk_mux_sel *mux_sel, int clk_index)
 647 {
 648         struct device *dev = wiz->dev;
 649         struct clk_init_data *init;
 650         const char **parent_names;
 651         unsigned int num_parents;
 652         struct wiz_clk_mux *mux;
 653         char clk_name[100];
 654         struct clk *clk;
 655         int ret = 0, i;
 656
 657         mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 658         if (!mux)
 659                 return -ENOMEM;
 660
 661         num_parents = mux_sel->num_parents;
 662
 663         parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
 664         if (!parent_names)
 665                 return -ENOMEM;
 666
 667         for (i = 0; i < num_parents; i++) {
 668                 clk = wiz->input_clks[mux_sel->parents[i]];
 669                 if (IS_ERR_OR_NULL(clk)) {
 670                         dev_err(dev, "Failed to get parent clk for %s\n",
 671                                 output_clk_names[clk_index]);
 672                         ret = -EINVAL;
 673                         goto err;
 674                 }
 675                 parent_names[i] = __clk_get_name(clk);
 676         }
 677
 678         snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]);
 679
 680         init = &mux->clk_data;
 681
 682         init->ops = &wiz_clk_mux_ops;
 683         init->flags = CLK_SET_RATE_NO_REPARENT;
 684         init->parent_names = parent_names;
 685         init->num_parents = num_parents;
 686         init->name = clk_name;
 687
 688         mux->field = field;
 689         mux->table = mux_sel->table;
 690         mux->hw.init = init;
 691
 692         clk = devm_clk_register(dev, &mux->hw);
 693         if (IS_ERR(clk)) {
 694                 ret = PTR_ERR(clk);
 695                 goto err;
 696         }
 697
 698         wiz->output_clks[clk_index] = clk;
 699
 700 err:
 701         kfree(parent_names);
 702
 703         return ret;
 704 }
 705
 706 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node,
 707                                    struct regmap_field *field, const u32 *table)
 708 {
 709         struct device *dev = wiz->dev;
 710         struct clk_init_data *init;
 711         const char **parent_names;
 712         unsigned int num_parents;
 713         struct wiz_clk_mux *mux;
 714         char clk_name[100];
 715         struct clk *clk;
 716         int ret;
 717
 718         mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 719         if (!mux)
 720                 return -ENOMEM;
 721
 722         num_parents = of_clk_get_parent_count(node);
 723         if (num_parents < 2) {
 724                 dev_err(dev, "SERDES clock must have parents\n");
 725                 return -EINVAL;
 726         }
 727
 728         parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
 729                                     GFP_KERNEL);
 730         if (!parent_names)
 731                 return -ENOMEM;
 732
 733         of_clk_parent_fill(node, parent_names, num_parents);
 734
 735         snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
 736                  node->name);
 737
 738         init = &mux->clk_data;
 739
 740         init->ops = &wiz_clk_mux_ops;
 741         init->flags = CLK_SET_RATE_NO_REPARENT;
 742         init->parent_names = parent_names;
 743         init->num_parents = num_parents;
 744         init->name = clk_name;
 745
 746         mux->field = field;
 747         mux->table = table;
 748         mux->hw.init = init;
 749
 750         clk = devm_clk_register(dev, &mux->hw);
 751         if (IS_ERR(clk))
 752                 return PTR_ERR(clk);
 753
 754         ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 755         if (ret)
 756                 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
 757
 758         return ret;
 759 }
 760
 761 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
 762                                              unsigned long parent_rate)
 763 {
 764         struct wiz_clk_divider *div = to_wiz_clk_div(hw);
 765         struct regmap_field *field = div->field;
 766         int val;
 767
 768         regmap_field_read(field, &val);
 769
 770         return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
 771 }
 772
 773 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
 774                                    unsigned long *prate)
 775 {
 776         struct wiz_clk_divider *div = to_wiz_clk_div(hw);
 777
 778         return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
 779 }
 780
 781 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
 782                                 unsigned long parent_rate)
 783 {
 784         struct wiz_clk_divider *div = to_wiz_clk_div(hw);
 785         struct regmap_field *field = div->field;
 786         int val;
 787
 788         val = divider_get_val(rate, parent_rate, div->table, 2, 0x0);
 789         if (val < 0)
 790                 return val;
 791
 792         return regmap_field_write(field, val);
 793 }
 794
 795 static const struct clk_ops wiz_clk_div_ops = {
 796         .recalc_rate = wiz_clk_div_recalc_rate,
 797         .round_rate = wiz_clk_div_round_rate,
 798         .set_rate = wiz_clk_div_set_rate,
 799 };
 800
 801 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
 802                                 struct regmap_field *field,
 803                                 const struct clk_div_table *table)
 804 {
 805         struct device *dev = wiz->dev;
 806         struct wiz_clk_divider *div;
 807         struct clk_init_data *init;
 808         const char **parent_names;
 809         char clk_name[100];
 810         struct clk *clk;
 811         int ret;
 812
 813         div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 814         if (!div)
 815                 return -ENOMEM;
 816
 817         snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
 818                  node->name);
 819
 820         parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
 821         if (!parent_names)
 822                 return -ENOMEM;
 823
 824         of_clk_parent_fill(node, parent_names, 1);
 825
 826         init = &div->clk_data;
 827
 828         init->ops = &wiz_clk_div_ops;
 829         init->flags = 0;
 830         init->parent_names = parent_names;
 831         init->num_parents = 1;
 832         init->name = clk_name;
 833
 834         div->field = field;
 835         div->table = table;
 836         div->hw.init = init;
 837
 838         clk = devm_clk_register(dev, &div->hw);
 839         if (IS_ERR(clk))
 840                 return PTR_ERR(clk);
 841
 842         ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 843         if (ret)
 844                 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
 845
 846         return ret;
 847 }
 848
 849 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
 850 {
 851         const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
 852         struct device *dev = wiz->dev;
 853         struct device_node *clk_node;
 854         int i;
 855
 856         if (wiz->type == AM64_WIZ_10G) {
 857                 of_clk_del_provider(dev->of_node);
 858                 return;
 859         }
 860
 861         for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
 862                 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
 863                 of_clk_del_provider(clk_node);
 864                 of_node_put(clk_node);
 865         }
 866
 867         for (i = 0; i < wiz->clk_div_sel_num; i++) {
 868                 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name);
 869                 of_clk_del_provider(clk_node);
 870                 of_node_put(clk_node);
 871         }
 872
 873         of_clk_del_provider(wiz->dev->of_node);
 874 }
 875
 876 static int wiz_clock_register(struct wiz *wiz)
 877 {
 878         const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
 879         struct device *dev = wiz->dev;
 880         struct device_node *node = dev->of_node;
 881         int clk_index;
 882         int ret;
 883         int i;
 884
 885         if (wiz->type != AM64_WIZ_10G)
 886                 return 0;
 887
 888         clk_index = TI_WIZ_PLL0_REFCLK;
 889         for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) {
 890                 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
 891                 if (ret) {
 892                         dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]);
 893                         return ret;
 894                 }
 895         }
 896
 897         ret = wiz_phy_en_refclk_register(wiz);
 898         if (ret) {
 899                 dev_err(dev, "Failed to add phy-en-refclk\n");
 900                 return ret;
 901         }
 902
 903         wiz->clk_data.clks = wiz->output_clks;
 904         wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;
 905         ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);
 906         if (ret)
 907                 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
 908
 909         return ret;
 910 }
 911
 912 static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
 913 {
 914         const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
 915         struct device *dev = wiz->dev;
 916         struct device_node *clk_node;
 917         const char *node_name;
 918         unsigned long rate;
 919         struct clk *clk;
 920         int ret;
 921         int i;
 922
 923         clk = devm_clk_get(dev, "core_ref_clk");
 924         if (IS_ERR(clk)) {
 925                 dev_err(dev, "core_ref_clk clock not found\n");
 926                 ret = PTR_ERR(clk);
 927                 return ret;
 928         }
 929         wiz->input_clks[WIZ_CORE_REFCLK] = clk;
 930
 931         rate = clk_get_rate(clk);
 932         if (rate >= 100000000)
 933                 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
 934         else
 935                 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
 936
 937         clk = devm_clk_get(dev, "ext_ref_clk");
 938         if (IS_ERR(clk)) {
 939                 dev_err(dev, "ext_ref_clk clock not found\n");
 940                 ret = PTR_ERR(clk);
 941                 return ret;
 942         }
 943         wiz->input_clks[WIZ_EXT_REFCLK] = clk;
 944
 945         rate = clk_get_rate(clk);
 946         if (rate >= 100000000)
 947                 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
 948         else
 949                 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
 950
 951         if (wiz->type == AM64_WIZ_10G) {
 952                 ret = wiz_clock_register(wiz);
 953                 if (ret)
 954                         dev_err(dev, "Failed to register wiz clocks\n");
 955                 return ret;
 956         }
 957
 958         for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
 959                 node_name = clk_mux_sel[i].node_name;
 960                 clk_node = of_get_child_by_name(node, node_name);
 961                 if (!clk_node) {
 962                         dev_err(dev, "Unable to get %s node\n", node_name);
 963                         ret = -EINVAL;
 964                         goto err;
 965                 }
 966
 967                 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i],
 968                                               clk_mux_sel[i].table);
 969                 if (ret) {
 970                         dev_err(dev, "Failed to register %s clock\n",
 971                                 node_name);
 972                         of_node_put(clk_node);
 973                         goto err;
 974                 }
 975
 976                 of_node_put(clk_node);
 977         }
 978
 979         for (i = 0; i < wiz->clk_div_sel_num; i++) {
 980                 node_name = clk_div_sel[i].node_name;
 981                 clk_node = of_get_child_by_name(node, node_name);
 982                 if (!clk_node) {
 983                         dev_err(dev, "Unable to get %s node\n", node_name);
 984                         ret = -EINVAL;
 985                         goto err;
 986                 }
 987
 988                 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i],
 989                                            clk_div_sel[i].table);
 990                 if (ret) {
 991                         dev_err(dev, "Failed to register %s clock\n",
 992                                 node_name);
 993                         of_node_put(clk_node);
 994                         goto err;
 995                 }
 996
 997                 of_node_put(clk_node);
 998         }
 999
1000         return 0;
1001 err:
1002         wiz_clock_cleanup(wiz, node);
1003
1004         return ret;
1005 }
1006
1007 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
1008                                 unsigned long id)
1009 {
1010         struct device *dev = rcdev->dev;
1011         struct wiz *wiz = dev_get_drvdata(dev);
1012         int ret = 0;
1013
1014         if (id == 0) {
1015                 ret = regmap_field_write(wiz->phy_reset_n, false);
1016                 return ret;
1017         }
1018
1019         ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
1020         return ret;
1021 }
1022
1023 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
1024 {
1025         if (wiz->type != AM64_WIZ_10G)
1026                 return 0;
1027
1028         if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
1029                 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
1030
1031         return 0;
1032 }
1033
1034 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
1035                                   unsigned long id)
1036 {
1037         struct device *dev = rcdev->dev;
1038         struct wiz *wiz = dev_get_drvdata(dev);
1039         int ret;
1040
1041         /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
1042         if (id == 0 && wiz->gpio_typec_dir) {
1043                 if (wiz->typec_dir_delay)
1044                         msleep_interruptible(wiz->typec_dir_delay);
1045
1046                 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1047                         regmap_field_write(wiz->typec_ln10_swap, 1);
1048                 else
1049                         regmap_field_write(wiz->typec_ln10_swap, 0);
1050         }
1051
1052         if (id == 0) {
1053                 ret = regmap_field_write(wiz->phy_reset_n, true);
1054                 return ret;
1055         }
1056
1057         ret = wiz_phy_fullrt_div(wiz, id - 1);
1058         if (ret)
1059                 return ret;
1060
1061         if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
1062                 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
1063         else
1064                 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
1065
1066         return ret;
1067 }
1068
1069 static const struct reset_control_ops wiz_phy_reset_ops = {
1070         .assert = wiz_phy_reset_assert,
1071         .deassert = wiz_phy_reset_deassert,
1072 };
1073
1074 static const struct regmap_config wiz_regmap_config = {
1075         .reg_bits = 32,
1076         .val_bits = 32,
1077         .reg_stride = 4,
1078         .fast_io = true,
1079 };
1080
1081 static const struct of_device_id wiz_id_table[] = {
1082         {
1083                 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
1084         },
1085         {
1086                 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
1087         },
1088         {
1089                 .compatible = "ti,am64-wiz-10g", .data = (void *)AM64_WIZ_10G
1090         },
1091         {}
1092 };
1093 MODULE_DEVICE_TABLE(of, wiz_id_table);
1094
1095 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
1096 {
1097         struct device_node *serdes, *subnode;
1098
1099         serdes = of_get_child_by_name(dev->of_node, "serdes");
1100         if (!serdes) {
1101                 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
1102                 return -EINVAL;
1103         }
1104
1105         for_each_child_of_node(serdes, subnode) {
1106                 u32 reg, num_lanes = 1, phy_type = PHY_NONE;
1107                 int ret, i;
1108
1109                 if (!(of_node_name_eq(subnode, "phy") ||
1110                       of_node_name_eq(subnode, "link")))
1111                         continue;
1112
1113                 ret = of_property_read_u32(subnode, "reg", &reg);
1114                 if (ret) {
1115                         of_node_put(subnode);
1116                         dev_err(dev,
1117                                 "%s: Reading \"reg\" from \"%s\" failed: %d\n",
1118                                 __func__, subnode->name, ret);
1119                         return ret;
1120                 }
1121                 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes);
1122                 of_property_read_u32(subnode, "cdns,phy-type", &phy_type);
1123
1124                 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
1125                         reg, reg + num_lanes - 1, phy_type);
1126
1127                 for (i = reg; i < reg + num_lanes; i++)
1128                         wiz->lane_phy_type[i] = phy_type;
1129         }
1130
1131         return 0;
1132 }
1133
1134 static int wiz_probe(struct platform_device *pdev)
1135 {
1136         struct reset_controller_dev *phy_reset_dev;
1137         struct device *dev = &pdev->dev;
1138         struct device_node *node = dev->of_node;
1139         struct platform_device *serdes_pdev;
1140         bool already_configured = false;
1141         struct device_node *child_node;
1142         struct regmap *regmap;
1143         struct resource res;
1144         void __iomem *base;
1145         struct wiz *wiz;
1146         int ret, val, i;
1147         u32 num_lanes;
1148
1149         wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
1150         if (!wiz)
1151                 return -ENOMEM;
1152
1153         wiz->type = (enum wiz_type)of_device_get_match_data(dev);
1154
1155         child_node = of_get_child_by_name(node, "serdes");
1156         if (!child_node) {
1157                 dev_err(dev, "Failed to get SERDES child DT node\n");
1158                 return -ENODEV;
1159         }
1160
1161         ret = of_address_to_resource(child_node, 0, &res);
1162         if (ret) {
1163                 dev_err(dev, "Failed to get memory resource\n");
1164                 goto err_addr_to_resource;
1165         }
1166
1167         base = devm_ioremap(dev, res.start, resource_size(&res));
1168         if (!base) {
1169                 ret = -ENOMEM;
1170                 goto err_addr_to_resource;
1171         }
1172
1173         regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config);
1174         if (IS_ERR(regmap)) {
1175                 dev_err(dev, "Failed to initialize regmap\n");
1176                 ret = PTR_ERR(regmap);
1177                 goto err_addr_to_resource;
1178         }
1179
1180         ret = of_property_read_u32(node, "num-lanes", &num_lanes);
1181         if (ret) {
1182                 dev_err(dev, "Failed to read num-lanes property\n");
1183                 goto err_addr_to_resource;
1184         }
1185
1186         if (num_lanes > WIZ_MAX_LANES) {
1187                 dev_err(dev, "Cannot support %d lanes\n", num_lanes);
1188                 ret = -ENODEV;
1189                 goto err_addr_to_resource;
1190         }
1191
1192         wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
1193                                                       GPIOD_IN);
1194         if (IS_ERR(wiz->gpio_typec_dir)) {
1195                 ret = PTR_ERR(wiz->gpio_typec_dir);
1196                 if (ret != -EPROBE_DEFER)
1197                         dev_err(dev, "Failed to request typec-dir gpio: %d\n",
1198                                 ret);
1199                 goto err_addr_to_resource;
1200         }
1201
1202         if (wiz->gpio_typec_dir) {
1203                 ret = of_property_read_u32(node, "typec-dir-debounce-ms",
1204                                            &wiz->typec_dir_delay);
1205                 if (ret && ret != -EINVAL) {
1206                         dev_err(dev, "Invalid typec-dir-debounce property\n");
1207                         goto err_addr_to_resource;
1208                 }
1209
1210                 /* use min. debounce from Type-C spec if not provided in DT  */
1211                 if (ret == -EINVAL)
1212                         wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
1213
1214                 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
1215                     wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
1216                         ret = -EINVAL;
1217                         dev_err(dev, "Invalid typec-dir-debounce property\n");
1218                         goto err_addr_to_resource;
1219                 }
1220         }
1221
1222         ret = wiz_get_lane_phy_types(dev, wiz);
1223         if (ret)
1224                 return ret;
1225
1226         wiz->dev = dev;
1227         wiz->regmap = regmap;
1228         wiz->num_lanes = num_lanes;
1229         if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
1230                 wiz->clk_mux_sel = clk_mux_sel_10g;
1231         else
1232                 wiz->clk_mux_sel = clk_mux_sel_16g;
1233
1234         wiz->clk_div_sel = clk_div_sel;
1235
1236         if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
1237                 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
1238         else
1239                 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
1240
1241         platform_set_drvdata(pdev, wiz);
1242
1243         ret = wiz_regfield_init(wiz);
1244         if (ret) {
1245                 dev_err(dev, "Failed to initialize regfields\n");
1246                 goto err_addr_to_resource;
1247         }
1248
1249         phy_reset_dev = &wiz->wiz_phy_reset_dev;
1250         phy_reset_dev->dev = dev;
1251         phy_reset_dev->ops = &wiz_phy_reset_ops,
1252         phy_reset_dev->owner = THIS_MODULE,
1253         phy_reset_dev->of_node = node;
1254         /* Reset for each of the lane and one for the entire SERDES */
1255         phy_reset_dev->nr_resets = num_lanes + 1;
1256
1257         ret = devm_reset_controller_register(dev, phy_reset_dev);
1258         if (ret < 0) {
1259                 dev_warn(dev, "Failed to register reset controller\n");
1260                 goto err_addr_to_resource;
1261         }
1262
1263         pm_runtime_enable(dev);
1264         ret = pm_runtime_get_sync(dev);
1265         if (ret < 0) {
1266                 dev_err(dev, "pm_runtime_get_sync failed\n");
1267                 goto err_get_sync;
1268         }
1269
1270         ret = wiz_clock_init(wiz, node);
1271         if (ret < 0) {
1272                 dev_warn(dev, "Failed to initialize clocks\n");
1273                 goto err_get_sync;
1274         }
1275
1276         for (i = 0; i < wiz->num_lanes; i++) {
1277                 regmap_field_read(wiz->p_enable[i], &val);
1278                 if (val & (P_ENABLE | P_ENABLE_FORCE)) {
1279                         already_configured = true;
1280                         break;
1281                 }
1282         }
1283
1284         if (!already_configured) {
1285                 ret = wiz_init(wiz);
1286                 if (ret) {
1287                         dev_err(dev, "WIZ initialization failed\n");
1288                         goto err_wiz_init;
1289                 }
1290         }
1291
1292         serdes_pdev = of_platform_device_create(child_node, NULL, dev);
1293         if (!serdes_pdev) {
1294                 dev_WARN(dev, "Unable to create SERDES platform device\n");
1295                 ret = -ENOMEM;
1296                 goto err_wiz_init;
1297         }
1298         wiz->serdes_pdev = serdes_pdev;
1299
1300         of_node_put(child_node);
1301         return 0;
1302
1303 err_wiz_init:
1304         wiz_clock_cleanup(wiz, node);
1305
1306 err_get_sync:
1307         pm_runtime_put(dev);
1308         pm_runtime_disable(dev);
1309
1310 err_addr_to_resource:
1311         of_node_put(child_node);
1312
1313         return ret;
1314 }
1315
1316 static int wiz_remove(struct platform_device *pdev)
1317 {
1318         struct device *dev = &pdev->dev;
1319         struct device_node *node = dev->of_node;
1320         struct platform_device *serdes_pdev;
1321         struct wiz *wiz;
1322
1323         wiz = dev_get_drvdata(dev);
1324         serdes_pdev = wiz->serdes_pdev;
1325
1326         of_platform_device_destroy(&serdes_pdev->dev, NULL);
1327         wiz_clock_cleanup(wiz, node);
1328         pm_runtime_put(dev);
1329         pm_runtime_disable(dev);
1330
1331         return 0;
1332 }
1333
1334 static struct platform_driver wiz_driver = {
1335         .probe          = wiz_probe,
1336         .remove         = wiz_remove,
1337         .driver         = {
1338                 .name   = "wiz",
1339                 .of_match_table = wiz_id_table,
1340         },
1341 };
1342 module_platform_driver(wiz_driver);
1343
1344 MODULE_AUTHOR("Texas Instruments Inc.");
1345 MODULE_DESCRIPTION("TI J721E WIZ driver");
1346 MODULE_LICENSE("GPL v2");