drivers/phy/ti/phy-j721e-wiz.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * Wrapper driver for SERDES used in J721E
   4  *
   5  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
   6  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   7  */
   8
   9 #include <dt-bindings/phy/phy.h>
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/gpio.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/mux/consumer.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset-controller.h>
  23 #include <dt-bindings/phy/phy.h>
  24
  25 #define WIZ_SERDES_CTRL         0x404
  26 #define WIZ_SERDES_TOP_CTRL     0x408
  27 #define WIZ_SERDES_RST          0x40c
  28 #define WIZ_SERDES_TYPEC        0x410
  29 #define WIZ_LANECTL(n)          (0x480 + (0x40 * (n)))
  30
  31 #define WIZ_MAX_LANES           4
  32 #define WIZ_MUX_NUM_CLOCKS      3
  33 #define WIZ_DIV_NUM_CLOCKS_16G  2
  34 #define WIZ_DIV_NUM_CLOCKS_10G  1
  35
  36 #define WIZ_SERDES_TYPEC_LN10_SWAP      BIT(30)
  37
  38 enum wiz_lane_standard_mode {
  39         LANE_MODE_GEN1,
  40         LANE_MODE_GEN2,
  41         LANE_MODE_GEN3,
  42         LANE_MODE_GEN4,
  43 };
  44
  45 enum wiz_refclk_mux_sel {
  46         PLL0_REFCLK,
  47         PLL1_REFCLK,
  48         REFCLK_DIG,
  49 };
  50
  51 enum wiz_refclk_div_sel {
  52         CMN_REFCLK_DIG_DIV,
  53         CMN_REFCLK1_DIG_DIV,
  54 };
  55
  56 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
  57 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
  58 static const struct reg_field pll1_refclk_mux_sel =
  59                                         REG_FIELD(WIZ_SERDES_RST, 29, 29);
  60 static const struct reg_field pll0_refclk_mux_sel =
  61                                         REG_FIELD(WIZ_SERDES_RST, 28, 28);
  62 static const struct reg_field refclk_dig_sel_16g =
  63                                         REG_FIELD(WIZ_SERDES_RST, 24, 25);
  64 static const struct reg_field refclk_dig_sel_10g =
  65                                         REG_FIELD(WIZ_SERDES_RST, 24, 24);
  66 static const struct reg_field pma_cmn_refclk_int_mode =
  67                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
  68 static const struct reg_field pma_cmn_refclk_mode =
  69                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
  70 static const struct reg_field pma_cmn_refclk_dig_div =
  71                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
  72 static const struct reg_field pma_cmn_refclk1_dig_div =
  73                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
  74
  75 static const struct reg_field p_enable[WIZ_MAX_LANES] = {
  76         REG_FIELD(WIZ_LANECTL(0), 30, 31),
  77         REG_FIELD(WIZ_LANECTL(1), 30, 31),
  78         REG_FIELD(WIZ_LANECTL(2), 30, 31),
  79         REG_FIELD(WIZ_LANECTL(3), 30, 31),
  80 };
  81
  82 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
  83
  84 static const struct reg_field p_align[WIZ_MAX_LANES] = {
  85         REG_FIELD(WIZ_LANECTL(0), 29, 29),
  86         REG_FIELD(WIZ_LANECTL(1), 29, 29),
  87         REG_FIELD(WIZ_LANECTL(2), 29, 29),
  88         REG_FIELD(WIZ_LANECTL(3), 29, 29),
  89 };
  90
  91 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
  92         REG_FIELD(WIZ_LANECTL(0), 28, 28),
  93         REG_FIELD(WIZ_LANECTL(1), 28, 28),
  94         REG_FIELD(WIZ_LANECTL(2), 28, 28),
  95         REG_FIELD(WIZ_LANECTL(3), 28, 28),
  96 };
  97
  98 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
  99         REG_FIELD(WIZ_LANECTL(0), 24, 25),
 100         REG_FIELD(WIZ_LANECTL(1), 24, 25),
 101         REG_FIELD(WIZ_LANECTL(2), 24, 25),
 102         REG_FIELD(WIZ_LANECTL(3), 24, 25),
 103 };
 104
 105 static const struct reg_field typec_ln10_swap =
 106                                         REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
 107
 108 struct wiz_clk_mux {
 109         struct clk_hw           hw;
 110         struct regmap_field     *field;
 111         u32                     *table;
 112         struct clk_init_data    clk_data;
 113 };
 114
 115 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw)
 116
 117 struct wiz_clk_divider {
 118         struct clk_hw           hw;
 119         struct regmap_field     *field;
 120         struct clk_div_table    *table;
 121         struct clk_init_data    clk_data;
 122 };
 123
 124 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
 125
 126 struct wiz_clk_mux_sel {
 127         struct regmap_field     *field;
 128         u32                     table[4];
 129         const char              *node_name;
 130 };
 131
 132 struct wiz_clk_div_sel {
 133         struct regmap_field     *field;
 134         struct clk_div_table    *table;
 135         const char              *node_name;
 136 };
 137
 138 static struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
 139         {
 140                 /*
 141                  * Mux value to be configured for each of the input clocks
 142                  * in the order populated in device tree
 143                  */
 144                 .table = { 1, 0 },
 145                 .node_name = "pll0-refclk",
 146         },
 147         {
 148                 .table = { 1, 0 },
 149                 .node_name = "pll1-refclk",
 150         },
 151         {
 152                 .table = { 1, 3, 0, 2 },
 153                 .node_name = "refclk-dig",
 154         },
 155 };
 156
 157 static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
 158         {
 159                 /*
 160                  * Mux value to be configured for each of the input clocks
 161                  * in the order populated in device tree
 162                  */
 163                 .table = { 1, 0 },
 164                 .node_name = "pll0-refclk",
 165         },
 166         {
 167                 .table = { 1, 0 },
 168                 .node_name = "pll1-refclk",
 169         },
 170         {
 171                 .table = { 1, 0 },
 172                 .node_name = "refclk-dig",
 173         },
 174 };
 175
 176 static struct clk_div_table clk_div_table[] = {
 177         { .val = 0, .div = 1, },
 178         { .val = 1, .div = 2, },
 179         { .val = 2, .div = 4, },
 180         { .val = 3, .div = 8, },
 181 };
 182
 183 static struct wiz_clk_div_sel clk_div_sel[] = {
 184         {
 185                 .table = clk_div_table,
 186                 .node_name = "cmn-refclk-dig-div",
 187         },
 188         {
 189                 .table = clk_div_table,
 190                 .node_name = "cmn-refclk1-dig-div",
 191         },
 192 };
 193
 194 enum wiz_type {
 195         J721E_WIZ_16G,
 196         J721E_WIZ_10G,
 197 };
 198
 199 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN      100     /* ms */
 200 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX      1000
 201
 202 struct wiz {
 203         struct regmap           *regmap;
 204         enum wiz_type           type;
 205         struct wiz_clk_mux_sel  *clk_mux_sel;
 206         struct wiz_clk_div_sel  *clk_div_sel;
 207         unsigned int            clk_div_sel_num;
 208         struct regmap_field     *por_en;
 209         struct regmap_field     *phy_reset_n;
 210         struct regmap_field     *p_enable[WIZ_MAX_LANES];
 211         struct regmap_field     *p_align[WIZ_MAX_LANES];
 212         struct regmap_field     *p_raw_auto_start[WIZ_MAX_LANES];
 213         struct regmap_field     *p_standard_mode[WIZ_MAX_LANES];
 214         struct regmap_field     *pma_cmn_refclk_int_mode;
 215         struct regmap_field     *pma_cmn_refclk_mode;
 216         struct regmap_field     *pma_cmn_refclk_dig_div;
 217         struct regmap_field     *pma_cmn_refclk1_dig_div;
 218         struct regmap_field     *typec_ln10_swap;
 219
 220         struct device           *dev;
 221         u32                     num_lanes;
 222         struct platform_device  *serdes_pdev;
 223         struct reset_controller_dev wiz_phy_reset_dev;
 224         struct gpio_desc        *gpio_typec_dir;
 225         int                     typec_dir_delay;
 226         u32 lane_phy_type[WIZ_MAX_LANES];
 227 };
 228
 229 static int wiz_reset(struct wiz *wiz)
 230 {
 231         int ret;
 232
 233         ret = regmap_field_write(wiz->por_en, 0x1);
 234         if (ret)
 235                 return ret;
 236
 237         mdelay(1);
 238
 239         ret = regmap_field_write(wiz->por_en, 0x0);
 240         if (ret)
 241                 return ret;
 242
 243         return 0;
 244 }
 245
 246 static int wiz_mode_select(struct wiz *wiz)
 247 {
 248         u32 num_lanes = wiz->num_lanes;
 249         enum wiz_lane_standard_mode mode;
 250         int ret;
 251         int i;
 252
 253         for (i = 0; i < num_lanes; i++) {
 254                 if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
 255                         mode = LANE_MODE_GEN1;
 256                 else
 257                         mode = LANE_MODE_GEN4;
 258
 259                 ret = regmap_field_write(wiz->p_standard_mode[i], mode);
 260                 if (ret)
 261                         return ret;
 262         }
 263
 264         return 0;
 265 }
 266
 267 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
 268 {
 269         u32 num_lanes = wiz->num_lanes;
 270         int i;
 271         int ret;
 272
 273         for (i = 0; i < num_lanes; i++) {
 274                 ret = regmap_field_write(wiz->p_align[i], enable);
 275                 if (ret)
 276                         return ret;
 277
 278                 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
 279                 if (ret)
 280                         return ret;
 281         }
 282
 283         return 0;
 284 }
 285
 286 static int wiz_init(struct wiz *wiz)
 287 {
 288         struct device *dev = wiz->dev;
 289         int ret;
 290
 291         ret = wiz_reset(wiz);
 292         if (ret) {
 293                 dev_err(dev, "WIZ reset failed\n");
 294                 return ret;
 295         }
 296
 297         ret = wiz_mode_select(wiz);
 298         if (ret) {
 299                 dev_err(dev, "WIZ mode select failed\n");
 300                 return ret;
 301         }
 302
 303         ret = wiz_init_raw_interface(wiz, true);
 304         if (ret) {
 305                 dev_err(dev, "WIZ interface initialization failed\n");
 306                 return ret;
 307         }
 308
 309         return 0;
 310 }
 311
 312 static int wiz_regfield_init(struct wiz *wiz)
 313 {
 314         struct wiz_clk_mux_sel *clk_mux_sel;
 315         struct wiz_clk_div_sel *clk_div_sel;
 316         struct regmap *regmap = wiz->regmap;
 317         int num_lanes = wiz->num_lanes;
 318         struct device *dev = wiz->dev;
 319         int i;
 320
 321         wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
 322         if (IS_ERR(wiz->por_en)) {
 323                 dev_err(dev, "POR_EN reg field init failed\n");
 324                 return PTR_ERR(wiz->por_en);
 325         }
 326
 327         wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
 328                                                    phy_reset_n);
 329         if (IS_ERR(wiz->phy_reset_n)) {
 330                 dev_err(dev, "PHY_RESET_N reg field init failed\n");
 331                 return PTR_ERR(wiz->phy_reset_n);
 332         }
 333
 334         wiz->pma_cmn_refclk_int_mode =
 335                 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
 336         if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
 337                 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
 338                 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
 339         }
 340
 341         wiz->pma_cmn_refclk_mode =
 342                 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
 343         if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
 344                 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
 345                 return PTR_ERR(wiz->pma_cmn_refclk_mode);
 346         }
 347
 348         clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV];
 349         clk_div_sel->field = devm_regmap_field_alloc(dev, regmap,
 350                                                      pma_cmn_refclk_dig_div);
 351         if (IS_ERR(clk_div_sel->field)) {
 352                 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
 353                 return PTR_ERR(clk_div_sel->field);
 354         }
 355
 356         if (wiz->type == J721E_WIZ_16G) {
 357                 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV];
 358                 clk_div_sel->field =
 359                         devm_regmap_field_alloc(dev, regmap,
 360                                                 pma_cmn_refclk1_dig_div);
 361                 if (IS_ERR(clk_div_sel->field)) {
 362                         dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
 363                         return PTR_ERR(clk_div_sel->field);
 364                 }
 365         }
 366
 367         clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK];
 368         clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap,
 369                                                      pll0_refclk_mux_sel);
 370         if (IS_ERR(clk_mux_sel->field)) {
 371                 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
 372                 return PTR_ERR(clk_mux_sel->field);
 373         }
 374
 375         clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK];
 376         clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap,
 377                                                      pll1_refclk_mux_sel);
 378         if (IS_ERR(clk_mux_sel->field)) {
 379                 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
 380                 return PTR_ERR(clk_mux_sel->field);
 381         }
 382
 383         clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG];
 384         if (wiz->type == J721E_WIZ_10G)
 385                 clk_mux_sel->field =
 386                         devm_regmap_field_alloc(dev, regmap,
 387                                                 refclk_dig_sel_10g);
 388         else
 389                 clk_mux_sel->field =
 390                         devm_regmap_field_alloc(dev, regmap,
 391                                                 refclk_dig_sel_16g);
 392
 393         if (IS_ERR(clk_mux_sel->field)) {
 394                 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
 395                 return PTR_ERR(clk_mux_sel->field);
 396         }
 397
 398         for (i = 0; i < num_lanes; i++) {
 399                 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
 400                                                            p_enable[i]);
 401                 if (IS_ERR(wiz->p_enable[i])) {
 402                         dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
 403                         return PTR_ERR(wiz->p_enable[i]);
 404                 }
 405
 406                 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
 407                                                           p_align[i]);
 408                 if (IS_ERR(wiz->p_align[i])) {
 409                         dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
 410                         return PTR_ERR(wiz->p_align[i]);
 411                 }
 412
 413                 wiz->p_raw_auto_start[i] =
 414                   devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
 415                 if (IS_ERR(wiz->p_raw_auto_start[i])) {
 416                         dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
 417                                 i);
 418                         return PTR_ERR(wiz->p_raw_auto_start[i]);
 419                 }
 420
 421                 wiz->p_standard_mode[i] =
 422                   devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
 423                 if (IS_ERR(wiz->p_standard_mode[i])) {
 424                         dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
 425                                 i);
 426                         return PTR_ERR(wiz->p_standard_mode[i]);
 427                 }
 428         }
 429
 430         wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
 431                                                        typec_ln10_swap);
 432         if (IS_ERR(wiz->typec_ln10_swap)) {
 433                 dev_err(dev, "LN10_SWAP reg field init failed\n");
 434                 return PTR_ERR(wiz->typec_ln10_swap);
 435         }
 436
 437         return 0;
 438 }
 439
 440 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw)
 441 {
 442         struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
 443         struct regmap_field *field = mux->field;
 444         unsigned int val;
 445
 446         regmap_field_read(field, &val);
 447         return clk_mux_val_to_index(hw, mux->table, 0, val);
 448 }
 449
 450 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index)
 451 {
 452         struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
 453         struct regmap_field *field = mux->field;
 454         int val;
 455
 456         val = mux->table[index];
 457         return regmap_field_write(field, val);
 458 }
 459
 460 static const struct clk_ops wiz_clk_mux_ops = {
 461         .set_parent = wiz_clk_mux_set_parent,
 462         .get_parent = wiz_clk_mux_get_parent,
 463 };
 464
 465 static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node,
 466                                 struct regmap_field *field, u32 *table)
 467 {
 468         struct device *dev = wiz->dev;
 469         struct clk_init_data *init;
 470         const char **parent_names;
 471         unsigned int num_parents;
 472         struct wiz_clk_mux *mux;
 473         char clk_name[100];
 474         struct clk *clk;
 475         int ret;
 476
 477         mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 478         if (!mux)
 479                 return -ENOMEM;
 480
 481         num_parents = of_clk_get_parent_count(node);
 482         if (num_parents < 2) {
 483                 dev_err(dev, "SERDES clock must have parents\n");
 484                 return -EINVAL;
 485         }
 486
 487         parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
 488                                     GFP_KERNEL);
 489         if (!parent_names)
 490                 return -ENOMEM;
 491
 492         of_clk_parent_fill(node, parent_names, num_parents);
 493
 494         snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
 495                  node->name);
 496
 497         init = &mux->clk_data;
 498
 499         init->ops = &wiz_clk_mux_ops;
 500         init->flags = CLK_SET_RATE_NO_REPARENT;
 501         init->parent_names = parent_names;
 502         init->num_parents = num_parents;
 503         init->name = clk_name;
 504
 505         mux->field = field;
 506         mux->table = table;
 507         mux->hw.init = init;
 508
 509         clk = devm_clk_register(dev, &mux->hw);
 510         if (IS_ERR(clk))
 511                 return PTR_ERR(clk);
 512
 513         ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 514         if (ret)
 515                 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
 516
 517         return ret;
 518 }
 519
 520 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
 521                                              unsigned long parent_rate)
 522 {
 523         struct wiz_clk_divider *div = to_wiz_clk_div(hw);
 524         struct regmap_field *field = div->field;
 525         int val;
 526
 527         regmap_field_read(field, &val);
 528
 529         return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
 530 }
 531
 532 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
 533                                    unsigned long *prate)
 534 {
 535         struct wiz_clk_divider *div = to_wiz_clk_div(hw);
 536
 537         return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
 538 }
 539
 540 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
 541                                 unsigned long parent_rate)
 542 {
 543         struct wiz_clk_divider *div = to_wiz_clk_div(hw);
 544         struct regmap_field *field = div->field;
 545         int val;
 546
 547         val = divider_get_val(rate, parent_rate, div->table, 2, 0x0);
 548         if (val < 0)
 549                 return val;
 550
 551         return regmap_field_write(field, val);
 552 }
 553
 554 static const struct clk_ops wiz_clk_div_ops = {
 555         .recalc_rate = wiz_clk_div_recalc_rate,
 556         .round_rate = wiz_clk_div_round_rate,
 557         .set_rate = wiz_clk_div_set_rate,
 558 };
 559
 560 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
 561                                 struct regmap_field *field,
 562                                 struct clk_div_table *table)
 563 {
 564         struct device *dev = wiz->dev;
 565         struct wiz_clk_divider *div;
 566         struct clk_init_data *init;
 567         const char **parent_names;
 568         char clk_name[100];
 569         struct clk *clk;
 570         int ret;
 571
 572         div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 573         if (!div)
 574                 return -ENOMEM;
 575
 576         snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
 577                  node->name);
 578
 579         parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
 580         if (!parent_names)
 581                 return -ENOMEM;
 582
 583         of_clk_parent_fill(node, parent_names, 1);
 584
 585         init = &div->clk_data;
 586
 587         init->ops = &wiz_clk_div_ops;
 588         init->flags = 0;
 589         init->parent_names = parent_names;
 590         init->num_parents = 1;
 591         init->name = clk_name;
 592
 593         div->field = field;
 594         div->table = table;
 595         div->hw.init = init;
 596
 597         clk = devm_clk_register(dev, &div->hw);
 598         if (IS_ERR(clk))
 599                 return PTR_ERR(clk);
 600
 601         ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 602         if (ret)
 603                 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
 604
 605         return ret;
 606 }
 607
 608 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
 609 {
 610         struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
 611         struct device_node *clk_node;
 612         int i;
 613
 614         for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
 615                 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
 616                 of_clk_del_provider(clk_node);
 617                 of_node_put(clk_node);
 618         }
 619 }
 620
 621 static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
 622 {
 623         struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
 624         struct device *dev = wiz->dev;
 625         struct device_node *clk_node;
 626         const char *node_name;
 627         unsigned long rate;
 628         struct clk *clk;
 629         int ret;
 630         int i;
 631
 632         clk = devm_clk_get(dev, "core_ref_clk");
 633         if (IS_ERR(clk)) {
 634                 dev_err(dev, "core_ref_clk clock not found\n");
 635                 ret = PTR_ERR(clk);
 636                 return ret;
 637         }
 638
 639         rate = clk_get_rate(clk);
 640         if (rate >= 100000000)
 641                 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
 642         else
 643                 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
 644
 645         clk = devm_clk_get(dev, "ext_ref_clk");
 646         if (IS_ERR(clk)) {
 647                 dev_err(dev, "ext_ref_clk clock not found\n");
 648                 ret = PTR_ERR(clk);
 649                 return ret;
 650         }
 651
 652         rate = clk_get_rate(clk);
 653         if (rate >= 100000000)
 654                 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
 655         else
 656                 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
 657
 658         for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
 659                 node_name = clk_mux_sel[i].node_name;
 660                 clk_node = of_get_child_by_name(node, node_name);
 661                 if (!clk_node) {
 662                         dev_err(dev, "Unable to get %s node\n", node_name);
 663                         ret = -EINVAL;
 664                         goto err;
 665                 }
 666
 667                 ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field,
 668                                            clk_mux_sel[i].table);
 669                 if (ret) {
 670                         dev_err(dev, "Failed to register %s clock\n",
 671                                 node_name);
 672                         of_node_put(clk_node);
 673                         goto err;
 674                 }
 675
 676                 of_node_put(clk_node);
 677         }
 678
 679         for (i = 0; i < wiz->clk_div_sel_num; i++) {
 680                 node_name = clk_div_sel[i].node_name;
 681                 clk_node = of_get_child_by_name(node, node_name);
 682                 if (!clk_node) {
 683                         dev_err(dev, "Unable to get %s node\n", node_name);
 684                         ret = -EINVAL;
 685                         goto err;
 686                 }
 687
 688                 ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field,
 689                                            clk_div_sel[i].table);
 690                 if (ret) {
 691                         dev_err(dev, "Failed to register %s clock\n",
 692                                 node_name);
 693                         of_node_put(clk_node);
 694                         goto err;
 695                 }
 696
 697                 of_node_put(clk_node);
 698         }
 699
 700         return 0;
 701 err:
 702         wiz_clock_cleanup(wiz, node);
 703
 704         return ret;
 705 }
 706
 707 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
 708                                 unsigned long id)
 709 {
 710         struct device *dev = rcdev->dev;
 711         struct wiz *wiz = dev_get_drvdata(dev);
 712         int ret = 0;
 713
 714         if (id == 0) {
 715                 ret = regmap_field_write(wiz->phy_reset_n, false);
 716                 return ret;
 717         }
 718
 719         ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
 720         return ret;
 721 }
 722
 723 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
 724                                   unsigned long id)
 725 {
 726         struct device *dev = rcdev->dev;
 727         struct wiz *wiz = dev_get_drvdata(dev);
 728         int ret;
 729
 730         /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
 731         if (id == 0 && wiz->gpio_typec_dir) {
 732                 if (wiz->typec_dir_delay)
 733                         msleep_interruptible(wiz->typec_dir_delay);
 734
 735                 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
 736                         regmap_field_write(wiz->typec_ln10_swap, 1);
 737                 else
 738                         regmap_field_write(wiz->typec_ln10_swap, 0);
 739         }
 740
 741         if (id == 0) {
 742                 ret = regmap_field_write(wiz->phy_reset_n, true);
 743                 return ret;
 744         }
 745
 746         if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
 747                 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
 748         else
 749                 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
 750
 751         return ret;
 752 }
 753
 754 static const struct reset_control_ops wiz_phy_reset_ops = {
 755         .assert = wiz_phy_reset_assert,
 756         .deassert = wiz_phy_reset_deassert,
 757 };
 758
 759 static struct regmap_config wiz_regmap_config = {
 760         .reg_bits = 32,
 761         .val_bits = 32,
 762         .reg_stride = 4,
 763         .fast_io = true,
 764 };
 765
 766 static const struct of_device_id wiz_id_table[] = {
 767         {
 768                 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
 769         },
 770         {
 771                 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
 772         },
 773         {}
 774 };
 775 MODULE_DEVICE_TABLE(of, wiz_id_table);
 776
 777 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
 778 {
 779         struct device_node *serdes, *subnode;
 780
 781         serdes = of_get_child_by_name(dev->of_node, "serdes");
 782         if (!serdes) {
 783                 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
 784                 return -EINVAL;
 785         }
 786
 787         for_each_child_of_node(serdes, subnode) {
 788                 u32 reg, num_lanes = 1, phy_type = PHY_NONE;
 789                 int ret, i;
 790
 791                 ret = of_property_read_u32(subnode, "reg", &reg);
 792                 if (ret) {
 793                         dev_err(dev,
 794                                 "%s: Reading \"reg\" from \"%s\" failed: %d\n",
 795                                 __func__, subnode->name, ret);
 796                         return ret;
 797                 }
 798                 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes);
 799                 of_property_read_u32(subnode, "cdns,phy-type", &phy_type);
 800
 801                 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
 802                         reg, reg + num_lanes - 1, phy_type);
 803
 804                 for (i = reg; i < reg + num_lanes; i++)
 805                         wiz->lane_phy_type[i] = phy_type;
 806         }
 807
 808         return 0;
 809 }
 810
 811 static int wiz_probe(struct platform_device *pdev)
 812 {
 813         struct reset_controller_dev *phy_reset_dev;
 814         struct device *dev = &pdev->dev;
 815         struct device_node *node = dev->of_node;
 816         struct platform_device *serdes_pdev;
 817         struct device_node *child_node;
 818         struct regmap *regmap;
 819         struct resource res;
 820         void __iomem *base;
 821         struct wiz *wiz;
 822         u32 num_lanes;
 823         int ret;
 824
 825         wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
 826         if (!wiz)
 827                 return -ENOMEM;
 828
 829         wiz->type = (enum wiz_type)of_device_get_match_data(dev);
 830
 831         child_node = of_get_child_by_name(node, "serdes");
 832         if (!child_node) {
 833                 dev_err(dev, "Failed to get SERDES child DT node\n");
 834                 return -ENODEV;
 835         }
 836
 837         ret = of_address_to_resource(child_node, 0, &res);
 838         if (ret) {
 839                 dev_err(dev, "Failed to get memory resource\n");
 840                 goto err_addr_to_resource;
 841         }
 842
 843         base = devm_ioremap(dev, res.start, resource_size(&res));
 844         if (!base) {
 845                 ret = -ENOMEM;
 846                 goto err_addr_to_resource;
 847         }
 848
 849         regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config);
 850         if (IS_ERR(regmap)) {
 851                 dev_err(dev, "Failed to initialize regmap\n");
 852                 ret = PTR_ERR(regmap);
 853                 goto err_addr_to_resource;
 854         }
 855
 856         ret = of_property_read_u32(node, "num-lanes", &num_lanes);
 857         if (ret) {
 858                 dev_err(dev, "Failed to read num-lanes property\n");
 859                 goto err_addr_to_resource;
 860         }
 861
 862         if (num_lanes > WIZ_MAX_LANES) {
 863                 dev_err(dev, "Cannot support %d lanes\n", num_lanes);
 864                 ret = -ENODEV;
 865                 goto err_addr_to_resource;
 866         }
 867
 868         wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
 869                                                       GPIOD_IN);
 870         if (IS_ERR(wiz->gpio_typec_dir)) {
 871                 ret = PTR_ERR(wiz->gpio_typec_dir);
 872                 if (ret != -EPROBE_DEFER)
 873                         dev_err(dev, "Failed to request typec-dir gpio: %d\n",
 874                                 ret);
 875                 goto err_addr_to_resource;
 876         }
 877
 878         if (wiz->gpio_typec_dir) {
 879                 ret = of_property_read_u32(node, "typec-dir-debounce-ms",
 880                                            &wiz->typec_dir_delay);
 881                 if (ret && ret != -EINVAL) {
 882                         dev_err(dev, "Invalid typec-dir-debounce property\n");
 883                         goto err_addr_to_resource;
 884                 }
 885
 886                 /* use min. debounce from Type-C spec if not provided in DT  */
 887                 if (ret == -EINVAL)
 888                         wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
 889
 890                 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
 891                     wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
 892                         dev_err(dev, "Invalid typec-dir-debounce property\n");
 893                         goto err_addr_to_resource;
 894                 }
 895         }
 896
 897         ret = wiz_get_lane_phy_types(dev, wiz);
 898         if (ret)
 899                 return ret;
 900
 901         wiz->dev = dev;
 902         wiz->regmap = regmap;
 903         wiz->num_lanes = num_lanes;
 904         if (wiz->type == J721E_WIZ_10G)
 905                 wiz->clk_mux_sel = clk_mux_sel_10g;
 906         else
 907                 wiz->clk_mux_sel = clk_mux_sel_16g;
 908
 909         wiz->clk_div_sel = clk_div_sel;
 910
 911         if (wiz->type == J721E_WIZ_10G)
 912                 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
 913         else
 914                 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
 915
 916         platform_set_drvdata(pdev, wiz);
 917
 918         ret = wiz_regfield_init(wiz);
 919         if (ret) {
 920                 dev_err(dev, "Failed to initialize regfields\n");
 921                 goto err_addr_to_resource;
 922         }
 923
 924         phy_reset_dev = &wiz->wiz_phy_reset_dev;
 925         phy_reset_dev->dev = dev;
 926         phy_reset_dev->ops = &wiz_phy_reset_ops,
 927         phy_reset_dev->owner = THIS_MODULE,
 928         phy_reset_dev->of_node = node;
 929         /* Reset for each of the lane and one for the entire SERDES */
 930         phy_reset_dev->nr_resets = num_lanes + 1;
 931
 932         ret = devm_reset_controller_register(dev, phy_reset_dev);
 933         if (ret < 0) {
 934                 dev_warn(dev, "Failed to register reset controller\n");
 935                 goto err_addr_to_resource;
 936         }
 937
 938         pm_runtime_enable(dev);
 939         ret = pm_runtime_get_sync(dev);
 940         if (ret < 0) {
 941                 dev_err(dev, "pm_runtime_get_sync failed\n");
 942                 goto err_get_sync;
 943         }
 944
 945         ret = wiz_clock_init(wiz, node);
 946         if (ret < 0) {
 947                 dev_warn(dev, "Failed to initialize clocks\n");
 948                 goto err_get_sync;
 949         }
 950
 951         serdes_pdev = of_platform_device_create(child_node, NULL, dev);
 952         if (!serdes_pdev) {
 953                 dev_WARN(dev, "Unable to create SERDES platform device\n");
 954                 ret = -ENOMEM;
 955                 goto err_pdev_create;
 956         }
 957         wiz->serdes_pdev = serdes_pdev;
 958
 959         ret = wiz_init(wiz);
 960         if (ret) {
 961                 dev_err(dev, "WIZ initialization failed\n");
 962                 goto err_wiz_init;
 963         }
 964
 965         of_node_put(child_node);
 966         return 0;
 967
 968 err_wiz_init:
 969         of_platform_device_destroy(&serdes_pdev->dev, NULL);
 970
 971 err_pdev_create:
 972         wiz_clock_cleanup(wiz, node);
 973
 974 err_get_sync:
 975         pm_runtime_put(dev);
 976         pm_runtime_disable(dev);
 977
 978 err_addr_to_resource:
 979         of_node_put(child_node);
 980
 981         return ret;
 982 }
 983
 984 static int wiz_remove(struct platform_device *pdev)
 985 {
 986         struct device *dev = &pdev->dev;
 987         struct device_node *node = dev->of_node;
 988         struct platform_device *serdes_pdev;
 989         struct wiz *wiz;
 990
 991         wiz = dev_get_drvdata(dev);
 992         serdes_pdev = wiz->serdes_pdev;
 993
 994         of_platform_device_destroy(&serdes_pdev->dev, NULL);
 995         wiz_clock_cleanup(wiz, node);
 996         pm_runtime_put(dev);
 997         pm_runtime_disable(dev);
 998
 999         return 0;
1000 }
1001
1002 static struct platform_driver wiz_driver = {
1003         .probe          = wiz_probe,
1004         .remove         = wiz_remove,
1005         .driver         = {
1006                 .name   = "wiz",
1007                 .of_match_table = wiz_id_table,
1008         },
1009 };
1010 module_platform_driver(wiz_driver);
1011
1012 MODULE_AUTHOR("Texas Instruments Inc.");
1013 MODULE_DESCRIPTION("TI J721E WIZ driver");
1014 MODULE_LICENSE("GPL v2");