drivers/phy/st/phy-stm32-usbphyc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * STMicroelectronics STM32 USB PHY Controller driver
   4  *
   5  * Copyright (C) 2018 STMicroelectronics
   6  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
   7  */
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/delay.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/reset.h>
  18 #include <linux/units.h>
  19
  20 #define STM32_USBPHYC_PLL       0x0
  21 #define STM32_USBPHYC_MISC      0x8
  22 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
  23 #define STM32_USBPHYC_TUNE(X)   (0x10C + ((X) * 0x100))
  24 #define STM32_USBPHYC_VERSION   0x3F4
  25
  26 /* STM32_USBPHYC_PLL bit fields */
  27 #define PLLNDIV                 GENMASK(6, 0)
  28 #define PLLFRACIN               GENMASK(25, 10)
  29 #define PLLEN                   BIT(26)
  30 #define PLLSTRB                 BIT(27)
  31 #define PLLSTRBYP               BIT(28)
  32 #define PLLFRACCTL              BIT(29)
  33 #define PLLDITHEN0              BIT(30)
  34 #define PLLDITHEN1              BIT(31)
  35
  36 /* STM32_USBPHYC_MISC bit fields */
  37 #define SWITHOST                BIT(0)
  38
  39 /* STM32_USBPHYC_MONITOR bit fields */
  40 #define STM32_USBPHYC_MON_OUT   GENMASK(3, 0)
  41 #define STM32_USBPHYC_MON_SEL   GENMASK(8, 4)
  42 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
  43 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
  44
  45 /* STM32_USBPHYC_TUNE bit fields */
  46 #define INCURREN                BIT(0)
  47 #define INCURRINT               BIT(1)
  48 #define LFSCAPEN                BIT(2)
  49 #define HSDRVSLEW               BIT(3)
  50 #define HSDRVDCCUR              BIT(4)
  51 #define HSDRVDCLEV              BIT(5)
  52 #define HSDRVCURINCR            BIT(6)
  53 #define FSDRVRFADJ              BIT(7)
  54 #define HSDRVRFRED              BIT(8)
  55 #define HSDRVCHKITRM            GENMASK(12, 9)
  56 #define HSDRVCHKZTRM            GENMASK(14, 13)
  57 #define OTPCOMP                 GENMASK(19, 15)
  58 #define SQLCHCTL                GENMASK(21, 20)
  59 #define HDRXGNEQEN              BIT(22)
  60 #define HSRXOFF                 GENMASK(24, 23)
  61 #define HSFALLPREEM             BIT(25)
  62 #define SHTCCTCTLPROT           BIT(26)
  63 #define STAGSEL                 BIT(27)
  64
  65 enum boosting_vals {
  66         BOOST_1000_UA = 1000,
  67         BOOST_2000_UA = 2000,
  68 };
  69
  70 enum dc_level_vals {
  71         DC_NOMINAL,
  72         DC_PLUS_5_TO_7_MV,
  73         DC_PLUS_10_TO_14_MV,
  74         DC_MINUS_5_TO_7_MV,
  75         DC_MAX,
  76 };
  77
  78 enum current_trim {
  79         CUR_NOMINAL,
  80         CUR_PLUS_1_56_PCT,
  81         CUR_PLUS_3_12_PCT,
  82         CUR_PLUS_4_68_PCT,
  83         CUR_PLUS_6_24_PCT,
  84         CUR_PLUS_7_8_PCT,
  85         CUR_PLUS_9_36_PCT,
  86         CUR_PLUS_10_92_PCT,
  87         CUR_PLUS_12_48_PCT,
  88         CUR_PLUS_14_04_PCT,
  89         CUR_PLUS_15_6_PCT,
  90         CUR_PLUS_17_16_PCT,
  91         CUR_PLUS_19_01_PCT,
  92         CUR_PLUS_20_58_PCT,
  93         CUR_PLUS_22_16_PCT,
  94         CUR_PLUS_23_73_PCT,
  95         CUR_MAX,
  96 };
  97
  98 enum impedance_trim {
  99         IMP_NOMINAL,
 100         IMP_MINUS_2_OHMS,
 101         IMP_MINUS_4_OMHS,
 102         IMP_MINUS_6_OHMS,
 103         IMP_MAX,
 104 };
 105
 106 enum squelch_level {
 107         SQLCH_NOMINAL,
 108         SQLCH_PLUS_7_MV,
 109         SQLCH_MINUS_5_MV,
 110         SQLCH_PLUS_14_MV,
 111         SQLCH_MAX,
 112 };
 113
 114 enum rx_offset {
 115         NO_RX_OFFSET,
 116         RX_OFFSET_PLUS_5_MV,
 117         RX_OFFSET_PLUS_10_MV,
 118         RX_OFFSET_MINUS_5_MV,
 119         RX_OFFSET_MAX,
 120 };
 121
 122 /* STM32_USBPHYC_VERSION bit fields */
 123 #define MINREV                  GENMASK(3, 0)
 124 #define MAJREV                  GENMASK(7, 4)
 125
 126 #define PLL_FVCO_MHZ            2880
 127 #define PLL_INFF_MIN_RATE_HZ    19200000
 128 #define PLL_INFF_MAX_RATE_HZ    38400000
 129
 130 struct pll_params {
 131         u8 ndiv;
 132         u16 frac;
 133 };
 134
 135 struct stm32_usbphyc_phy {
 136         struct phy *phy;
 137         struct stm32_usbphyc *usbphyc;
 138         struct regulator *vbus;
 139         u32 index;
 140         bool active;
 141         u32 tune;
 142 };
 143
 144 struct stm32_usbphyc {
 145         struct device *dev;
 146         void __iomem *base;
 147         struct clk *clk;
 148         struct reset_control *rst;
 149         struct stm32_usbphyc_phy **phys;
 150         int nphys;
 151         struct regulator *vdda1v1;
 152         struct regulator *vdda1v8;
 153         atomic_t n_pll_cons;
 154         struct clk_hw clk48_hw;
 155         int switch_setup;
 156 };
 157
 158 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
 159 {
 160         writel_relaxed(readl_relaxed(reg) | bits, reg);
 161 }
 162
 163 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
 164 {
 165         writel_relaxed(readl_relaxed(reg) & ~bits, reg);
 166 }
 167
 168 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
 169 {
 170         int ret;
 171
 172         ret = regulator_enable(usbphyc->vdda1v1);
 173         if (ret)
 174                 return ret;
 175
 176         ret = regulator_enable(usbphyc->vdda1v8);
 177         if (ret)
 178                 goto vdda1v1_disable;
 179
 180         return 0;
 181
 182 vdda1v1_disable:
 183         regulator_disable(usbphyc->vdda1v1);
 184
 185         return ret;
 186 }
 187
 188 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
 189 {
 190         int ret;
 191
 192         ret = regulator_disable(usbphyc->vdda1v8);
 193         if (ret)
 194                 return ret;
 195
 196         ret = regulator_disable(usbphyc->vdda1v1);
 197         if (ret)
 198                 return ret;
 199
 200         return 0;
 201 }
 202
 203 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
 204                                          struct pll_params *pll_params)
 205 {
 206         unsigned long long fvco, ndiv, frac;
 207
 208         /*    _
 209          *   | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
 210          *   | FVCO = 2880MHz
 211          *  <
 212          *   | NDIV = integer part of input bits to set the LDF
 213          *   |_FRACT = fractional part of input bits to set the LDF
 214          *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
 215          *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
 216          * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
 217          */
 218         fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
 219
 220         ndiv = fvco;
 221         do_div(ndiv, (clk_rate * 2));
 222         pll_params->ndiv = (u8)ndiv;
 223
 224         frac = fvco * (1 << 16);
 225         do_div(frac, (clk_rate * 2));
 226         frac = frac - (ndiv * (1 << 16));
 227         pll_params->frac = (u16)frac;
 228 }
 229
 230 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
 231 {
 232         struct pll_params pll_params;
 233         u32 clk_rate = clk_get_rate(usbphyc->clk);
 234         u32 ndiv, frac;
 235         u32 usbphyc_pll;
 236
 237         if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
 238             (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
 239                 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
 240                         clk_rate);
 241                 return -EINVAL;
 242         }
 243
 244         stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
 245         ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
 246         frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
 247
 248         usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
 249
 250         if (pll_params.frac)
 251                 usbphyc_pll |= PLLFRACCTL | frac;
 252
 253         writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
 254
 255         dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
 256                 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
 257                 FIELD_GET(PLLFRACIN, usbphyc_pll));
 258
 259         return 0;
 260 }
 261
 262 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 263 {
 264         void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
 265         u32 pllen;
 266
 267         stm32_usbphyc_clr_bits(pll_reg, PLLEN);
 268
 269         /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
 270         if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
 271                 dev_err(usbphyc->dev, "PLL not reset\n");
 272
 273         return stm32_usbphyc_regulators_disable(usbphyc);
 274 }
 275
 276 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 277 {
 278         /* Check if a phy port is still active or clk48 in use */
 279         if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
 280                 return 0;
 281
 282         return __stm32_usbphyc_pll_disable(usbphyc);
 283 }
 284
 285 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
 286 {
 287         void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
 288         bool pllen = readl_relaxed(pll_reg) & PLLEN;
 289         int ret;
 290
 291         /*
 292          * Check if a phy port or clk48 prepare has configured the pll
 293          * and ensure the PLL is enabled
 294          */
 295         if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
 296                 return 0;
 297
 298         if (pllen) {
 299                 /*
 300                  * PLL shouldn't be enabled without known consumer,
 301                  * disable it and reinit n_pll_cons
 302                  */
 303                 dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
 304
 305                 ret = __stm32_usbphyc_pll_disable(usbphyc);
 306                 if (ret)
 307                         goto dec_n_pll_cons;
 308         }
 309
 310         ret = stm32_usbphyc_regulators_enable(usbphyc);
 311         if (ret)
 312                 goto dec_n_pll_cons;
 313
 314         ret = stm32_usbphyc_pll_init(usbphyc);
 315         if (ret)
 316                 goto reg_disable;
 317
 318         stm32_usbphyc_set_bits(pll_reg, PLLEN);
 319
 320         return 0;
 321
 322 reg_disable:
 323         stm32_usbphyc_regulators_disable(usbphyc);
 324
 325 dec_n_pll_cons:
 326         atomic_dec(&usbphyc->n_pll_cons);
 327
 328         return ret;
 329 }
 330
 331 static int stm32_usbphyc_phy_init(struct phy *phy)
 332 {
 333         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 334         struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
 335         u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
 336         u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
 337                                 STM32_USBPHYC_MON_SEL_LOCKP);
 338         u32 monout;
 339         int ret;
 340
 341         ret = stm32_usbphyc_pll_enable(usbphyc);
 342         if (ret)
 343                 return ret;
 344
 345         /* Check that PLL Lock input to PHY is High */
 346         writel_relaxed(monsel, usbphyc->base + reg_mon);
 347         ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
 348                                          (monout & STM32_USBPHYC_MON_OUT_LOCKP),
 349                                          100, 1000);
 350         if (ret) {
 351                 dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
 352                         (u32)(monout & STM32_USBPHYC_MON_OUT));
 353                 goto pll_disable;
 354         }
 355
 356         usbphyc_phy->active = true;
 357
 358         return 0;
 359
 360 pll_disable:
 361         return stm32_usbphyc_pll_disable(usbphyc);
 362 }
 363
 364 static int stm32_usbphyc_phy_exit(struct phy *phy)
 365 {
 366         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 367         struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
 368
 369         usbphyc_phy->active = false;
 370
 371         return stm32_usbphyc_pll_disable(usbphyc);
 372 }
 373
 374 static int stm32_usbphyc_phy_power_on(struct phy *phy)
 375 {
 376         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 377
 378         if (usbphyc_phy->vbus)
 379                 return regulator_enable(usbphyc_phy->vbus);
 380
 381         return 0;
 382 }
 383
 384 static int stm32_usbphyc_phy_power_off(struct phy *phy)
 385 {
 386         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 387
 388         if (usbphyc_phy->vbus)
 389                 return regulator_disable(usbphyc_phy->vbus);
 390
 391         return 0;
 392 }
 393
 394 static const struct phy_ops stm32_usbphyc_phy_ops = {
 395         .init = stm32_usbphyc_phy_init,
 396         .exit = stm32_usbphyc_phy_exit,
 397         .power_on = stm32_usbphyc_phy_power_on,
 398         .power_off = stm32_usbphyc_phy_power_off,
 399         .owner = THIS_MODULE,
 400 };
 401
 402 static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
 403 {
 404         struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
 405
 406         return stm32_usbphyc_pll_enable(usbphyc);
 407 }
 408
 409 static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
 410 {
 411         struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
 412
 413         stm32_usbphyc_pll_disable(usbphyc);
 414 }
 415
 416 static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 417 {
 418         return 48000000;
 419 }
 420
 421 static const struct clk_ops usbphyc_clk48_ops = {
 422         .prepare = stm32_usbphyc_clk48_prepare,
 423         .unprepare = stm32_usbphyc_clk48_unprepare,
 424         .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
 425 };
 426
 427 static void stm32_usbphyc_clk48_unregister(void *data)
 428 {
 429         struct stm32_usbphyc *usbphyc = data;
 430
 431         of_clk_del_provider(usbphyc->dev->of_node);
 432         clk_hw_unregister(&usbphyc->clk48_hw);
 433 }
 434
 435 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
 436 {
 437         struct device_node *node = usbphyc->dev->of_node;
 438         struct clk_init_data init = { };
 439         int ret = 0;
 440
 441         init.name = "ck_usbo_48m";
 442         init.ops = &usbphyc_clk48_ops;
 443
 444         usbphyc->clk48_hw.init = &init;
 445
 446         ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
 447         if (ret)
 448                 return ret;
 449
 450         ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
 451         if (ret)
 452                 clk_hw_unregister(&usbphyc->clk48_hw);
 453
 454         return ret;
 455 }
 456
 457 static void stm32_usbphyc_phy_tuning(struct stm32_usbphyc *usbphyc,
 458                                      struct device_node *np, u32 index)
 459 {
 460         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys[index];
 461         u32 reg = STM32_USBPHYC_TUNE(index);
 462         u32 otpcomp, val;
 463         int ret;
 464
 465         /* Backup OTP compensation code */
 466         otpcomp = FIELD_GET(OTPCOMP, readl_relaxed(usbphyc->base + reg));
 467
 468         ret = of_property_read_u32(np, "st,current-boost-microamp", &val);
 469         if (ret != -EINVAL) {
 470                 if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
 471                         val = (val == BOOST_2000_UA) ? 1 : 0;
 472                         usbphyc_phy->tune |= INCURREN | FIELD_PREP(INCURRINT, val);
 473                 } else {
 474                         dev_warn(usbphyc->dev, "phy%d: invalid st,current-boost-microamp\n", index);
 475                 }
 476         }
 477
 478         if (!of_property_read_bool(np, "st,no-lsfs-fb-cap"))
 479                 usbphyc_phy->tune |= LFSCAPEN;
 480
 481         if (of_property_read_bool(np, "st,decrease-hs-slew-rate"))
 482                 usbphyc_phy->tune |= HSDRVSLEW;
 483
 484         ret = of_property_read_u32(np, "st,tune-hs-dc-level", &val);
 485         if (ret != -EINVAL) {
 486                 if (!ret && val < DC_MAX) {
 487                         if (val == DC_MINUS_5_TO_7_MV) {/* Decreases HS driver DC level */
 488                                 usbphyc_phy->tune |= HSDRVDCCUR;
 489                         } else if (val > 0) {           /* Increases HS driver DC level */
 490                                 val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
 491                                 usbphyc_phy->tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
 492                         }
 493                 } else {
 494                         dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-dc-level\n", index);
 495                 }
 496         }
 497
 498         if (of_property_read_bool(np, "st,enable-fs-rftime-tuning"))
 499                 usbphyc_phy->tune |= FSDRVRFADJ;
 500
 501         if (of_property_read_bool(np, "st,enable-hs-rftime-reduction"))
 502                 usbphyc_phy->tune |= HSDRVRFRED;
 503
 504         ret = of_property_read_u32(np, "st,trim-hs-current", &val);
 505         if (ret != -EINVAL) {
 506                 if (!ret && val < CUR_MAX)
 507                         usbphyc_phy->tune |= FIELD_PREP(HSDRVCHKITRM, val);
 508                 else
 509                         dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-current\n", index);
 510         }
 511
 512         ret = of_property_read_u32(np, "st,trim-hs-impedance", &val);
 513         if (ret != -EINVAL) {
 514                 if (!ret && val < IMP_MAX)
 515                         usbphyc_phy->tune |= FIELD_PREP(HSDRVCHKZTRM, val);
 516                 else
 517                         dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-impedance\n", index);
 518         }
 519
 520         ret = of_property_read_u32(np, "st,tune-squelch-level", &val);
 521         if (ret != -EINVAL) {
 522                 if (!ret && val < SQLCH_MAX)
 523                         usbphyc_phy->tune |= FIELD_PREP(SQLCHCTL, val);
 524                 else
 525                         dev_warn(usbphyc->dev, "phy%d: invalid st,tune-squelch\n", index);
 526         }
 527
 528         if (of_property_read_bool(np, "st,enable-hs-rx-gain-eq"))
 529                 usbphyc_phy->tune |= HDRXGNEQEN;
 530
 531         ret = of_property_read_u32(np, "st,tune-hs-rx-offset", &val);
 532         if (ret != -EINVAL) {
 533                 if (!ret && val < RX_OFFSET_MAX)
 534                         usbphyc_phy->tune |= FIELD_PREP(HSRXOFF, val);
 535                 else
 536                         dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-rx-offset\n", index);
 537         }
 538
 539         if (of_property_read_bool(np, "st,no-hs-ftime-ctrl"))
 540                 usbphyc_phy->tune |= HSFALLPREEM;
 541
 542         if (!of_property_read_bool(np, "st,no-lsfs-sc"))
 543                 usbphyc_phy->tune |= SHTCCTCTLPROT;
 544
 545         if (of_property_read_bool(np, "st,enable-hs-tx-staggering"))
 546                 usbphyc_phy->tune |= STAGSEL;
 547
 548         /* Restore OTP compensation code */
 549         usbphyc_phy->tune |= FIELD_PREP(OTPCOMP, otpcomp);
 550
 551         /*
 552          * By default, if no st,xxx tuning property is used, usbphyc_phy->tune is equal to
 553          * STM32_USBPHYC_TUNE reset value (LFSCAPEN | SHTCCTCTLPROT | OTPCOMP).
 554          */
 555         writel_relaxed(usbphyc_phy->tune, usbphyc->base + reg);
 556 }
 557
 558 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
 559                                        u32 utmi_switch)
 560 {
 561         if (!utmi_switch)
 562                 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
 563                                        SWITHOST);
 564         else
 565                 stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
 566                                        SWITHOST);
 567         usbphyc->switch_setup = utmi_switch;
 568 }
 569
 570 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
 571                                           struct of_phandle_args *args)
 572 {
 573         struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
 574         struct stm32_usbphyc_phy *usbphyc_phy = NULL;
 575         struct device_node *phynode = args->np;
 576         int port = 0;
 577
 578         for (port = 0; port < usbphyc->nphys; port++) {
 579                 if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
 580                         usbphyc_phy = usbphyc->phys[port];
 581                         break;
 582                 }
 583         }
 584         if (!usbphyc_phy) {
 585                 dev_err(dev, "failed to find phy\n");
 586                 return ERR_PTR(-EINVAL);
 587         }
 588
 589         if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
 590             ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
 591                 dev_err(dev, "invalid number of cells for phy port%d\n",
 592                         usbphyc_phy->index);
 593                 return ERR_PTR(-EINVAL);
 594         }
 595
 596         /* Configure the UTMI switch for PHY port#2 */
 597         if (usbphyc_phy->index == 1) {
 598                 if (usbphyc->switch_setup < 0) {
 599                         stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
 600                 } else {
 601                         if (args->args[0] != usbphyc->switch_setup) {
 602                                 dev_err(dev, "phy port1 already used\n");
 603                                 return ERR_PTR(-EBUSY);
 604                         }
 605                 }
 606         }
 607
 608         return usbphyc_phy->phy;
 609 }
 610
 611 static int stm32_usbphyc_probe(struct platform_device *pdev)
 612 {
 613         struct stm32_usbphyc *usbphyc;
 614         struct device *dev = &pdev->dev;
 615         struct device_node *child, *np = dev->of_node;
 616         struct phy_provider *phy_provider;
 617         u32 pllen, version;
 618         int ret, port = 0;
 619
 620         usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
 621         if (!usbphyc)
 622                 return -ENOMEM;
 623         usbphyc->dev = dev;
 624         dev_set_drvdata(dev, usbphyc);
 625
 626         usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
 627         if (IS_ERR(usbphyc->base))
 628                 return PTR_ERR(usbphyc->base);
 629
 630         usbphyc->clk = devm_clk_get(dev, NULL);
 631         if (IS_ERR(usbphyc->clk))
 632                 return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
 633
 634         ret = clk_prepare_enable(usbphyc->clk);
 635         if (ret) {
 636                 dev_err(dev, "clk enable failed: %d\n", ret);
 637                 return ret;
 638         }
 639
 640         usbphyc->rst = devm_reset_control_get(dev, NULL);
 641         if (!IS_ERR(usbphyc->rst)) {
 642                 reset_control_assert(usbphyc->rst);
 643                 udelay(2);
 644                 reset_control_deassert(usbphyc->rst);
 645         } else {
 646                 ret = PTR_ERR(usbphyc->rst);
 647                 if (ret == -EPROBE_DEFER)
 648                         goto clk_disable;
 649
 650                 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 651         }
 652
 653         /*
 654          * Wait for minimum width of powerdown pulse (ENABLE = Low):
 655          * we have to ensure the PLL is disabled before phys initialization.
 656          */
 657         if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
 658                                        pllen, !(pllen & PLLEN), 5, 50)) {
 659                 dev_warn(usbphyc->dev, "PLL not reset\n");
 660                 ret = -EPROBE_DEFER;
 661                 goto clk_disable;
 662         }
 663
 664         usbphyc->switch_setup = -EINVAL;
 665         usbphyc->nphys = of_get_child_count(np);
 666         usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
 667                                      sizeof(*usbphyc->phys), GFP_KERNEL);
 668         if (!usbphyc->phys) {
 669                 ret = -ENOMEM;
 670                 goto clk_disable;
 671         }
 672
 673         usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
 674         if (IS_ERR(usbphyc->vdda1v1)) {
 675                 ret = dev_err_probe(dev, PTR_ERR(usbphyc->vdda1v1),
 676                                     "failed to get vdda1v1 supply\n");
 677                 goto clk_disable;
 678         }
 679
 680         usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
 681         if (IS_ERR(usbphyc->vdda1v8)) {
 682                 ret = dev_err_probe(dev, PTR_ERR(usbphyc->vdda1v8),
 683                                     "failed to get vdda1v8 supply\n");
 684                 goto clk_disable;
 685         }
 686
 687         for_each_child_of_node(np, child) {
 688                 struct stm32_usbphyc_phy *usbphyc_phy;
 689                 struct phy *phy;
 690                 u32 index;
 691
 692                 phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
 693                 if (IS_ERR(phy)) {
 694                         ret = PTR_ERR(phy);
 695                         if (ret != -EPROBE_DEFER)
 696                                 dev_err(dev, "failed to create phy%d: %d\n",
 697                                         port, ret);
 698                         goto put_child;
 699                 }
 700
 701                 usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
 702                                            GFP_KERNEL);
 703                 if (!usbphyc_phy) {
 704                         ret = -ENOMEM;
 705                         goto put_child;
 706                 }
 707
 708                 ret = of_property_read_u32(child, "reg", &index);
 709                 if (ret || index > usbphyc->nphys) {
 710                         dev_err(&phy->dev, "invalid reg property: %d\n", ret);
 711                         goto put_child;
 712                 }
 713
 714                 usbphyc->phys[port] = usbphyc_phy;
 715                 phy_set_bus_width(phy, 8);
 716                 phy_set_drvdata(phy, usbphyc_phy);
 717
 718                 usbphyc->phys[port]->phy = phy;
 719                 usbphyc->phys[port]->usbphyc = usbphyc;
 720                 usbphyc->phys[port]->index = index;
 721                 usbphyc->phys[port]->active = false;
 722
 723                 usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
 724                 if (IS_ERR(usbphyc->phys[port]->vbus)) {
 725                         ret = PTR_ERR(usbphyc->phys[port]->vbus);
 726                         if (ret == -EPROBE_DEFER)
 727                                 goto put_child;
 728                         usbphyc->phys[port]->vbus = NULL;
 729                 }
 730
 731                 /* Configure phy tuning */
 732                 stm32_usbphyc_phy_tuning(usbphyc, child, index);
 733
 734                 port++;
 735         }
 736
 737         phy_provider = devm_of_phy_provider_register(dev,
 738                                                      stm32_usbphyc_of_xlate);
 739         if (IS_ERR(phy_provider)) {
 740                 ret = PTR_ERR(phy_provider);
 741                 dev_err(dev, "failed to register phy provider: %d\n", ret);
 742                 goto clk_disable;
 743         }
 744
 745         ret = stm32_usbphyc_clk48_register(usbphyc);
 746         if (ret) {
 747                 dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
 748                 goto clk_disable;
 749         }
 750
 751         version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
 752         dev_info(dev, "registered rev:%lu.%lu\n",
 753                  FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
 754
 755         return 0;
 756
 757 put_child:
 758         of_node_put(child);
 759 clk_disable:
 760         clk_disable_unprepare(usbphyc->clk);
 761
 762         return ret;
 763 }
 764
 765 static int stm32_usbphyc_remove(struct platform_device *pdev)
 766 {
 767         struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
 768         int port;
 769
 770         /* Ensure PHYs are not active, to allow PLL disabling */
 771         for (port = 0; port < usbphyc->nphys; port++)
 772                 if (usbphyc->phys[port]->active)
 773                         stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
 774
 775         stm32_usbphyc_clk48_unregister(usbphyc);
 776
 777         clk_disable_unprepare(usbphyc->clk);
 778
 779         return 0;
 780 }
 781
 782 static int __maybe_unused stm32_usbphyc_resume(struct device *dev)
 783 {
 784         struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
 785         struct stm32_usbphyc_phy *usbphyc_phy;
 786         int port;
 787
 788         if (usbphyc->switch_setup >= 0)
 789                 stm32_usbphyc_switch_setup(usbphyc, usbphyc->switch_setup);
 790
 791         for (port = 0; port < usbphyc->nphys; port++) {
 792                 usbphyc_phy = usbphyc->phys[port];
 793                 writel_relaxed(usbphyc_phy->tune, usbphyc->base + STM32_USBPHYC_TUNE(port));
 794         }
 795
 796         return 0;
 797 }
 798
 799 static SIMPLE_DEV_PM_OPS(stm32_usbphyc_pm_ops, NULL, stm32_usbphyc_resume);
 800
 801 static const struct of_device_id stm32_usbphyc_of_match[] = {
 802         { .compatible = "st,stm32mp1-usbphyc", },
 803         { },
 804 };
 805 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
 806
 807 static struct platform_driver stm32_usbphyc_driver = {
 808         .probe = stm32_usbphyc_probe,
 809         .remove = stm32_usbphyc_remove,
 810         .driver = {
 811                 .of_match_table = stm32_usbphyc_of_match,
 812                 .name = "stm32-usbphyc",
 813                 .pm = &stm32_usbphyc_pm_ops,
 814         }
 815 };
 816 module_platform_driver(stm32_usbphyc_driver);
 817
 818 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
 819 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
 820 MODULE_LICENSE("GPL v2");