drivers/phy/rockchip/phy-rockchip-inno-usb2.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   4  *
   5  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/delay.h>
  11 #include <linux/extcon-provider.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/power_supply.h>
  26 #include <linux/regmap.h>
  27 #include <linux/mfd/syscon.h>
  28 #include <linux/usb/of.h>
  29 #include <linux/usb/otg.h>
  30
  31 #define BIT_WRITEABLE_SHIFT     16
  32 #define SCHEDULE_DELAY          (60 * HZ)
  33 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  34
  35 enum rockchip_usb2phy_port_id {
  36         USB2PHY_PORT_OTG,
  37         USB2PHY_PORT_HOST,
  38         USB2PHY_NUM_PORTS,
  39 };
  40
  41 enum rockchip_usb2phy_host_state {
  42         PHY_STATE_HS_ONLINE     = 0,
  43         PHY_STATE_DISCONNECT    = 1,
  44         PHY_STATE_CONNECT       = 2,
  45         PHY_STATE_FS_LS_ONLINE  = 4,
  46 };
  47
  48 /**
  49  * enum usb_chg_state - Different states involved in USB charger detection.
  50  * @USB_CHG_STATE_UNDEFINED:    USB charger is not connected or detection
  51  *                              process is not yet started.
  52  * @USB_CHG_STATE_WAIT_FOR_DCD: Waiting for Data pins contact.
  53  * @USB_CHG_STATE_DCD_DONE:     Data pin contact is detected.
  54  * @USB_CHG_STATE_PRIMARY_DONE: Primary detection is completed (Detects
  55  *                              between SDP and DCP/CDP).
  56  * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects
  57  *                                between DCP and CDP).
  58  * @USB_CHG_STATE_DETECTED:     USB charger type is determined.
  59  */
  60 enum usb_chg_state {
  61         USB_CHG_STATE_UNDEFINED = 0,
  62         USB_CHG_STATE_WAIT_FOR_DCD,
  63         USB_CHG_STATE_DCD_DONE,
  64         USB_CHG_STATE_PRIMARY_DONE,
  65         USB_CHG_STATE_SECONDARY_DONE,
  66         USB_CHG_STATE_DETECTED,
  67 };
  68
  69 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  70         EXTCON_USB,
  71         EXTCON_USB_HOST,
  72         EXTCON_CHG_USB_SDP,
  73         EXTCON_CHG_USB_CDP,
  74         EXTCON_CHG_USB_DCP,
  75         EXTCON_CHG_USB_SLOW,
  76         EXTCON_NONE,
  77 };
  78
  79 struct usb2phy_reg {
  80         unsigned int    offset;
  81         unsigned int    bitend;
  82         unsigned int    bitstart;
  83         unsigned int    disable;
  84         unsigned int    enable;
  85 };
  86
  87 /**
  88  * struct rockchip_chg_det_reg - usb charger detect registers
  89  * @cp_det: charging port detected successfully.
  90  * @dcp_det: dedicated charging port detected successfully.
  91  * @dp_det: assert data pin connect successfully.
  92  * @idm_sink_en: open dm sink curren.
  93  * @idp_sink_en: open dp sink current.
  94  * @idp_src_en: open dm source current.
  95  * @rdm_pdwn_en: open dm pull down resistor.
  96  * @vdm_src_en: open dm voltage source.
  97  * @vdp_src_en: open dp voltage source.
  98  * @opmode: utmi operational mode.
  99  */
 100 struct rockchip_chg_det_reg {
 101         struct usb2phy_reg      cp_det;
 102         struct usb2phy_reg      dcp_det;
 103         struct usb2phy_reg      dp_det;
 104         struct usb2phy_reg      idm_sink_en;
 105         struct usb2phy_reg      idp_sink_en;
 106         struct usb2phy_reg      idp_src_en;
 107         struct usb2phy_reg      rdm_pdwn_en;
 108         struct usb2phy_reg      vdm_src_en;
 109         struct usb2phy_reg      vdp_src_en;
 110         struct usb2phy_reg      opmode;
 111 };
 112
 113 /**
 114  * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
 115  * @phy_sus: phy suspend register.
 116  * @bvalid_det_en: vbus valid rise detection enable register.
 117  * @bvalid_det_st: vbus valid rise detection status register.
 118  * @bvalid_det_clr: vbus valid rise detection clear register.
 119  * @ls_det_en: linestate detection enable register.
 120  * @ls_det_st: linestate detection state register.
 121  * @ls_det_clr: linestate detection clear register.
 122  * @utmi_avalid: utmi vbus avalid status register.
 123  * @utmi_bvalid: utmi vbus bvalid status register.
 124  * @utmi_ls: utmi linestate state register.
 125  * @utmi_hstdet: utmi host disconnect register.
 126  */
 127 struct rockchip_usb2phy_port_cfg {
 128         struct usb2phy_reg      phy_sus;
 129         struct usb2phy_reg      bvalid_det_en;
 130         struct usb2phy_reg      bvalid_det_st;
 131         struct usb2phy_reg      bvalid_det_clr;
 132         struct usb2phy_reg      ls_det_en;
 133         struct usb2phy_reg      ls_det_st;
 134         struct usb2phy_reg      ls_det_clr;
 135         struct usb2phy_reg      utmi_avalid;
 136         struct usb2phy_reg      utmi_bvalid;
 137         struct usb2phy_reg      utmi_ls;
 138         struct usb2phy_reg      utmi_hstdet;
 139 };
 140
 141 /**
 142  * struct rockchip_usb2phy_cfg - usb-phy configuration.
 143  * @reg: the address offset of grf for usb-phy config.
 144  * @num_ports: specify how many ports that the phy has.
 145  * @clkout_ctl: keep on/turn off output clk of phy.
 146  * @port_cfgs: usb-phy port configurations.
 147  * @chg_det: charger detection registers.
 148  */
 149 struct rockchip_usb2phy_cfg {
 150         unsigned int    reg;
 151         unsigned int    num_ports;
 152         struct usb2phy_reg      clkout_ctl;
 153         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 154         const struct rockchip_chg_det_reg       chg_det;
 155 };
 156
 157 /**
 158  * struct rockchip_usb2phy_port - usb-phy port data.
 159  * @phy: generic phy.
 160  * @port_id: flag for otg port or host port.
 161  * @suspended: phy suspended flag.
 162  * @vbus_attached: otg device vbus status.
 163  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 164  * @ls_irq: IRQ number assigned for linestate detection.
 165  * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
 166  *               irqs to one irq in otg-port.
 167  * @mutex: for register updating in sm_work.
 168  * @chg_work: charge detect work.
 169  * @otg_sm_work: OTG state machine work.
 170  * @sm_work: HOST state machine work.
 171  * @port_cfg: port register configuration, assigned by driver data.
 172  * @event_nb: hold event notification callback.
 173  * @state: define OTG enumeration states before device reset.
 174  * @mode: the dr_mode of the controller.
 175  */
 176 struct rockchip_usb2phy_port {
 177         struct phy      *phy;
 178         unsigned int    port_id;
 179         bool            suspended;
 180         bool            vbus_attached;
 181         int             bvalid_irq;
 182         int             ls_irq;
 183         int             otg_mux_irq;
 184         struct mutex    mutex;
 185         struct          delayed_work chg_work;
 186         struct          delayed_work otg_sm_work;
 187         struct          delayed_work sm_work;
 188         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 189         struct notifier_block   event_nb;
 190         enum usb_otg_state      state;
 191         enum usb_dr_mode        mode;
 192 };
 193
 194 /**
 195  * struct rockchip_usb2phy - usb2.0 phy driver data.
 196  * @dev: pointer to device.
 197  * @grf: General Register Files regmap.
 198  * @usbgrf: USB General Register Files regmap.
 199  * @clk: clock struct of phy input clk.
 200  * @clk480m: clock struct of phy output clk.
 201  * @clk480m_hw: clock struct of phy output clk management.
 202  * @chg_state: states involved in USB charger detection.
 203  * @chg_type: USB charger types.
 204  * @dcd_retries: The retry count used to track Data contact
 205  *               detection process.
 206  * @edev: extcon device for notification registration
 207  * @irq: muxed interrupt for single irq configuration
 208  * @phy_cfg: phy register configuration, assigned by driver data.
 209  * @ports: phy port instance.
 210  */
 211 struct rockchip_usb2phy {
 212         struct device   *dev;
 213         struct regmap   *grf;
 214         struct regmap   *usbgrf;
 215         struct clk      *clk;
 216         struct clk      *clk480m;
 217         struct clk_hw   clk480m_hw;
 218         enum usb_chg_state      chg_state;
 219         enum power_supply_type  chg_type;
 220         u8                      dcd_retries;
 221         struct extcon_dev       *edev;
 222         int                     irq;
 223         const struct rockchip_usb2phy_cfg       *phy_cfg;
 224         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 225 };
 226
 227 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
 228 {
 229         return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
 230 }
 231
 232 static inline int property_enable(struct regmap *base,
 233                                   const struct usb2phy_reg *reg, bool en)
 234 {
 235         unsigned int val, mask, tmp;
 236
 237         tmp = en ? reg->enable : reg->disable;
 238         mask = GENMASK(reg->bitend, reg->bitstart);
 239         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 240
 241         return regmap_write(base, reg->offset, val);
 242 }
 243
 244 static inline bool property_enabled(struct regmap *base,
 245                                     const struct usb2phy_reg *reg)
 246 {
 247         int ret;
 248         unsigned int tmp, orig;
 249         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 250
 251         ret = regmap_read(base, reg->offset, &orig);
 252         if (ret)
 253                 return false;
 254
 255         tmp = (orig & mask) >> reg->bitstart;
 256         return tmp == reg->enable;
 257 }
 258
 259 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
 260 {
 261         struct rockchip_usb2phy *rphy =
 262                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 263         struct regmap *base = get_reg_base(rphy);
 264         int ret;
 265
 266         /* turn on 480m clk output if it is off */
 267         if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
 268                 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
 269                 if (ret)
 270                         return ret;
 271
 272                 /* waiting for the clk become stable */
 273                 usleep_range(1200, 1300);
 274         }
 275
 276         return 0;
 277 }
 278
 279 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
 280 {
 281         struct rockchip_usb2phy *rphy =
 282                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 283         struct regmap *base = get_reg_base(rphy);
 284
 285         /* turn off 480m clk output */
 286         property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
 287 }
 288
 289 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
 290 {
 291         struct rockchip_usb2phy *rphy =
 292                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 293         struct regmap *base = get_reg_base(rphy);
 294
 295         return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
 296 }
 297
 298 static unsigned long
 299 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 300                                      unsigned long parent_rate)
 301 {
 302         return 480000000;
 303 }
 304
 305 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 306         .prepare = rockchip_usb2phy_clk480m_prepare,
 307         .unprepare = rockchip_usb2phy_clk480m_unprepare,
 308         .is_prepared = rockchip_usb2phy_clk480m_prepared,
 309         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 310 };
 311
 312 static void rockchip_usb2phy_clk480m_unregister(void *data)
 313 {
 314         struct rockchip_usb2phy *rphy = data;
 315
 316         of_clk_del_provider(rphy->dev->of_node);
 317         clk_unregister(rphy->clk480m);
 318 }
 319
 320 static int
 321 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 322 {
 323         struct device_node *node = rphy->dev->of_node;
 324         struct clk_init_data init;
 325         const char *clk_name;
 326         int ret = 0;
 327
 328         init.flags = 0;
 329         init.name = "clk_usbphy_480m";
 330         init.ops = &rockchip_usb2phy_clkout_ops;
 331
 332         /* optional override of the clockname */
 333         of_property_read_string(node, "clock-output-names", &init.name);
 334
 335         if (rphy->clk) {
 336                 clk_name = __clk_get_name(rphy->clk);
 337                 init.parent_names = &clk_name;
 338                 init.num_parents = 1;
 339         } else {
 340                 init.parent_names = NULL;
 341                 init.num_parents = 0;
 342         }
 343
 344         rphy->clk480m_hw.init = &init;
 345
 346         /* register the clock */
 347         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 348         if (IS_ERR(rphy->clk480m)) {
 349                 ret = PTR_ERR(rphy->clk480m);
 350                 goto err_ret;
 351         }
 352
 353         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 354         if (ret < 0)
 355                 goto err_clk_provider;
 356
 357         return devm_add_action_or_reset(rphy->dev, rockchip_usb2phy_clk480m_unregister, rphy);
 358
 359 err_clk_provider:
 360         clk_unregister(rphy->clk480m);
 361 err_ret:
 362         return ret;
 363 }
 364
 365 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 366 {
 367         int ret;
 368         struct device_node *node = rphy->dev->of_node;
 369         struct extcon_dev *edev;
 370
 371         if (of_property_read_bool(node, "extcon")) {
 372                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 373                 if (IS_ERR(edev)) {
 374                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 375                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 376                         return PTR_ERR(edev);
 377                 }
 378         } else {
 379                 /* Initialize extcon device */
 380                 edev = devm_extcon_dev_allocate(rphy->dev,
 381                                                 rockchip_usb2phy_extcon_cable);
 382
 383                 if (IS_ERR(edev))
 384                         return -ENOMEM;
 385
 386                 ret = devm_extcon_dev_register(rphy->dev, edev);
 387                 if (ret) {
 388                         dev_err(rphy->dev, "failed to register extcon device\n");
 389                         return ret;
 390                 }
 391         }
 392
 393         rphy->edev = edev;
 394
 395         return 0;
 396 }
 397
 398 static int rockchip_usb2phy_init(struct phy *phy)
 399 {
 400         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 401         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 402         int ret = 0;
 403
 404         mutex_lock(&rport->mutex);
 405
 406         if (rport->port_id == USB2PHY_PORT_OTG) {
 407                 if (rport->mode != USB_DR_MODE_HOST &&
 408                     rport->mode != USB_DR_MODE_UNKNOWN) {
 409                         /* clear bvalid status and enable bvalid detect irq */
 410                         ret = property_enable(rphy->grf,
 411                                               &rport->port_cfg->bvalid_det_clr,
 412                                               true);
 413                         if (ret)
 414                                 goto out;
 415
 416                         ret = property_enable(rphy->grf,
 417                                               &rport->port_cfg->bvalid_det_en,
 418                                               true);
 419                         if (ret)
 420                                 goto out;
 421
 422                         schedule_delayed_work(&rport->otg_sm_work,
 423                                               OTG_SCHEDULE_DELAY * 3);
 424                 } else {
 425                         /* If OTG works in host only mode, do nothing. */
 426                         dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
 427                 }
 428         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 429                 /* clear linestate and enable linestate detect irq */
 430                 ret = property_enable(rphy->grf,
 431                                       &rport->port_cfg->ls_det_clr, true);
 432                 if (ret)
 433                         goto out;
 434
 435                 ret = property_enable(rphy->grf,
 436                                       &rport->port_cfg->ls_det_en, true);
 437                 if (ret)
 438                         goto out;
 439
 440                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 441         }
 442
 443 out:
 444         mutex_unlock(&rport->mutex);
 445         return ret;
 446 }
 447
 448 static int rockchip_usb2phy_power_on(struct phy *phy)
 449 {
 450         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 451         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 452         struct regmap *base = get_reg_base(rphy);
 453         int ret;
 454
 455         dev_dbg(&rport->phy->dev, "port power on\n");
 456
 457         if (!rport->suspended)
 458                 return 0;
 459
 460         ret = clk_prepare_enable(rphy->clk480m);
 461         if (ret)
 462                 return ret;
 463
 464         ret = property_enable(base, &rport->port_cfg->phy_sus, false);
 465         if (ret)
 466                 return ret;
 467
 468         /* waiting for the utmi_clk to become stable */
 469         usleep_range(1500, 2000);
 470
 471         rport->suspended = false;
 472         return 0;
 473 }
 474
 475 static int rockchip_usb2phy_power_off(struct phy *phy)
 476 {
 477         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 478         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 479         struct regmap *base = get_reg_base(rphy);
 480         int ret;
 481
 482         dev_dbg(&rport->phy->dev, "port power off\n");
 483
 484         if (rport->suspended)
 485                 return 0;
 486
 487         ret = property_enable(base, &rport->port_cfg->phy_sus, true);
 488         if (ret)
 489                 return ret;
 490
 491         rport->suspended = true;
 492         clk_disable_unprepare(rphy->clk480m);
 493
 494         return 0;
 495 }
 496
 497 static int rockchip_usb2phy_exit(struct phy *phy)
 498 {
 499         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 500
 501         if (rport->port_id == USB2PHY_PORT_OTG &&
 502             rport->mode != USB_DR_MODE_HOST &&
 503             rport->mode != USB_DR_MODE_UNKNOWN) {
 504                 cancel_delayed_work_sync(&rport->otg_sm_work);
 505                 cancel_delayed_work_sync(&rport->chg_work);
 506         } else if (rport->port_id == USB2PHY_PORT_HOST)
 507                 cancel_delayed_work_sync(&rport->sm_work);
 508
 509         return 0;
 510 }
 511
 512 static const struct phy_ops rockchip_usb2phy_ops = {
 513         .init           = rockchip_usb2phy_init,
 514         .exit           = rockchip_usb2phy_exit,
 515         .power_on       = rockchip_usb2phy_power_on,
 516         .power_off      = rockchip_usb2phy_power_off,
 517         .owner          = THIS_MODULE,
 518 };
 519
 520 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 521 {
 522         struct rockchip_usb2phy_port *rport =
 523                 container_of(work, struct rockchip_usb2phy_port,
 524                              otg_sm_work.work);
 525         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 526         static unsigned int cable;
 527         unsigned long delay;
 528         bool vbus_attach, sch_work, notify_charger;
 529
 530         vbus_attach = property_enabled(rphy->grf,
 531                                        &rport->port_cfg->utmi_bvalid);
 532
 533         sch_work = false;
 534         notify_charger = false;
 535         delay = OTG_SCHEDULE_DELAY;
 536         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 537                 usb_otg_state_string(rport->state));
 538
 539         switch (rport->state) {
 540         case OTG_STATE_UNDEFINED:
 541                 rport->state = OTG_STATE_B_IDLE;
 542                 if (!vbus_attach)
 543                         rockchip_usb2phy_power_off(rport->phy);
 544                 fallthrough;
 545         case OTG_STATE_B_IDLE:
 546                 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) {
 547                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 548                         rport->state = OTG_STATE_A_HOST;
 549                         rockchip_usb2phy_power_on(rport->phy);
 550                         return;
 551                 } else if (vbus_attach) {
 552                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 553                         switch (rphy->chg_state) {
 554                         case USB_CHG_STATE_UNDEFINED:
 555                                 schedule_delayed_work(&rport->chg_work, 0);
 556                                 return;
 557                         case USB_CHG_STATE_DETECTED:
 558                                 switch (rphy->chg_type) {
 559                                 case POWER_SUPPLY_TYPE_USB:
 560                                         dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
 561                                         rockchip_usb2phy_power_on(rport->phy);
 562                                         rport->state = OTG_STATE_B_PERIPHERAL;
 563                                         notify_charger = true;
 564                                         sch_work = true;
 565                                         cable = EXTCON_CHG_USB_SDP;
 566                                         break;
 567                                 case POWER_SUPPLY_TYPE_USB_DCP:
 568                                         dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
 569                                         rockchip_usb2phy_power_off(rport->phy);
 570                                         notify_charger = true;
 571                                         sch_work = true;
 572                                         cable = EXTCON_CHG_USB_DCP;
 573                                         break;
 574                                 case POWER_SUPPLY_TYPE_USB_CDP:
 575                                         dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
 576                                         rockchip_usb2phy_power_on(rport->phy);
 577                                         rport->state = OTG_STATE_B_PERIPHERAL;
 578                                         notify_charger = true;
 579                                         sch_work = true;
 580                                         cable = EXTCON_CHG_USB_CDP;
 581                                         break;
 582                                 default:
 583                                         break;
 584                                 }
 585                                 break;
 586                         default:
 587                                 break;
 588                         }
 589                 } else {
 590                         notify_charger = true;
 591                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 592                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 593                 }
 594
 595                 if (rport->vbus_attached != vbus_attach) {
 596                         rport->vbus_attached = vbus_attach;
 597
 598                         if (notify_charger && rphy->edev) {
 599                                 extcon_set_state_sync(rphy->edev,
 600                                                         cable, vbus_attach);
 601                                 if (cable == EXTCON_CHG_USB_SDP)
 602                                         extcon_set_state_sync(rphy->edev,
 603                                                               EXTCON_USB,
 604                                                               vbus_attach);
 605                         }
 606                 }
 607                 break;
 608         case OTG_STATE_B_PERIPHERAL:
 609                 if (!vbus_attach) {
 610                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 611                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 612                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 613                         rport->state = OTG_STATE_B_IDLE;
 614                         delay = 0;
 615                         rockchip_usb2phy_power_off(rport->phy);
 616                 }
 617                 sch_work = true;
 618                 break;
 619         case OTG_STATE_A_HOST:
 620                 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
 621                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 622                         rport->state = OTG_STATE_B_IDLE;
 623                         rockchip_usb2phy_power_off(rport->phy);
 624                 }
 625                 break;
 626         default:
 627                 break;
 628         }
 629
 630         if (sch_work)
 631                 schedule_delayed_work(&rport->otg_sm_work, delay);
 632 }
 633
 634 static const char *chg_to_string(enum power_supply_type chg_type)
 635 {
 636         switch (chg_type) {
 637         case POWER_SUPPLY_TYPE_USB:
 638                 return "USB_SDP_CHARGER";
 639         case POWER_SUPPLY_TYPE_USB_DCP:
 640                 return "USB_DCP_CHARGER";
 641         case POWER_SUPPLY_TYPE_USB_CDP:
 642                 return "USB_CDP_CHARGER";
 643         default:
 644                 return "INVALID_CHARGER";
 645         }
 646 }
 647
 648 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 649                                     bool en)
 650 {
 651         struct regmap *base = get_reg_base(rphy);
 652
 653         property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 654         property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
 655 }
 656
 657 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 658                                             bool en)
 659 {
 660         struct regmap *base = get_reg_base(rphy);
 661
 662         property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 663         property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 664 }
 665
 666 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 667                                               bool en)
 668 {
 669         struct regmap *base = get_reg_base(rphy);
 670
 671         property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 672         property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 673 }
 674
 675 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 676 #define CHG_DCD_MAX_RETRIES     6
 677 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 678 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 679 static void rockchip_chg_detect_work(struct work_struct *work)
 680 {
 681         struct rockchip_usb2phy_port *rport =
 682                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 683         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 684         struct regmap *base = get_reg_base(rphy);
 685         bool is_dcd, tmout, vout;
 686         unsigned long delay;
 687
 688         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 689                 rphy->chg_state);
 690         switch (rphy->chg_state) {
 691         case USB_CHG_STATE_UNDEFINED:
 692                 if (!rport->suspended)
 693                         rockchip_usb2phy_power_off(rport->phy);
 694                 /* put the controller in non-driving mode */
 695                 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
 696                 /* Start DCD processing stage 1 */
 697                 rockchip_chg_enable_dcd(rphy, true);
 698                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 699                 rphy->dcd_retries = 0;
 700                 delay = CHG_DCD_POLL_TIME;
 701                 break;
 702         case USB_CHG_STATE_WAIT_FOR_DCD:
 703                 /* get data contact detection status */
 704                 is_dcd = property_enabled(rphy->grf,
 705                                           &rphy->phy_cfg->chg_det.dp_det);
 706                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 707                 /* stage 2 */
 708                 if (is_dcd || tmout) {
 709                         /* stage 4 */
 710                         /* Turn off DCD circuitry */
 711                         rockchip_chg_enable_dcd(rphy, false);
 712                         /* Voltage Source on DP, Probe on DM */
 713                         rockchip_chg_enable_primary_det(rphy, true);
 714                         delay = CHG_PRIMARY_DET_TIME;
 715                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 716                 } else {
 717                         /* stage 3 */
 718                         delay = CHG_DCD_POLL_TIME;
 719                 }
 720                 break;
 721         case USB_CHG_STATE_DCD_DONE:
 722                 vout = property_enabled(rphy->grf,
 723                                         &rphy->phy_cfg->chg_det.cp_det);
 724                 rockchip_chg_enable_primary_det(rphy, false);
 725                 if (vout) {
 726                         /* Voltage Source on DM, Probe on DP  */
 727                         rockchip_chg_enable_secondary_det(rphy, true);
 728                         delay = CHG_SECONDARY_DET_TIME;
 729                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 730                 } else {
 731                         if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
 732                                 /* floating charger found */
 733                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 734                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 735                                 delay = 0;
 736                         } else {
 737                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 738                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 739                                 delay = 0;
 740                         }
 741                 }
 742                 break;
 743         case USB_CHG_STATE_PRIMARY_DONE:
 744                 vout = property_enabled(rphy->grf,
 745                                         &rphy->phy_cfg->chg_det.dcp_det);
 746                 /* Turn off voltage source */
 747                 rockchip_chg_enable_secondary_det(rphy, false);
 748                 if (vout)
 749                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 750                 else
 751                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 752                 fallthrough;
 753         case USB_CHG_STATE_SECONDARY_DONE:
 754                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 755                 fallthrough;
 756         case USB_CHG_STATE_DETECTED:
 757                 /* put the controller in normal mode */
 758                 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
 759                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 760                 dev_dbg(&rport->phy->dev, "charger = %s\n",
 761                          chg_to_string(rphy->chg_type));
 762                 return;
 763         default:
 764                 return;
 765         }
 766
 767         schedule_delayed_work(&rport->chg_work, delay);
 768 }
 769
 770 /*
 771  * The function manage host-phy port state and suspend/resume phy port
 772  * to save power.
 773  *
 774  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 775  * devices is disconnect or not. Besides, we do not need care it is FS/LS
 776  * disconnected or HS disconnected, actually, we just only need get the
 777  * device is disconnected at last through rearm the delayed work,
 778  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 779  *
 780  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 781  * some clk related APIs, so do not invoke it from interrupt context directly.
 782  */
 783 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 784 {
 785         struct rockchip_usb2phy_port *rport =
 786                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 787         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 788         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 789                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 790         unsigned int ul, uhd, state;
 791         unsigned int ul_mask, uhd_mask;
 792         int ret;
 793
 794         mutex_lock(&rport->mutex);
 795
 796         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 797         if (ret < 0)
 798                 goto next_schedule;
 799
 800         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
 801         if (ret < 0)
 802                 goto next_schedule;
 803
 804         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 805                            rport->port_cfg->utmi_hstdet.bitstart);
 806         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 807                           rport->port_cfg->utmi_ls.bitstart);
 808
 809         /* stitch on utmi_ls and utmi_hstdet as phy state */
 810         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 811                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 812
 813         switch (state) {
 814         case PHY_STATE_HS_ONLINE:
 815                 dev_dbg(&rport->phy->dev, "HS online\n");
 816                 break;
 817         case PHY_STATE_FS_LS_ONLINE:
 818                 /*
 819                  * For FS/LS device, the online state share with connect state
 820                  * from utmi_ls and utmi_hstdet register, so we distinguish
 821                  * them via suspended flag.
 822                  *
 823                  * Plus, there are two cases, one is D- Line pull-up, and D+
 824                  * line pull-down, the state is 4; another is D+ line pull-up,
 825                  * and D- line pull-down, the state is 2.
 826                  */
 827                 if (!rport->suspended) {
 828                         /* D- line pull-up, D+ line pull-down */
 829                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 830                         break;
 831                 }
 832                 fallthrough;
 833         case PHY_STATE_CONNECT:
 834                 if (rport->suspended) {
 835                         dev_dbg(&rport->phy->dev, "Connected\n");
 836                         rockchip_usb2phy_power_on(rport->phy);
 837                         rport->suspended = false;
 838                 } else {
 839                         /* D+ line pull-up, D- line pull-down */
 840                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 841                 }
 842                 break;
 843         case PHY_STATE_DISCONNECT:
 844                 if (!rport->suspended) {
 845                         dev_dbg(&rport->phy->dev, "Disconnected\n");
 846                         rockchip_usb2phy_power_off(rport->phy);
 847                         rport->suspended = true;
 848                 }
 849
 850                 /*
 851                  * activate the linestate detection to get the next device
 852                  * plug-in irq.
 853                  */
 854                 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
 855                 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
 856
 857                 /*
 858                  * we don't need to rearm the delayed work when the phy port
 859                  * is suspended.
 860                  */
 861                 mutex_unlock(&rport->mutex);
 862                 return;
 863         default:
 864                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 865                 break;
 866         }
 867
 868 next_schedule:
 869         mutex_unlock(&rport->mutex);
 870         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 871 }
 872
 873 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
 874 {
 875         struct rockchip_usb2phy_port *rport = data;
 876         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 877
 878         if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
 879                 return IRQ_NONE;
 880
 881         mutex_lock(&rport->mutex);
 882
 883         /* disable linestate detect irq and clear its status */
 884         property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
 885         property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
 886
 887         mutex_unlock(&rport->mutex);
 888
 889         /*
 890          * In this case for host phy port, a new device is plugged in,
 891          * meanwhile, if the phy port is suspended, we need rearm the work to
 892          * resume it and mange its states; otherwise, we do nothing about that.
 893          */
 894         if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
 895                 rockchip_usb2phy_sm_work(&rport->sm_work.work);
 896
 897         return IRQ_HANDLED;
 898 }
 899
 900 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
 901 {
 902         struct rockchip_usb2phy_port *rport = data;
 903         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 904
 905         if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
 906                 return IRQ_NONE;
 907
 908         mutex_lock(&rport->mutex);
 909
 910         /* clear bvalid detect irq pending status */
 911         property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
 912
 913         mutex_unlock(&rport->mutex);
 914
 915         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 916
 917         return IRQ_HANDLED;
 918 }
 919
 920 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
 921 {
 922         struct rockchip_usb2phy_port *rport = data;
 923         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 924
 925         if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
 926                 return rockchip_usb2phy_bvalid_irq(irq, data);
 927         else
 928                 return IRQ_NONE;
 929 }
 930
 931 static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
 932 {
 933         struct rockchip_usb2phy *rphy = data;
 934         struct rockchip_usb2phy_port *rport;
 935         irqreturn_t ret = IRQ_NONE;
 936         unsigned int index;
 937
 938         for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
 939                 rport = &rphy->ports[index];
 940                 if (!rport->phy)
 941                         continue;
 942
 943                 /* Handle linestate irq for both otg port and host port */
 944                 ret = rockchip_usb2phy_linestate_irq(irq, rport);
 945         }
 946
 947         return ret;
 948 }
 949
 950 static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
 951                                           struct rockchip_usb2phy_port *rport,
 952                                           struct device_node *child_np)
 953 {
 954         int ret;
 955
 956         /*
 957          * If the usb2 phy used combined irq for otg and host port,
 958          * don't need to init otg and host port irq separately.
 959          */
 960         if (rphy->irq > 0)
 961                 return 0;
 962
 963         switch (rport->port_id) {
 964         case USB2PHY_PORT_HOST:
 965                 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
 966                 if (rport->ls_irq < 0) {
 967                         dev_err(rphy->dev, "no linestate irq provided\n");
 968                         return rport->ls_irq;
 969                 }
 970
 971                 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
 972                                                 rockchip_usb2phy_linestate_irq,
 973                                                 IRQF_ONESHOT,
 974                                                 "rockchip_usb2phy", rport);
 975                 if (ret) {
 976                         dev_err(rphy->dev, "failed to request linestate irq handle\n");
 977                         return ret;
 978                 }
 979                 break;
 980         case USB2PHY_PORT_OTG:
 981                 /*
 982                  * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
 983                  * interrupts muxed together, so probe the otg-mux interrupt first,
 984                  * if not found, then look for the regular interrupts one by one.
 985                  */
 986                 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
 987                 if (rport->otg_mux_irq > 0) {
 988                         ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
 989                                                         NULL,
 990                                                         rockchip_usb2phy_otg_mux_irq,
 991                                                         IRQF_ONESHOT,
 992                                                         "rockchip_usb2phy_otg",
 993                                                         rport);
 994                         if (ret) {
 995                                 dev_err(rphy->dev,
 996                                         "failed to request otg-mux irq handle\n");
 997                                 return ret;
 998                         }
 999                 } else {
1000                         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1001                         if (rport->bvalid_irq < 0) {
1002                                 dev_err(rphy->dev, "no vbus valid irq provided\n");
1003                                 ret = rport->bvalid_irq;
1004                                 return ret;
1005                         }
1006
1007                         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
1008                                                         NULL,
1009                                                         rockchip_usb2phy_bvalid_irq,
1010                                                         IRQF_ONESHOT,
1011                                                         "rockchip_usb2phy_bvalid",
1012                                                         rport);
1013                         if (ret) {
1014                                 dev_err(rphy->dev,
1015                                         "failed to request otg-bvalid irq handle\n");
1016                                 return ret;
1017                         }
1018                 }
1019                 break;
1020         default:
1021                 return -EINVAL;
1022         }
1023
1024         return 0;
1025 }
1026
1027 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1028                                            struct rockchip_usb2phy_port *rport,
1029                                            struct device_node *child_np)
1030 {
1031         int ret;
1032
1033         rport->port_id = USB2PHY_PORT_HOST;
1034         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1035         rport->suspended = true;
1036
1037         mutex_init(&rport->mutex);
1038         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1039
1040         ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1041         if (ret) {
1042                 dev_err(rphy->dev, "failed to setup host irq\n");
1043                 return ret;
1044         }
1045
1046         return 0;
1047 }
1048
1049 static int rockchip_otg_event(struct notifier_block *nb,
1050                               unsigned long event, void *ptr)
1051 {
1052         struct rockchip_usb2phy_port *rport =
1053                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1054
1055         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1056
1057         return NOTIFY_DONE;
1058 }
1059
1060 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1061                                           struct rockchip_usb2phy_port *rport,
1062                                           struct device_node *child_np)
1063 {
1064         int ret;
1065
1066         rport->port_id = USB2PHY_PORT_OTG;
1067         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1068         rport->state = OTG_STATE_UNDEFINED;
1069
1070         /*
1071          * set suspended flag to true, but actually don't
1072          * put phy in suspend mode, it aims to enable usb
1073          * phy and clock in power_on() called by usb controller
1074          * driver during probe.
1075          */
1076         rport->suspended = true;
1077         rport->vbus_attached = false;
1078
1079         mutex_init(&rport->mutex);
1080
1081         rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1082         if (rport->mode == USB_DR_MODE_HOST ||
1083             rport->mode == USB_DR_MODE_UNKNOWN) {
1084                 ret = 0;
1085                 goto out;
1086         }
1087
1088         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1089         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1090
1091         ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1092         if (ret) {
1093                 dev_err(rphy->dev, "failed to init irq for host port\n");
1094                 goto out;
1095         }
1096
1097         if (!IS_ERR(rphy->edev)) {
1098                 rport->event_nb.notifier_call = rockchip_otg_event;
1099
1100                 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev,
1101                                         EXTCON_USB_HOST, &rport->event_nb);
1102                 if (ret)
1103                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1104         }
1105
1106 out:
1107         return ret;
1108 }
1109
1110 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1111 {
1112         struct device *dev = &pdev->dev;
1113         struct device_node *np = dev->of_node;
1114         struct device_node *child_np;
1115         struct phy_provider *provider;
1116         struct rockchip_usb2phy *rphy;
1117         const struct rockchip_usb2phy_cfg *phy_cfgs;
1118         const struct of_device_id *match;
1119         unsigned int reg;
1120         int index, ret;
1121
1122         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1123         if (!rphy)
1124                 return -ENOMEM;
1125
1126         match = of_match_device(dev->driver->of_match_table, dev);
1127         if (!match || !match->data) {
1128                 dev_err(dev, "phy configs are not assigned!\n");
1129                 return -EINVAL;
1130         }
1131
1132         if (!dev->parent || !dev->parent->of_node) {
1133                 rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
1134                 if (IS_ERR(rphy->grf)) {
1135                         dev_err(dev, "failed to locate usbgrf\n");
1136                         return PTR_ERR(rphy->grf);
1137                 }
1138         }
1139
1140         else {
1141                 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1142                         if (IS_ERR(rphy->grf))
1143                                 return PTR_ERR(rphy->grf);
1144         }
1145
1146         if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
1147                 rphy->usbgrf =
1148                         syscon_regmap_lookup_by_phandle(dev->of_node,
1149                                                         "rockchip,usbgrf");
1150                 if (IS_ERR(rphy->usbgrf))
1151                         return PTR_ERR(rphy->usbgrf);
1152         } else {
1153                 rphy->usbgrf = NULL;
1154         }
1155
1156         if (of_property_read_u32_index(np, "reg", 0, &reg)) {
1157                 dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1158                         np);
1159                 return -EINVAL;
1160         }
1161
1162         /* support address_cells=2 */
1163         if (reg == 0) {
1164                 if (of_property_read_u32_index(np, "reg", 1, &reg)) {
1165                         dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1166                                 np);
1167                         return -EINVAL;
1168                 }
1169         }
1170
1171         rphy->dev = dev;
1172         phy_cfgs = match->data;
1173         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1174         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1175         rphy->irq = platform_get_irq_optional(pdev, 0);
1176         platform_set_drvdata(pdev, rphy);
1177
1178         ret = rockchip_usb2phy_extcon_register(rphy);
1179         if (ret)
1180                 return ret;
1181
1182         /* find out a proper config which can be matched with dt. */
1183         index = 0;
1184         while (phy_cfgs[index].reg) {
1185                 if (phy_cfgs[index].reg == reg) {
1186                         rphy->phy_cfg = &phy_cfgs[index];
1187                         break;
1188                 }
1189
1190                 ++index;
1191         }
1192
1193         if (!rphy->phy_cfg) {
1194                 dev_err(dev, "no phy-config can be matched with %pOFn node\n",
1195                         np);
1196                 return -EINVAL;
1197         }
1198
1199         rphy->clk = of_clk_get_by_name(np, "phyclk");
1200         if (!IS_ERR(rphy->clk)) {
1201                 clk_prepare_enable(rphy->clk);
1202         } else {
1203                 dev_info(&pdev->dev, "no phyclk specified\n");
1204                 rphy->clk = NULL;
1205         }
1206
1207         ret = rockchip_usb2phy_clk480m_register(rphy);
1208         if (ret) {
1209                 dev_err(dev, "failed to register 480m output clock\n");
1210                 goto disable_clks;
1211         }
1212
1213         index = 0;
1214         for_each_available_child_of_node(np, child_np) {
1215                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1216                 struct phy *phy;
1217
1218                 /* This driver aims to support both otg-port and host-port */
1219                 if (!of_node_name_eq(child_np, "host-port") &&
1220                     !of_node_name_eq(child_np, "otg-port"))
1221                         goto next_child;
1222
1223                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1224                 if (IS_ERR(phy)) {
1225                         dev_err(dev, "failed to create phy\n");
1226                         ret = PTR_ERR(phy);
1227                         goto put_child;
1228                 }
1229
1230                 rport->phy = phy;
1231                 phy_set_drvdata(rport->phy, rport);
1232
1233                 /* initialize otg/host port separately */
1234                 if (of_node_name_eq(child_np, "host-port")) {
1235                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1236                                                               child_np);
1237                         if (ret)
1238                                 goto put_child;
1239                 } else {
1240                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1241                                                              child_np);
1242                         if (ret)
1243                                 goto put_child;
1244                 }
1245
1246 next_child:
1247                 /* to prevent out of boundary */
1248                 if (++index >= rphy->phy_cfg->num_ports) {
1249                         of_node_put(child_np);
1250                         break;
1251                 }
1252         }
1253
1254         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1255
1256         if (rphy->irq > 0) {
1257                 ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
1258                                                 rockchip_usb2phy_irq,
1259                                                 IRQF_ONESHOT,
1260                                                 "rockchip_usb2phy",
1261                                                 rphy);
1262                 if (ret) {
1263                         dev_err(rphy->dev,
1264                                 "failed to request usb2phy irq handle\n");
1265                         goto put_child;
1266                 }
1267         }
1268
1269         return PTR_ERR_OR_ZERO(provider);
1270
1271 put_child:
1272         of_node_put(child_np);
1273 disable_clks:
1274         if (rphy->clk) {
1275                 clk_disable_unprepare(rphy->clk);
1276                 clk_put(rphy->clk);
1277         }
1278         return ret;
1279 }
1280
1281 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
1282         {
1283                 .reg = 0x760,
1284                 .num_ports      = 2,
1285                 .clkout_ctl     = { 0x0768, 4, 4, 1, 0 },
1286                 .port_cfgs      = {
1287                         [USB2PHY_PORT_OTG] = {
1288                                 .phy_sus        = { 0x0760, 15, 0, 0, 0x1d1 },
1289                                 .bvalid_det_en  = { 0x0680, 3, 3, 0, 1 },
1290                                 .bvalid_det_st  = { 0x0690, 3, 3, 0, 1 },
1291                                 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1292                                 .ls_det_en      = { 0x0680, 2, 2, 0, 1 },
1293                                 .ls_det_st      = { 0x0690, 2, 2, 0, 1 },
1294                                 .ls_det_clr     = { 0x06a0, 2, 2, 0, 1 },
1295                                 .utmi_bvalid    = { 0x0480, 4, 4, 0, 1 },
1296                                 .utmi_ls        = { 0x0480, 3, 2, 0, 1 },
1297                         },
1298                         [USB2PHY_PORT_HOST] = {
1299                                 .phy_sus        = { 0x0764, 15, 0, 0, 0x1d1 },
1300                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1301                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1302                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 }
1303                         }
1304                 },
1305                 .chg_det = {
1306                         .opmode         = { 0x0760, 3, 0, 5, 1 },
1307                         .cp_det         = { 0x0884, 4, 4, 0, 1 },
1308                         .dcp_det        = { 0x0884, 3, 3, 0, 1 },
1309                         .dp_det         = { 0x0884, 5, 5, 0, 1 },
1310                         .idm_sink_en    = { 0x0768, 8, 8, 0, 1 },
1311                         .idp_sink_en    = { 0x0768, 7, 7, 0, 1 },
1312                         .idp_src_en     = { 0x0768, 9, 9, 0, 1 },
1313                         .rdm_pdwn_en    = { 0x0768, 10, 10, 0, 1 },
1314                         .vdm_src_en     = { 0x0768, 12, 12, 0, 1 },
1315                         .vdp_src_en     = { 0x0768, 11, 11, 0, 1 },
1316                 },
1317         },
1318         {
1319                 .reg = 0x800,
1320                 .num_ports      = 2,
1321                 .clkout_ctl     = { 0x0808, 4, 4, 1, 0 },
1322                 .port_cfgs      = {
1323                         [USB2PHY_PORT_OTG] = {
1324                                 .phy_sus        = { 0x800, 15, 0, 0, 0x1d1 },
1325                                 .ls_det_en      = { 0x0684, 0, 0, 0, 1 },
1326                                 .ls_det_st      = { 0x0694, 0, 0, 0, 1 },
1327                                 .ls_det_clr     = { 0x06a4, 0, 0, 0, 1 }
1328                         },
1329                         [USB2PHY_PORT_HOST] = {
1330                                 .phy_sus        = { 0x804, 15, 0, 0, 0x1d1 },
1331                                 .ls_det_en      = { 0x0684, 1, 1, 0, 1 },
1332                                 .ls_det_st      = { 0x0694, 1, 1, 0, 1 },
1333                                 .ls_det_clr     = { 0x06a4, 1, 1, 0, 1 }
1334                         }
1335                 },
1336         },
1337         { /* sentinel */ }
1338 };
1339
1340 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
1341         {
1342                 .reg = 0x100,
1343                 .num_ports      = 2,
1344                 .clkout_ctl     = { 0x108, 4, 4, 1, 0 },
1345                 .port_cfgs      = {
1346                         [USB2PHY_PORT_OTG] = {
1347                                 .phy_sus        = { 0x0100, 8, 0, 0, 0x1d1 },
1348                                 .bvalid_det_en  = { 0x3020, 2, 2, 0, 1 },
1349                                 .bvalid_det_st  = { 0x3024, 2, 2, 0, 1 },
1350                                 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 },
1351                                 .ls_det_en      = { 0x3020, 0, 0, 0, 1 },
1352                                 .ls_det_st      = { 0x3024, 0, 0, 0, 1 },
1353                                 .ls_det_clr     = { 0x3028, 0, 0, 0, 1 },
1354                                 .utmi_avalid    = { 0x0120, 10, 10, 0, 1 },
1355                                 .utmi_bvalid    = { 0x0120, 9, 9, 0, 1 },
1356                                 .utmi_ls        = { 0x0120, 5, 4, 0, 1 },
1357                         },
1358                         [USB2PHY_PORT_HOST] = {
1359                                 .phy_sus        = { 0x0104, 8, 0, 0, 0x1d1 },
1360                                 .ls_det_en      = { 0x3020, 1, 1, 0, 1 },
1361                                 .ls_det_st      = { 0x3024, 1, 1, 0, 1 },
1362                                 .ls_det_clr     = { 0x3028, 1, 1, 0, 1 },
1363                                 .utmi_ls        = { 0x0120, 17, 16, 0, 1 },
1364                                 .utmi_hstdet    = { 0x0120, 19, 19, 0, 1 }
1365                         }
1366                 },
1367                 .chg_det = {
1368                         .opmode         = { 0x0100, 3, 0, 5, 1 },
1369                         .cp_det         = { 0x0120, 24, 24, 0, 1 },
1370                         .dcp_det        = { 0x0120, 23, 23, 0, 1 },
1371                         .dp_det         = { 0x0120, 25, 25, 0, 1 },
1372                         .idm_sink_en    = { 0x0108, 8, 8, 0, 1 },
1373                         .idp_sink_en    = { 0x0108, 7, 7, 0, 1 },
1374                         .idp_src_en     = { 0x0108, 9, 9, 0, 1 },
1375                         .rdm_pdwn_en    = { 0x0108, 10, 10, 0, 1 },
1376                         .vdm_src_en     = { 0x0108, 12, 12, 0, 1 },
1377                         .vdp_src_en     = { 0x0108, 11, 11, 0, 1 },
1378                 },
1379         },
1380         { /* sentinel */ }
1381 };
1382
1383 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1384         {
1385                 .reg = 0x100,
1386                 .num_ports      = 2,
1387                 .clkout_ctl     = { 0x108, 4, 4, 1, 0 },
1388                 .port_cfgs      = {
1389                         [USB2PHY_PORT_OTG] = {
1390                                 .phy_sus        = { 0x0100, 15, 0, 0, 0x1d1 },
1391                                 .bvalid_det_en  = { 0x0110, 2, 2, 0, 1 },
1392                                 .bvalid_det_st  = { 0x0114, 2, 2, 0, 1 },
1393                                 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1394                                 .ls_det_en      = { 0x0110, 0, 0, 0, 1 },
1395                                 .ls_det_st      = { 0x0114, 0, 0, 0, 1 },
1396                                 .ls_det_clr     = { 0x0118, 0, 0, 0, 1 },
1397                                 .utmi_avalid    = { 0x0120, 10, 10, 0, 1 },
1398                                 .utmi_bvalid    = { 0x0120, 9, 9, 0, 1 },
1399                                 .utmi_ls        = { 0x0120, 5, 4, 0, 1 },
1400                         },
1401                         [USB2PHY_PORT_HOST] = {
1402                                 .phy_sus        = { 0x104, 15, 0, 0, 0x1d1 },
1403                                 .ls_det_en      = { 0x110, 1, 1, 0, 1 },
1404                                 .ls_det_st      = { 0x114, 1, 1, 0, 1 },
1405                                 .ls_det_clr     = { 0x118, 1, 1, 0, 1 },
1406                                 .utmi_ls        = { 0x120, 17, 16, 0, 1 },
1407                                 .utmi_hstdet    = { 0x120, 19, 19, 0, 1 }
1408                         }
1409                 },
1410                 .chg_det = {
1411                         .opmode         = { 0x0100, 3, 0, 5, 1 },
1412                         .cp_det         = { 0x0120, 24, 24, 0, 1 },
1413                         .dcp_det        = { 0x0120, 23, 23, 0, 1 },
1414                         .dp_det         = { 0x0120, 25, 25, 0, 1 },
1415                         .idm_sink_en    = { 0x0108, 8, 8, 0, 1 },
1416                         .idp_sink_en    = { 0x0108, 7, 7, 0, 1 },
1417                         .idp_src_en     = { 0x0108, 9, 9, 0, 1 },
1418                         .rdm_pdwn_en    = { 0x0108, 10, 10, 0, 1 },
1419                         .vdm_src_en     = { 0x0108, 12, 12, 0, 1 },
1420                         .vdp_src_en     = { 0x0108, 11, 11, 0, 1 },
1421                 },
1422         },
1423         { /* sentinel */ }
1424 };
1425
1426 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1427         {
1428                 .reg = 0x700,
1429                 .num_ports      = 2,
1430                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1431                 .port_cfgs      = {
1432                         [USB2PHY_PORT_HOST] = {
1433                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1434                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1435                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1436                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1437                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1438                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1439                         }
1440                 },
1441         },
1442         { /* sentinel */ }
1443 };
1444
1445 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1446         {
1447                 .reg            = 0xe450,
1448                 .num_ports      = 2,
1449                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1450                 .port_cfgs      = {
1451                         [USB2PHY_PORT_OTG] = {
1452                                 .phy_sus        = { 0xe454, 1, 0, 2, 1 },
1453                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1454                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1455                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1456                                 .utmi_avalid    = { 0xe2ac, 7, 7, 0, 1 },
1457                                 .utmi_bvalid    = { 0xe2ac, 12, 12, 0, 1 },
1458                         },
1459                         [USB2PHY_PORT_HOST] = {
1460                                 .phy_sus        = { 0xe458, 1, 0, 0x2, 0x1 },
1461                                 .ls_det_en      = { 0xe3c0, 6, 6, 0, 1 },
1462                                 .ls_det_st      = { 0xe3e0, 6, 6, 0, 1 },
1463                                 .ls_det_clr     = { 0xe3d0, 6, 6, 0, 1 },
1464                                 .utmi_ls        = { 0xe2ac, 22, 21, 0, 1 },
1465                                 .utmi_hstdet    = { 0xe2ac, 23, 23, 0, 1 }
1466                         }
1467                 },
1468                 .chg_det = {
1469                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1470                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1471                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1472                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1473                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1474                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1475                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1476                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1477                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1478                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1479                 },
1480         },
1481         {
1482                 .reg            = 0xe460,
1483                 .num_ports      = 2,
1484                 .clkout_ctl     = { 0xe460, 4, 4, 1, 0 },
1485                 .port_cfgs      = {
1486                         [USB2PHY_PORT_OTG] = {
1487                                 .phy_sus        = { 0xe464, 1, 0, 2, 1 },
1488                                 .bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1489                                 .bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1490                                 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1491                                 .utmi_avalid    = { 0xe2ac, 10, 10, 0, 1 },
1492                                 .utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1493                         },
1494                         [USB2PHY_PORT_HOST] = {
1495                                 .phy_sus        = { 0xe468, 1, 0, 0x2, 0x1 },
1496                                 .ls_det_en      = { 0xe3c0, 11, 11, 0, 1 },
1497                                 .ls_det_st      = { 0xe3e0, 11, 11, 0, 1 },
1498                                 .ls_det_clr     = { 0xe3d0, 11, 11, 0, 1 },
1499                                 .utmi_ls        = { 0xe2ac, 26, 25, 0, 1 },
1500                                 .utmi_hstdet    = { 0xe2ac, 27, 27, 0, 1 }
1501                         }
1502                 },
1503         },
1504         { /* sentinel */ }
1505 };
1506
1507 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
1508         {
1509                 .reg = 0xfe8a0000,
1510                 .num_ports      = 2,
1511                 .clkout_ctl     = { 0x0008, 4, 4, 1, 0 },
1512                 .port_cfgs      = {
1513                         [USB2PHY_PORT_OTG] = {
1514                                 .phy_sus        = { 0x0000, 8, 0, 0, 0x1d1 },
1515                                 .bvalid_det_en  = { 0x0080, 2, 2, 0, 1 },
1516                                 .bvalid_det_st  = { 0x0084, 2, 2, 0, 1 },
1517                                 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
1518                                 .utmi_avalid    = { 0x00c0, 10, 10, 0, 1 },
1519                                 .utmi_bvalid    = { 0x00c0, 9, 9, 0, 1 },
1520                         },
1521                         [USB2PHY_PORT_HOST] = {
1522                                 /* Select suspend control from controller */
1523                                 .phy_sus        = { 0x0004, 8, 0, 0x1d2, 0x1d2 },
1524                                 .ls_det_en      = { 0x0080, 1, 1, 0, 1 },
1525                                 .ls_det_st      = { 0x0084, 1, 1, 0, 1 },
1526                                 .ls_det_clr     = { 0x0088, 1, 1, 0, 1 },
1527                                 .utmi_ls        = { 0x00c0, 17, 16, 0, 1 },
1528                                 .utmi_hstdet    = { 0x00c0, 19, 19, 0, 1 }
1529                         }
1530                 },
1531                 .chg_det = {
1532                         .opmode         = { 0x0000, 3, 0, 5, 1 },
1533                         .cp_det         = { 0x00c0, 24, 24, 0, 1 },
1534                         .dcp_det        = { 0x00c0, 23, 23, 0, 1 },
1535                         .dp_det         = { 0x00c0, 25, 25, 0, 1 },
1536                         .idm_sink_en    = { 0x0008, 8, 8, 0, 1 },
1537                         .idp_sink_en    = { 0x0008, 7, 7, 0, 1 },
1538                         .idp_src_en     = { 0x0008, 9, 9, 0, 1 },
1539                         .rdm_pdwn_en    = { 0x0008, 10, 10, 0, 1 },
1540                         .vdm_src_en     = { 0x0008, 12, 12, 0, 1 },
1541                         .vdp_src_en     = { 0x0008, 11, 11, 0, 1 },
1542                 },
1543         },
1544         {
1545                 .reg = 0xfe8b0000,
1546                 .num_ports      = 2,
1547                 .clkout_ctl     = { 0x0008, 4, 4, 1, 0 },
1548                 .port_cfgs      = {
1549                         [USB2PHY_PORT_OTG] = {
1550                                 .phy_sus        = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
1551                                 .ls_det_en      = { 0x0080, 0, 0, 0, 1 },
1552                                 .ls_det_st      = { 0x0084, 0, 0, 0, 1 },
1553                                 .ls_det_clr     = { 0x0088, 0, 0, 0, 1 },
1554                                 .utmi_ls        = { 0x00c0, 5, 4, 0, 1 },
1555                                 .utmi_hstdet    = { 0x00c0, 7, 7, 0, 1 }
1556                         },
1557                         [USB2PHY_PORT_HOST] = {
1558                                 .phy_sus        = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1559                                 .ls_det_en      = { 0x0080, 1, 1, 0, 1 },
1560                                 .ls_det_st      = { 0x0084, 1, 1, 0, 1 },
1561                                 .ls_det_clr     = { 0x0088, 1, 1, 0, 1 },
1562                                 .utmi_ls        = { 0x00c0, 17, 16, 0, 1 },
1563                                 .utmi_hstdet    = { 0x00c0, 19, 19, 0, 1 }
1564                         }
1565                 },
1566         },
1567         { /* sentinel */ }
1568 };
1569
1570 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
1571         {
1572                 .reg = 0x100,
1573                 .num_ports      = 2,
1574                 .clkout_ctl     = { 0x108, 4, 4, 1, 0 },
1575                 .port_cfgs      = {
1576                         [USB2PHY_PORT_OTG] = {
1577                                 .phy_sus        = { 0x0100, 15, 0, 0, 0x1d1 },
1578                                 .bvalid_det_en  = { 0x0680, 3, 3, 0, 1 },
1579                                 .bvalid_det_st  = { 0x0690, 3, 3, 0, 1 },
1580                                 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1581                                 .ls_det_en      = { 0x0680, 2, 2, 0, 1 },
1582                                 .ls_det_st      = { 0x0690, 2, 2, 0, 1 },
1583                                 .ls_det_clr     = { 0x06a0, 2, 2, 0, 1 },
1584                                 .utmi_bvalid    = { 0x0804, 10, 10, 0, 1 },
1585                                 .utmi_ls        = { 0x0804, 13, 12, 0, 1 },
1586                         },
1587                         [USB2PHY_PORT_HOST] = {
1588                                 .phy_sus        = { 0x0104, 15, 0, 0, 0x1d1 },
1589                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1590                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1591                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1592                                 .utmi_ls        = { 0x0804, 9, 8, 0, 1 },
1593                                 .utmi_hstdet    = { 0x0804, 7, 7, 0, 1 }
1594                         }
1595                 },
1596                 .chg_det = {
1597                         .opmode         = { 0x0100, 3, 0, 5, 1 },
1598                         .cp_det         = { 0x0804, 1, 1, 0, 1 },
1599                         .dcp_det        = { 0x0804, 0, 0, 0, 1 },
1600                         .dp_det         = { 0x0804, 2, 2, 0, 1 },
1601                         .idm_sink_en    = { 0x0108, 8, 8, 0, 1 },
1602                         .idp_sink_en    = { 0x0108, 7, 7, 0, 1 },
1603                         .idp_src_en     = { 0x0108, 9, 9, 0, 1 },
1604                         .rdm_pdwn_en    = { 0x0108, 10, 10, 0, 1 },
1605                         .vdm_src_en     = { 0x0108, 12, 12, 0, 1 },
1606                         .vdp_src_en     = { 0x0108, 11, 11, 0, 1 },
1607                 },
1608         },
1609         { /* sentinel */ }
1610 };
1611
1612 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1613         { .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
1614         { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
1615         { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
1616         { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1617         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1618         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1619         { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
1620         { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
1621         {}
1622 };
1623 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1624
1625 static struct platform_driver rockchip_usb2phy_driver = {
1626         .probe          = rockchip_usb2phy_probe,
1627         .driver         = {
1628                 .name   = "rockchip-usb2phy",
1629                 .of_match_table = rockchip_usb2phy_dt_match,
1630         },
1631 };
1632 module_platform_driver(rockchip_usb2phy_driver);
1633
1634 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1635 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1636 MODULE_LICENSE("GPL v2");