drivers/phy/cadence/phy-cadence-sierra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cadence Sierra PHY Driver
   4  *
   5  * Copyright (c) 2018 Cadence Design Systems
   6  * Author: Alan Douglas <adouglas@cadence.com>
   7  *
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/regmap.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <dt-bindings/phy/phy.h>
  24 #include <dt-bindings/phy/phy-cadence.h>
  25
  26 #define NUM_SSC_MODE            3
  27 #define NUM_PHY_TYPE            4
  28
  29 /* PHY register offsets */
  30 #define SIERRA_COMMON_CDB_OFFSET                        0x0
  31 #define SIERRA_MACRO_ID_REG                             0x0
  32 #define SIERRA_CMN_PLLLC_GEN_PREG                       0x42
  33 #define SIERRA_CMN_PLLLC_MODE_PREG                      0x48
  34 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG            0x49
  35 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG            0x4A
  36 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG             0x4B
  37 #define SIERRA_CMN_PLLLC_CLK1_PREG                      0x4D
  38 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG               0x4F
  39 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG               0x50
  40 #define SIERRA_CMN_PLLLC_DSMCORR_PREG                   0x51
  41 #define SIERRA_CMN_PLLLC_SS_PREG                        0x52
  42 #define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG          0x53
  43 #define SIERRA_CMN_PLLLC_SSTWOPT_PREG                   0x54
  44 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG     0x62
  45 #define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG           0x63
  46 #define SIERRA_CMN_REFRCV_PREG                          0x98
  47 #define SIERRA_CMN_REFRCV1_PREG                         0xB8
  48 #define SIERRA_CMN_PLLLC1_GEN_PREG                      0xC2
  49 #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG           0xCA
  50 #define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG              0xD0
  51 #define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG    0xE2
  52
  53 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset)    \
  54                                 ((0x4000 << (block_offset)) + \
  55                                  (((ln) << 9) << (reg_offset)))
  56
  57 #define SIERRA_DET_STANDEC_A_PREG                       0x000
  58 #define SIERRA_DET_STANDEC_B_PREG                       0x001
  59 #define SIERRA_DET_STANDEC_C_PREG                       0x002
  60 #define SIERRA_DET_STANDEC_D_PREG                       0x003
  61 #define SIERRA_DET_STANDEC_E_PREG                       0x004
  62 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG           0x008
  63 #define SIERRA_PSM_A0IN_TMR_PREG                        0x009
  64 #define SIERRA_PSM_A3IN_TMR_PREG                        0x00C
  65 #define SIERRA_PSM_DIAG_PREG                            0x015
  66 #define SIERRA_PSC_LN_A3_PREG                           0x023
  67 #define SIERRA_PSC_LN_A4_PREG                           0x024
  68 #define SIERRA_PSC_LN_IDLE_PREG                         0x026
  69 #define SIERRA_PSC_TX_A0_PREG                           0x028
  70 #define SIERRA_PSC_TX_A1_PREG                           0x029
  71 #define SIERRA_PSC_TX_A2_PREG                           0x02A
  72 #define SIERRA_PSC_TX_A3_PREG                           0x02B
  73 #define SIERRA_PSC_RX_A0_PREG                           0x030
  74 #define SIERRA_PSC_RX_A1_PREG                           0x031
  75 #define SIERRA_PSC_RX_A2_PREG                           0x032
  76 #define SIERRA_PSC_RX_A3_PREG                           0x033
  77 #define SIERRA_PLLCTRL_SUBRATE_PREG                     0x03A
  78 #define SIERRA_PLLCTRL_GEN_A_PREG                       0x03B
  79 #define SIERRA_PLLCTRL_GEN_D_PREG                       0x03E
  80 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG                 0x03F
  81 #define SIERRA_PLLCTRL_STATUS_PREG                      0x044
  82 #define SIERRA_CLKPATH_BIASTRIM_PREG                    0x04B
  83 #define SIERRA_DFE_BIASTRIM_PREG                        0x04C
  84 #define SIERRA_DRVCTRL_ATTEN_PREG                       0x06A
  85 #define SIERRA_DRVCTRL_BOOST_PREG                       0x06F
  86 #define SIERRA_CLKPATHCTRL_TMR_PREG                     0x081
  87 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG                0x085
  88 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG                0x086
  89 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG                0x087
  90 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG                0x088
  91 #define SIERRA_CREQ_DCBIASATTEN_OVR_PREG                0x08C
  92 #define SIERRA_CREQ_CCLKDET_MODE01_PREG                 0x08E
  93 #define SIERRA_RX_CTLE_CAL_PREG                         0x08F
  94 #define SIERRA_RX_CTLE_MAINTENANCE_PREG                 0x091
  95 #define SIERRA_CREQ_FSMCLK_SEL_PREG                     0x092
  96 #define SIERRA_CREQ_EQ_CTRL_PREG                        0x093
  97 #define SIERRA_CREQ_SPARE_PREG                          0x096
  98 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG             0x097
  99 #define SIERRA_CTLELUT_CTRL_PREG                        0x098
 100 #define SIERRA_DFE_ECMP_RATESEL_PREG                    0x0C0
 101 #define SIERRA_DFE_SMP_RATESEL_PREG                     0x0C1
 102 #define SIERRA_DEQ_PHALIGN_CTRL                         0x0C4
 103 #define SIERRA_DEQ_CONCUR_CTRL1_PREG                    0x0C8
 104 #define SIERRA_DEQ_CONCUR_CTRL2_PREG                    0x0C9
 105 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG                    0x0CD
 106 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG               0x0CE
 107 #define SIERRA_DEQ_ERRCMP_CTRL_PREG                     0x0D0
 108 #define SIERRA_DEQ_OFFSET_CTRL_PREG                     0x0D8
 109 #define SIERRA_DEQ_GAIN_CTRL_PREG                       0x0E0
 110 #define SIERRA_DEQ_VGATUNE_CTRL_PREG                    0x0E1
 111 #define SIERRA_DEQ_GLUT0                                0x0E8
 112 #define SIERRA_DEQ_GLUT1                                0x0E9
 113 #define SIERRA_DEQ_GLUT2                                0x0EA
 114 #define SIERRA_DEQ_GLUT3                                0x0EB
 115 #define SIERRA_DEQ_GLUT4                                0x0EC
 116 #define SIERRA_DEQ_GLUT5                                0x0ED
 117 #define SIERRA_DEQ_GLUT6                                0x0EE
 118 #define SIERRA_DEQ_GLUT7                                0x0EF
 119 #define SIERRA_DEQ_GLUT8                                0x0F0
 120 #define SIERRA_DEQ_GLUT9                                0x0F1
 121 #define SIERRA_DEQ_GLUT10                               0x0F2
 122 #define SIERRA_DEQ_GLUT11                               0x0F3
 123 #define SIERRA_DEQ_GLUT12                               0x0F4
 124 #define SIERRA_DEQ_GLUT13                               0x0F5
 125 #define SIERRA_DEQ_GLUT14                               0x0F6
 126 #define SIERRA_DEQ_GLUT15                               0x0F7
 127 #define SIERRA_DEQ_GLUT16                               0x0F8
 128 #define SIERRA_DEQ_ALUT0                                0x108
 129 #define SIERRA_DEQ_ALUT1                                0x109
 130 #define SIERRA_DEQ_ALUT2                                0x10A
 131 #define SIERRA_DEQ_ALUT3                                0x10B
 132 #define SIERRA_DEQ_ALUT4                                0x10C
 133 #define SIERRA_DEQ_ALUT5                                0x10D
 134 #define SIERRA_DEQ_ALUT6                                0x10E
 135 #define SIERRA_DEQ_ALUT7                                0x10F
 136 #define SIERRA_DEQ_ALUT8                                0x110
 137 #define SIERRA_DEQ_ALUT9                                0x111
 138 #define SIERRA_DEQ_ALUT10                               0x112
 139 #define SIERRA_DEQ_ALUT11                               0x113
 140 #define SIERRA_DEQ_ALUT12                               0x114
 141 #define SIERRA_DEQ_ALUT13                               0x115
 142 #define SIERRA_DEQ_DFETAP_CTRL_PREG                     0x128
 143 #define SIERRA_DEQ_DFETAP0                              0x129
 144 #define SIERRA_DEQ_DFETAP1                              0x12B
 145 #define SIERRA_DEQ_DFETAP2                              0x12D
 146 #define SIERRA_DEQ_DFETAP3                              0x12F
 147 #define SIERRA_DEQ_DFETAP4                              0x131
 148 #define SIERRA_DFE_EN_1010_IGNORE_PREG                  0x134
 149 #define SIERRA_DEQ_PRECUR_PREG                          0x138
 150 #define SIERRA_DEQ_POSTCUR_PREG                         0x140
 151 #define SIERRA_DEQ_POSTCUR_DECR_PREG                    0x142
 152 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG            0x150
 153 #define SIERRA_DEQ_TAU_CTRL2_PREG                       0x151
 154 #define SIERRA_DEQ_TAU_CTRL3_PREG                       0x152
 155 #define SIERRA_DEQ_OPENEYE_CTRL_PREG                    0x158
 156 #define SIERRA_DEQ_PICTRL_PREG                          0x161
 157 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG                 0x170
 158 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG                 0x171
 159 #define SIERRA_CPICAL_PICNT_MODE1_PREG                  0x174
 160 #define SIERRA_CPI_OUTBUF_RATESEL_PREG                  0x17C
 161 #define SIERRA_CPI_RESBIAS_BIN_PREG                     0x17E
 162 #define SIERRA_CPI_TRIM_PREG                            0x17F
 163 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG         0x183
 164 #define SIERRA_EPI_CTRL_PREG                            0x187
 165 #define SIERRA_LFPSDET_SUPPORT_PREG                     0x188
 166 #define SIERRA_LFPSFILT_NS_PREG                         0x18A
 167 #define SIERRA_LFPSFILT_RD_PREG                         0x18B
 168 #define SIERRA_LFPSFILT_MP_PREG                         0x18C
 169 #define SIERRA_SIGDET_SUPPORT_PREG                      0x190
 170 #define SIERRA_SDFILT_H2L_A_PREG                        0x191
 171 #define SIERRA_SDFILT_L2H_PREG                          0x193
 172 #define SIERRA_RXBUFFER_CTLECTRL_PREG                   0x19E
 173 #define SIERRA_RXBUFFER_RCDFECTRL_PREG                  0x19F
 174 #define SIERRA_RXBUFFER_DFECTRL_PREG                    0x1A0
 175 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG            0x14F
 176 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG            0x150
 177
 178 /* PHY PCS common registers */
 179 #define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset)      \
 180                                      (0xc000 << (block_offset))
 181 #define SIERRA_PHY_PIPE_CMN_CTRL1                       0x0
 182 #define SIERRA_PHY_PLL_CFG                              0xe
 183
 184 /* PHY PCS lane registers */
 185 #define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset)    \
 186                                        ((0xD000 << (block_offset)) +    \
 187                                        (((ln) << 8) << (reg_offset)))
 188
 189 #define SIERRA_PHY_ISO_LINK_CTRL                        0xB
 190
 191 /* PHY PMA common registers */
 192 #define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset)      \
 193                                      (0xE000 << (block_offset))
 194 #define SIERRA_PHY_PMA_CMN_CTRL                         0x000
 195
 196 /* PHY PMA lane registers */
 197 #define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset)    \
 198                                        ((0xF000 << (block_offset)) +    \
 199                                        (((ln) << 8) << (reg_offset)))
 200
 201 #define SIERRA_PHY_PMA_XCVR_CTRL                        0x000
 202
 203 #define SIERRA_MACRO_ID                                 0x00007364
 204 #define SIERRA_MAX_LANES                                16
 205 #define PLL_LOCK_TIME                                   100000
 206
 207 #define CDNS_SIERRA_OUTPUT_CLOCKS                       3
 208 #define CDNS_SIERRA_INPUT_CLOCKS                        5
 209 enum cdns_sierra_clock_input {
 210         PHY_CLK,
 211         CMN_REFCLK_DIG_DIV,
 212         CMN_REFCLK1_DIG_DIV,
 213         PLL0_REFCLK,
 214         PLL1_REFCLK,
 215 };
 216
 217 #define SIERRA_NUM_CMN_PLLC                             2
 218 #define SIERRA_NUM_CMN_PLLC_PARENTS                     2
 219
 220 static const struct reg_field macro_id_type =
 221                                 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
 222 static const struct reg_field phy_pll_cfg_1 =
 223                                 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
 224 static const struct reg_field pma_cmn_ready =
 225                                 REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
 226 static const struct reg_field pllctrl_lock =
 227                                 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
 228 static const struct reg_field phy_iso_link_ctrl_1 =
 229                                 REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1);
 230 static const struct reg_field cmn_plllc_clk1outdiv_preg =
 231                                 REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6);
 232 static const struct reg_field cmn_plllc_clk1_en_preg =
 233                                 REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 12, 12);
 234
 235 static const char * const clk_names[] = {
 236         [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
 237         [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
 238         [CDNS_SIERRA_DERIVED_REFCLK] = "refclk_der",
 239 };
 240
 241 enum cdns_sierra_cmn_plllc {
 242         CMN_PLLLC,
 243         CMN_PLLLC1,
 244 };
 245
 246 struct cdns_sierra_pll_mux_reg_fields {
 247         struct reg_field        pfdclk_sel_preg;
 248         struct reg_field        plllc1en_field;
 249         struct reg_field        termen_field;
 250 };
 251
 252 static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = {
 253         [CMN_PLLLC] = {
 254                 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
 255                 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
 256                 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
 257         },
 258         [CMN_PLLLC1] = {
 259                 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
 260                 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
 261                 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
 262         },
 263 };
 264
 265 struct cdns_sierra_pll_mux {
 266         struct clk_hw           hw;
 267         struct regmap_field     *pfdclk_sel_preg;
 268         struct regmap_field     *plllc1en_field;
 269         struct regmap_field     *termen_field;
 270         struct clk_init_data    clk_data;
 271 };
 272
 273 #define to_cdns_sierra_pll_mux(_hw)     \
 274                         container_of(_hw, struct cdns_sierra_pll_mux, hw)
 275
 276 static const int pll_mux_parent_index[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
 277         [CMN_PLLLC] = { PLL0_REFCLK, PLL1_REFCLK },
 278         [CMN_PLLLC1] = { PLL1_REFCLK, PLL0_REFCLK },
 279 };
 280
 281 static u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
 282         [CMN_PLLLC] = { 0, 1 },
 283         [CMN_PLLLC1] = { 1, 0 },
 284 };
 285
 286 struct cdns_sierra_derived_refclk {
 287         struct clk_hw           hw;
 288         struct regmap_field     *cmn_plllc_clk1outdiv_preg;
 289         struct regmap_field     *cmn_plllc_clk1_en_preg;
 290         struct clk_init_data    clk_data;
 291 };
 292
 293 #define to_cdns_sierra_derived_refclk(_hw)      \
 294                         container_of(_hw, struct cdns_sierra_derived_refclk, hw)
 295
 296 enum cdns_sierra_phy_type {
 297         TYPE_NONE,
 298         TYPE_PCIE,
 299         TYPE_USB,
 300         TYPE_QSGMII
 301 };
 302
 303 enum cdns_sierra_ssc_mode {
 304         NO_SSC,
 305         EXTERNAL_SSC,
 306         INTERNAL_SSC
 307 };
 308
 309 struct cdns_sierra_inst {
 310         struct phy *phy;
 311         enum cdns_sierra_phy_type phy_type;
 312         u32 num_lanes;
 313         u32 mlane;
 314         struct reset_control *lnk_rst;
 315         enum cdns_sierra_ssc_mode ssc_mode;
 316 };
 317
 318 struct cdns_reg_pairs {
 319         u16 val;
 320         u32 off;
 321 };
 322
 323 struct cdns_sierra_vals {
 324         const struct cdns_reg_pairs *reg_pairs;
 325         u32 num_regs;
 326 };
 327
 328 struct cdns_sierra_data {
 329         u32 id_value;
 330         u8 block_offset_shift;
 331         u8 reg_offset_shift;
 332         struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 333                                              [NUM_SSC_MODE];
 334         struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 335                                                 [NUM_SSC_MODE];
 336         struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 337                                              [NUM_SSC_MODE];
 338         struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 339                                             [NUM_SSC_MODE];
 340 };
 341
 342 struct cdns_regmap_cdb_context {
 343         struct device *dev;
 344         void __iomem *base;
 345         u8 reg_offset_shift;
 346 };
 347
 348 struct cdns_sierra_phy {
 349         struct device *dev;
 350         struct regmap *regmap;
 351         const struct cdns_sierra_data *init_data;
 352         struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
 353         struct reset_control *phy_rst;
 354         struct reset_control *apb_rst;
 355         struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
 356         struct regmap *regmap_phy_pcs_common_cdb;
 357         struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
 358         struct regmap *regmap_phy_pma_common_cdb;
 359         struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES];
 360         struct regmap *regmap_common_cdb;
 361         struct regmap_field *macro_id_type;
 362         struct regmap_field *phy_pll_cfg_1;
 363         struct regmap_field *pma_cmn_ready;
 364         struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
 365         struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES];
 366         struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
 367         struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
 368         struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
 369         struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
 370         int nsubnodes;
 371         u32 num_lanes;
 372         bool autoconf;
 373         struct clk_onecell_data clk_data;
 374         struct clk *output_clks[CDNS_SIERRA_OUTPUT_CLOCKS];
 375 };
 376
 377 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
 378 {
 379         struct cdns_regmap_cdb_context *ctx = context;
 380         u32 offset = reg << ctx->reg_offset_shift;
 381
 382         writew(val, ctx->base + offset);
 383
 384         return 0;
 385 }
 386
 387 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
 388 {
 389         struct cdns_regmap_cdb_context *ctx = context;
 390         u32 offset = reg << ctx->reg_offset_shift;
 391
 392         *val = readw(ctx->base + offset);
 393         return 0;
 394 }
 395
 396 #define SIERRA_LANE_CDB_REGMAP_CONF(n) \
 397 { \
 398         .name = "sierra_lane" n "_cdb", \
 399         .reg_stride = 1, \
 400         .fast_io = true, \
 401         .reg_write = cdns_regmap_write, \
 402         .reg_read = cdns_regmap_read, \
 403 }
 404
 405 static const struct regmap_config cdns_sierra_lane_cdb_config[] = {
 406         SIERRA_LANE_CDB_REGMAP_CONF("0"),
 407         SIERRA_LANE_CDB_REGMAP_CONF("1"),
 408         SIERRA_LANE_CDB_REGMAP_CONF("2"),
 409         SIERRA_LANE_CDB_REGMAP_CONF("3"),
 410         SIERRA_LANE_CDB_REGMAP_CONF("4"),
 411         SIERRA_LANE_CDB_REGMAP_CONF("5"),
 412         SIERRA_LANE_CDB_REGMAP_CONF("6"),
 413         SIERRA_LANE_CDB_REGMAP_CONF("7"),
 414         SIERRA_LANE_CDB_REGMAP_CONF("8"),
 415         SIERRA_LANE_CDB_REGMAP_CONF("9"),
 416         SIERRA_LANE_CDB_REGMAP_CONF("10"),
 417         SIERRA_LANE_CDB_REGMAP_CONF("11"),
 418         SIERRA_LANE_CDB_REGMAP_CONF("12"),
 419         SIERRA_LANE_CDB_REGMAP_CONF("13"),
 420         SIERRA_LANE_CDB_REGMAP_CONF("14"),
 421         SIERRA_LANE_CDB_REGMAP_CONF("15"),
 422 };
 423
 424 static const struct regmap_config cdns_sierra_common_cdb_config = {
 425         .name = "sierra_common_cdb",
 426         .reg_stride = 1,
 427         .fast_io = true,
 428         .reg_write = cdns_regmap_write,
 429         .reg_read = cdns_regmap_read,
 430 };
 431
 432 static const struct regmap_config cdns_sierra_phy_pcs_cmn_cdb_config = {
 433         .name = "sierra_phy_pcs_cmn_cdb",
 434         .reg_stride = 1,
 435         .fast_io = true,
 436         .reg_write = cdns_regmap_write,
 437         .reg_read = cdns_regmap_read,
 438 };
 439
 440 #define SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
 441 { \
 442         .name = "sierra_phy_pcs_lane" n "_cdb", \
 443         .reg_stride = 1, \
 444         .fast_io = true, \
 445         .reg_write = cdns_regmap_write, \
 446         .reg_read = cdns_regmap_read, \
 447 }
 448
 449 static const struct regmap_config cdns_sierra_phy_pcs_lane_cdb_config[] = {
 450         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
 451         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
 452         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
 453         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
 454         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("4"),
 455         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("5"),
 456         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("6"),
 457         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("7"),
 458         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("8"),
 459         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("9"),
 460         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("10"),
 461         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("11"),
 462         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("12"),
 463         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("13"),
 464         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("14"),
 465         SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("15"),
 466 };
 467
 468 static const struct regmap_config cdns_sierra_phy_pma_cmn_cdb_config = {
 469         .name = "sierra_phy_pma_cmn_cdb",
 470         .reg_stride = 1,
 471         .fast_io = true,
 472         .reg_write = cdns_regmap_write,
 473         .reg_read = cdns_regmap_read,
 474 };
 475
 476 #define SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF(n) \
 477 { \
 478         .name = "sierra_phy_pma_lane" n "_cdb", \
 479         .reg_stride = 1, \
 480         .fast_io = true, \
 481         .reg_write = cdns_regmap_write, \
 482         .reg_read = cdns_regmap_read, \
 483 }
 484
 485 static const struct regmap_config cdns_sierra_phy_pma_lane_cdb_config[] = {
 486         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("0"),
 487         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("1"),
 488         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("2"),
 489         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("3"),
 490         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("4"),
 491         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("5"),
 492         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("6"),
 493         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("7"),
 494         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("8"),
 495         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("9"),
 496         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("10"),
 497         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("11"),
 498         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("12"),
 499         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("13"),
 500         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("14"),
 501         SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("15"),
 502 };
 503
 504 static int cdns_sierra_phy_init(struct phy *gphy)
 505 {
 506         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 507         struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent);
 508         const struct cdns_sierra_data *init_data = phy->init_data;
 509         struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
 510         enum cdns_sierra_phy_type phy_type = ins->phy_type;
 511         enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
 512         struct cdns_sierra_vals *phy_pma_ln_vals;
 513         const struct cdns_reg_pairs *reg_pairs;
 514         struct cdns_sierra_vals *pcs_cmn_vals;
 515         struct regmap *regmap;
 516         u32 num_regs;
 517         int i, j;
 518
 519         /* Initialise the PHY registers, unless auto configured */
 520         if (phy->autoconf || phy->nsubnodes > 1)
 521                 return 0;
 522
 523         clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
 524         clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
 525
 526         /* PHY PCS common registers configurations */
 527         pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
 528         if (pcs_cmn_vals) {
 529                 reg_pairs = pcs_cmn_vals->reg_pairs;
 530                 num_regs = pcs_cmn_vals->num_regs;
 531                 regmap = phy->regmap_phy_pcs_common_cdb;
 532                 for (i = 0; i < num_regs; i++)
 533                         regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
 534         }
 535
 536         /* PHY PMA lane registers configurations */
 537         phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc];
 538         if (phy_pma_ln_vals) {
 539                 reg_pairs = phy_pma_ln_vals->reg_pairs;
 540                 num_regs = phy_pma_ln_vals->num_regs;
 541                 for (i = 0; i < ins->num_lanes; i++) {
 542                         regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane];
 543                         for (j = 0; j < num_regs; j++)
 544                                 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
 545                 }
 546         }
 547
 548         /* PMA common registers configurations */
 549         pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
 550         if (pma_cmn_vals) {
 551                 reg_pairs = pma_cmn_vals->reg_pairs;
 552                 num_regs = pma_cmn_vals->num_regs;
 553                 regmap = phy->regmap_common_cdb;
 554                 for (i = 0; i < num_regs; i++)
 555                         regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
 556         }
 557
 558         /* PMA lane registers configurations */
 559         pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];
 560         if (pma_ln_vals) {
 561                 reg_pairs = pma_ln_vals->reg_pairs;
 562                 num_regs = pma_ln_vals->num_regs;
 563                 for (i = 0; i < ins->num_lanes; i++) {
 564                         regmap = phy->regmap_lane_cdb[i + ins->mlane];
 565                         for (j = 0; j < num_regs; j++)
 566                                 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
 567                 }
 568         }
 569
 570         return 0;
 571 }
 572
 573 static int cdns_sierra_phy_on(struct phy *gphy)
 574 {
 575         struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
 576         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 577         struct device *dev = sp->dev;
 578         u32 val;
 579         int ret;
 580
 581         if (sp->nsubnodes == 1) {
 582                 /* Take the PHY out of reset */
 583                 ret = reset_control_deassert(sp->phy_rst);
 584                 if (ret) {
 585                         dev_err(dev, "Failed to take the PHY out of reset\n");
 586                         return ret;
 587                 }
 588         }
 589
 590         /* Take the PHY lane group out of reset */
 591         ret = reset_control_deassert(ins->lnk_rst);
 592         if (ret) {
 593                 dev_err(dev, "Failed to take the PHY lane out of reset\n");
 594                 return ret;
 595         }
 596
 597         if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) {
 598                 ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane],
 599                                                      val, !val, 1000, PLL_LOCK_TIME);
 600                 if (ret) {
 601                         dev_err(dev, "Timeout waiting for PHY status ready\n");
 602                         return ret;
 603                 }
 604         }
 605
 606         /*
 607          * Wait for cmn_ready assertion
 608          * PHY_PMA_CMN_CTRL[0] == 1
 609          */
 610         ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val,
 611                                              1000, PLL_LOCK_TIME);
 612         if (ret) {
 613                 dev_err(dev, "Timeout waiting for CMN ready\n");
 614                 return ret;
 615         }
 616
 617         ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
 618                                              val, val, 1000, PLL_LOCK_TIME);
 619         if (ret < 0)
 620                 dev_err(dev, "PLL lock of lane failed\n");
 621
 622         return ret;
 623 }
 624
 625 static int cdns_sierra_phy_off(struct phy *gphy)
 626 {
 627         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 628
 629         return reset_control_assert(ins->lnk_rst);
 630 }
 631
 632 static int cdns_sierra_phy_reset(struct phy *gphy)
 633 {
 634         struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
 635
 636         reset_control_assert(sp->phy_rst);
 637         reset_control_deassert(sp->phy_rst);
 638         return 0;
 639 };
 640
 641 static const struct phy_ops ops = {
 642         .init           = cdns_sierra_phy_init,
 643         .power_on       = cdns_sierra_phy_on,
 644         .power_off      = cdns_sierra_phy_off,
 645         .reset          = cdns_sierra_phy_reset,
 646         .owner          = THIS_MODULE,
 647 };
 648
 649 static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw)
 650 {
 651         struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
 652         struct regmap_field *plllc1en_field = mux->plllc1en_field;
 653         struct regmap_field *termen_field = mux->termen_field;
 654         struct regmap_field *field = mux->pfdclk_sel_preg;
 655         unsigned int val;
 656         int index;
 657
 658         regmap_field_read(field, &val);
 659
 660         if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) {
 661                 index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val);
 662                 if (index == 1) {
 663                         regmap_field_write(plllc1en_field, 1);
 664                         regmap_field_write(termen_field, 1);
 665                 }
 666         } else {
 667                 index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val);
 668         }
 669
 670         return index;
 671 }
 672
 673 static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index)
 674 {
 675         struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
 676         struct regmap_field *plllc1en_field = mux->plllc1en_field;
 677         struct regmap_field *termen_field = mux->termen_field;
 678         struct regmap_field *field = mux->pfdclk_sel_preg;
 679         int val, ret;
 680
 681         ret = regmap_field_write(plllc1en_field, 0);
 682         ret |= regmap_field_write(termen_field, 0);
 683         if (index == 1) {
 684                 ret |= regmap_field_write(plllc1en_field, 1);
 685                 ret |= regmap_field_write(termen_field, 1);
 686         }
 687
 688         if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1]))
 689                 val = cdns_sierra_pll_mux_table[CMN_PLLLC1][index];
 690         else
 691                 val = cdns_sierra_pll_mux_table[CMN_PLLLC][index];
 692
 693         ret |= regmap_field_write(field, val);
 694
 695         return ret;
 696 }
 697
 698 static const struct clk_ops cdns_sierra_pll_mux_ops = {
 699         .set_parent = cdns_sierra_pll_mux_set_parent,
 700         .get_parent = cdns_sierra_pll_mux_get_parent,
 701 };
 702
 703 static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp,
 704                                         struct regmap_field *pfdclk1_sel_field,
 705                                         struct regmap_field *plllc1en_field,
 706                                         struct regmap_field *termen_field,
 707                                         int clk_index)
 708 {
 709         struct cdns_sierra_pll_mux *mux;
 710         struct device *dev = sp->dev;
 711         struct clk_init_data *init;
 712         const char **parent_names;
 713         unsigned int num_parents;
 714         char clk_name[100];
 715         struct clk *clk;
 716         int i;
 717
 718         mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 719         if (!mux)
 720                 return -ENOMEM;
 721
 722         num_parents = SIERRA_NUM_CMN_PLLC_PARENTS;
 723         parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);
 724         if (!parent_names)
 725                 return -ENOMEM;
 726
 727         for (i = 0; i < num_parents; i++) {
 728                 clk = sp->input_clks[pll_mux_parent_index[clk_index][i]];
 729                 if (IS_ERR_OR_NULL(clk)) {
 730                         dev_err(dev, "No parent clock for PLL mux clocks\n");
 731                         return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT;
 732                 }
 733                 parent_names[i] = __clk_get_name(clk);
 734         }
 735
 736         snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]);
 737
 738         init = &mux->clk_data;
 739
 740         init->ops = &cdns_sierra_pll_mux_ops;
 741         init->flags = CLK_SET_RATE_NO_REPARENT;
 742         init->parent_names = parent_names;
 743         init->num_parents = num_parents;
 744         init->name = clk_name;
 745
 746         mux->pfdclk_sel_preg = pfdclk1_sel_field;
 747         mux->plllc1en_field = plllc1en_field;
 748         mux->termen_field = termen_field;
 749         mux->hw.init = init;
 750
 751         clk = devm_clk_register(dev, &mux->hw);
 752         if (IS_ERR(clk))
 753                 return PTR_ERR(clk);
 754
 755         sp->output_clks[clk_index] = clk;
 756
 757         return 0;
 758 }
 759
 760 static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp)
 761 {
 762         struct regmap_field *pfdclk1_sel_field;
 763         struct regmap_field *plllc1en_field;
 764         struct regmap_field *termen_field;
 765         struct device *dev = sp->dev;
 766         int ret = 0, i, clk_index;
 767
 768         clk_index = CDNS_SIERRA_PLL_CMNLC;
 769         for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) {
 770                 pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i];
 771                 plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i];
 772                 termen_field = sp->cmn_refrcv_refclk_termen_preg[i];
 773
 774                 ret = cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, plllc1en_field,
 775                                                    termen_field, clk_index);
 776                 if (ret) {
 777                         dev_err(dev, "Fail to register cmn plllc mux\n");
 778                         return ret;
 779                 }
 780         }
 781
 782         return 0;
 783 }
 784
 785 static int cdns_sierra_derived_refclk_enable(struct clk_hw *hw)
 786 {
 787         struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);
 788
 789         regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0x1);
 790
 791         /* Programming to get 100Mhz clock output in ref_der_clk_out 5GHz VCO/50 = 100MHz */
 792         regmap_field_write(derived_refclk->cmn_plllc_clk1outdiv_preg, 0x2E);
 793
 794         return 0;
 795 }
 796
 797 static void cdns_sierra_derived_refclk_disable(struct clk_hw *hw)
 798 {
 799         struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);
 800
 801         regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0);
 802 }
 803
 804 static int cdns_sierra_derived_refclk_is_enabled(struct clk_hw *hw)
 805 {
 806         struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);
 807         int val;
 808
 809         regmap_field_read(derived_refclk->cmn_plllc_clk1_en_preg, &val);
 810
 811         return !!val;
 812 }
 813
 814 static const struct clk_ops cdns_sierra_derived_refclk_ops = {
 815         .enable = cdns_sierra_derived_refclk_enable,
 816         .disable = cdns_sierra_derived_refclk_disable,
 817         .is_enabled = cdns_sierra_derived_refclk_is_enabled,
 818 };
 819
 820 static int cdns_sierra_derived_refclk_register(struct cdns_sierra_phy *sp)
 821 {
 822         struct cdns_sierra_derived_refclk *derived_refclk;
 823         struct device *dev = sp->dev;
 824         struct regmap_field *field;
 825         struct clk_init_data *init;
 826         struct regmap *regmap;
 827         char clk_name[100];
 828         struct clk *clk;
 829
 830         derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
 831         if (!derived_refclk)
 832                 return -ENOMEM;
 833
 834         snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
 835                  clk_names[CDNS_SIERRA_DERIVED_REFCLK]);
 836
 837         init = &derived_refclk->clk_data;
 838
 839         init->ops = &cdns_sierra_derived_refclk_ops;
 840         init->flags = 0;
 841         init->name = clk_name;
 842
 843         regmap = sp->regmap_common_cdb;
 844
 845         field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1outdiv_preg);
 846         if (IS_ERR(field)) {
 847                 dev_err(dev, "cmn_plllc_clk1outdiv_preg reg field init failed\n");
 848                 return PTR_ERR(field);
 849         }
 850         derived_refclk->cmn_plllc_clk1outdiv_preg = field;
 851
 852         field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1_en_preg);
 853         if (IS_ERR(field)) {
 854                 dev_err(dev, "cmn_plllc_clk1_en_preg reg field init failed\n");
 855                 return PTR_ERR(field);
 856         }
 857         derived_refclk->cmn_plllc_clk1_en_preg = field;
 858
 859         derived_refclk->hw.init = init;
 860
 861         clk = devm_clk_register(dev, &derived_refclk->hw);
 862         if (IS_ERR(clk))
 863                 return PTR_ERR(clk);
 864
 865         sp->output_clks[CDNS_SIERRA_DERIVED_REFCLK] = clk;
 866
 867         return 0;
 868 }
 869
 870 static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp)
 871 {
 872         struct device *dev = sp->dev;
 873         struct device_node *node = dev->of_node;
 874
 875         of_clk_del_provider(node);
 876 }
 877
 878 static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp)
 879 {
 880         struct device *dev = sp->dev;
 881         struct device_node *node = dev->of_node;
 882         int ret;
 883
 884         ret = cdns_sierra_phy_register_pll_mux(sp);
 885         if (ret) {
 886                 dev_err(dev, "Failed to pll mux clocks\n");
 887                 return ret;
 888         }
 889
 890         ret = cdns_sierra_derived_refclk_register(sp);
 891         if (ret) {
 892                 dev_err(dev, "Failed to register derived refclk\n");
 893                 return ret;
 894         }
 895
 896         sp->clk_data.clks = sp->output_clks;
 897         sp->clk_data.clk_num = CDNS_SIERRA_OUTPUT_CLOCKS;
 898         ret = of_clk_add_provider(node, of_clk_src_onecell_get, &sp->clk_data);
 899         if (ret)
 900                 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
 901
 902         return ret;
 903 }
 904
 905 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
 906                                     struct device_node *child)
 907 {
 908         u32 phy_type;
 909
 910         if (of_property_read_u32(child, "reg", &inst->mlane))
 911                 return -EINVAL;
 912
 913         if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
 914                 return -EINVAL;
 915
 916         if (of_property_read_u32(child, "cdns,phy-type", &phy_type))
 917                 return -EINVAL;
 918
 919         switch (phy_type) {
 920         case PHY_TYPE_PCIE:
 921                 inst->phy_type = TYPE_PCIE;
 922                 break;
 923         case PHY_TYPE_USB3:
 924                 inst->phy_type = TYPE_USB;
 925                 break;
 926         case PHY_TYPE_QSGMII:
 927                 inst->phy_type = TYPE_QSGMII;
 928                 break;
 929         default:
 930                 return -EINVAL;
 931         }
 932
 933         inst->ssc_mode = EXTERNAL_SSC;
 934         of_property_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode);
 935
 936         return 0;
 937 }
 938
 939 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
 940                                        u32 block_offset, u8 reg_offset_shift,
 941                                        const struct regmap_config *config)
 942 {
 943         struct cdns_regmap_cdb_context *ctx;
 944
 945         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 946         if (!ctx)
 947                 return ERR_PTR(-ENOMEM);
 948
 949         ctx->dev = dev;
 950         ctx->base = base + block_offset;
 951         ctx->reg_offset_shift = reg_offset_shift;
 952
 953         return devm_regmap_init(dev, NULL, ctx, config);
 954 }
 955
 956 static int cdns_regfield_init(struct cdns_sierra_phy *sp)
 957 {
 958         struct device *dev = sp->dev;
 959         struct regmap_field *field;
 960         struct reg_field reg_field;
 961         struct regmap *regmap;
 962         int i;
 963
 964         regmap = sp->regmap_common_cdb;
 965         field = devm_regmap_field_alloc(dev, regmap, macro_id_type);
 966         if (IS_ERR(field)) {
 967                 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
 968                 return PTR_ERR(field);
 969         }
 970         sp->macro_id_type = field;
 971
 972         for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) {
 973                 reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg;
 974                 field = devm_regmap_field_alloc(dev, regmap, reg_field);
 975                 if (IS_ERR(field)) {
 976                         dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i);
 977                         return PTR_ERR(field);
 978                 }
 979                 sp->cmn_plllc_pfdclk1_sel_preg[i] = field;
 980
 981                 reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field;
 982                 field = devm_regmap_field_alloc(dev, regmap, reg_field);
 983                 if (IS_ERR(field)) {
 984                         dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i);
 985                         return PTR_ERR(field);
 986                 }
 987                 sp->cmn_refrcv_refclk_plllc1en_preg[i] = field;
 988
 989                 reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field;
 990                 field = devm_regmap_field_alloc(dev, regmap, reg_field);
 991                 if (IS_ERR(field)) {
 992                         dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i);
 993                         return PTR_ERR(field);
 994                 }
 995                 sp->cmn_refrcv_refclk_termen_preg[i] = field;
 996         }
 997
 998         regmap = sp->regmap_phy_pcs_common_cdb;
 999         field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
1000         if (IS_ERR(field)) {
1001                 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
1002                 return PTR_ERR(field);
1003         }
1004         sp->phy_pll_cfg_1 = field;
1005
1006         regmap = sp->regmap_phy_pma_common_cdb;
1007         field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready);
1008         if (IS_ERR(field)) {
1009                 dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n");
1010                 return PTR_ERR(field);
1011         }
1012         sp->pma_cmn_ready = field;
1013
1014         for (i = 0; i < SIERRA_MAX_LANES; i++) {
1015                 regmap = sp->regmap_lane_cdb[i];
1016                 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
1017                 if (IS_ERR(field)) {
1018                         dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
1019                         return PTR_ERR(field);
1020                 }
1021                 sp->pllctrl_lock[i] = field;
1022         }
1023
1024         for (i = 0; i < SIERRA_MAX_LANES; i++) {
1025                 regmap = sp->regmap_phy_pcs_lane_cdb[i];
1026                 field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1);
1027                 if (IS_ERR(field)) {
1028                         dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i);
1029                         return PTR_ERR(field);
1030                 }
1031                 sp->phy_iso_link_ctrl_1[i] = field;
1032         }
1033
1034         return 0;
1035 }
1036
1037 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
1038                                    void __iomem *base, u8 block_offset_shift,
1039                                    u8 reg_offset_shift)
1040 {
1041         struct device *dev = sp->dev;
1042         struct regmap *regmap;
1043         u32 block_offset;
1044         int i;
1045
1046         for (i = 0; i < SIERRA_MAX_LANES; i++) {
1047                 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift,
1048                                                       reg_offset_shift);
1049                 regmap = cdns_regmap_init(dev, base, block_offset,
1050                                           reg_offset_shift,
1051                                           &cdns_sierra_lane_cdb_config[i]);
1052                 if (IS_ERR(regmap)) {
1053                         dev_err(dev, "Failed to init lane CDB regmap\n");
1054                         return PTR_ERR(regmap);
1055                 }
1056                 sp->regmap_lane_cdb[i] = regmap;
1057         }
1058
1059         regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,
1060                                   reg_offset_shift,
1061                                   &cdns_sierra_common_cdb_config);
1062         if (IS_ERR(regmap)) {
1063                 dev_err(dev, "Failed to init common CDB regmap\n");
1064                 return PTR_ERR(regmap);
1065         }
1066         sp->regmap_common_cdb = regmap;
1067
1068         block_offset = SIERRA_PHY_PCS_COMMON_OFFSET(block_offset_shift);
1069         regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
1070                                   &cdns_sierra_phy_pcs_cmn_cdb_config);
1071         if (IS_ERR(regmap)) {
1072                 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
1073                 return PTR_ERR(regmap);
1074         }
1075         sp->regmap_phy_pcs_common_cdb = regmap;
1076
1077         for (i = 0; i < SIERRA_MAX_LANES; i++) {
1078                 block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
1079                                                               reg_offset_shift);
1080                 regmap = cdns_regmap_init(dev, base, block_offset,
1081                                           reg_offset_shift,
1082                                           &cdns_sierra_phy_pcs_lane_cdb_config[i]);
1083                 if (IS_ERR(regmap)) {
1084                         dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
1085                         return PTR_ERR(regmap);
1086                 }
1087                 sp->regmap_phy_pcs_lane_cdb[i] = regmap;
1088         }
1089
1090         block_offset = SIERRA_PHY_PMA_COMMON_OFFSET(block_offset_shift);
1091         regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
1092                                   &cdns_sierra_phy_pma_cmn_cdb_config);
1093         if (IS_ERR(regmap)) {
1094                 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
1095                 return PTR_ERR(regmap);
1096         }
1097         sp->regmap_phy_pma_common_cdb = regmap;
1098
1099         for (i = 0; i < SIERRA_MAX_LANES; i++) {
1100                 block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, block_offset_shift,
1101                                                               reg_offset_shift);
1102                 regmap = cdns_regmap_init(dev, base, block_offset,
1103                                           reg_offset_shift,
1104                                           &cdns_sierra_phy_pma_lane_cdb_config[i]);
1105                 if (IS_ERR(regmap)) {
1106                         dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n");
1107                         return PTR_ERR(regmap);
1108                 }
1109                 sp->regmap_phy_pma_lane_cdb[i] = regmap;
1110         }
1111
1112         return 0;
1113 }
1114
1115 static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
1116                                       struct device *dev)
1117 {
1118         struct clk *clk;
1119         int ret;
1120
1121         clk = devm_clk_get_optional(dev, "phy_clk");
1122         if (IS_ERR(clk)) {
1123                 dev_err(dev, "failed to get clock phy_clk\n");
1124                 return PTR_ERR(clk);
1125         }
1126         sp->input_clks[PHY_CLK] = clk;
1127
1128         clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
1129         if (IS_ERR(clk)) {
1130                 dev_err(dev, "cmn_refclk_dig_div clock not found\n");
1131                 ret = PTR_ERR(clk);
1132                 return ret;
1133         }
1134         sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;
1135
1136         clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
1137         if (IS_ERR(clk)) {
1138                 dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
1139                 ret = PTR_ERR(clk);
1140                 return ret;
1141         }
1142         sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
1143
1144         clk = devm_clk_get_optional(dev, "pll0_refclk");
1145         if (IS_ERR(clk)) {
1146                 dev_err(dev, "pll0_refclk clock not found\n");
1147                 ret = PTR_ERR(clk);
1148                 return ret;
1149         }
1150         sp->input_clks[PLL0_REFCLK] = clk;
1151
1152         clk = devm_clk_get_optional(dev, "pll1_refclk");
1153         if (IS_ERR(clk)) {
1154                 dev_err(dev, "pll1_refclk clock not found\n");
1155                 ret = PTR_ERR(clk);
1156                 return ret;
1157         }
1158         sp->input_clks[PLL1_REFCLK] = clk;
1159
1160         return 0;
1161 }
1162
1163 static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp)
1164 {
1165         int ret;
1166
1167         ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
1168         if (ret)
1169                 return ret;
1170
1171         ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
1172         if (ret)
1173                 goto err_pll_cmnlc;
1174
1175         ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]);
1176         if (ret)
1177                 goto err_pll_cmnlc1;
1178
1179         return 0;
1180
1181 err_pll_cmnlc1:
1182         clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
1183
1184 err_pll_cmnlc:
1185         clk_disable_unprepare(sp->input_clks[PHY_CLK]);
1186
1187         return ret;
1188 }
1189
1190 static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp)
1191 {
1192         clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]);
1193         clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
1194         clk_disable_unprepare(sp->input_clks[PHY_CLK]);
1195 }
1196
1197 static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
1198                                       struct device *dev)
1199 {
1200         struct reset_control *rst;
1201
1202         rst = devm_reset_control_get_exclusive(dev, "sierra_reset");
1203         if (IS_ERR(rst)) {
1204                 dev_err(dev, "failed to get reset\n");
1205                 return PTR_ERR(rst);
1206         }
1207         sp->phy_rst = rst;
1208
1209         rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb");
1210         if (IS_ERR(rst)) {
1211                 dev_err(dev, "failed to get apb reset\n");
1212                 return PTR_ERR(rst);
1213         }
1214         sp->apb_rst = rst;
1215
1216         return 0;
1217 }
1218
1219 static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp)
1220 {
1221         const struct cdns_sierra_data *init_data = sp->init_data;
1222         struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
1223         enum cdns_sierra_phy_type phy_t1, phy_t2;
1224         struct cdns_sierra_vals *phy_pma_ln_vals;
1225         const struct cdns_reg_pairs *reg_pairs;
1226         struct cdns_sierra_vals *pcs_cmn_vals;
1227         int i, j, node, mlane, num_lanes, ret;
1228         enum cdns_sierra_ssc_mode ssc;
1229         struct regmap *regmap;
1230         u32 num_regs;
1231
1232         /* Maximum 2 links (subnodes) are supported */
1233         if (sp->nsubnodes != 2)
1234                 return -EINVAL;
1235
1236         clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
1237         clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
1238
1239         /* PHY configured to use both PLL LC and LC1 */
1240         regmap_field_write(sp->phy_pll_cfg_1, 0x1);
1241
1242         phy_t1 = sp->phys[0].phy_type;
1243         phy_t2 = sp->phys[1].phy_type;
1244
1245         /*
1246          * PHY configuration for multi-link operation is done in two steps.
1247          * e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes.
1248          * Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe
1249          * and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below.
1250          *
1251          * [1] For first step, phy_t1 = TYPE_PCIE and phy_t2 = TYPE_QSGMII
1252          *     So the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc].
1253          *     This will configure PHY registers associated for PCIe (i.e. first protocol)
1254          *     involving PLLLC registers and registers for first 2 lanes of PHY.
1255          * [2] In second step, the variables phy_t1 and phy_t2 are swapped. So now,
1256          *     phy_t1 = TYPE_QSGMII and phy_t2 = TYPE_PCIE. And the register values are selected as
1257          *     [TYPE_QSGMII][TYPE_PCIE][ssc].
1258          *     This will configure PHY registers associated for QSGMII (i.e. second protocol)
1259          *     involving PLLLC1 registers and registers for other 2 lanes of PHY.
1260          *
1261          * This completes the PHY configuration for multilink operation. This approach enables
1262          * dividing the large number of PHY register configurations into protocol specific
1263          * smaller groups.
1264          */
1265         for (node = 0; node < sp->nsubnodes; node++) {
1266                 if (node == 1) {
1267                         /*
1268                          * If first link with phy_t1 is configured, then configure the PHY for
1269                          * second link with phy_t2. Get the array values as [phy_t2][phy_t1][ssc].
1270                          */
1271                         swap(phy_t1, phy_t2);
1272                 }
1273
1274                 mlane = sp->phys[node].mlane;
1275                 ssc = sp->phys[node].ssc_mode;
1276                 num_lanes = sp->phys[node].num_lanes;
1277
1278                 /* PHY PCS common registers configurations */
1279                 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
1280                 if (pcs_cmn_vals) {
1281                         reg_pairs = pcs_cmn_vals->reg_pairs;
1282                         num_regs = pcs_cmn_vals->num_regs;
1283                         regmap = sp->regmap_phy_pcs_common_cdb;
1284                         for (i = 0; i < num_regs; i++)
1285                                 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
1286                 }
1287
1288                 /* PHY PMA lane registers configurations */
1289                 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc];
1290                 if (phy_pma_ln_vals) {
1291                         reg_pairs = phy_pma_ln_vals->reg_pairs;
1292                         num_regs = phy_pma_ln_vals->num_regs;
1293                         for (i = 0; i < num_lanes; i++) {
1294                                 regmap = sp->regmap_phy_pma_lane_cdb[i + mlane];
1295                                 for (j = 0; j < num_regs; j++)
1296                                         regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
1297                         }
1298                 }
1299
1300                 /* PMA common registers configurations */
1301                 pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc];
1302                 if (pma_cmn_vals) {
1303                         reg_pairs = pma_cmn_vals->reg_pairs;
1304                         num_regs = pma_cmn_vals->num_regs;
1305                         regmap = sp->regmap_common_cdb;
1306                         for (i = 0; i < num_regs; i++)
1307                                 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
1308                 }
1309
1310                 /* PMA lane registers configurations */
1311                 pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc];
1312                 if (pma_ln_vals) {
1313                         reg_pairs = pma_ln_vals->reg_pairs;
1314                         num_regs = pma_ln_vals->num_regs;
1315                         for (i = 0; i < num_lanes; i++) {
1316                                 regmap = sp->regmap_lane_cdb[i + mlane];
1317                                 for (j = 0; j < num_regs; j++)
1318                                         regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
1319                         }
1320                 }
1321
1322                 if (phy_t1 == TYPE_QSGMII)
1323                         reset_control_deassert(sp->phys[node].lnk_rst);
1324         }
1325
1326         /* Take the PHY out of reset */
1327         ret = reset_control_deassert(sp->phy_rst);
1328         if (ret)
1329                 return ret;
1330
1331         return 0;
1332 }
1333
1334 static int cdns_sierra_phy_probe(struct platform_device *pdev)
1335 {
1336         struct cdns_sierra_phy *sp;
1337         struct phy_provider *phy_provider;
1338         struct device *dev = &pdev->dev;
1339         const struct cdns_sierra_data *data;
1340         unsigned int id_value;
1341         int ret, node = 0;
1342         void __iomem *base;
1343         struct device_node *dn = dev->of_node, *child;
1344
1345         if (of_get_child_count(dn) == 0)
1346                 return -ENODEV;
1347
1348         /* Get init data for this PHY */
1349         data = of_device_get_match_data(dev);
1350         if (!data)
1351                 return -EINVAL;
1352
1353         sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL);
1354         if (!sp)
1355                 return -ENOMEM;
1356         dev_set_drvdata(dev, sp);
1357         sp->dev = dev;
1358         sp->init_data = data;
1359
1360         base = devm_platform_ioremap_resource(pdev, 0);
1361         if (IS_ERR(base)) {
1362                 dev_err(dev, "missing \"reg\"\n");
1363                 return PTR_ERR(base);
1364         }
1365
1366         ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift,
1367                                       data->reg_offset_shift);
1368         if (ret)
1369                 return ret;
1370
1371         ret = cdns_regfield_init(sp);
1372         if (ret)
1373                 return ret;
1374
1375         platform_set_drvdata(pdev, sp);
1376
1377         ret = cdns_sierra_phy_get_clocks(sp, dev);
1378         if (ret)
1379                 return ret;
1380
1381         ret = cdns_sierra_clk_register(sp);
1382         if (ret)
1383                 return ret;
1384
1385         ret = cdns_sierra_phy_get_resets(sp, dev);
1386         if (ret)
1387                 goto unregister_clk;
1388
1389         ret = cdns_sierra_phy_enable_clocks(sp);
1390         if (ret)
1391                 goto unregister_clk;
1392
1393         /* Enable APB */
1394         reset_control_deassert(sp->apb_rst);
1395
1396         /* Check that PHY is present */
1397         regmap_field_read(sp->macro_id_type, &id_value);
1398         if  (sp->init_data->id_value != id_value) {
1399                 ret = -EINVAL;
1400                 goto clk_disable;
1401         }
1402
1403         sp->autoconf = of_property_read_bool(dn, "cdns,autoconf");
1404
1405         for_each_available_child_of_node(dn, child) {
1406                 struct phy *gphy;
1407
1408                 if (!(of_node_name_eq(child, "phy") ||
1409                       of_node_name_eq(child, "link")))
1410                         continue;
1411
1412                 sp->phys[node].lnk_rst =
1413                         of_reset_control_array_get_exclusive(child);
1414
1415                 if (IS_ERR(sp->phys[node].lnk_rst)) {
1416                         dev_err(dev, "failed to get reset %s\n",
1417                                 child->full_name);
1418                         ret = PTR_ERR(sp->phys[node].lnk_rst);
1419                         of_node_put(child);
1420                         goto put_control;
1421                 }
1422
1423                 if (!sp->autoconf) {
1424                         ret = cdns_sierra_get_optional(&sp->phys[node], child);
1425                         if (ret) {
1426                                 dev_err(dev, "missing property in node %s\n",
1427                                         child->name);
1428                                 of_node_put(child);
1429                                 reset_control_put(sp->phys[node].lnk_rst);
1430                                 goto put_control;
1431                         }
1432                 }
1433
1434                 sp->num_lanes += sp->phys[node].num_lanes;
1435
1436                 gphy = devm_phy_create(dev, child, &ops);
1437
1438                 if (IS_ERR(gphy)) {
1439                         ret = PTR_ERR(gphy);
1440                         of_node_put(child);
1441                         reset_control_put(sp->phys[node].lnk_rst);
1442                         goto put_control;
1443                 }
1444                 sp->phys[node].phy = gphy;
1445                 phy_set_drvdata(gphy, &sp->phys[node]);
1446
1447                 node++;
1448         }
1449         sp->nsubnodes = node;
1450
1451         if (sp->num_lanes > SIERRA_MAX_LANES) {
1452                 ret = -EINVAL;
1453                 dev_err(dev, "Invalid lane configuration\n");
1454                 goto put_control;
1455         }
1456
1457         /* If more than one subnode, configure the PHY as multilink */
1458         if (!sp->autoconf && sp->nsubnodes > 1) {
1459                 ret = cdns_sierra_phy_configure_multilink(sp);
1460                 if (ret)
1461                         goto put_control;
1462         }
1463
1464         pm_runtime_enable(dev);
1465         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1466         if (IS_ERR(phy_provider)) {
1467                 ret = PTR_ERR(phy_provider);
1468                 goto put_control;
1469         }
1470
1471         return 0;
1472
1473 put_control:
1474         while (--node >= 0)
1475                 reset_control_put(sp->phys[node].lnk_rst);
1476 clk_disable:
1477         cdns_sierra_phy_disable_clocks(sp);
1478         reset_control_assert(sp->apb_rst);
1479 unregister_clk:
1480         cdns_sierra_clk_unregister(sp);
1481         return ret;
1482 }
1483
1484 static int cdns_sierra_phy_remove(struct platform_device *pdev)
1485 {
1486         struct cdns_sierra_phy *phy = platform_get_drvdata(pdev);
1487         int i;
1488
1489         reset_control_assert(phy->phy_rst);
1490         reset_control_assert(phy->apb_rst);
1491         pm_runtime_disable(&pdev->dev);
1492
1493         cdns_sierra_phy_disable_clocks(phy);
1494         /*
1495          * The device level resets will be put automatically.
1496          * Need to put the subnode resets here though.
1497          */
1498         for (i = 0; i < phy->nsubnodes; i++) {
1499                 reset_control_assert(phy->phys[i].lnk_rst);
1500                 reset_control_put(phy->phys[i].lnk_rst);
1501         }
1502
1503         cdns_sierra_clk_unregister(phy);
1504
1505         return 0;
1506 }
1507
1508 /* QSGMII PHY PMA lane configuration */
1509 static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {
1510         {0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
1511 };
1512
1513 static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = {
1514         .reg_pairs = qsgmii_phy_pma_ln_regs,
1515         .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs),
1516 };
1517
1518 /* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */
1519 static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = {
1520         {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
1521         {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
1522         {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
1523 };
1524
1525 static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = {
1526         {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1527         {0x0252, SIERRA_DET_STANDEC_E_PREG},
1528         {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1529         {0x0FFE, SIERRA_PSC_RX_A0_PREG},
1530         {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG},
1531         {0x0001, SIERRA_PLLCTRL_GEN_A_PREG},
1532         {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
1533         {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
1534         {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1535         {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
1536         {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG},
1537         {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
1538         {0x8422, SIERRA_CTLELUT_CTRL_PREG},
1539         {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG},
1540         {0x4111, SIERRA_DFE_SMP_RATESEL_PREG},
1541         {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
1542         {0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG},
1543         {0x0186, SIERRA_DEQ_GLUT0},
1544         {0x0186, SIERRA_DEQ_GLUT1},
1545         {0x0186, SIERRA_DEQ_GLUT2},
1546         {0x0186, SIERRA_DEQ_GLUT3},
1547         {0x0186, SIERRA_DEQ_GLUT4},
1548         {0x0861, SIERRA_DEQ_ALUT0},
1549         {0x07E0, SIERRA_DEQ_ALUT1},
1550         {0x079E, SIERRA_DEQ_ALUT2},
1551         {0x071D, SIERRA_DEQ_ALUT3},
1552         {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
1553         {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
1554         {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1555         {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
1556         {0x0033, SIERRA_DEQ_PICTRL_PREG},
1557         {0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
1558         {0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG},
1559         {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
1560         {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
1561         {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
1562 };
1563
1564 static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = {
1565         .reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs,
1566         .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs),
1567 };
1568
1569 static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = {
1570         .reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs,
1571         .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs),
1572 };
1573
1574 /* PCIE PHY PCS common configuration */
1575 static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {
1576         {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
1577 };
1578
1579 static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
1580         .reg_pairs = pcie_phy_pcs_cmn_regs,
1581         .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
1582 };
1583
1584 /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */
1585 static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = {
1586         {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1587         {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1588         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1589         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
1590 };
1591
1592 /*
1593  * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc,
1594  * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
1595  */
1596 static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = {
1597         {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1598         {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1599         {0x0004, SIERRA_PSC_LN_A3_PREG},
1600         {0x0004, SIERRA_PSC_LN_A4_PREG},
1601         {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1602         {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1603         {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1604         {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1605         {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1606         {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1607         {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1608         {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1609         {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1610         {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1611         {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1612         {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1613         {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1614         {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1615         {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1616         {0x0041, SIERRA_DEQ_GLUT0},
1617         {0x0082, SIERRA_DEQ_GLUT1},
1618         {0x00C3, SIERRA_DEQ_GLUT2},
1619         {0x0145, SIERRA_DEQ_GLUT3},
1620         {0x0186, SIERRA_DEQ_GLUT4},
1621         {0x09E7, SIERRA_DEQ_ALUT0},
1622         {0x09A6, SIERRA_DEQ_ALUT1},
1623         {0x0965, SIERRA_DEQ_ALUT2},
1624         {0x08E3, SIERRA_DEQ_ALUT3},
1625         {0x00FA, SIERRA_DEQ_DFETAP0},
1626         {0x00FA, SIERRA_DEQ_DFETAP1},
1627         {0x00FA, SIERRA_DEQ_DFETAP2},
1628         {0x00FA, SIERRA_DEQ_DFETAP3},
1629         {0x00FA, SIERRA_DEQ_DFETAP4},
1630         {0x000F, SIERRA_DEQ_PRECUR_PREG},
1631         {0x0280, SIERRA_DEQ_POSTCUR_PREG},
1632         {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1633         {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1634         {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1635         {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1636         {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1637         {0x002B, SIERRA_CPI_TRIM_PREG},
1638         {0x0003, SIERRA_EPI_CTRL_PREG},
1639         {0x803F, SIERRA_SDFILT_H2L_A_PREG},
1640         {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1641         {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1642         {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
1643 };
1644
1645 static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = {
1646         .reg_pairs = pcie_100_no_ssc_plllc_cmn_regs,
1647         .num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs),
1648 };
1649
1650 static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = {
1651         .reg_pairs = ml_pcie_100_no_ssc_ln_regs,
1652         .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs),
1653 };
1654
1655 /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */
1656 static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = {
1657         {0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
1658         {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1659         {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1660         {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1661         {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
1662         {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
1663         {0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
1664         {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
1665         {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
1666         {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
1667         {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
1668 };
1669
1670 /*
1671  * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc,
1672  * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
1673  */
1674 static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = {
1675         {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1676         {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1677         {0x0004, SIERRA_PSC_LN_A3_PREG},
1678         {0x0004, SIERRA_PSC_LN_A4_PREG},
1679         {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1680         {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1681         {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1682         {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1683         {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1684         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1685         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1686         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1687         {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1688         {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1689         {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1690         {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1691         {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1692         {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1693         {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1694         {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1695         {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1696         {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1697         {0x0041, SIERRA_DEQ_GLUT0},
1698         {0x0082, SIERRA_DEQ_GLUT1},
1699         {0x00C3, SIERRA_DEQ_GLUT2},
1700         {0x0145, SIERRA_DEQ_GLUT3},
1701         {0x0186, SIERRA_DEQ_GLUT4},
1702         {0x09E7, SIERRA_DEQ_ALUT0},
1703         {0x09A6, SIERRA_DEQ_ALUT1},
1704         {0x0965, SIERRA_DEQ_ALUT2},
1705         {0x08E3, SIERRA_DEQ_ALUT3},
1706         {0x00FA, SIERRA_DEQ_DFETAP0},
1707         {0x00FA, SIERRA_DEQ_DFETAP1},
1708         {0x00FA, SIERRA_DEQ_DFETAP2},
1709         {0x00FA, SIERRA_DEQ_DFETAP3},
1710         {0x00FA, SIERRA_DEQ_DFETAP4},
1711         {0x000F, SIERRA_DEQ_PRECUR_PREG},
1712         {0x0280, SIERRA_DEQ_POSTCUR_PREG},
1713         {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1714         {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1715         {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1716         {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1717         {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1718         {0x002B, SIERRA_CPI_TRIM_PREG},
1719         {0x0003, SIERRA_EPI_CTRL_PREG},
1720         {0x803F, SIERRA_SDFILT_H2L_A_PREG},
1721         {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1722         {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1723         {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
1724 };
1725
1726 static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = {
1727         .reg_pairs = pcie_100_int_ssc_plllc_cmn_regs,
1728         .num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs),
1729 };
1730
1731 static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = {
1732         .reg_pairs = ml_pcie_100_int_ssc_ln_regs,
1733         .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs),
1734 };
1735
1736 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */
1737 static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = {
1738         {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1739         {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1740         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1741         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
1742         {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
1743 };
1744
1745 /*
1746  * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc,
1747  * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
1748  */
1749 static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = {
1750         {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1751         {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1752         {0x0004, SIERRA_PSC_LN_A3_PREG},
1753         {0x0004, SIERRA_PSC_LN_A4_PREG},
1754         {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1755         {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1756         {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1757         {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1758         {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1759         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1760         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1761         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1762         {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1763         {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1764         {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1765         {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1766         {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1767         {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1768         {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1769         {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1770         {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1771         {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1772         {0x0041, SIERRA_DEQ_GLUT0},
1773         {0x0082, SIERRA_DEQ_GLUT1},
1774         {0x00C3, SIERRA_DEQ_GLUT2},
1775         {0x0145, SIERRA_DEQ_GLUT3},
1776         {0x0186, SIERRA_DEQ_GLUT4},
1777         {0x09E7, SIERRA_DEQ_ALUT0},
1778         {0x09A6, SIERRA_DEQ_ALUT1},
1779         {0x0965, SIERRA_DEQ_ALUT2},
1780         {0x08E3, SIERRA_DEQ_ALUT3},
1781         {0x00FA, SIERRA_DEQ_DFETAP0},
1782         {0x00FA, SIERRA_DEQ_DFETAP1},
1783         {0x00FA, SIERRA_DEQ_DFETAP2},
1784         {0x00FA, SIERRA_DEQ_DFETAP3},
1785         {0x00FA, SIERRA_DEQ_DFETAP4},
1786         {0x000F, SIERRA_DEQ_PRECUR_PREG},
1787         {0x0280, SIERRA_DEQ_POSTCUR_PREG},
1788         {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1789         {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1790         {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1791         {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1792         {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1793         {0x002B, SIERRA_CPI_TRIM_PREG},
1794         {0x0003, SIERRA_EPI_CTRL_PREG},
1795         {0x803F, SIERRA_SDFILT_H2L_A_PREG},
1796         {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1797         {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1798         {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
1799 };
1800
1801 static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = {
1802         .reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs,
1803         .num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs),
1804 };
1805
1806 static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = {
1807         .reg_pairs = ml_pcie_100_ext_ssc_ln_regs,
1808         .num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs),
1809 };
1810
1811 /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */
1812 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = {
1813         {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1814         {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1815         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1816         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
1817 };
1818
1819 /* refclk100MHz_32b_PCIe_ln_no_ssc */
1820 static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = {
1821         {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1822         {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1823         {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1824         {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1825         {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1826         {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1827         {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1828         {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1829         {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1830         {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1831         {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1832         {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1833         {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1834         {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1835         {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1836         {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1837         {0x0041, SIERRA_DEQ_GLUT0},
1838         {0x0082, SIERRA_DEQ_GLUT1},
1839         {0x00C3, SIERRA_DEQ_GLUT2},
1840         {0x0145, SIERRA_DEQ_GLUT3},
1841         {0x0186, SIERRA_DEQ_GLUT4},
1842         {0x09E7, SIERRA_DEQ_ALUT0},
1843         {0x09A6, SIERRA_DEQ_ALUT1},
1844         {0x0965, SIERRA_DEQ_ALUT2},
1845         {0x08E3, SIERRA_DEQ_ALUT3},
1846         {0x00FA, SIERRA_DEQ_DFETAP0},
1847         {0x00FA, SIERRA_DEQ_DFETAP1},
1848         {0x00FA, SIERRA_DEQ_DFETAP2},
1849         {0x00FA, SIERRA_DEQ_DFETAP3},
1850         {0x00FA, SIERRA_DEQ_DFETAP4},
1851         {0x000F, SIERRA_DEQ_PRECUR_PREG},
1852         {0x0280, SIERRA_DEQ_POSTCUR_PREG},
1853         {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1854         {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1855         {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1856         {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1857         {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1858         {0x002B, SIERRA_CPI_TRIM_PREG},
1859         {0x0003, SIERRA_EPI_CTRL_PREG},
1860         {0x803F, SIERRA_SDFILT_H2L_A_PREG},
1861         {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1862         {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1863         {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
1864 };
1865
1866 static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = {
1867         .reg_pairs = cdns_pcie_cmn_regs_no_ssc,
1868         .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc),
1869 };
1870
1871 static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = {
1872         .reg_pairs = cdns_pcie_ln_regs_no_ssc,
1873         .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc),
1874 };
1875
1876 /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */
1877 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = {
1878         {0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
1879         {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1880         {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1881         {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1882         {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
1883         {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
1884         {0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
1885         {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
1886         {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
1887         {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
1888         {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
1889 };
1890
1891 /* refclk100MHz_32b_PCIe_ln_int_ssc */
1892 static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = {
1893         {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1894         {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1895         {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1896         {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1897         {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1898         {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1899         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1900         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1901         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1902         {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1903         {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1904         {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1905         {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1906         {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1907         {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1908         {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1909         {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1910         {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1911         {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1912         {0x0041, SIERRA_DEQ_GLUT0},
1913         {0x0082, SIERRA_DEQ_GLUT1},
1914         {0x00C3, SIERRA_DEQ_GLUT2},
1915         {0x0145, SIERRA_DEQ_GLUT3},
1916         {0x0186, SIERRA_DEQ_GLUT4},
1917         {0x09E7, SIERRA_DEQ_ALUT0},
1918         {0x09A6, SIERRA_DEQ_ALUT1},
1919         {0x0965, SIERRA_DEQ_ALUT2},
1920         {0x08E3, SIERRA_DEQ_ALUT3},
1921         {0x00FA, SIERRA_DEQ_DFETAP0},
1922         {0x00FA, SIERRA_DEQ_DFETAP1},
1923         {0x00FA, SIERRA_DEQ_DFETAP2},
1924         {0x00FA, SIERRA_DEQ_DFETAP3},
1925         {0x00FA, SIERRA_DEQ_DFETAP4},
1926         {0x000F, SIERRA_DEQ_PRECUR_PREG},
1927         {0x0280, SIERRA_DEQ_POSTCUR_PREG},
1928         {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1929         {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1930         {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1931         {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1932         {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
1933         {0x002B, SIERRA_CPI_TRIM_PREG},
1934         {0x0003, SIERRA_EPI_CTRL_PREG},
1935         {0x803F, SIERRA_SDFILT_H2L_A_PREG},
1936         {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1937         {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1938         {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
1939 };
1940
1941 static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = {
1942         .reg_pairs = cdns_pcie_cmn_regs_int_ssc,
1943         .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc),
1944 };
1945
1946 static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = {
1947         .reg_pairs = cdns_pcie_ln_regs_int_ssc,
1948         .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc),
1949 };
1950
1951 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
1952 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
1953         {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1954         {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1955         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1956         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
1957         {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
1958 };
1959
1960 /* refclk100MHz_32b_PCIe_ln_ext_ssc */
1961 static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
1962         {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1963         {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1964         {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1965         {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1966         {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1967         {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1968         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1969         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1970         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1971         {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1972         {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1973         {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1974         {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1975         {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1976         {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1977         {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1978         {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1979         {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1980         {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1981         {0x0041, SIERRA_DEQ_GLUT0},
1982         {0x0082, SIERRA_DEQ_GLUT1},
1983         {0x00C3, SIERRA_DEQ_GLUT2},
1984         {0x0145, SIERRA_DEQ_GLUT3},
1985         {0x0186, SIERRA_DEQ_GLUT4},
1986         {0x09E7, SIERRA_DEQ_ALUT0},
1987         {0x09A6, SIERRA_DEQ_ALUT1},
1988         {0x0965, SIERRA_DEQ_ALUT2},
1989         {0x08E3, SIERRA_DEQ_ALUT3},
1990         {0x00FA, SIERRA_DEQ_DFETAP0},
1991         {0x00FA, SIERRA_DEQ_DFETAP1},
1992         {0x00FA, SIERRA_DEQ_DFETAP2},
1993         {0x00FA, SIERRA_DEQ_DFETAP3},
1994         {0x00FA, SIERRA_DEQ_DFETAP4},
1995         {0x000F, SIERRA_DEQ_PRECUR_PREG},
1996         {0x0280, SIERRA_DEQ_POSTCUR_PREG},
1997         {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1998         {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1999         {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2000         {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2001         {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2002         {0x002B, SIERRA_CPI_TRIM_PREG},
2003         {0x0003, SIERRA_EPI_CTRL_PREG},
2004         {0x803F, SIERRA_SDFILT_H2L_A_PREG},
2005         {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
2006         {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2007         {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
2008 };
2009
2010 static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {
2011         .reg_pairs = cdns_pcie_cmn_regs_ext_ssc,
2012         .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
2013 };
2014
2015 static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = {
2016         .reg_pairs = cdns_pcie_ln_regs_ext_ssc,
2017         .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
2018 };
2019
2020 /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
2021 static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
2022         {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
2023         {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2024         {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
2025         {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
2026 };
2027
2028 /* refclk100MHz_20b_USB_ln_ext_ssc */
2029 static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
2030         {0xFE0A, SIERRA_DET_STANDEC_A_PREG},
2031         {0x000F, SIERRA_DET_STANDEC_B_PREG},
2032         {0x55A5, SIERRA_DET_STANDEC_C_PREG},
2033         {0x69ad, SIERRA_DET_STANDEC_D_PREG},
2034         {0x0241, SIERRA_DET_STANDEC_E_PREG},
2035         {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
2036         {0x0014, SIERRA_PSM_A0IN_TMR_PREG},
2037         {0xCF00, SIERRA_PSM_DIAG_PREG},
2038         {0x001F, SIERRA_PSC_TX_A0_PREG},
2039         {0x0007, SIERRA_PSC_TX_A1_PREG},
2040         {0x0003, SIERRA_PSC_TX_A2_PREG},
2041         {0x0003, SIERRA_PSC_TX_A3_PREG},
2042         {0x0FFF, SIERRA_PSC_RX_A0_PREG},
2043         {0x0003, SIERRA_PSC_RX_A1_PREG},
2044         {0x0003, SIERRA_PSC_RX_A2_PREG},
2045         {0x0001, SIERRA_PSC_RX_A3_PREG},
2046         {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
2047         {0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
2048         {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
2049         {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
2050         {0x2512, SIERRA_DFE_BIASTRIM_PREG},
2051         {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
2052         {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
2053         {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
2054         {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2055         {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
2056         {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
2057         {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
2058         {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
2059         {0x0000, SIERRA_CREQ_SPARE_PREG},
2060         {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
2061         {0x8452, SIERRA_CTLELUT_CTRL_PREG},
2062         {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
2063         {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
2064         {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
2065         {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
2066         {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2067         {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
2068         {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
2069         {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
2070         {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
2071         {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
2072         {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
2073         {0x0014, SIERRA_DEQ_GLUT0},
2074         {0x0014, SIERRA_DEQ_GLUT1},
2075         {0x0014, SIERRA_DEQ_GLUT2},
2076         {0x0014, SIERRA_DEQ_GLUT3},
2077         {0x0014, SIERRA_DEQ_GLUT4},
2078         {0x0014, SIERRA_DEQ_GLUT5},
2079         {0x0014, SIERRA_DEQ_GLUT6},
2080         {0x0014, SIERRA_DEQ_GLUT7},
2081         {0x0014, SIERRA_DEQ_GLUT8},
2082         {0x0014, SIERRA_DEQ_GLUT9},
2083         {0x0014, SIERRA_DEQ_GLUT10},
2084         {0x0014, SIERRA_DEQ_GLUT11},
2085         {0x0014, SIERRA_DEQ_GLUT12},
2086         {0x0014, SIERRA_DEQ_GLUT13},
2087         {0x0014, SIERRA_DEQ_GLUT14},
2088         {0x0014, SIERRA_DEQ_GLUT15},
2089         {0x0014, SIERRA_DEQ_GLUT16},
2090         {0x0BAE, SIERRA_DEQ_ALUT0},
2091         {0x0AEB, SIERRA_DEQ_ALUT1},
2092         {0x0A28, SIERRA_DEQ_ALUT2},
2093         {0x0965, SIERRA_DEQ_ALUT3},
2094         {0x08A2, SIERRA_DEQ_ALUT4},
2095         {0x07DF, SIERRA_DEQ_ALUT5},
2096         {0x071C, SIERRA_DEQ_ALUT6},
2097         {0x0659, SIERRA_DEQ_ALUT7},
2098         {0x0596, SIERRA_DEQ_ALUT8},
2099         {0x0514, SIERRA_DEQ_ALUT9},
2100         {0x0492, SIERRA_DEQ_ALUT10},
2101         {0x0410, SIERRA_DEQ_ALUT11},
2102         {0x038E, SIERRA_DEQ_ALUT12},
2103         {0x030C, SIERRA_DEQ_ALUT13},
2104         {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
2105         {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
2106         {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
2107         {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2108         {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
2109         {0x0033, SIERRA_DEQ_PICTRL_PREG},
2110         {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},
2111         {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
2112         {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
2113         {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
2114         {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
2115         {0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
2116         {0x000F, SIERRA_LFPSFILT_NS_PREG},
2117         {0x0009, SIERRA_LFPSFILT_RD_PREG},
2118         {0x0001, SIERRA_LFPSFILT_MP_PREG},
2119         {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
2120         {0x8013, SIERRA_SDFILT_H2L_A_PREG},
2121         {0x8009, SIERRA_SDFILT_L2H_PREG},
2122         {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
2123         {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2124         {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
2125 };
2126
2127 static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = {
2128         .reg_pairs = cdns_usb_cmn_regs_ext_ssc,
2129         .num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
2130 };
2131
2132 static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = {
2133         .reg_pairs = cdns_usb_ln_regs_ext_ssc,
2134         .num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
2135 };
2136
2137 static const struct cdns_sierra_data cdns_map_sierra = {
2138         .id_value = SIERRA_MACRO_ID,
2139         .block_offset_shift = 0x2,
2140         .reg_offset_shift = 0x2,
2141         .pcs_cmn_vals = {
2142                 [TYPE_PCIE] = {
2143                         [TYPE_NONE] = {
2144                                 [NO_SSC] = &pcie_phy_pcs_cmn_vals,
2145                                 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2146                                 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2147                         },
2148                         [TYPE_QSGMII] = {
2149                                 [NO_SSC] = &pcie_phy_pcs_cmn_vals,
2150                                 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2151                                 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2152                         },
2153                 },
2154         },
2155         .pma_cmn_vals = {
2156                 [TYPE_PCIE] = {
2157                         [TYPE_NONE] = {
2158                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
2159                                 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
2160                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2161                         },
2162                         [TYPE_QSGMII] = {
2163                                 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2164                                 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2165                                 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2166                         },
2167                 },
2168                 [TYPE_USB] = {
2169                         [TYPE_NONE] = {
2170                                 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
2171                         },
2172                 },
2173                 [TYPE_QSGMII] = {
2174                         [TYPE_PCIE] = {
2175                                 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2176                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2177                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2178                         },
2179                 },
2180         },
2181         .pma_ln_vals = {
2182                 [TYPE_PCIE] = {
2183                         [TYPE_NONE] = {
2184                                 [NO_SSC] = &pcie_100_no_ssc_ln_vals,
2185                                 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
2186                                 [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
2187                         },
2188                         [TYPE_QSGMII] = {
2189                                 [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
2190                                 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
2191                                 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
2192                         },
2193                 },
2194                 [TYPE_USB] = {
2195                         [TYPE_NONE] = {
2196                                 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
2197                         },
2198                 },
2199                 [TYPE_QSGMII] = {
2200                         [TYPE_PCIE] = {
2201                                 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2202                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2203                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2204                         },
2205                 },
2206         },
2207 };
2208
2209 static const struct cdns_sierra_data cdns_ti_map_sierra = {
2210         .id_value = SIERRA_MACRO_ID,
2211         .block_offset_shift = 0x0,
2212         .reg_offset_shift = 0x1,
2213         .pcs_cmn_vals = {
2214                 [TYPE_PCIE] = {
2215                         [TYPE_NONE] = {
2216                                 [NO_SSC] = &pcie_phy_pcs_cmn_vals,
2217                                 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2218                                 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2219                         },
2220                         [TYPE_QSGMII] = {
2221                                 [NO_SSC] = &pcie_phy_pcs_cmn_vals,
2222                                 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2223                                 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2224                         },
2225                 },
2226         },
2227         .phy_pma_ln_vals = {
2228                 [TYPE_QSGMII] = {
2229                         [TYPE_PCIE] = {
2230                                 [NO_SSC] = &qsgmii_phy_pma_ln_vals,
2231                                 [EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,
2232                                 [INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,
2233                         },
2234                 },
2235         },
2236         .pma_cmn_vals = {
2237                 [TYPE_PCIE] = {
2238                         [TYPE_NONE] = {
2239                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
2240                                 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
2241                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2242                         },
2243                         [TYPE_QSGMII] = {
2244                                 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2245                                 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2246                                 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2247                         },
2248                 },
2249                 [TYPE_USB] = {
2250                         [TYPE_NONE] = {
2251                                 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
2252                         },
2253                 },
2254                 [TYPE_QSGMII] = {
2255                         [TYPE_PCIE] = {
2256                                 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2257                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2258                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
2259                         },
2260                 },
2261         },
2262         .pma_ln_vals = {
2263                 [TYPE_PCIE] = {
2264                         [TYPE_NONE] = {
2265                                 [NO_SSC] = &pcie_100_no_ssc_ln_vals,
2266                                 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
2267                                 [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
2268                         },
2269                         [TYPE_QSGMII] = {
2270                                 [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
2271                                 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
2272                                 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
2273                         },
2274                 },
2275                 [TYPE_USB] = {
2276                         [TYPE_NONE] = {
2277                                 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
2278                         },
2279                 },
2280                 [TYPE_QSGMII] = {
2281                         [TYPE_PCIE] = {
2282                                 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2283                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2284                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
2285                         },
2286                 },
2287         },
2288 };
2289
2290 static const struct of_device_id cdns_sierra_id_table[] = {
2291         {
2292                 .compatible = "cdns,sierra-phy-t0",
2293                 .data = &cdns_map_sierra,
2294         },
2295         {
2296                 .compatible = "ti,sierra-phy-t0",
2297                 .data = &cdns_ti_map_sierra,
2298         },
2299         {}
2300 };
2301 MODULE_DEVICE_TABLE(of, cdns_sierra_id_table);
2302
2303 static struct platform_driver cdns_sierra_driver = {
2304         .probe          = cdns_sierra_phy_probe,
2305         .remove         = cdns_sierra_phy_remove,
2306         .driver         = {
2307                 .name   = "cdns-sierra-phy",
2308                 .of_match_table = cdns_sierra_id_table,
2309         },
2310 };
2311 module_platform_driver(cdns_sierra_driver);
2312
2313 MODULE_ALIAS("platform:cdns_sierra");
2314 MODULE_AUTHOR("Cadence Design Systems");
2315 MODULE_DESCRIPTION("CDNS sierra phy driver");
2316 MODULE_LICENSE("GPL v2");