drivers/perf/arm_smmuv3_pmu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * This driver adds support for perf events to use the Performance
   5  * Monitor Counter Groups (PMCG) associated with an SMMUv3 node
   6  * to monitor that node.
   7  *
   8  * SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where
   9  * <phys_addr_page> is the physical page address of the SMMU PMCG wrapped
  10  * to 4K boundary. For example, the PMCG at 0xff88840000 is named
  11  * smmuv3_pmcg_ff88840
  12  *
  13  * Filtering by stream id is done by specifying filtering parameters
  14  * with the event. options are:
  15  *   filter_enable    - 0 = no filtering, 1 = filtering enabled
  16  *   filter_span      - 0 = exact match, 1 = pattern match
  17  *   filter_stream_id - pattern to filter against
  18  *
  19  * To match a partial StreamID where the X most-significant bits must match
  20  * but the Y least-significant bits might differ, STREAMID is programmed
  21  * with a value that contains:
  22  *  STREAMID[Y - 1] == 0.
  23  *  STREAMID[Y - 2:0] == 1 (where Y > 1).
  24  * The remainder of implemented bits of STREAMID (X bits, from bit Y upwards)
  25  * contain a value to match from the corresponding bits of event StreamID.
  26  *
  27  * Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
  28  *                    filter_span=1,filter_stream_id=0x42/ -a netperf
  29  * Applies filter pattern 0x42 to transaction events, which means events
  30  * matching stream ids 0x42 and 0x43 are counted. Further filtering
  31  * information is available in the SMMU documentation.
  32  *
  33  * SMMU events are not attributable to a CPU, so task mode and sampling
  34  * are not supported.
  35  */
  36
  37 #include <linux/acpi.h>
  38 #include <linux/acpi_iort.h>
  39 #include <linux/bitfield.h>
  40 #include <linux/bitops.h>
  41 #include <linux/cpuhotplug.h>
  42 #include <linux/cpumask.h>
  43 #include <linux/device.h>
  44 #include <linux/errno.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/irq.h>
  47 #include <linux/kernel.h>
  48 #include <linux/list.h>
  49 #include <linux/msi.h>
  50 #include <linux/perf_event.h>
  51 #include <linux/platform_device.h>
  52 #include <linux/smp.h>
  53 #include <linux/sysfs.h>
  54 #include <linux/types.h>
  55
  56 #define SMMU_PMCG_EVCNTR0               0x0
  57 #define SMMU_PMCG_EVCNTR(n, stride)     (SMMU_PMCG_EVCNTR0 + (n) * (stride))
  58 #define SMMU_PMCG_EVTYPER0              0x400
  59 #define SMMU_PMCG_EVTYPER(n)            (SMMU_PMCG_EVTYPER0 + (n) * 4)
  60 #define SMMU_PMCG_SID_SPAN_SHIFT        29
  61 #define SMMU_PMCG_SMR0                  0xA00
  62 #define SMMU_PMCG_SMR(n)                (SMMU_PMCG_SMR0 + (n) * 4)
  63 #define SMMU_PMCG_CNTENSET0             0xC00
  64 #define SMMU_PMCG_CNTENCLR0             0xC20
  65 #define SMMU_PMCG_INTENSET0             0xC40
  66 #define SMMU_PMCG_INTENCLR0             0xC60
  67 #define SMMU_PMCG_OVSCLR0               0xC80
  68 #define SMMU_PMCG_OVSSET0               0xCC0
  69 #define SMMU_PMCG_CFGR                  0xE00
  70 #define SMMU_PMCG_CFGR_SID_FILTER_TYPE  BIT(23)
  71 #define SMMU_PMCG_CFGR_MSI              BIT(21)
  72 #define SMMU_PMCG_CFGR_RELOC_CTRS       BIT(20)
  73 #define SMMU_PMCG_CFGR_SIZE             GENMASK(13, 8)
  74 #define SMMU_PMCG_CFGR_NCTR             GENMASK(5, 0)
  75 #define SMMU_PMCG_CR                    0xE04
  76 #define SMMU_PMCG_CR_ENABLE             BIT(0)
  77 #define SMMU_PMCG_IIDR                  0xE08
  78 #define SMMU_PMCG_CEID0                 0xE20
  79 #define SMMU_PMCG_CEID1                 0xE28
  80 #define SMMU_PMCG_IRQ_CTRL              0xE50
  81 #define SMMU_PMCG_IRQ_CTRL_IRQEN        BIT(0)
  82 #define SMMU_PMCG_IRQ_CFG0              0xE58
  83 #define SMMU_PMCG_IRQ_CFG1              0xE60
  84 #define SMMU_PMCG_IRQ_CFG2              0xE64
  85
  86 /* MSI config fields */
  87 #define MSI_CFG0_ADDR_MASK              GENMASK_ULL(51, 2)
  88 #define MSI_CFG2_MEMATTR_DEVICE_nGnRE   0x1
  89
  90 #define SMMU_PMCG_DEFAULT_FILTER_SPAN   1
  91 #define SMMU_PMCG_DEFAULT_FILTER_SID    GENMASK(31, 0)
  92
  93 #define SMMU_PMCG_MAX_COUNTERS          64
  94 #define SMMU_PMCG_ARCH_MAX_EVENTS       128
  95
  96 #define SMMU_PMCG_PA_SHIFT              12
  97
  98 #define SMMU_PMCG_EVCNTR_RDONLY         BIT(0)
  99
 100 static int cpuhp_state_num;
 101
 102 struct smmu_pmu {
 103         struct hlist_node node;
 104         struct perf_event *events[SMMU_PMCG_MAX_COUNTERS];
 105         DECLARE_BITMAP(used_counters, SMMU_PMCG_MAX_COUNTERS);
 106         DECLARE_BITMAP(supported_events, SMMU_PMCG_ARCH_MAX_EVENTS);
 107         unsigned int irq;
 108         unsigned int on_cpu;
 109         struct pmu pmu;
 110         unsigned int num_counters;
 111         struct device *dev;
 112         void __iomem *reg_base;
 113         void __iomem *reloc_base;
 114         u64 counter_mask;
 115         u32 options;
 116         u32 iidr;
 117         bool global_filter;
 118 };
 119
 120 #define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu))
 121
 122 #define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, _end)        \
 123         static inline u32 get_##_name(struct perf_event *event)            \
 124         {                                                                  \
 125                 return FIELD_GET(GENMASK_ULL(_end, _start),                \
 126                                  event->attr._config);                     \
 127         }                                                                  \
 128
 129 SMMU_PMU_EVENT_ATTR_EXTRACTOR(event, config, 0, 15);
 130 SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_stream_id, config1, 0, 31);
 131 SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_span, config1, 32, 32);
 132 SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_enable, config1, 33, 33);
 133
 134 static inline void smmu_pmu_enable(struct pmu *pmu)
 135 {
 136         struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
 137
 138         writel(SMMU_PMCG_IRQ_CTRL_IRQEN,
 139                smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
 140         writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
 141 }
 142
 143 static inline void smmu_pmu_disable(struct pmu *pmu)
 144 {
 145         struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
 146
 147         writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
 148         writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
 149 }
 150
 151 static inline void smmu_pmu_counter_set_value(struct smmu_pmu *smmu_pmu,
 152                                               u32 idx, u64 value)
 153 {
 154         if (smmu_pmu->counter_mask & BIT(32))
 155                 writeq(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
 156         else
 157                 writel(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
 158 }
 159
 160 static inline u64 smmu_pmu_counter_get_value(struct smmu_pmu *smmu_pmu, u32 idx)
 161 {
 162         u64 value;
 163
 164         if (smmu_pmu->counter_mask & BIT(32))
 165                 value = readq(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
 166         else
 167                 value = readl(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
 168
 169         return value;
 170 }
 171
 172 static inline void smmu_pmu_counter_enable(struct smmu_pmu *smmu_pmu, u32 idx)
 173 {
 174         writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0);
 175 }
 176
 177 static inline void smmu_pmu_counter_disable(struct smmu_pmu *smmu_pmu, u32 idx)
 178 {
 179         writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
 180 }
 181
 182 static inline void smmu_pmu_interrupt_enable(struct smmu_pmu *smmu_pmu, u32 idx)
 183 {
 184         writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0);
 185 }
 186
 187 static inline void smmu_pmu_interrupt_disable(struct smmu_pmu *smmu_pmu,
 188                                               u32 idx)
 189 {
 190         writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
 191 }
 192
 193 static inline void smmu_pmu_set_evtyper(struct smmu_pmu *smmu_pmu, u32 idx,
 194                                         u32 val)
 195 {
 196         writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
 197 }
 198
 199 static inline void smmu_pmu_set_smr(struct smmu_pmu *smmu_pmu, u32 idx, u32 val)
 200 {
 201         writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx));
 202 }
 203
 204 static void smmu_pmu_event_update(struct perf_event *event)
 205 {
 206         struct hw_perf_event *hwc = &event->hw;
 207         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 208         u64 delta, prev, now;
 209         u32 idx = hwc->idx;
 210
 211         do {
 212                 prev = local64_read(&hwc->prev_count);
 213                 now = smmu_pmu_counter_get_value(smmu_pmu, idx);
 214         } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev);
 215
 216         /* handle overflow. */
 217         delta = now - prev;
 218         delta &= smmu_pmu->counter_mask;
 219
 220         local64_add(delta, &event->count);
 221 }
 222
 223 static void smmu_pmu_set_period(struct smmu_pmu *smmu_pmu,
 224                                 struct hw_perf_event *hwc)
 225 {
 226         u32 idx = hwc->idx;
 227         u64 new;
 228
 229         if (smmu_pmu->options & SMMU_PMCG_EVCNTR_RDONLY) {
 230                 /*
 231                  * On platforms that require this quirk, if the counter starts
 232                  * at < half_counter value and wraps, the current logic of
 233                  * handling the overflow may not work. It is expected that,
 234                  * those platforms will have full 64 counter bits implemented
 235                  * so that such a possibility is remote(eg: HiSilicon HIP08).
 236                  */
 237                 new = smmu_pmu_counter_get_value(smmu_pmu, idx);
 238         } else {
 239                 /*
 240                  * We limit the max period to half the max counter value
 241                  * of the counter size, so that even in the case of extreme
 242                  * interrupt latency the counter will (hopefully) not wrap
 243                  * past its initial value.
 244                  */
 245                 new = smmu_pmu->counter_mask >> 1;
 246                 smmu_pmu_counter_set_value(smmu_pmu, idx, new);
 247         }
 248
 249         local64_set(&hwc->prev_count, new);
 250 }
 251
 252 static void smmu_pmu_set_event_filter(struct perf_event *event,
 253                                       int idx, u32 span, u32 sid)
 254 {
 255         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 256         u32 evtyper;
 257
 258         evtyper = get_event(event) | span << SMMU_PMCG_SID_SPAN_SHIFT;
 259         smmu_pmu_set_evtyper(smmu_pmu, idx, evtyper);
 260         smmu_pmu_set_smr(smmu_pmu, idx, sid);
 261 }
 262
 263 static bool smmu_pmu_check_global_filter(struct perf_event *curr,
 264                                          struct perf_event *new)
 265 {
 266         if (get_filter_enable(new) != get_filter_enable(curr))
 267                 return false;
 268
 269         if (!get_filter_enable(new))
 270                 return true;
 271
 272         return get_filter_span(new) == get_filter_span(curr) &&
 273                get_filter_stream_id(new) == get_filter_stream_id(curr);
 274 }
 275
 276 static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu,
 277                                        struct perf_event *event, int idx)
 278 {
 279         u32 span, sid;
 280         unsigned int num_ctrs = smmu_pmu->num_counters;
 281         bool filter_en = !!get_filter_enable(event);
 282
 283         span = filter_en ? get_filter_span(event) :
 284                            SMMU_PMCG_DEFAULT_FILTER_SPAN;
 285         sid = filter_en ? get_filter_stream_id(event) :
 286                            SMMU_PMCG_DEFAULT_FILTER_SID;
 287
 288         /* Support individual filter settings */
 289         if (!smmu_pmu->global_filter) {
 290                 smmu_pmu_set_event_filter(event, idx, span, sid);
 291                 return 0;
 292         }
 293
 294         /* Requested settings same as current global settings*/
 295         idx = find_first_bit(smmu_pmu->used_counters, num_ctrs);
 296         if (idx == num_ctrs ||
 297             smmu_pmu_check_global_filter(smmu_pmu->events[idx], event)) {
 298                 smmu_pmu_set_event_filter(event, 0, span, sid);
 299                 return 0;
 300         }
 301
 302         return -EAGAIN;
 303 }
 304
 305 static int smmu_pmu_get_event_idx(struct smmu_pmu *smmu_pmu,
 306                                   struct perf_event *event)
 307 {
 308         int idx, err;
 309         unsigned int num_ctrs = smmu_pmu->num_counters;
 310
 311         idx = find_first_zero_bit(smmu_pmu->used_counters, num_ctrs);
 312         if (idx == num_ctrs)
 313                 /* The counters are all in use. */
 314                 return -EAGAIN;
 315
 316         err = smmu_pmu_apply_event_filter(smmu_pmu, event, idx);
 317         if (err)
 318                 return err;
 319
 320         set_bit(idx, smmu_pmu->used_counters);
 321
 322         return idx;
 323 }
 324
 325 static bool smmu_pmu_events_compatible(struct perf_event *curr,
 326                                        struct perf_event *new)
 327 {
 328         if (new->pmu != curr->pmu)
 329                 return false;
 330
 331         if (to_smmu_pmu(new->pmu)->global_filter &&
 332             !smmu_pmu_check_global_filter(curr, new))
 333                 return false;
 334
 335         return true;
 336 }
 337
 338 /*
 339  * Implementation of abstract pmu functionality required by
 340  * the core perf events code.
 341  */
 342
 343 static int smmu_pmu_event_init(struct perf_event *event)
 344 {
 345         struct hw_perf_event *hwc = &event->hw;
 346         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 347         struct device *dev = smmu_pmu->dev;
 348         struct perf_event *sibling;
 349         int group_num_events = 1;
 350         u16 event_id;
 351
 352         if (event->attr.type != event->pmu->type)
 353                 return -ENOENT;
 354
 355         if (hwc->sample_period) {
 356                 dev_dbg(dev, "Sampling not supported\n");
 357                 return -EOPNOTSUPP;
 358         }
 359
 360         if (event->cpu < 0) {
 361                 dev_dbg(dev, "Per-task mode not supported\n");
 362                 return -EOPNOTSUPP;
 363         }
 364
 365         /* Verify specified event is supported on this PMU */
 366         event_id = get_event(event);
 367         if (event_id < SMMU_PMCG_ARCH_MAX_EVENTS &&
 368             (!test_bit(event_id, smmu_pmu->supported_events))) {
 369                 dev_dbg(dev, "Invalid event %d for this PMU\n", event_id);
 370                 return -EINVAL;
 371         }
 372
 373         /* Don't allow groups with mixed PMUs, except for s/w events */
 374         if (!is_software_event(event->group_leader)) {
 375                 if (!smmu_pmu_events_compatible(event->group_leader, event))
 376                         return -EINVAL;
 377
 378                 if (++group_num_events > smmu_pmu->num_counters)
 379                         return -EINVAL;
 380         }
 381
 382         for_each_sibling_event(sibling, event->group_leader) {
 383                 if (is_software_event(sibling))
 384                         continue;
 385
 386                 if (!smmu_pmu_events_compatible(sibling, event))
 387                         return -EINVAL;
 388
 389                 if (++group_num_events > smmu_pmu->num_counters)
 390                         return -EINVAL;
 391         }
 392
 393         hwc->idx = -1;
 394
 395         /*
 396          * Ensure all events are on the same cpu so all events are in the
 397          * same cpu context, to avoid races on pmu_enable etc.
 398          */
 399         event->cpu = smmu_pmu->on_cpu;
 400
 401         return 0;
 402 }
 403
 404 static void smmu_pmu_event_start(struct perf_event *event, int flags)
 405 {
 406         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 407         struct hw_perf_event *hwc = &event->hw;
 408         int idx = hwc->idx;
 409
 410         hwc->state = 0;
 411
 412         smmu_pmu_set_period(smmu_pmu, hwc);
 413
 414         smmu_pmu_counter_enable(smmu_pmu, idx);
 415 }
 416
 417 static void smmu_pmu_event_stop(struct perf_event *event, int flags)
 418 {
 419         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 420         struct hw_perf_event *hwc = &event->hw;
 421         int idx = hwc->idx;
 422
 423         if (hwc->state & PERF_HES_STOPPED)
 424                 return;
 425
 426         smmu_pmu_counter_disable(smmu_pmu, idx);
 427         /* As the counter gets updated on _start, ignore PERF_EF_UPDATE */
 428         smmu_pmu_event_update(event);
 429         hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 430 }
 431
 432 static int smmu_pmu_event_add(struct perf_event *event, int flags)
 433 {
 434         struct hw_perf_event *hwc = &event->hw;
 435         int idx;
 436         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 437
 438         idx = smmu_pmu_get_event_idx(smmu_pmu, event);
 439         if (idx < 0)
 440                 return idx;
 441
 442         hwc->idx = idx;
 443         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 444         smmu_pmu->events[idx] = event;
 445         local64_set(&hwc->prev_count, 0);
 446
 447         smmu_pmu_interrupt_enable(smmu_pmu, idx);
 448
 449         if (flags & PERF_EF_START)
 450                 smmu_pmu_event_start(event, flags);
 451
 452         /* Propagate changes to the userspace mapping. */
 453         perf_event_update_userpage(event);
 454
 455         return 0;
 456 }
 457
 458 static void smmu_pmu_event_del(struct perf_event *event, int flags)
 459 {
 460         struct hw_perf_event *hwc = &event->hw;
 461         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 462         int idx = hwc->idx;
 463
 464         smmu_pmu_event_stop(event, flags | PERF_EF_UPDATE);
 465         smmu_pmu_interrupt_disable(smmu_pmu, idx);
 466         smmu_pmu->events[idx] = NULL;
 467         clear_bit(idx, smmu_pmu->used_counters);
 468
 469         perf_event_update_userpage(event);
 470 }
 471
 472 static void smmu_pmu_event_read(struct perf_event *event)
 473 {
 474         smmu_pmu_event_update(event);
 475 }
 476
 477 /* cpumask */
 478
 479 static ssize_t smmu_pmu_cpumask_show(struct device *dev,
 480                                      struct device_attribute *attr,
 481                                      char *buf)
 482 {
 483         struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
 484
 485         return cpumap_print_to_pagebuf(true, buf, cpumask_of(smmu_pmu->on_cpu));
 486 }
 487
 488 static struct device_attribute smmu_pmu_cpumask_attr =
 489                 __ATTR(cpumask, 0444, smmu_pmu_cpumask_show, NULL);
 490
 491 static struct attribute *smmu_pmu_cpumask_attrs[] = {
 492         &smmu_pmu_cpumask_attr.attr,
 493         NULL
 494 };
 495
 496 static struct attribute_group smmu_pmu_cpumask_group = {
 497         .attrs = smmu_pmu_cpumask_attrs,
 498 };
 499
 500 /* Events */
 501
 502 static ssize_t smmu_pmu_event_show(struct device *dev,
 503                                    struct device_attribute *attr, char *page)
 504 {
 505         struct perf_pmu_events_attr *pmu_attr;
 506
 507         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 508
 509         return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
 510 }
 511
 512 #define SMMU_EVENT_ATTR(name, config) \
 513         PMU_EVENT_ATTR(name, smmu_event_attr_##name, \
 514                        config, smmu_pmu_event_show)
 515 SMMU_EVENT_ATTR(cycles, 0);
 516 SMMU_EVENT_ATTR(transaction, 1);
 517 SMMU_EVENT_ATTR(tlb_miss, 2);
 518 SMMU_EVENT_ATTR(config_cache_miss, 3);
 519 SMMU_EVENT_ATTR(trans_table_walk_access, 4);
 520 SMMU_EVENT_ATTR(config_struct_access, 5);
 521 SMMU_EVENT_ATTR(pcie_ats_trans_rq, 6);
 522 SMMU_EVENT_ATTR(pcie_ats_trans_passed, 7);
 523
 524 static struct attribute *smmu_pmu_events[] = {
 525         &smmu_event_attr_cycles.attr.attr,
 526         &smmu_event_attr_transaction.attr.attr,
 527         &smmu_event_attr_tlb_miss.attr.attr,
 528         &smmu_event_attr_config_cache_miss.attr.attr,
 529         &smmu_event_attr_trans_table_walk_access.attr.attr,
 530         &smmu_event_attr_config_struct_access.attr.attr,
 531         &smmu_event_attr_pcie_ats_trans_rq.attr.attr,
 532         &smmu_event_attr_pcie_ats_trans_passed.attr.attr,
 533         NULL
 534 };
 535
 536 static umode_t smmu_pmu_event_is_visible(struct kobject *kobj,
 537                                          struct attribute *attr, int unused)
 538 {
 539         struct device *dev = kobj_to_dev(kobj);
 540         struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
 541         struct perf_pmu_events_attr *pmu_attr;
 542
 543         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
 544
 545         if (test_bit(pmu_attr->id, smmu_pmu->supported_events))
 546                 return attr->mode;
 547
 548         return 0;
 549 }
 550
 551 static struct attribute_group smmu_pmu_events_group = {
 552         .name = "events",
 553         .attrs = smmu_pmu_events,
 554         .is_visible = smmu_pmu_event_is_visible,
 555 };
 556
 557 static ssize_t smmu_pmu_identifier_attr_show(struct device *dev,
 558                                         struct device_attribute *attr,
 559                                         char *page)
 560 {
 561         struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
 562
 563         return snprintf(page, PAGE_SIZE, "0x%08x\n", smmu_pmu->iidr);
 564 }
 565
 566 static umode_t smmu_pmu_identifier_attr_visible(struct kobject *kobj,
 567                                                 struct attribute *attr,
 568                                                 int n)
 569 {
 570         struct device *dev = kobj_to_dev(kobj);
 571         struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
 572
 573         if (!smmu_pmu->iidr)
 574                 return 0;
 575         return attr->mode;
 576 }
 577
 578 static struct device_attribute smmu_pmu_identifier_attr =
 579         __ATTR(identifier, 0444, smmu_pmu_identifier_attr_show, NULL);
 580
 581 static struct attribute *smmu_pmu_identifier_attrs[] = {
 582         &smmu_pmu_identifier_attr.attr,
 583         NULL
 584 };
 585
 586 static struct attribute_group smmu_pmu_identifier_group = {
 587         .attrs = smmu_pmu_identifier_attrs,
 588         .is_visible = smmu_pmu_identifier_attr_visible,
 589 };
 590
 591 /* Formats */
 592 PMU_FORMAT_ATTR(event,             "config:0-15");
 593 PMU_FORMAT_ATTR(filter_stream_id,  "config1:0-31");
 594 PMU_FORMAT_ATTR(filter_span,       "config1:32");
 595 PMU_FORMAT_ATTR(filter_enable,     "config1:33");
 596
 597 static struct attribute *smmu_pmu_formats[] = {
 598         &format_attr_event.attr,
 599         &format_attr_filter_stream_id.attr,
 600         &format_attr_filter_span.attr,
 601         &format_attr_filter_enable.attr,
 602         NULL
 603 };
 604
 605 static struct attribute_group smmu_pmu_format_group = {
 606         .name = "format",
 607         .attrs = smmu_pmu_formats,
 608 };
 609
 610 static const struct attribute_group *smmu_pmu_attr_grps[] = {
 611         &smmu_pmu_cpumask_group,
 612         &smmu_pmu_events_group,
 613         &smmu_pmu_format_group,
 614         &smmu_pmu_identifier_group,
 615         NULL
 616 };
 617
 618 /*
 619  * Generic device handlers
 620  */
 621
 622 static int smmu_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
 623 {
 624         struct smmu_pmu *smmu_pmu;
 625         unsigned int target;
 626
 627         smmu_pmu = hlist_entry_safe(node, struct smmu_pmu, node);
 628         if (cpu != smmu_pmu->on_cpu)
 629                 return 0;
 630
 631         target = cpumask_any_but(cpu_online_mask, cpu);
 632         if (target >= nr_cpu_ids)
 633                 return 0;
 634
 635         perf_pmu_migrate_context(&smmu_pmu->pmu, cpu, target);
 636         smmu_pmu->on_cpu = target;
 637         WARN_ON(irq_set_affinity_hint(smmu_pmu->irq, cpumask_of(target)));
 638
 639         return 0;
 640 }
 641
 642 static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data)
 643 {
 644         struct smmu_pmu *smmu_pmu = data;
 645         u64 ovsr;
 646         unsigned int idx;
 647
 648         ovsr = readq(smmu_pmu->reloc_base + SMMU_PMCG_OVSSET0);
 649         if (!ovsr)
 650                 return IRQ_NONE;
 651
 652         writeq(ovsr, smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
 653
 654         for_each_set_bit(idx, (unsigned long *)&ovsr, smmu_pmu->num_counters) {
 655                 struct perf_event *event = smmu_pmu->events[idx];
 656                 struct hw_perf_event *hwc;
 657
 658                 if (WARN_ON_ONCE(!event))
 659                         continue;
 660
 661                 smmu_pmu_event_update(event);
 662                 hwc = &event->hw;
 663
 664                 smmu_pmu_set_period(smmu_pmu, hwc);
 665         }
 666
 667         return IRQ_HANDLED;
 668 }
 669
 670 static void smmu_pmu_free_msis(void *data)
 671 {
 672         struct device *dev = data;
 673
 674         platform_msi_domain_free_irqs(dev);
 675 }
 676
 677 static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
 678 {
 679         phys_addr_t doorbell;
 680         struct device *dev = msi_desc_to_dev(desc);
 681         struct smmu_pmu *pmu = dev_get_drvdata(dev);
 682
 683         doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
 684         doorbell &= MSI_CFG0_ADDR_MASK;
 685
 686         writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
 687         writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1);
 688         writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE,
 689                        pmu->reg_base + SMMU_PMCG_IRQ_CFG2);
 690 }
 691
 692 static void smmu_pmu_setup_msi(struct smmu_pmu *pmu)
 693 {
 694         struct msi_desc *desc;
 695         struct device *dev = pmu->dev;
 696         int ret;
 697
 698         /* Clear MSI address reg */
 699         writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
 700
 701         /* MSI supported or not */
 702         if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI))
 703                 return;
 704
 705         ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg);
 706         if (ret) {
 707                 dev_warn(dev, "failed to allocate MSIs\n");
 708                 return;
 709         }
 710
 711         desc = first_msi_entry(dev);
 712         if (desc)
 713                 pmu->irq = desc->irq;
 714
 715         /* Add callback to free MSIs on teardown */
 716         devm_add_action(dev, smmu_pmu_free_msis, dev);
 717 }
 718
 719 static int smmu_pmu_setup_irq(struct smmu_pmu *pmu)
 720 {
 721         unsigned long flags = IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD;
 722         int irq, ret = -ENXIO;
 723
 724         smmu_pmu_setup_msi(pmu);
 725
 726         irq = pmu->irq;
 727         if (irq)
 728                 ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq,
 729                                        flags, "smmuv3-pmu", pmu);
 730         return ret;
 731 }
 732
 733 static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu)
 734 {
 735         u64 counter_present_mask = GENMASK_ULL(smmu_pmu->num_counters - 1, 0);
 736
 737         smmu_pmu_disable(&smmu_pmu->pmu);
 738
 739         /* Disable counter and interrupt */
 740         writeq_relaxed(counter_present_mask,
 741                        smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
 742         writeq_relaxed(counter_present_mask,
 743                        smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
 744         writeq_relaxed(counter_present_mask,
 745                        smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
 746 }
 747
 748 static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
 749 {
 750         u32 model;
 751
 752         model = *(u32 *)dev_get_platdata(smmu_pmu->dev);
 753
 754         switch (model) {
 755         case IORT_SMMU_V3_PMCG_HISI_HIP08:
 756                 /* HiSilicon Erratum 162001800 */
 757                 smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
 758                 break;
 759         }
 760
 761         dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
 762 }
 763
 764 static int smmu_pmu_probe(struct platform_device *pdev)
 765 {
 766         struct smmu_pmu *smmu_pmu;
 767         struct resource *res_0;
 768         u32 cfgr, reg_size;
 769         u64 ceid_64[2];
 770         int irq, err;
 771         char *name;
 772         struct device *dev = &pdev->dev;
 773
 774         smmu_pmu = devm_kzalloc(dev, sizeof(*smmu_pmu), GFP_KERNEL);
 775         if (!smmu_pmu)
 776                 return -ENOMEM;
 777
 778         smmu_pmu->dev = dev;
 779         platform_set_drvdata(pdev, smmu_pmu);
 780
 781         smmu_pmu->pmu = (struct pmu) {
 782                 .module         = THIS_MODULE,
 783                 .task_ctx_nr    = perf_invalid_context,
 784                 .pmu_enable     = smmu_pmu_enable,
 785                 .pmu_disable    = smmu_pmu_disable,
 786                 .event_init     = smmu_pmu_event_init,
 787                 .add            = smmu_pmu_event_add,
 788                 .del            = smmu_pmu_event_del,
 789                 .start          = smmu_pmu_event_start,
 790                 .stop           = smmu_pmu_event_stop,
 791                 .read           = smmu_pmu_event_read,
 792                 .attr_groups    = smmu_pmu_attr_grps,
 793                 .capabilities   = PERF_PMU_CAP_NO_EXCLUDE,
 794         };
 795
 796         smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0);
 797         if (IS_ERR(smmu_pmu->reg_base))
 798                 return PTR_ERR(smmu_pmu->reg_base);
 799
 800         cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
 801
 802         /* Determine if page 1 is present */
 803         if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
 804                 smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
 805                 if (IS_ERR(smmu_pmu->reloc_base))
 806                         return PTR_ERR(smmu_pmu->reloc_base);
 807         } else {
 808                 smmu_pmu->reloc_base = smmu_pmu->reg_base;
 809         }
 810
 811         irq = platform_get_irq_optional(pdev, 0);
 812         if (irq > 0)
 813                 smmu_pmu->irq = irq;
 814
 815         ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
 816         ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);
 817         bitmap_from_arr32(smmu_pmu->supported_events, (u32 *)ceid_64,
 818                           SMMU_PMCG_ARCH_MAX_EVENTS);
 819
 820         smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1;
 821
 822         smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE);
 823
 824         reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr);
 825         smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0);
 826
 827         smmu_pmu_reset(smmu_pmu);
 828
 829         err = smmu_pmu_setup_irq(smmu_pmu);
 830         if (err) {
 831                 dev_err(dev, "Setup irq failed, PMU @%pa\n", &res_0->start);
 832                 return err;
 833         }
 834
 835         smmu_pmu->iidr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_IIDR);
 836
 837         name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "smmuv3_pmcg_%llx",
 838                               (res_0->start) >> SMMU_PMCG_PA_SHIFT);
 839         if (!name) {
 840                 dev_err(dev, "Create name failed, PMU @%pa\n", &res_0->start);
 841                 return -EINVAL;
 842         }
 843
 844         smmu_pmu_get_acpi_options(smmu_pmu);
 845
 846         /* Pick one CPU to be the preferred one to use */
 847         smmu_pmu->on_cpu = raw_smp_processor_id();
 848         WARN_ON(irq_set_affinity_hint(smmu_pmu->irq,
 849                                       cpumask_of(smmu_pmu->on_cpu)));
 850
 851         err = cpuhp_state_add_instance_nocalls(cpuhp_state_num,
 852                                                &smmu_pmu->node);
 853         if (err) {
 854                 dev_err(dev, "Error %d registering hotplug, PMU @%pa\n",
 855                         err, &res_0->start);
 856                 goto out_clear_affinity;
 857         }
 858
 859         err = perf_pmu_register(&smmu_pmu->pmu, name, -1);
 860         if (err) {
 861                 dev_err(dev, "Error %d registering PMU @%pa\n",
 862                         err, &res_0->start);
 863                 goto out_unregister;
 864         }
 865
 866         dev_info(dev, "Registered PMU @ %pa using %d counters with %s filter settings\n",
 867                  &res_0->start, smmu_pmu->num_counters,
 868                  smmu_pmu->global_filter ? "Global(Counter0)" :
 869                  "Individual");
 870
 871         return 0;
 872
 873 out_unregister:
 874         cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
 875 out_clear_affinity:
 876         irq_set_affinity_hint(smmu_pmu->irq, NULL);
 877         return err;
 878 }
 879
 880 static int smmu_pmu_remove(struct platform_device *pdev)
 881 {
 882         struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
 883
 884         perf_pmu_unregister(&smmu_pmu->pmu);
 885         cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
 886         irq_set_affinity_hint(smmu_pmu->irq, NULL);
 887
 888         return 0;
 889 }
 890
 891 static void smmu_pmu_shutdown(struct platform_device *pdev)
 892 {
 893         struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
 894
 895         smmu_pmu_disable(&smmu_pmu->pmu);
 896 }
 897
 898 static struct platform_driver smmu_pmu_driver = {
 899         .driver = {
 900                 .name = "arm-smmu-v3-pmcg",
 901                 .suppress_bind_attrs = true,
 902         },
 903         .probe = smmu_pmu_probe,
 904         .remove = smmu_pmu_remove,
 905         .shutdown = smmu_pmu_shutdown,
 906 };
 907
 908 static int __init arm_smmu_pmu_init(void)
 909 {
 910         cpuhp_state_num = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
 911                                                   "perf/arm/pmcg:online",
 912                                                   NULL,
 913                                                   smmu_pmu_offline_cpu);
 914         if (cpuhp_state_num < 0)
 915                 return cpuhp_state_num;
 916
 917         return platform_driver_register(&smmu_pmu_driver);
 918 }
 919 module_init(arm_smmu_pmu_init);
 920
 921 static void __exit arm_smmu_pmu_exit(void)
 922 {
 923         platform_driver_unregister(&smmu_pmu_driver);
 924         cpuhp_remove_multi_state(cpuhp_state_num);
 925 }
 926
 927 module_exit(arm_smmu_pmu_exit);
 928
 929 MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
 930 MODULE_AUTHOR("Neil Leeder <nleeder@codeaurora.org>");
 931 MODULE_AUTHOR("Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>");
 932 MODULE_LICENSE("GPL v2");