1 // SPDX-License-Identifier: GPL-2.0
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects root port status and schedules work.
7 * Copyright (C) 2006 Intel Corp.
8 * Tom Long Nguyen (tom.l.nguyen@intel.com)
9 * Zhang Yanmin (yanmin.zhang@intel.com)
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
12 * Andrew Patterson <andrew.patterson@hp.com>
15 #define pr_fmt(fmt) "AER: " fmt
16 #define dev_fmt pr_fmt
18 #include <linux/bitops.h>
19 #include <linux/cper.h>
20 #include <linux/pci.h>
21 #include <linux/pci-acpi.h>
22 #include <linux/sched.h>
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/kfifo.h>
30 #include <linux/slab.h>
31 #include <acpi/apei.h>
32 #include <ras/ras_event.h>
37 #define AER_ERROR_SOURCES_MAX 128
39 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
40 #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/
42 struct aer_err_source {
48 struct pci_dev *rpd; /* Root Port device */
49 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX);
52 /* AER stats for the device */
56 * Fields for all AER capable devices. They indicate the errors
57 * "as seen by this device". Note that this may mean that if an
58 * end point is causing problems, the AER counters may increment
59 * at its link partner (e.g. root port) because the errors will be
60 * "seen" by the link partner and not the the problematic end point
61 * itself (which may report all counters as 0 as it never saw any
64 /* Counters for different type of correctable errors */
65 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
66 /* Counters for different type of fatal uncorrectable errors */
67 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
68 /* Counters for different type of nonfatal uncorrectable errors */
69 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
70 /* Total number of ERR_COR sent by this device */
71 u64 dev_total_cor_errs;
72 /* Total number of ERR_FATAL sent by this device */
73 u64 dev_total_fatal_errs;
74 /* Total number of ERR_NONFATAL sent by this device */
75 u64 dev_total_nonfatal_errs;
78 * Fields for Root ports & root complex event collectors only, these
79 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
80 * messages received by the root port / event collector, INCLUDING the
81 * ones that are generated internally (by the rootport itself)
83 u64 rootport_total_cor_errs;
84 u64 rootport_total_fatal_errs;
85 u64 rootport_total_nonfatal_errs;
88 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
91 PCI_ERR_UNC_COMP_ABORT| \
92 PCI_ERR_UNC_UNX_COMP| \
95 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
96 PCI_EXP_RTCTL_SENFEE| \
98 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
99 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
100 PCI_ERR_ROOT_CMD_FATAL_EN)
101 #define ERR_COR_ID(d) (d & 0xffff)
102 #define ERR_UNCOR_ID(d) (d >> 16)
104 static int pcie_aer_disable;
105 static pci_ers_result_t aer_root_reset(struct pci_dev *dev);
107 void pci_no_aer(void)
109 pcie_aer_disable = 1;
112 bool pci_aer_available(void)
114 return !pcie_aer_disable && pci_msi_enabled();
117 #ifdef CONFIG_PCIE_ECRC
119 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
120 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */
121 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
123 static int ecrc_policy = ECRC_POLICY_DEFAULT;
125 static const char * const ecrc_policy_str[] = {
126 [ECRC_POLICY_DEFAULT] = "bios",
127 [ECRC_POLICY_OFF] = "off",
128 [ECRC_POLICY_ON] = "on"
132 * enable_ercr_checking - enable PCIe ECRC checking for a device
133 * @dev: the PCI device
135 * Returns 0 on success, or negative on failure.
137 static int enable_ecrc_checking(struct pci_dev *dev)
139 int aer = dev->aer_cap;
145 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
146 if (reg32 & PCI_ERR_CAP_ECRC_GENC)
147 reg32 |= PCI_ERR_CAP_ECRC_GENE;
148 if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
149 reg32 |= PCI_ERR_CAP_ECRC_CHKE;
150 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
156 * disable_ercr_checking - disables PCIe ECRC checking for a device
157 * @dev: the PCI device
159 * Returns 0 on success, or negative on failure.
161 static int disable_ecrc_checking(struct pci_dev *dev)
163 int aer = dev->aer_cap;
169 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
170 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
171 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
177 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
178 * @dev: the PCI device
180 void pcie_set_ecrc_checking(struct pci_dev *dev)
182 switch (ecrc_policy) {
183 case ECRC_POLICY_DEFAULT:
185 case ECRC_POLICY_OFF:
186 disable_ecrc_checking(dev);
189 enable_ecrc_checking(dev);
197 * pcie_ecrc_get_policy - parse kernel command-line ecrc option
198 * @str: ECRC policy from kernel command line to use
200 void pcie_ecrc_get_policy(char *str)
204 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str);
210 #endif /* CONFIG_PCIE_ECRC */
212 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
213 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
215 int pcie_aer_is_native(struct pci_dev *dev)
217 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
222 return pcie_ports_native || host->native_aer;
225 int pci_enable_pcie_error_reporting(struct pci_dev *dev)
227 if (!pcie_aer_is_native(dev))
230 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
232 EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
234 int pci_disable_pcie_error_reporting(struct pci_dev *dev)
236 if (!pcie_aer_is_native(dev))
239 return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
242 EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
244 void pci_aer_clear_device_status(struct pci_dev *dev)
248 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
249 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
252 int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
254 int aer = dev->aer_cap;
257 if (!pcie_aer_is_native(dev))
260 /* Clear status bits for ERR_NONFATAL errors only */
261 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
262 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
265 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
269 EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status);
271 void pci_aer_clear_fatal_status(struct pci_dev *dev)
273 int aer = dev->aer_cap;
276 if (!pcie_aer_is_native(dev))
279 /* Clear status bits for ERR_FATAL errors only */
280 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
281 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
284 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
288 * pci_aer_raw_clear_status - Clear AER error registers.
289 * @dev: the PCI device
291 * Clearing AER error status registers unconditionally, regardless of
292 * whether they're owned by firmware or the OS.
294 * Returns 0 on success, or negative on failure.
296 int pci_aer_raw_clear_status(struct pci_dev *dev)
298 int aer = dev->aer_cap;
305 port_type = pci_pcie_type(dev);
306 if (port_type == PCI_EXP_TYPE_ROOT_PORT) {
307 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);
308 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);
311 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
312 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);
314 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
315 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
320 int pci_aer_clear_status(struct pci_dev *dev)
322 if (!pcie_aer_is_native(dev))
325 return pci_aer_raw_clear_status(dev);
328 void pci_save_aer_state(struct pci_dev *dev)
330 int aer = dev->aer_cap;
331 struct pci_cap_saved_state *save_state;
337 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
341 cap = &save_state->cap.data[0];
342 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);
343 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);
344 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
345 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);
346 if (pcie_cap_has_rtctl(dev))
347 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);
350 void pci_restore_aer_state(struct pci_dev *dev)
352 int aer = dev->aer_cap;
353 struct pci_cap_saved_state *save_state;
359 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
363 cap = &save_state->cap.data[0];
364 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);
365 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);
366 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
367 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);
368 if (pcie_cap_has_rtctl(dev))
369 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);
372 void pci_aer_init(struct pci_dev *dev)
376 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
380 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL);
383 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
384 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
385 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec
388 n = pcie_cap_has_rtctl(dev) ? 5 : 4;
389 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
391 pci_aer_clear_status(dev);
394 void pci_aer_exit(struct pci_dev *dev)
396 kfree(dev->aer_stats);
397 dev->aer_stats = NULL;
400 #define AER_AGENT_RECEIVER 0
401 #define AER_AGENT_REQUESTER 1
402 #define AER_AGENT_COMPLETER 2
403 #define AER_AGENT_TRANSMITTER 3
405 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
406 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
407 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
408 0 : PCI_ERR_UNC_COMP_ABORT)
409 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
410 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
412 #define AER_GET_AGENT(t, e) \
413 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
414 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
415 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
418 #define AER_PHYSICAL_LAYER_ERROR 0
419 #define AER_DATA_LINK_LAYER_ERROR 1
420 #define AER_TRANSACTION_LAYER_ERROR 2
422 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
423 PCI_ERR_COR_RCVR : 0)
424 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
425 (PCI_ERR_COR_BAD_TLP| \
426 PCI_ERR_COR_BAD_DLLP| \
427 PCI_ERR_COR_REP_ROLL| \
428 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
430 #define AER_GET_LAYER_ERROR(t, e) \
431 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
432 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
433 AER_TRANSACTION_LAYER_ERROR)
438 static const char *aer_error_severity_string[] = {
439 "Uncorrected (Non-Fatal)",
440 "Uncorrected (Fatal)",
444 static const char *aer_error_layer[] = {
450 static const char *aer_correctable_error_string[AER_MAX_TYPEOF_COR_ERRS] = {
451 "RxErr", /* Bit Position 0 */
457 "BadTLP", /* Bit Position 6 */
458 "BadDLLP", /* Bit Position 7 */
459 "Rollover", /* Bit Position 8 */
463 "Timeout", /* Bit Position 12 */
464 "NonFatalErr", /* Bit Position 13 */
465 "CorrIntErr", /* Bit Position 14 */
466 "HeaderOF", /* Bit Position 15 */
469 static const char *aer_uncorrectable_error_string[AER_MAX_TYPEOF_UNCOR_ERRS] = {
470 "Undefined", /* Bit Position 0 */
474 "DLP", /* Bit Position 4 */
475 "SDES", /* Bit Position 5 */
482 "TLP", /* Bit Position 12 */
483 "FCP", /* Bit Position 13 */
484 "CmpltTO", /* Bit Position 14 */
485 "CmpltAbrt", /* Bit Position 15 */
486 "UnxCmplt", /* Bit Position 16 */
487 "RxOF", /* Bit Position 17 */
488 "MalfTLP", /* Bit Position 18 */
489 "ECRC", /* Bit Position 19 */
490 "UnsupReq", /* Bit Position 20 */
491 "ACSViol", /* Bit Position 21 */
492 "UncorrIntErr", /* Bit Position 22 */
493 "BlockedTLP", /* Bit Position 23 */
494 "AtomicOpBlocked", /* Bit Position 24 */
495 "TLPBlockedErr", /* Bit Position 25 */
496 "PoisonTLPBlocked", /* Bit Position 26 */
499 static const char *aer_agent_string[] = {
506 #define aer_stats_dev_attr(name, stats_array, strings_array, \
507 total_string, total_field) \
509 name##_show(struct device *dev, struct device_attribute *attr, \
514 struct pci_dev *pdev = to_pci_dev(dev); \
515 u64 *stats = pdev->aer_stats->stats_array; \
517 for (i = 0; i < ARRAY_SIZE(strings_array); i++) { \
518 if (strings_array[i]) \
519 str += sprintf(str, "%s %llu\n", \
520 strings_array[i], stats[i]); \
522 str += sprintf(str, #stats_array "_bit[%d] %llu\n",\
525 str += sprintf(str, "TOTAL_%s %llu\n", total_string, \
526 pdev->aer_stats->total_field); \
529 static DEVICE_ATTR_RO(name)
531 aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs,
532 aer_correctable_error_string, "ERR_COR",
534 aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs,
535 aer_uncorrectable_error_string, "ERR_FATAL",
536 dev_total_fatal_errs);
537 aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs,
538 aer_uncorrectable_error_string, "ERR_NONFATAL",
539 dev_total_nonfatal_errs);
541 #define aer_stats_rootport_attr(name, field) \
543 name##_show(struct device *dev, struct device_attribute *attr, \
546 struct pci_dev *pdev = to_pci_dev(dev); \
547 return sprintf(buf, "%llu\n", pdev->aer_stats->field); \
549 static DEVICE_ATTR_RO(name)
551 aer_stats_rootport_attr(aer_rootport_total_err_cor,
552 rootport_total_cor_errs);
553 aer_stats_rootport_attr(aer_rootport_total_err_fatal,
554 rootport_total_fatal_errs);
555 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal,
556 rootport_total_nonfatal_errs);
558 static struct attribute *aer_stats_attrs[] __ro_after_init = {
559 &dev_attr_aer_dev_correctable.attr,
560 &dev_attr_aer_dev_fatal.attr,
561 &dev_attr_aer_dev_nonfatal.attr,
562 &dev_attr_aer_rootport_total_err_cor.attr,
563 &dev_attr_aer_rootport_total_err_fatal.attr,
564 &dev_attr_aer_rootport_total_err_nonfatal.attr,
568 static umode_t aer_stats_attrs_are_visible(struct kobject *kobj,
569 struct attribute *a, int n)
571 struct device *dev = kobj_to_dev(kobj);
572 struct pci_dev *pdev = to_pci_dev(dev);
574 if (!pdev->aer_stats)
577 if ((a == &dev_attr_aer_rootport_total_err_cor.attr ||
578 a == &dev_attr_aer_rootport_total_err_fatal.attr ||
579 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) &&
580 pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT)
586 const struct attribute_group aer_stats_attr_group = {
587 .attrs = aer_stats_attrs,
588 .is_visible = aer_stats_attrs_are_visible,
591 static void pci_dev_aer_stats_incr(struct pci_dev *pdev,
592 struct aer_err_info *info)
594 unsigned long status = info->status & ~info->mask;
597 struct aer_stats *aer_stats = pdev->aer_stats;
602 switch (info->severity) {
603 case AER_CORRECTABLE:
604 aer_stats->dev_total_cor_errs++;
605 counter = &aer_stats->dev_cor_errs[0];
606 max = AER_MAX_TYPEOF_COR_ERRS;
609 aer_stats->dev_total_nonfatal_errs++;
610 counter = &aer_stats->dev_nonfatal_errs[0];
611 max = AER_MAX_TYPEOF_UNCOR_ERRS;
614 aer_stats->dev_total_fatal_errs++;
615 counter = &aer_stats->dev_fatal_errs[0];
616 max = AER_MAX_TYPEOF_UNCOR_ERRS;
620 for_each_set_bit(i, &status, max)
624 static void pci_rootport_aer_stats_incr(struct pci_dev *pdev,
625 struct aer_err_source *e_src)
627 struct aer_stats *aer_stats = pdev->aer_stats;
632 if (e_src->status & PCI_ERR_ROOT_COR_RCV)
633 aer_stats->rootport_total_cor_errs++;
635 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
636 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
637 aer_stats->rootport_total_fatal_errs++;
639 aer_stats->rootport_total_nonfatal_errs++;
643 static void __print_tlp_header(struct pci_dev *dev,
644 struct aer_header_log_regs *t)
646 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n",
647 t->dw0, t->dw1, t->dw2, t->dw3);
650 static void __aer_print_error(struct pci_dev *dev,
651 struct aer_err_info *info)
653 unsigned long status = info->status & ~info->mask;
654 const char *errmsg = NULL;
657 for_each_set_bit(i, &status, 32) {
658 if (info->severity == AER_CORRECTABLE)
659 errmsg = i < ARRAY_SIZE(aer_correctable_error_string) ?
660 aer_correctable_error_string[i] : NULL;
662 errmsg = i < ARRAY_SIZE(aer_uncorrectable_error_string) ?
663 aer_uncorrectable_error_string[i] : NULL;
666 pci_err(dev, " [%2d] %-22s%s\n", i, errmsg,
667 info->first_error == i ? " (First)" : "");
669 pci_err(dev, " [%2d] Unknown Error Bit%s\n",
670 i, info->first_error == i ? " (First)" : "");
672 pci_dev_aer_stats_incr(dev, info);
675 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
678 int id = ((dev->bus->number << 8) | dev->devfn);
681 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
682 aer_error_severity_string[info->severity]);
686 layer = AER_GET_LAYER_ERROR(info->severity, info->status);
687 agent = AER_GET_AGENT(info->severity, info->status);
689 pci_err(dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
690 aer_error_severity_string[info->severity],
691 aer_error_layer[layer], aer_agent_string[agent]);
693 pci_err(dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
694 dev->vendor, dev->device,
695 info->status, info->mask);
697 __aer_print_error(dev, info);
699 if (info->tlp_header_valid)
700 __print_tlp_header(dev, &info->tlp);
703 if (info->id && info->error_dev_num > 1 && info->id == id)
704 pci_err(dev, " Error of this Agent is reported first\n");
706 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
707 info->severity, info->tlp_header_valid, &info->tlp);
710 static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
712 u8 bus = info->id >> 8;
713 u8 devfn = info->id & 0xff;
715 pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n",
716 info->multi_error_valid ? "Multiple " : "",
717 aer_error_severity_string[info->severity],
718 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn),
722 #ifdef CONFIG_ACPI_APEI_PCIEAER
723 int cper_severity_to_aer(int cper_severity)
725 switch (cper_severity) {
726 case CPER_SEV_RECOVERABLE:
731 return AER_CORRECTABLE;
734 EXPORT_SYMBOL_GPL(cper_severity_to_aer);
736 void cper_print_aer(struct pci_dev *dev, int aer_severity,
737 struct aer_capability_regs *aer)
739 int layer, agent, tlp_header_valid = 0;
741 struct aer_err_info info;
743 if (aer_severity == AER_CORRECTABLE) {
744 status = aer->cor_status;
745 mask = aer->cor_mask;
747 status = aer->uncor_status;
748 mask = aer->uncor_mask;
749 tlp_header_valid = status & AER_LOG_TLP_MASKS;
752 layer = AER_GET_LAYER_ERROR(aer_severity, status);
753 agent = AER_GET_AGENT(aer_severity, status);
755 memset(&info, 0, sizeof(info));
756 info.severity = aer_severity;
757 info.status = status;
759 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);
761 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
762 __aer_print_error(dev, &info);
763 pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
764 aer_error_layer[layer], aer_agent_string[agent]);
766 if (aer_severity != AER_CORRECTABLE)
767 pci_err(dev, "aer_uncor_severity: 0x%08x\n",
768 aer->uncor_severity);
770 if (tlp_header_valid)
771 __print_tlp_header(dev, &aer->header_log);
773 trace_aer_event(dev_name(&dev->dev), (status & ~mask),
774 aer_severity, tlp_header_valid, &aer->header_log);
779 * add_error_device - list device to be handled
780 * @e_info: pointer to error info
781 * @dev: pointer to pci_dev to be added
783 static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
785 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) {
786 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev);
787 e_info->error_dev_num++;
794 * is_error_source - check whether the device is source of reported error
795 * @dev: pointer to pci_dev to be checked
796 * @e_info: pointer to reported error info
798 static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
800 int aer = dev->aer_cap;
805 * When bus id is equal to 0, it might be a bad id
806 * reported by root port.
808 if ((PCI_BUS_NUM(e_info->id) != 0) &&
809 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
810 /* Device ID match? */
811 if (e_info->id == ((dev->bus->number << 8) | dev->devfn))
814 /* Continue id comparing if there is no multiple error */
815 if (!e_info->multi_error_valid)
821 * 1) bus id is equal to 0. Some ports might lose the bus
822 * id of error source id;
823 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
824 * 3) There are multiple errors and prior ID comparing fails;
825 * We check AER status registers to find possible reporter.
827 if (atomic_read(&dev->enable_cnt) == 0)
830 /* Check if AER is enabled */
831 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16);
832 if (!(reg16 & PCI_EXP_AER_FLAGS))
838 /* Check if error is recorded */
839 if (e_info->severity == AER_CORRECTABLE) {
840 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
841 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
843 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
844 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
852 static int find_device_iter(struct pci_dev *dev, void *data)
854 struct aer_err_info *e_info = (struct aer_err_info *)data;
856 if (is_error_source(dev, e_info)) {
857 /* List this device */
858 if (add_error_device(e_info, dev)) {
859 /* We cannot handle more... Stop iteration */
860 /* TODO: Should print error message here? */
864 /* If there is only a single error, stop iteration */
865 if (!e_info->multi_error_valid)
872 * find_source_device - search through device hierarchy for source device
873 * @parent: pointer to Root Port pci_dev data structure
874 * @e_info: including detailed error information such like id
876 * Return true if found.
878 * Invoked by DPC when error is detected at the Root Port.
879 * Caller of this function must set id, severity, and multi_error_valid of
880 * struct aer_err_info pointed by @e_info properly. This function must fill
881 * e_info->error_dev_num and e_info->dev[], based on the given information.
883 static bool find_source_device(struct pci_dev *parent,
884 struct aer_err_info *e_info)
886 struct pci_dev *dev = parent;
889 /* Must reset in this function */
890 e_info->error_dev_num = 0;
892 /* Is Root Port an agent that sends error message? */
893 result = find_device_iter(dev, e_info);
897 pci_walk_bus(parent->subordinate, find_device_iter, e_info);
899 if (!e_info->error_dev_num) {
900 pci_info(parent, "can't find device of ID%04x\n", e_info->id);
907 * handle_error_source - handle logging error into an event log
908 * @dev: pointer to pci_dev data structure of error source device
909 * @info: comprehensive error information
911 * Invoked when an error being detected by Root Port.
913 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
915 int aer = dev->aer_cap;
917 if (info->severity == AER_CORRECTABLE) {
919 * Correctable error does not need software intervention.
920 * No need to go through error recovery process.
923 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
925 pci_aer_clear_device_status(dev);
926 } else if (info->severity == AER_NONFATAL)
927 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
928 else if (info->severity == AER_FATAL)
929 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
933 #ifdef CONFIG_ACPI_APEI_PCIEAER
935 #define AER_RECOVER_RING_ORDER 4
936 #define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
938 struct aer_recover_entry {
943 struct aer_capability_regs *regs;
946 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
947 AER_RECOVER_RING_SIZE);
949 static void aer_recover_work_func(struct work_struct *work)
951 struct aer_recover_entry entry;
952 struct pci_dev *pdev;
954 while (kfifo_get(&aer_recover_ring, &entry)) {
955 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
958 pr_err("AER recover: Can not find pci_dev for %04x:%02x:%02x:%x\n",
959 entry.domain, entry.bus,
960 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
963 cper_print_aer(pdev, entry.severity, entry.regs);
964 if (entry.severity == AER_NONFATAL)
965 pcie_do_recovery(pdev, pci_channel_io_normal,
967 else if (entry.severity == AER_FATAL)
968 pcie_do_recovery(pdev, pci_channel_io_frozen,
975 * Mutual exclusion for writers of aer_recover_ring, reader side don't
976 * need lock, because there is only one reader and lock is not needed
977 * between reader and writer.
979 static DEFINE_SPINLOCK(aer_recover_ring_lock);
980 static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
982 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
983 int severity, struct aer_capability_regs *aer_regs)
985 struct aer_recover_entry entry = {
989 .severity = severity,
993 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1,
994 &aer_recover_ring_lock))
995 schedule_work(&aer_recover_work);
997 pr_err("AER recover: Buffer overflow when recovering AER for %04x:%02x:%02x:%x\n",
998 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1000 EXPORT_SYMBOL_GPL(aer_recover_queue);
1004 * aer_get_device_error_info - read error status from dev and store it to info
1005 * @dev: pointer to the device expected to have a error record
1006 * @info: pointer to structure to store the error record
1008 * Return 1 on success, 0 on error.
1010 * Note that @info is reused among all error devices. Clear fields properly.
1012 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
1014 int aer = dev->aer_cap;
1017 /* Must reset in this function */
1019 info->tlp_header_valid = 0;
1021 /* The device might not support AER */
1025 if (info->severity == AER_CORRECTABLE) {
1026 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,
1028 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
1030 if (!(info->status & ~info->mask))
1032 } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
1033 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM ||
1034 info->severity == AER_NONFATAL) {
1036 /* Link is still healthy for IO reads */
1037 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
1039 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
1041 if (!(info->status & ~info->mask))
1044 /* Get First Error Pointer */
1045 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);
1046 info->first_error = PCI_ERR_CAP_FEP(temp);
1048 if (info->status & AER_LOG_TLP_MASKS) {
1049 info->tlp_header_valid = 1;
1050 pci_read_config_dword(dev,
1051 aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
1052 pci_read_config_dword(dev,
1053 aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
1054 pci_read_config_dword(dev,
1055 aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
1056 pci_read_config_dword(dev,
1057 aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
1064 static inline void aer_process_err_devices(struct aer_err_info *e_info)
1068 /* Report all before handle them, not to lost records by reset etc. */
1069 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1070 if (aer_get_device_error_info(e_info->dev[i], e_info))
1071 aer_print_error(e_info->dev[i], e_info);
1073 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1074 if (aer_get_device_error_info(e_info->dev[i], e_info))
1075 handle_error_source(e_info->dev[i], e_info);
1080 * aer_isr_one_error - consume an error detected by root port
1081 * @rpc: pointer to the root port which holds an error
1082 * @e_src: pointer to an error source
1084 static void aer_isr_one_error(struct aer_rpc *rpc,
1085 struct aer_err_source *e_src)
1087 struct pci_dev *pdev = rpc->rpd;
1088 struct aer_err_info e_info;
1090 pci_rootport_aer_stats_incr(pdev, e_src);
1093 * There is a possibility that both correctable error and
1094 * uncorrectable error being logged. Report correctable error first.
1096 if (e_src->status & PCI_ERR_ROOT_COR_RCV) {
1097 e_info.id = ERR_COR_ID(e_src->id);
1098 e_info.severity = AER_CORRECTABLE;
1100 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV)
1101 e_info.multi_error_valid = 1;
1103 e_info.multi_error_valid = 0;
1104 aer_print_port_info(pdev, &e_info);
1106 if (find_source_device(pdev, &e_info))
1107 aer_process_err_devices(&e_info);
1110 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
1111 e_info.id = ERR_UNCOR_ID(e_src->id);
1113 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
1114 e_info.severity = AER_FATAL;
1116 e_info.severity = AER_NONFATAL;
1118 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV)
1119 e_info.multi_error_valid = 1;
1121 e_info.multi_error_valid = 0;
1123 aer_print_port_info(pdev, &e_info);
1125 if (find_source_device(pdev, &e_info))
1126 aer_process_err_devices(&e_info);
1131 * aer_isr - consume errors detected by root port
1132 * @irq: IRQ assigned to Root Port
1133 * @context: pointer to Root Port data structure
1135 * Invoked, as DPC, when root port records new detected error
1137 static irqreturn_t aer_isr(int irq, void *context)
1139 struct pcie_device *dev = (struct pcie_device *)context;
1140 struct aer_rpc *rpc = get_service_data(dev);
1141 struct aer_err_source e_src;
1143 if (kfifo_is_empty(&rpc->aer_fifo))
1146 while (kfifo_get(&rpc->aer_fifo, &e_src))
1147 aer_isr_one_error(rpc, &e_src);
1152 * aer_irq - Root Port's ISR
1153 * @irq: IRQ assigned to Root Port
1154 * @context: pointer to Root Port data structure
1156 * Invoked when Root Port detects AER messages.
1158 static irqreturn_t aer_irq(int irq, void *context)
1160 struct pcie_device *pdev = (struct pcie_device *)context;
1161 struct aer_rpc *rpc = get_service_data(pdev);
1162 struct pci_dev *rp = rpc->rpd;
1163 int aer = rp->aer_cap;
1164 struct aer_err_source e_src = {};
1166 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);
1167 if (!(e_src.status & (PCI_ERR_ROOT_UNCOR_RCV|PCI_ERR_ROOT_COR_RCV)))
1170 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
1171 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);
1173 if (!kfifo_put(&rpc->aer_fifo, e_src))
1176 return IRQ_WAKE_THREAD;
1179 static int set_device_error_reporting(struct pci_dev *dev, void *data)
1181 bool enable = *((bool *)data);
1182 int type = pci_pcie_type(dev);
1184 if ((type == PCI_EXP_TYPE_ROOT_PORT) ||
1185 (type == PCI_EXP_TYPE_UPSTREAM) ||
1186 (type == PCI_EXP_TYPE_DOWNSTREAM)) {
1188 pci_enable_pcie_error_reporting(dev);
1190 pci_disable_pcie_error_reporting(dev);
1194 pcie_set_ecrc_checking(dev);
1200 * set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports.
1201 * @dev: pointer to root port's pci_dev data structure
1202 * @enable: true = enable error reporting, false = disable error reporting.
1204 static void set_downstream_devices_error_reporting(struct pci_dev *dev,
1207 set_device_error_reporting(dev, &enable);
1209 if (!dev->subordinate)
1211 pci_walk_bus(dev->subordinate, set_device_error_reporting, &enable);
1215 * aer_enable_rootport - enable Root Port's interrupts when receiving messages
1216 * @rpc: pointer to a Root Port data structure
1218 * Invoked when PCIe bus loads AER service driver.
1220 static void aer_enable_rootport(struct aer_rpc *rpc)
1222 struct pci_dev *pdev = rpc->rpd;
1223 int aer = pdev->aer_cap;
1227 /* Clear PCIe Capability's Device Status */
1228 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16);
1229 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
1231 /* Disable system error generation in response to error messages */
1232 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
1233 SYSTEM_ERROR_INTR_ON_MESG_MASK);
1235 /* Clear error status */
1236 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1237 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1238 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32);
1239 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);
1240 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32);
1241 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);
1244 * Enable error reporting for the root port device and downstream port
1247 set_downstream_devices_error_reporting(pdev, true);
1249 /* Enable Root Port's interrupt in response to error messages */
1250 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1251 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1252 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1256 * aer_disable_rootport - disable Root Port's interrupts when receiving messages
1257 * @rpc: pointer to a Root Port data structure
1259 * Invoked when PCIe bus unloads AER service driver.
1261 static void aer_disable_rootport(struct aer_rpc *rpc)
1263 struct pci_dev *pdev = rpc->rpd;
1264 int aer = pdev->aer_cap;
1268 * Disable error reporting for the root port device and downstream port
1271 set_downstream_devices_error_reporting(pdev, false);
1273 /* Disable Root's interrupt in response to error messages */
1274 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1275 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1276 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1278 /* Clear Root's error status reg */
1279 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1280 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1284 * aer_remove - clean up resources
1285 * @dev: pointer to the pcie_dev data structure
1287 * Invoked when PCI Express bus unloads or AER probe fails.
1289 static void aer_remove(struct pcie_device *dev)
1291 struct aer_rpc *rpc = get_service_data(dev);
1293 aer_disable_rootport(rpc);
1297 * aer_probe - initialize resources
1298 * @dev: pointer to the pcie_dev data structure
1300 * Invoked when PCI Express bus loads AER service driver.
1302 static int aer_probe(struct pcie_device *dev)
1305 struct aer_rpc *rpc;
1306 struct device *device = &dev->device;
1307 struct pci_dev *port = dev->port;
1309 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
1314 INIT_KFIFO(rpc->aer_fifo);
1315 set_service_data(dev, rpc);
1317 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr,
1318 IRQF_SHARED, "aerdrv", dev);
1320 pci_err(port, "request AER IRQ %d failed\n", dev->irq);
1324 aer_enable_rootport(rpc);
1325 pci_info(port, "enabled with IRQ %d\n", dev->irq);
1330 * aer_root_reset - reset link on Root Port
1331 * @dev: pointer to Root Port's pci_dev data structure
1333 * Invoked by Port Bus driver when performing link reset at Root Port.
1335 static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
1337 int aer = dev->aer_cap;
1342 /* Disable Root's interrupt in response to error messages */
1343 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1344 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1345 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1347 rc = pci_bus_error_reset(dev);
1348 pci_info(dev, "Root Port link has been reset\n");
1350 /* Clear Root Error Status */
1351 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, ®32);
1352 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, reg32);
1354 /* Enable Root Port's interrupt in response to error messages */
1355 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1356 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1357 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1359 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1362 static struct pcie_port_service_driver aerdriver = {
1364 .port_type = PCI_EXP_TYPE_ROOT_PORT,
1365 .service = PCIE_PORT_SERVICE_AER,
1368 .remove = aer_remove,
1372 * aer_service_init - register AER root service driver
1374 * Invoked when AER root service driver is loaded.
1376 int __init pcie_aer_init(void)
1378 if (!pci_aer_available())
1380 return pcie_port_service_register(&aerdriver);