1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
10 #define PCI_FIND_CAP_TTL 48
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
14 extern const unsigned char pcie_link_speed[];
15 extern bool pci_early_dump;
17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
18 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
20 /* Functions internal to the PCI core code */
22 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
24 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
25 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
27 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
30 void pci_create_firmware_label_files(struct pci_dev *pdev);
31 void pci_remove_firmware_label_files(struct pci_dev *pdev);
33 void pci_cleanup_rom(struct pci_dev *dev);
36 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
37 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
39 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
40 enum pci_mmap_api mmap_api);
42 int pci_probe_reset_function(struct pci_dev *dev);
43 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
44 int pci_bus_error_reset(struct pci_dev *dev);
46 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
47 #define PCI_PM_D3HOT_WAIT 10 /* msec */
48 #define PCI_PM_D3COLD_WAIT 100 /* msec */
51 * struct pci_platform_pm_ops - Firmware PM callbacks
53 * @bridge_d3: Does the bridge allow entering into D3
55 * @is_manageable: returns 'true' if given device is power manageable by the
58 * @set_state: invokes the platform firmware to set the device's power state
60 * @get_state: queries the platform firmware for a device's current power state
62 * @refresh_state: asks the platform to refresh the device's power state data
64 * @choose_state: returns PCI power state of given device preferred by the
65 * platform; to be used during system-wide transitions from a
66 * sleeping state to the working state and vice versa
68 * @set_wakeup: enables/disables wakeup capability for the device
70 * @need_resume: returns 'true' if the given device (which is currently
71 * suspended) needs to be resumed to be configured for system
74 * If given platform is generally capable of power managing PCI devices, all of
75 * these callbacks are mandatory.
77 struct pci_platform_pm_ops {
78 bool (*bridge_d3)(struct pci_dev *dev);
79 bool (*is_manageable)(struct pci_dev *dev);
80 int (*set_state)(struct pci_dev *dev, pci_power_t state);
81 pci_power_t (*get_state)(struct pci_dev *dev);
82 void (*refresh_state)(struct pci_dev *dev);
83 pci_power_t (*choose_state)(struct pci_dev *dev);
84 int (*set_wakeup)(struct pci_dev *dev, bool enable);
85 bool (*need_resume)(struct pci_dev *dev);
88 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
89 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
90 void pci_refresh_power_state(struct pci_dev *dev);
91 int pci_power_up(struct pci_dev *dev);
92 void pci_disable_enabled_device(struct pci_dev *dev);
93 int pci_finish_runtime_suspend(struct pci_dev *dev);
94 void pcie_clear_device_status(struct pci_dev *dev);
95 void pcie_clear_root_pme_status(struct pci_dev *dev);
96 bool pci_check_pme_status(struct pci_dev *dev);
97 void pci_pme_wakeup_bus(struct pci_bus *bus);
98 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
99 void pci_pme_restore(struct pci_dev *dev);
100 bool pci_dev_need_resume(struct pci_dev *dev);
101 void pci_dev_adjust_pme(struct pci_dev *dev);
102 void pci_dev_complete_resume(struct pci_dev *pci_dev);
103 void pci_config_pm_runtime_get(struct pci_dev *dev);
104 void pci_config_pm_runtime_put(struct pci_dev *dev);
105 void pci_pm_init(struct pci_dev *dev);
106 void pci_ea_init(struct pci_dev *dev);
107 void pci_msi_init(struct pci_dev *dev);
108 void pci_msix_init(struct pci_dev *dev);
109 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
110 void pci_free_cap_save_buffers(struct pci_dev *dev);
111 bool pci_bridge_d3_possible(struct pci_dev *dev);
112 void pci_bridge_d3_update(struct pci_dev *dev);
113 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
115 static inline void pci_wakeup_event(struct pci_dev *dev)
117 /* Wait 100 ms before the system can be put into a sleep state. */
118 pm_wakeup_event(&dev->dev, 100);
121 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
123 return !!(pci_dev->subordinate);
126 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
129 * Currently we allow normal PCI devices and PCI bridges transition
130 * into D3 if their bridge_d3 is set.
132 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
135 static inline bool pcie_downstream_port(const struct pci_dev *dev)
137 int type = pci_pcie_type(dev);
139 return type == PCI_EXP_TYPE_ROOT_PORT ||
140 type == PCI_EXP_TYPE_DOWNSTREAM ||
141 type == PCI_EXP_TYPE_PCIE_BRIDGE;
144 int pci_vpd_init(struct pci_dev *dev);
145 void pci_vpd_release(struct pci_dev *dev);
146 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
147 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
149 /* PCI Virtual Channel */
150 int pci_save_vc_state(struct pci_dev *dev);
151 void pci_restore_vc_state(struct pci_dev *dev);
152 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
154 /* PCI /proc functions */
155 #ifdef CONFIG_PROC_FS
156 int pci_proc_attach_device(struct pci_dev *dev);
157 int pci_proc_detach_device(struct pci_dev *dev);
158 int pci_proc_detach_bus(struct pci_bus *bus);
160 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
161 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
162 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
165 /* Functions for PCI Hotplug drivers to use */
166 int pci_hp_add_bridge(struct pci_dev *dev);
168 #ifdef HAVE_PCI_LEGACY
169 void pci_create_legacy_files(struct pci_bus *bus);
170 void pci_remove_legacy_files(struct pci_bus *bus);
172 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
173 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
176 /* Lock for read/write access to pci device and bus lists */
177 extern struct rw_semaphore pci_bus_sem;
178 extern struct mutex pci_slot_mutex;
180 extern raw_spinlock_t pci_lock;
182 extern unsigned int pci_pm_d3hot_delay;
184 #ifdef CONFIG_PCI_MSI
185 void pci_no_msi(void);
187 static inline void pci_no_msi(void) { }
190 void pci_realloc_get_opt(char *);
192 static inline int pci_no_d1d2(struct pci_dev *dev)
194 unsigned int parent_dstates = 0;
197 parent_dstates = dev->bus->self->no_d1d2;
198 return (dev->no_d1d2 || parent_dstates);
201 extern const struct attribute_group *pci_dev_groups[];
202 extern const struct attribute_group *pcibus_groups[];
203 extern const struct device_type pci_dev_type;
204 extern const struct attribute_group *pci_bus_groups[];
206 extern unsigned long pci_hotplug_io_size;
207 extern unsigned long pci_hotplug_mmio_size;
208 extern unsigned long pci_hotplug_mmio_pref_size;
209 extern unsigned long pci_hotplug_bus_size;
212 * pci_match_one_device - Tell if a PCI device structure has a matching
213 * PCI device id structure
214 * @id: single PCI device id structure to match
215 * @dev: the PCI device structure to match against
217 * Returns the matching pci_device_id structure or %NULL if there is no match.
219 static inline const struct pci_device_id *
220 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
222 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
223 (id->device == PCI_ANY_ID || id->device == dev->device) &&
224 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
225 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
226 !((id->class ^ dev->class) & id->class_mask))
231 /* PCI slot sysfs helper code */
232 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
234 extern struct kset *pci_slots_kset;
236 struct pci_slot_attribute {
237 struct attribute attr;
238 ssize_t (*show)(struct pci_slot *, char *);
239 ssize_t (*store)(struct pci_slot *, const char *, size_t);
241 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
244 pci_bar_unknown, /* Standard PCI BAR probe */
245 pci_bar_io, /* An I/O port BAR */
246 pci_bar_mem32, /* A 32-bit memory BAR */
247 pci_bar_mem64, /* A 64-bit memory BAR */
250 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
251 void pci_put_host_bridge_device(struct device *dev);
253 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
254 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
256 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
258 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
260 int pci_setup_device(struct pci_dev *dev);
261 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
262 struct resource *res, unsigned int reg);
263 void pci_configure_ari(struct pci_dev *dev);
264 void __pci_bus_size_bridges(struct pci_bus *bus,
265 struct list_head *realloc_head);
266 void __pci_bus_assign_resources(const struct pci_bus *bus,
267 struct list_head *realloc_head,
268 struct list_head *fail_head);
269 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
271 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
272 void pci_disable_bridge_window(struct pci_dev *dev);
273 struct pci_bus *pci_bus_get(struct pci_bus *bus);
274 void pci_bus_put(struct pci_bus *bus);
276 /* PCIe link information from Link Capabilities 2 */
277 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
278 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
279 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
280 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
281 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
282 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
285 /* PCIe speed to Mb/s reduced by encoding overhead */
286 #define PCIE_SPEED2MBS_ENC(speed) \
287 ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
288 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
289 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
290 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
291 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
294 const char *pci_speed_string(enum pci_bus_speed speed);
295 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
296 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
297 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
298 enum pcie_link_width *width);
299 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
300 void pcie_report_downtraining(struct pci_dev *dev);
301 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
303 /* Single Root I/O Virtualization */
305 int pos; /* Capability position */
306 int nres; /* Number of resources */
307 u32 cap; /* SR-IOV Capabilities */
308 u16 ctrl; /* SR-IOV Control */
309 u16 total_VFs; /* Total VFs associated with the PF */
310 u16 initial_VFs; /* Initial VFs associated with the PF */
311 u16 num_VFs; /* Number of VFs available */
312 u16 offset; /* First VF Routing ID offset */
313 u16 stride; /* Following VF stride */
314 u16 vf_device; /* VF device ID */
315 u32 pgsz; /* Page size for BAR alignment */
316 u8 link; /* Function Dependency Link */
317 u8 max_VF_buses; /* Max buses consumed by VFs */
318 u16 driver_max_VFs; /* Max num VFs driver supports */
319 struct pci_dev *dev; /* Lowest numbered PF */
320 struct pci_dev *self; /* This PF */
321 u32 class; /* VF device */
322 u8 hdr_type; /* VF header type */
323 u16 subsystem_vendor; /* VF subsystem vendor */
324 u16 subsystem_device; /* VF subsystem device */
325 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
326 bool drivers_autoprobe; /* Auto probing of VFs by driver */
330 * pci_dev_set_io_state - Set the new error state if possible.
332 * @dev - pci device to set new error_state
333 * @new - the state we want dev to be in
335 * Must be called with device_lock held.
337 * Returns true if state has been changed to the requested state.
339 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
340 pci_channel_state_t new)
342 bool changed = false;
344 device_lock_assert(&dev->dev);
346 case pci_channel_io_perm_failure:
347 switch (dev->error_state) {
348 case pci_channel_io_frozen:
349 case pci_channel_io_normal:
350 case pci_channel_io_perm_failure:
355 case pci_channel_io_frozen:
356 switch (dev->error_state) {
357 case pci_channel_io_frozen:
358 case pci_channel_io_normal:
363 case pci_channel_io_normal:
364 switch (dev->error_state) {
365 case pci_channel_io_frozen:
366 case pci_channel_io_normal:
373 dev->error_state = new;
377 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
379 device_lock(&dev->dev);
380 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
381 device_unlock(&dev->dev);
386 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
388 return dev->error_state == pci_channel_io_perm_failure;
391 /* pci_dev priv_flags */
392 #define PCI_DEV_ADDED 0
394 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
396 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
399 static inline bool pci_dev_is_added(const struct pci_dev *dev)
401 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
404 #ifdef CONFIG_PCIEAER
405 #include <linux/aer.h>
407 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
409 struct aer_err_info {
410 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
415 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
416 unsigned int __pad1:5;
417 unsigned int multi_error_valid:1;
419 unsigned int first_error:5;
420 unsigned int __pad2:2;
421 unsigned int tlp_header_valid:1;
423 unsigned int status; /* COR/UNCOR Error Status */
424 unsigned int mask; /* COR/UNCOR Error Mask */
425 struct aer_header_log_regs tlp; /* TLP Header */
428 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
429 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
430 #endif /* CONFIG_PCIEAER */
432 #ifdef CONFIG_PCIE_DPC
433 void pci_save_dpc_state(struct pci_dev *dev);
434 void pci_restore_dpc_state(struct pci_dev *dev);
435 void pci_dpc_init(struct pci_dev *pdev);
436 void dpc_process_error(struct pci_dev *pdev);
437 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
439 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
440 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
441 static inline void pci_dpc_init(struct pci_dev *pdev) {}
444 #ifdef CONFIG_PCI_ATS
445 /* Address Translation Service */
446 void pci_ats_init(struct pci_dev *dev);
447 void pci_restore_ats_state(struct pci_dev *dev);
449 static inline void pci_ats_init(struct pci_dev *d) { }
450 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
451 #endif /* CONFIG_PCI_ATS */
453 #ifdef CONFIG_PCI_PRI
454 void pci_pri_init(struct pci_dev *dev);
455 void pci_restore_pri_state(struct pci_dev *pdev);
457 static inline void pci_pri_init(struct pci_dev *dev) { }
458 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
461 #ifdef CONFIG_PCI_PASID
462 void pci_pasid_init(struct pci_dev *dev);
463 void pci_restore_pasid_state(struct pci_dev *pdev);
465 static inline void pci_pasid_init(struct pci_dev *dev) { }
466 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
469 #ifdef CONFIG_PCI_IOV
470 int pci_iov_init(struct pci_dev *dev);
471 void pci_iov_release(struct pci_dev *dev);
472 void pci_iov_remove(struct pci_dev *dev);
473 void pci_iov_update_resource(struct pci_dev *dev, int resno);
474 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
475 void pci_restore_iov_state(struct pci_dev *dev);
476 int pci_iov_bus_range(struct pci_bus *bus);
477 extern const struct attribute_group sriov_dev_attr_group;
479 static inline int pci_iov_init(struct pci_dev *dev)
483 static inline void pci_iov_release(struct pci_dev *dev)
487 static inline void pci_iov_remove(struct pci_dev *dev)
490 static inline void pci_restore_iov_state(struct pci_dev *dev)
493 static inline int pci_iov_bus_range(struct pci_bus *bus)
498 #endif /* CONFIG_PCI_IOV */
500 unsigned long pci_cardbus_resource_alignment(struct resource *);
502 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
503 struct resource *res)
505 #ifdef CONFIG_PCI_IOV
506 int resno = res - dev->resource;
508 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
509 return pci_sriov_resource_alignment(dev, resno);
511 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
512 return pci_cardbus_resource_alignment(res);
513 return resource_alignment(res);
516 void pci_acs_init(struct pci_dev *dev);
517 #ifdef CONFIG_PCI_QUIRKS
518 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
519 int pci_dev_specific_enable_acs(struct pci_dev *dev);
520 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
522 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
527 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
531 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
537 /* PCI error reporting and recovery */
538 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
539 pci_channel_state_t state,
540 pci_ers_result_t (*reset_link)(struct pci_dev *pdev));
542 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
543 #ifdef CONFIG_PCIEASPM
544 void pcie_aspm_init_link_state(struct pci_dev *pdev);
545 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
546 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
547 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
549 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
550 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
551 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
552 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
555 #ifdef CONFIG_PCIE_ECRC
556 void pcie_set_ecrc_checking(struct pci_dev *dev);
557 void pcie_ecrc_get_policy(char *str);
559 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
560 static inline void pcie_ecrc_get_policy(char *str) { }
563 #ifdef CONFIG_PCIE_PTM
564 void pci_ptm_init(struct pci_dev *dev);
565 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
567 static inline void pci_ptm_init(struct pci_dev *dev) { }
568 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
572 struct pci_dev_reset_methods {
575 int (*reset)(struct pci_dev *dev, int probe);
578 #ifdef CONFIG_PCI_QUIRKS
579 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
581 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
587 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
588 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
589 struct resource *res);
592 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
593 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
594 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
595 static inline u64 pci_rebar_size_to_bytes(int size)
597 return 1ULL << (size + 20);
603 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
604 int of_get_pci_domain_nr(struct device_node *node);
605 int of_pci_get_max_link_speed(struct device_node *node);
606 void pci_set_of_node(struct pci_dev *dev);
607 void pci_release_of_node(struct pci_dev *dev);
608 void pci_set_bus_of_node(struct pci_bus *bus);
609 void pci_release_bus_of_node(struct pci_bus *bus);
611 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
615 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
621 of_get_pci_domain_nr(struct device_node *node)
627 of_pci_get_max_link_speed(struct device_node *node)
632 static inline void pci_set_of_node(struct pci_dev *dev) { }
633 static inline void pci_release_of_node(struct pci_dev *dev) { }
634 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
635 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
637 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
642 #endif /* CONFIG_OF */
644 #ifdef CONFIG_PCIEAER
645 void pci_no_aer(void);
646 void pci_aer_init(struct pci_dev *dev);
647 void pci_aer_exit(struct pci_dev *dev);
648 extern const struct attribute_group aer_stats_attr_group;
649 void pci_aer_clear_fatal_status(struct pci_dev *dev);
650 int pci_aer_clear_status(struct pci_dev *dev);
651 int pci_aer_raw_clear_status(struct pci_dev *dev);
653 static inline void pci_no_aer(void) { }
654 static inline void pci_aer_init(struct pci_dev *d) { }
655 static inline void pci_aer_exit(struct pci_dev *d) { }
656 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
657 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
658 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
662 int pci_acpi_program_hp_params(struct pci_dev *dev);
664 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
670 #ifdef CONFIG_PCIEASPM
671 extern const struct attribute_group aspm_ctrl_attr_group;
674 #endif /* DRIVERS_PCI_H */