1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex);
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
44 int isa_dma_bridge_buggy;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy);
48 EXPORT_SYMBOL(pci_pci_problems);
50 unsigned int pci_pm_d3hot_delay;
52 static void pci_pme_list_scan(struct work_struct *work);
54 static LIST_HEAD(pci_pme_list);
55 static DEFINE_MUTEX(pci_pme_list_mutex);
56 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
58 struct pci_pme_device {
59 struct list_head list;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev *dev)
67 unsigned int delay = dev->d3hot_delay;
69 if (delay < pci_pm_d3hot_delay)
70 delay = pci_pm_d3hot_delay;
76 bool pci_reset_supported(struct pci_dev *dev)
78 return dev->reset_methods[0] != 0;
81 #ifdef CONFIG_PCI_DOMAINS
82 int pci_domains_supported = 1;
85 #define DEFAULT_CARDBUS_IO_SIZE (256)
86 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
87 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
88 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
89 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
91 #define DEFAULT_HOTPLUG_IO_SIZE (256)
92 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
93 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
94 /* hpiosize=nn can override this */
95 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
97 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
98 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
99 * pci=hpmemsize=nnM overrides both
101 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
102 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
104 #define DEFAULT_HOTPLUG_BUS_SIZE 1
105 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
108 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
109 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
110 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
111 #elif defined CONFIG_PCIE_BUS_SAFE
112 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
113 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
114 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
115 #elif defined CONFIG_PCIE_BUS_PEER2PEER
116 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
118 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
122 * The default CLS is used if arch didn't set CLS explicitly and not
123 * all pci devices agree on the same value. Arch can override either
124 * the dfl or actual value as it sees fit. Don't forget this is
125 * measured in 32-bit words, not bytes.
127 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
128 u8 pci_cache_line_size;
131 * If we set up a device for bus mastering, we need to check the latency
132 * timer as certain BIOSes forget to set it properly.
134 unsigned int pcibios_max_latency = 255;
136 /* If set, the PCIe ARI capability will not be used. */
137 static bool pcie_ari_disabled;
139 /* If set, the PCIe ATS capability will not be used. */
140 static bool pcie_ats_disabled;
142 /* If set, the PCI config space of each device is printed during boot. */
145 bool pci_ats_disabled(void)
147 return pcie_ats_disabled;
149 EXPORT_SYMBOL_GPL(pci_ats_disabled);
151 /* Disable bridge_d3 for all PCIe ports */
152 static bool pci_bridge_d3_disable;
153 /* Force bridge_d3 for all PCIe ports */
154 static bool pci_bridge_d3_force;
156 static int __init pcie_port_pm_setup(char *str)
158 if (!strcmp(str, "off"))
159 pci_bridge_d3_disable = true;
160 else if (!strcmp(str, "force"))
161 pci_bridge_d3_force = true;
164 __setup("pcie_port_pm=", pcie_port_pm_setup);
166 /* Time to wait after a reset for device to become responsive */
167 #define PCIE_RESET_READY_POLL_MS 60000
170 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
171 * @bus: pointer to PCI bus structure to search
173 * Given a PCI bus, returns the highest PCI bus number present in the set
174 * including the given PCI bus and its list of child PCI buses.
176 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
179 unsigned char max, n;
181 max = bus->busn_res.end;
182 list_for_each_entry(tmp, &bus->children, node) {
183 n = pci_bus_max_busnr(tmp);
189 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
192 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
193 * @pdev: the PCI device
195 * Returns error bits set in PCI_STATUS and clears them.
197 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
202 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
203 if (ret != PCIBIOS_SUCCESSFUL)
206 status &= PCI_STATUS_ERROR_BITS;
208 pci_write_config_word(pdev, PCI_STATUS, status);
212 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
214 #ifdef CONFIG_HAS_IOMEM
215 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
218 struct resource *res = &pdev->resource[bar];
219 resource_size_t start = res->start;
220 resource_size_t size = resource_size(res);
223 * Make sure the BAR is actually a memory resource, not an IO resource
225 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
226 pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
231 return ioremap_wc(start, size);
233 return ioremap(start, size);
236 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
238 return __pci_ioremap_resource(pdev, bar, false);
240 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
242 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
244 return __pci_ioremap_resource(pdev, bar, true);
246 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
250 * pci_dev_str_match_path - test if a path string matches a device
251 * @dev: the PCI device to test
252 * @path: string to match the device against
253 * @endptr: pointer to the string after the match
255 * Test if a string (typically from a kernel parameter) formatted as a
256 * path of device/function addresses matches a PCI device. The string must
259 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
261 * A path for a device can be obtained using 'lspci -t'. Using a path
262 * is more robust against bus renumbering than using only a single bus,
263 * device and function address.
265 * Returns 1 if the string matches the device, 0 if it does not and
266 * a negative error code if it fails to parse the string.
268 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
272 unsigned int seg, bus, slot, func;
276 *endptr = strchrnul(path, ';');
278 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
283 p = strrchr(wpath, '/');
286 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
292 if (dev->devfn != PCI_DEVFN(slot, func)) {
298 * Note: we don't need to get a reference to the upstream
299 * bridge because we hold a reference to the top level
300 * device which should hold a reference to the bridge,
303 dev = pci_upstream_bridge(dev);
312 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
316 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
323 ret = (seg == pci_domain_nr(dev->bus) &&
324 bus == dev->bus->number &&
325 dev->devfn == PCI_DEVFN(slot, func));
333 * pci_dev_str_match - test if a string matches a device
334 * @dev: the PCI device to test
335 * @p: string to match the device against
336 * @endptr: pointer to the string after the match
338 * Test if a string (typically from a kernel parameter) matches a specified
339 * PCI device. The string may be of one of the following formats:
341 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
342 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
344 * The first format specifies a PCI bus/device/function address which
345 * may change if new hardware is inserted, if motherboard firmware changes,
346 * or due to changes caused in kernel parameters. If the domain is
347 * left unspecified, it is taken to be 0. In order to be robust against
348 * bus renumbering issues, a path of PCI device/function numbers may be used
349 * to address the specific device. The path for a device can be determined
350 * through the use of 'lspci -t'.
352 * The second format matches devices using IDs in the configuration
353 * space which may match multiple devices in the system. A value of 0
354 * for any field will match all devices. (Note: this differs from
355 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
356 * legacy reasons and convenience so users don't have to specify
357 * FFFFFFFFs on the command line.)
359 * Returns 1 if the string matches the device, 0 if it does not and
360 * a negative error code if the string cannot be parsed.
362 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
367 unsigned short vendor, device, subsystem_vendor, subsystem_device;
369 if (strncmp(p, "pci:", 4) == 0) {
370 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
372 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
373 &subsystem_vendor, &subsystem_device, &count);
375 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
379 subsystem_vendor = 0;
380 subsystem_device = 0;
385 if ((!vendor || vendor == dev->vendor) &&
386 (!device || device == dev->device) &&
387 (!subsystem_vendor ||
388 subsystem_vendor == dev->subsystem_vendor) &&
389 (!subsystem_device ||
390 subsystem_device == dev->subsystem_device))
394 * PCI Bus, Device, Function IDs are specified
395 * (optionally, may include a path of devfns following it)
397 ret = pci_dev_str_match_path(dev, p, &p);
412 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
413 u8 pos, int cap, int *ttl)
418 pci_bus_read_config_byte(bus, devfn, pos, &pos);
424 pci_bus_read_config_word(bus, devfn, pos, &ent);
436 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
439 int ttl = PCI_FIND_CAP_TTL;
441 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
444 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
446 return __pci_find_next_cap(dev->bus, dev->devfn,
447 pos + PCI_CAP_LIST_NEXT, cap);
449 EXPORT_SYMBOL_GPL(pci_find_next_capability);
451 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
452 unsigned int devfn, u8 hdr_type)
456 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
457 if (!(status & PCI_STATUS_CAP_LIST))
461 case PCI_HEADER_TYPE_NORMAL:
462 case PCI_HEADER_TYPE_BRIDGE:
463 return PCI_CAPABILITY_LIST;
464 case PCI_HEADER_TYPE_CARDBUS:
465 return PCI_CB_CAPABILITY_LIST;
472 * pci_find_capability - query for devices' capabilities
473 * @dev: PCI device to query
474 * @cap: capability code
476 * Tell if a device supports a given PCI capability.
477 * Returns the address of the requested capability structure within the
478 * device's PCI configuration space or 0 in case the device does not
479 * support it. Possible values for @cap include:
481 * %PCI_CAP_ID_PM Power Management
482 * %PCI_CAP_ID_AGP Accelerated Graphics Port
483 * %PCI_CAP_ID_VPD Vital Product Data
484 * %PCI_CAP_ID_SLOTID Slot Identification
485 * %PCI_CAP_ID_MSI Message Signalled Interrupts
486 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
487 * %PCI_CAP_ID_PCIX PCI-X
488 * %PCI_CAP_ID_EXP PCI Express
490 u8 pci_find_capability(struct pci_dev *dev, int cap)
494 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
496 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
500 EXPORT_SYMBOL(pci_find_capability);
503 * pci_bus_find_capability - query for devices' capabilities
504 * @bus: the PCI bus to query
505 * @devfn: PCI device to query
506 * @cap: capability code
508 * Like pci_find_capability() but works for PCI devices that do not have a
509 * pci_dev structure set up yet.
511 * Returns the address of the requested capability structure within the
512 * device's PCI configuration space or 0 in case the device does not
515 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
519 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
521 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
523 pos = __pci_find_next_cap(bus, devfn, pos, cap);
527 EXPORT_SYMBOL(pci_bus_find_capability);
530 * pci_find_next_ext_capability - Find an extended capability
531 * @dev: PCI device to query
532 * @start: address at which to start looking (0 to start at beginning of list)
533 * @cap: capability code
535 * Returns the address of the next matching extended capability structure
536 * within the device's PCI configuration space or 0 if the device does
537 * not support it. Some capabilities can occur several times, e.g., the
538 * vendor-specific capability, and this provides a way to find them all.
540 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
544 u16 pos = PCI_CFG_SPACE_SIZE;
546 /* minimum 8 bytes per capability */
547 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
549 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
555 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
559 * If we have no capabilities, this is indicated by cap ID,
560 * cap version and next pointer all being 0.
566 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
569 pos = PCI_EXT_CAP_NEXT(header);
570 if (pos < PCI_CFG_SPACE_SIZE)
573 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
579 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
582 * pci_find_ext_capability - Find an extended capability
583 * @dev: PCI device to query
584 * @cap: capability code
586 * Returns the address of the requested extended capability structure
587 * within the device's PCI configuration space or 0 if the device does
588 * not support it. Possible values for @cap include:
590 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
591 * %PCI_EXT_CAP_ID_VC Virtual Channel
592 * %PCI_EXT_CAP_ID_DSN Device Serial Number
593 * %PCI_EXT_CAP_ID_PWR Power Budgeting
595 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
597 return pci_find_next_ext_capability(dev, 0, cap);
599 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
602 * pci_get_dsn - Read and return the 8-byte Device Serial Number
603 * @dev: PCI device to query
605 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
608 * Returns the DSN, or zero if the capability does not exist.
610 u64 pci_get_dsn(struct pci_dev *dev)
616 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
621 * The Device Serial Number is two dwords offset 4 bytes from the
622 * capability position. The specification says that the first dword is
623 * the lower half, and the second dword is the upper half.
626 pci_read_config_dword(dev, pos, &dword);
628 pci_read_config_dword(dev, pos + 4, &dword);
629 dsn |= ((u64)dword) << 32;
633 EXPORT_SYMBOL_GPL(pci_get_dsn);
635 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
637 int rc, ttl = PCI_FIND_CAP_TTL;
640 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
641 mask = HT_3BIT_CAP_MASK;
643 mask = HT_5BIT_CAP_MASK;
645 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
646 PCI_CAP_ID_HT, &ttl);
648 rc = pci_read_config_byte(dev, pos + 3, &cap);
649 if (rc != PCIBIOS_SUCCESSFUL)
652 if ((cap & mask) == ht_cap)
655 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
656 pos + PCI_CAP_LIST_NEXT,
657 PCI_CAP_ID_HT, &ttl);
664 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
665 * @dev: PCI device to query
666 * @pos: Position from which to continue searching
667 * @ht_cap: HyperTransport capability code
669 * To be used in conjunction with pci_find_ht_capability() to search for
670 * all capabilities matching @ht_cap. @pos should always be a value returned
671 * from pci_find_ht_capability().
673 * NB. To be 100% safe against broken PCI devices, the caller should take
674 * steps to avoid an infinite loop.
676 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
678 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
680 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
683 * pci_find_ht_capability - query a device's HyperTransport capabilities
684 * @dev: PCI device to query
685 * @ht_cap: HyperTransport capability code
687 * Tell if a device supports a given HyperTransport capability.
688 * Returns an address within the device's PCI configuration space
689 * or 0 in case the device does not support the request capability.
690 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
691 * which has a HyperTransport capability matching @ht_cap.
693 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
697 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
699 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
703 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
706 * pci_find_vsec_capability - Find a vendor-specific extended capability
707 * @dev: PCI device to query
708 * @vendor: Vendor ID for which capability is defined
709 * @cap: Vendor-specific capability ID
711 * If @dev has Vendor ID @vendor, search for a VSEC capability with
712 * VSEC ID @cap. If found, return the capability offset in
713 * config space; otherwise return 0.
715 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
720 if (vendor != dev->vendor)
723 while ((vsec = pci_find_next_ext_capability(dev, vsec,
724 PCI_EXT_CAP_ID_VNDR))) {
725 if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,
726 &header) == PCIBIOS_SUCCESSFUL &&
727 PCI_VNDR_HEADER_ID(header) == cap)
733 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
736 * pci_find_dvsec_capability - Find DVSEC for vendor
737 * @dev: PCI device to query
738 * @vendor: Vendor ID to match for the DVSEC
739 * @dvsec: Designated Vendor-specific capability ID
741 * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
742 * offset in config space; otherwise return 0.
744 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)
748 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC);
755 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);
756 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id);
757 if (vendor == v && dvsec == id)
760 pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC);
765 EXPORT_SYMBOL_GPL(pci_find_dvsec_capability);
768 * pci_find_parent_resource - return resource region of parent bus of given
770 * @dev: PCI device structure contains resources to be searched
771 * @res: child resource record for which parent is sought
773 * For given resource region of given device, return the resource region of
774 * parent bus the given region is contained in.
776 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
777 struct resource *res)
779 const struct pci_bus *bus = dev->bus;
783 pci_bus_for_each_resource(bus, r, i) {
786 if (resource_contains(r, res)) {
789 * If the window is prefetchable but the BAR is
790 * not, the allocator made a mistake.
792 if (r->flags & IORESOURCE_PREFETCH &&
793 !(res->flags & IORESOURCE_PREFETCH))
797 * If we're below a transparent bridge, there may
798 * be both a positively-decoded aperture and a
799 * subtractively-decoded region that contain the BAR.
800 * We want the positively-decoded one, so this depends
801 * on pci_bus_for_each_resource() giving us those
809 EXPORT_SYMBOL(pci_find_parent_resource);
812 * pci_find_resource - Return matching PCI device resource
813 * @dev: PCI device to query
814 * @res: Resource to look for
816 * Goes over standard PCI resources (BARs) and checks if the given resource
817 * is partially or fully contained in any of them. In that case the
818 * matching resource is returned, %NULL otherwise.
820 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
824 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
825 struct resource *r = &dev->resource[i];
827 if (r->start && resource_contains(r, res))
833 EXPORT_SYMBOL(pci_find_resource);
836 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
837 * @dev: the PCI device to operate on
838 * @pos: config space offset of status word
839 * @mask: mask of bit(s) to care about in status word
841 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
843 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
847 /* Wait for Transaction Pending bit clean */
848 for (i = 0; i < 4; i++) {
851 msleep((1 << (i - 1)) * 100);
853 pci_read_config_word(dev, pos, &status);
854 if (!(status & mask))
861 static int pci_acs_enable;
864 * pci_request_acs - ask for ACS to be enabled if supported
866 void pci_request_acs(void)
871 static const char *disable_acs_redir_param;
874 * pci_disable_acs_redir - disable ACS redirect capabilities
875 * @dev: the PCI device
877 * For only devices specified in the disable_acs_redir parameter.
879 static void pci_disable_acs_redir(struct pci_dev *dev)
886 if (!disable_acs_redir_param)
889 p = disable_acs_redir_param;
891 ret = pci_dev_str_match(dev, p, &p);
893 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
894 disable_acs_redir_param);
897 } else if (ret == 1) {
902 if (*p != ';' && *p != ',') {
903 /* End of param or invalid format */
912 if (!pci_dev_specific_disable_acs_redir(dev))
917 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
921 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
923 /* P2P Request & Completion Redirect */
924 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
926 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
928 pci_info(dev, "disabled ACS redirect\n");
932 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
933 * @dev: the PCI device
935 static void pci_std_enable_acs(struct pci_dev *dev)
945 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
946 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
948 /* Source Validation */
949 ctrl |= (cap & PCI_ACS_SV);
951 /* P2P Request Redirect */
952 ctrl |= (cap & PCI_ACS_RR);
954 /* P2P Completion Redirect */
955 ctrl |= (cap & PCI_ACS_CR);
957 /* Upstream Forwarding */
958 ctrl |= (cap & PCI_ACS_UF);
960 /* Enable Translation Blocking for external devices and noats */
961 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
962 ctrl |= (cap & PCI_ACS_TB);
964 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
968 * pci_enable_acs - enable ACS if hardware support it
969 * @dev: the PCI device
971 static void pci_enable_acs(struct pci_dev *dev)
974 goto disable_acs_redir;
976 if (!pci_dev_specific_enable_acs(dev))
977 goto disable_acs_redir;
979 pci_std_enable_acs(dev);
983 * Note: pci_disable_acs_redir() must be called even if ACS was not
984 * enabled by the kernel because it may have been enabled by
985 * platform firmware. So if we are told to disable it, we should
986 * always disable it after setting the kernel's default
989 pci_disable_acs_redir(dev);
993 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
994 * @dev: PCI device to have its BARs restored
996 * Restore the BAR values for a given device, so as to make it
997 * accessible by its driver.
999 static void pci_restore_bars(struct pci_dev *dev)
1003 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
1004 pci_update_resource(dev, i);
1007 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
1009 if (pci_use_mid_pm())
1012 return acpi_pci_power_manageable(dev);
1015 static inline int platform_pci_set_power_state(struct pci_dev *dev,
1018 if (pci_use_mid_pm())
1019 return mid_pci_set_power_state(dev, t);
1021 return acpi_pci_set_power_state(dev, t);
1024 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
1026 if (pci_use_mid_pm())
1027 return mid_pci_get_power_state(dev);
1029 return acpi_pci_get_power_state(dev);
1032 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1034 if (!pci_use_mid_pm())
1035 acpi_pci_refresh_power_state(dev);
1038 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1040 if (pci_use_mid_pm())
1041 return PCI_POWER_ERROR;
1043 return acpi_pci_choose_state(dev);
1046 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1048 if (pci_use_mid_pm())
1049 return PCI_POWER_ERROR;
1051 return acpi_pci_wakeup(dev, enable);
1054 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1056 if (pci_use_mid_pm())
1059 return acpi_pci_need_resume(dev);
1062 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1064 if (pci_use_mid_pm())
1067 return acpi_pci_bridge_d3(dev);
1071 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
1073 * @dev: PCI device to handle.
1074 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1077 * -EINVAL if the requested state is invalid.
1078 * -EIO if device does not support PCI PM or its PM capabilities register has a
1079 * wrong version, or device doesn't support the requested state.
1080 * 0 if device already is in the requested state.
1081 * 0 if device's power state has been successfully changed.
1083 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1086 bool need_restore = false;
1088 /* Check if we're already there */
1089 if (dev->current_state == state)
1095 if (state < PCI_D0 || state > PCI_D3hot)
1099 * Validate transition: We can enter D0 from any state, but if
1100 * we're already in a low-power state, we can only go deeper. E.g.,
1101 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1102 * we'd have to go from D3 to D0, then to D1.
1104 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
1105 && dev->current_state > state) {
1106 pci_err(dev, "invalid power transition (from %s to %s)\n",
1107 pci_power_name(dev->current_state),
1108 pci_power_name(state));
1112 /* Check if this device supports the desired state */
1113 if ((state == PCI_D1 && !dev->d1_support)
1114 || (state == PCI_D2 && !dev->d2_support))
1117 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1118 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1119 pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
1120 pci_power_name(dev->current_state),
1121 pci_power_name(state));
1126 * If we're (effectively) in D3, force entire word to 0.
1127 * This doesn't affect PME_Status, disables PME_En, and
1128 * sets PowerState to 0.
1130 switch (dev->current_state) {
1134 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1139 case PCI_UNKNOWN: /* Boot-up */
1140 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
1141 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
1142 need_restore = true;
1143 fallthrough; /* force to D0 */
1149 /* Enter specified state */
1150 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1153 * Mandatory power management transition delays; see PCI PM 1.1
1156 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1157 pci_dev_d3_sleep(dev);
1158 else if (state == PCI_D2 || dev->current_state == PCI_D2)
1159 udelay(PCI_PM_D2_DELAY);
1161 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1162 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1163 if (dev->current_state != state)
1164 pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
1165 pci_power_name(dev->current_state),
1166 pci_power_name(state));
1169 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1170 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1171 * from D3hot to D0 _may_ perform an internal reset, thereby
1172 * going to "D0 Uninitialized" rather than "D0 Initialized".
1173 * For example, at least some versions of the 3c905B and the
1174 * 3c556B exhibit this behaviour.
1176 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1177 * devices in a D3hot state at boot. Consequently, we need to
1178 * restore at least the BARs so that the device will be
1179 * accessible to its driver.
1182 pci_restore_bars(dev);
1185 pcie_aspm_pm_state_change(dev->bus->self);
1191 * pci_update_current_state - Read power state of given device and cache it
1192 * @dev: PCI device to handle.
1193 * @state: State to cache in case the device doesn't have the PM capability
1195 * The power state is read from the PMCSR register, which however is
1196 * inaccessible in D3cold. The platform firmware is therefore queried first
1197 * to detect accessibility of the register. In case the platform firmware
1198 * reports an incorrect state or the device isn't power manageable by the
1199 * platform at all, we try to detect D3cold by testing accessibility of the
1200 * vendor ID in config space.
1202 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1204 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
1205 !pci_device_is_present(dev)) {
1206 dev->current_state = PCI_D3cold;
1207 } else if (dev->pm_cap) {
1210 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1211 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1213 dev->current_state = state;
1218 * pci_refresh_power_state - Refresh the given device's power state data
1219 * @dev: Target PCI device.
1221 * Ask the platform to refresh the devices power state information and invoke
1222 * pci_update_current_state() to update its current PCI power state.
1224 void pci_refresh_power_state(struct pci_dev *dev)
1226 platform_pci_refresh_power_state(dev);
1227 pci_update_current_state(dev, dev->current_state);
1231 * pci_platform_power_transition - Use platform to change device power state
1232 * @dev: PCI device to handle.
1233 * @state: State to put the device into.
1235 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1239 error = platform_pci_set_power_state(dev, state);
1241 pci_update_current_state(dev, state);
1242 else if (!dev->pm_cap) /* Fall back to PCI_D0 */
1243 dev->current_state = PCI_D0;
1247 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1249 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1251 pm_request_resume(&pci_dev->dev);
1256 * pci_resume_bus - Walk given bus and runtime resume devices on it
1257 * @bus: Top bus of the subtree to walk.
1259 void pci_resume_bus(struct pci_bus *bus)
1262 pci_walk_bus(bus, pci_resume_one, NULL);
1265 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1271 * After reset, the device should not silently discard config
1272 * requests, but it may still indicate that it needs more time by
1273 * responding to them with CRS completions. The Root Port will
1274 * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
1275 * the read (except when CRS SV is enabled and the read was for the
1276 * Vendor ID; in that case it synthesizes 0x0001 data).
1278 * Wait for the device to return a non-CRS completion. Read the
1279 * Command register instead of Vendor ID so we don't have to
1280 * contend with the CRS SV value.
1282 pci_read_config_dword(dev, PCI_COMMAND, &id);
1283 while (PCI_POSSIBLE_ERROR(id)) {
1284 if (delay > timeout) {
1285 pci_warn(dev, "not ready %dms after %s; giving up\n",
1286 delay - 1, reset_type);
1291 pci_info(dev, "not ready %dms after %s; waiting\n",
1292 delay - 1, reset_type);
1296 pci_read_config_dword(dev, PCI_COMMAND, &id);
1300 pci_info(dev, "ready %dms after %s\n", delay - 1,
1307 * pci_power_up - Put the given device into D0
1308 * @dev: PCI device to power up
1310 int pci_power_up(struct pci_dev *dev)
1312 pci_platform_power_transition(dev, PCI_D0);
1313 return pci_raw_set_power_state(dev, PCI_D0);
1317 * __pci_dev_set_current_state - Set current state of a PCI device
1318 * @dev: Device to handle
1319 * @data: pointer to state to be set
1321 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1323 pci_power_t state = *(pci_power_t *)data;
1325 dev->current_state = state;
1330 * pci_bus_set_current_state - Walk given bus and set current state of devices
1331 * @bus: Top bus of the subtree to walk.
1332 * @state: state to be set
1334 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1337 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1341 * pci_set_power_state - Set the power state of a PCI device
1342 * @dev: PCI device to handle.
1343 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1345 * Transition a device to a new power state, using the platform firmware and/or
1346 * the device's PCI PM registers.
1349 * -EINVAL if the requested state is invalid.
1350 * -EIO if device does not support PCI PM or its PM capabilities register has a
1351 * wrong version, or device doesn't support the requested state.
1352 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1353 * 0 if device already is in the requested state.
1354 * 0 if the transition is to D3 but D3 is not supported.
1355 * 0 if device's power state has been successfully changed.
1357 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1361 /* Bound the state we're entering */
1362 if (state > PCI_D3cold)
1364 else if (state < PCI_D0)
1366 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1369 * If the device or the parent bridge do not support PCI
1370 * PM, ignore the request if we're doing anything other
1371 * than putting it into D0 (which would only happen on
1376 /* Check if we're already there */
1377 if (dev->current_state == state)
1380 if (state == PCI_D0)
1381 return pci_power_up(dev);
1384 * This device is quirked not to be put into D3, so don't put it in
1387 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1391 * To put device in D3cold, we put device into D3hot in native
1392 * way, then put device into D3cold with platform ops
1394 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1397 if (pci_platform_power_transition(dev, state))
1400 /* Powering off a bridge may power off the whole hierarchy */
1401 if (state == PCI_D3cold)
1402 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1406 EXPORT_SYMBOL(pci_set_power_state);
1408 #define PCI_EXP_SAVE_REGS 7
1410 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1411 u16 cap, bool extended)
1413 struct pci_cap_saved_state *tmp;
1415 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1416 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1422 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1424 return _pci_find_saved_cap(dev, cap, false);
1427 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1429 return _pci_find_saved_cap(dev, cap, true);
1432 static int pci_save_pcie_state(struct pci_dev *dev)
1435 struct pci_cap_saved_state *save_state;
1438 if (!pci_is_pcie(dev))
1441 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1443 pci_err(dev, "buffer not found in %s\n", __func__);
1447 cap = (u16 *)&save_state->cap.data[0];
1448 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1449 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1450 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1451 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1452 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1453 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1454 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1459 void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1461 #ifdef CONFIG_PCIEASPM
1462 struct pci_dev *bridge;
1465 bridge = pci_upstream_bridge(dev);
1466 if (bridge && bridge->ltr_path) {
1467 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1468 if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1469 pci_dbg(bridge, "re-enabling LTR\n");
1470 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1471 PCI_EXP_DEVCTL2_LTR_EN);
1477 static void pci_restore_pcie_state(struct pci_dev *dev)
1480 struct pci_cap_saved_state *save_state;
1483 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1488 * Downstream ports reset the LTR enable bit when link goes down.
1489 * Check and re-configure the bit here before restoring device.
1490 * PCIe r5.0, sec 7.5.3.16.
1492 pci_bridge_reconfigure_ltr(dev);
1494 cap = (u16 *)&save_state->cap.data[0];
1495 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1496 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1497 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1498 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1499 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1500 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1501 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1504 static int pci_save_pcix_state(struct pci_dev *dev)
1507 struct pci_cap_saved_state *save_state;
1509 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1513 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1515 pci_err(dev, "buffer not found in %s\n", __func__);
1519 pci_read_config_word(dev, pos + PCI_X_CMD,
1520 (u16 *)save_state->cap.data);
1525 static void pci_restore_pcix_state(struct pci_dev *dev)
1528 struct pci_cap_saved_state *save_state;
1531 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1532 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1533 if (!save_state || !pos)
1535 cap = (u16 *)&save_state->cap.data[0];
1537 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1540 static void pci_save_ltr_state(struct pci_dev *dev)
1543 struct pci_cap_saved_state *save_state;
1546 if (!pci_is_pcie(dev))
1549 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1553 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1555 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1559 /* Some broken devices only support dword access to LTR */
1560 cap = &save_state->cap.data[0];
1561 pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
1564 static void pci_restore_ltr_state(struct pci_dev *dev)
1566 struct pci_cap_saved_state *save_state;
1570 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1571 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1572 if (!save_state || !ltr)
1575 /* Some broken devices only support dword access to LTR */
1576 cap = &save_state->cap.data[0];
1577 pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
1581 * pci_save_state - save the PCI configuration space of a device before
1583 * @dev: PCI device that we're dealing with
1585 int pci_save_state(struct pci_dev *dev)
1588 /* XXX: 100% dword access ok here? */
1589 for (i = 0; i < 16; i++) {
1590 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1591 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1592 i * 4, dev->saved_config_space[i]);
1594 dev->state_saved = true;
1596 i = pci_save_pcie_state(dev);
1600 i = pci_save_pcix_state(dev);
1604 pci_save_ltr_state(dev);
1605 pci_save_dpc_state(dev);
1606 pci_save_aer_state(dev);
1607 pci_save_ptm_state(dev);
1608 return pci_save_vc_state(dev);
1610 EXPORT_SYMBOL(pci_save_state);
1612 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1613 u32 saved_val, int retry, bool force)
1617 pci_read_config_dword(pdev, offset, &val);
1618 if (!force && val == saved_val)
1622 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1623 offset, val, saved_val);
1624 pci_write_config_dword(pdev, offset, saved_val);
1628 pci_read_config_dword(pdev, offset, &val);
1629 if (val == saved_val)
1636 static void pci_restore_config_space_range(struct pci_dev *pdev,
1637 int start, int end, int retry,
1642 for (index = end; index >= start; index--)
1643 pci_restore_config_dword(pdev, 4 * index,
1644 pdev->saved_config_space[index],
1648 static void pci_restore_config_space(struct pci_dev *pdev)
1650 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1651 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1652 /* Restore BARs before the command register. */
1653 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1654 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1655 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1656 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1659 * Force rewriting of prefetch registers to avoid S3 resume
1660 * issues on Intel PCI bridges that occur when these
1661 * registers are not explicitly written.
1663 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1664 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1666 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1670 static void pci_restore_rebar_state(struct pci_dev *pdev)
1672 unsigned int pos, nbars, i;
1675 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1679 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1680 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1681 PCI_REBAR_CTRL_NBAR_SHIFT;
1683 for (i = 0; i < nbars; i++, pos += 8) {
1684 struct resource *res;
1687 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1688 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1689 res = pdev->resource + bar_idx;
1690 size = pci_rebar_bytes_to_size(resource_size(res));
1691 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1692 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1693 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1698 * pci_restore_state - Restore the saved state of a PCI device
1699 * @dev: PCI device that we're dealing with
1701 void pci_restore_state(struct pci_dev *dev)
1703 if (!dev->state_saved)
1707 * Restore max latencies (in the LTR capability) before enabling
1708 * LTR itself (in the PCIe capability).
1710 pci_restore_ltr_state(dev);
1712 pci_restore_pcie_state(dev);
1713 pci_restore_pasid_state(dev);
1714 pci_restore_pri_state(dev);
1715 pci_restore_ats_state(dev);
1716 pci_restore_vc_state(dev);
1717 pci_restore_rebar_state(dev);
1718 pci_restore_dpc_state(dev);
1719 pci_restore_ptm_state(dev);
1721 pci_aer_clear_status(dev);
1722 pci_restore_aer_state(dev);
1724 pci_restore_config_space(dev);
1726 pci_restore_pcix_state(dev);
1727 pci_restore_msi_state(dev);
1729 /* Restore ACS and IOV configuration state */
1730 pci_enable_acs(dev);
1731 pci_restore_iov_state(dev);
1733 dev->state_saved = false;
1735 EXPORT_SYMBOL(pci_restore_state);
1737 struct pci_saved_state {
1738 u32 config_space[16];
1739 struct pci_cap_saved_data cap[];
1743 * pci_store_saved_state - Allocate and return an opaque struct containing
1744 * the device saved state.
1745 * @dev: PCI device that we're dealing with
1747 * Return NULL if no state or error.
1749 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1751 struct pci_saved_state *state;
1752 struct pci_cap_saved_state *tmp;
1753 struct pci_cap_saved_data *cap;
1756 if (!dev->state_saved)
1759 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1761 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1762 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1764 state = kzalloc(size, GFP_KERNEL);
1768 memcpy(state->config_space, dev->saved_config_space,
1769 sizeof(state->config_space));
1772 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1773 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1774 memcpy(cap, &tmp->cap, len);
1775 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1777 /* Empty cap_save terminates list */
1781 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1784 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1785 * @dev: PCI device that we're dealing with
1786 * @state: Saved state returned from pci_store_saved_state()
1788 int pci_load_saved_state(struct pci_dev *dev,
1789 struct pci_saved_state *state)
1791 struct pci_cap_saved_data *cap;
1793 dev->state_saved = false;
1798 memcpy(dev->saved_config_space, state->config_space,
1799 sizeof(state->config_space));
1803 struct pci_cap_saved_state *tmp;
1805 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1806 if (!tmp || tmp->cap.size != cap->size)
1809 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1810 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1811 sizeof(struct pci_cap_saved_data) + cap->size);
1814 dev->state_saved = true;
1817 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1820 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1821 * and free the memory allocated for it.
1822 * @dev: PCI device that we're dealing with
1823 * @state: Pointer to saved state returned from pci_store_saved_state()
1825 int pci_load_and_free_saved_state(struct pci_dev *dev,
1826 struct pci_saved_state **state)
1828 int ret = pci_load_saved_state(dev, *state);
1833 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1835 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1837 return pci_enable_resources(dev, bars);
1840 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1843 struct pci_dev *bridge;
1847 err = pci_set_power_state(dev, PCI_D0);
1848 if (err < 0 && err != -EIO)
1851 bridge = pci_upstream_bridge(dev);
1853 pcie_aspm_powersave_config_link(bridge);
1855 err = pcibios_enable_device(dev, bars);
1858 pci_fixup_device(pci_fixup_enable, dev);
1860 if (dev->msi_enabled || dev->msix_enabled)
1863 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1865 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1866 if (cmd & PCI_COMMAND_INTX_DISABLE)
1867 pci_write_config_word(dev, PCI_COMMAND,
1868 cmd & ~PCI_COMMAND_INTX_DISABLE);
1875 * pci_reenable_device - Resume abandoned device
1876 * @dev: PCI device to be resumed
1878 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1879 * to be called by normal code, write proper resume handler and use it instead.
1881 int pci_reenable_device(struct pci_dev *dev)
1883 if (pci_is_enabled(dev))
1884 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1887 EXPORT_SYMBOL(pci_reenable_device);
1889 static void pci_enable_bridge(struct pci_dev *dev)
1891 struct pci_dev *bridge;
1894 bridge = pci_upstream_bridge(dev);
1896 pci_enable_bridge(bridge);
1898 if (pci_is_enabled(dev)) {
1899 if (!dev->is_busmaster)
1900 pci_set_master(dev);
1904 retval = pci_enable_device(dev);
1906 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1908 pci_set_master(dev);
1911 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1913 struct pci_dev *bridge;
1918 * Power state could be unknown at this point, either due to a fresh
1919 * boot or a device removal call. So get the current power state
1920 * so that things like MSI message writing will behave as expected
1921 * (e.g. if the device really is in D0 at enable time).
1923 pci_update_current_state(dev, dev->current_state);
1925 if (atomic_inc_return(&dev->enable_cnt) > 1)
1926 return 0; /* already enabled */
1928 bridge = pci_upstream_bridge(dev);
1930 pci_enable_bridge(bridge);
1932 /* only skip sriov related */
1933 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1934 if (dev->resource[i].flags & flags)
1936 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1937 if (dev->resource[i].flags & flags)
1940 err = do_pci_enable_device(dev, bars);
1942 atomic_dec(&dev->enable_cnt);
1947 * pci_enable_device_io - Initialize a device for use with IO space
1948 * @dev: PCI device to be initialized
1950 * Initialize device before it's used by a driver. Ask low-level code
1951 * to enable I/O resources. Wake up the device if it was suspended.
1952 * Beware, this function can fail.
1954 int pci_enable_device_io(struct pci_dev *dev)
1956 return pci_enable_device_flags(dev, IORESOURCE_IO);
1958 EXPORT_SYMBOL(pci_enable_device_io);
1961 * pci_enable_device_mem - Initialize a device for use with Memory space
1962 * @dev: PCI device to be initialized
1964 * Initialize device before it's used by a driver. Ask low-level code
1965 * to enable Memory resources. Wake up the device if it was suspended.
1966 * Beware, this function can fail.
1968 int pci_enable_device_mem(struct pci_dev *dev)
1970 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1972 EXPORT_SYMBOL(pci_enable_device_mem);
1975 * pci_enable_device - Initialize device before it's used by a driver.
1976 * @dev: PCI device to be initialized
1978 * Initialize device before it's used by a driver. Ask low-level code
1979 * to enable I/O and memory. Wake up the device if it was suspended.
1980 * Beware, this function can fail.
1982 * Note we don't actually enable the device many times if we call
1983 * this function repeatedly (we just increment the count).
1985 int pci_enable_device(struct pci_dev *dev)
1987 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1989 EXPORT_SYMBOL(pci_enable_device);
1992 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1993 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1994 * there's no need to track it separately. pci_devres is initialized
1995 * when a device is enabled using managed PCI device enable interface.
1998 unsigned int enabled:1;
1999 unsigned int pinned:1;
2000 unsigned int orig_intx:1;
2001 unsigned int restore_intx:1;
2006 static void pcim_release(struct device *gendev, void *res)
2008 struct pci_dev *dev = to_pci_dev(gendev);
2009 struct pci_devres *this = res;
2012 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2013 if (this->region_mask & (1 << i))
2014 pci_release_region(dev, i);
2019 if (this->restore_intx)
2020 pci_intx(dev, this->orig_intx);
2022 if (this->enabled && !this->pinned)
2023 pci_disable_device(dev);
2026 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2028 struct pci_devres *dr, *new_dr;
2030 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2034 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2037 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2040 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2042 if (pci_is_managed(pdev))
2043 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2048 * pcim_enable_device - Managed pci_enable_device()
2049 * @pdev: PCI device to be initialized
2051 * Managed pci_enable_device().
2053 int pcim_enable_device(struct pci_dev *pdev)
2055 struct pci_devres *dr;
2058 dr = get_pci_dr(pdev);
2064 rc = pci_enable_device(pdev);
2066 pdev->is_managed = 1;
2071 EXPORT_SYMBOL(pcim_enable_device);
2074 * pcim_pin_device - Pin managed PCI device
2075 * @pdev: PCI device to pin
2077 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2078 * driver detach. @pdev must have been enabled with
2079 * pcim_enable_device().
2081 void pcim_pin_device(struct pci_dev *pdev)
2083 struct pci_devres *dr;
2085 dr = find_pci_dr(pdev);
2086 WARN_ON(!dr || !dr->enabled);
2090 EXPORT_SYMBOL(pcim_pin_device);
2093 * pcibios_device_add - provide arch specific hooks when adding device dev
2094 * @dev: the PCI device being added
2096 * Permits the platform to provide architecture specific functionality when
2097 * devices are added. This is the default implementation. Architecture
2098 * implementations can override this.
2100 int __weak pcibios_device_add(struct pci_dev *dev)
2106 * pcibios_release_device - provide arch specific hooks when releasing
2108 * @dev: the PCI device being released
2110 * Permits the platform to provide architecture specific functionality when
2111 * devices are released. This is the default implementation. Architecture
2112 * implementations can override this.
2114 void __weak pcibios_release_device(struct pci_dev *dev) {}
2117 * pcibios_disable_device - disable arch specific PCI resources for device dev
2118 * @dev: the PCI device to disable
2120 * Disables architecture specific PCI resources for the device. This
2121 * is the default implementation. Architecture implementations can
2124 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2127 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2128 * @irq: ISA IRQ to penalize
2129 * @active: IRQ active or not
2131 * Permits the platform to provide architecture-specific functionality when
2132 * penalizing ISA IRQs. This is the default implementation. Architecture
2133 * implementations can override this.
2135 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2137 static void do_pci_disable_device(struct pci_dev *dev)
2141 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2142 if (pci_command & PCI_COMMAND_MASTER) {
2143 pci_command &= ~PCI_COMMAND_MASTER;
2144 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2147 pcibios_disable_device(dev);
2151 * pci_disable_enabled_device - Disable device without updating enable_cnt
2152 * @dev: PCI device to disable
2154 * NOTE: This function is a backend of PCI power management routines and is
2155 * not supposed to be called drivers.
2157 void pci_disable_enabled_device(struct pci_dev *dev)
2159 if (pci_is_enabled(dev))
2160 do_pci_disable_device(dev);
2164 * pci_disable_device - Disable PCI device after use
2165 * @dev: PCI device to be disabled
2167 * Signal to the system that the PCI device is not in use by the system
2168 * anymore. This only involves disabling PCI bus-mastering, if active.
2170 * Note we don't actually disable the device until all callers of
2171 * pci_enable_device() have called pci_disable_device().
2173 void pci_disable_device(struct pci_dev *dev)
2175 struct pci_devres *dr;
2177 dr = find_pci_dr(dev);
2181 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2182 "disabling already-disabled device");
2184 if (atomic_dec_return(&dev->enable_cnt) != 0)
2187 do_pci_disable_device(dev);
2189 dev->is_busmaster = 0;
2191 EXPORT_SYMBOL(pci_disable_device);
2194 * pcibios_set_pcie_reset_state - set reset state for device dev
2195 * @dev: the PCIe device reset
2196 * @state: Reset state to enter into
2198 * Set the PCIe reset state for the device. This is the default
2199 * implementation. Architecture implementations can override this.
2201 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2202 enum pcie_reset_state state)
2208 * pci_set_pcie_reset_state - set reset state for device dev
2209 * @dev: the PCIe device reset
2210 * @state: Reset state to enter into
2212 * Sets the PCI reset state for the device.
2214 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2216 return pcibios_set_pcie_reset_state(dev, state);
2218 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2220 #ifdef CONFIG_PCIEAER
2221 void pcie_clear_device_status(struct pci_dev *dev)
2225 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2226 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2231 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2232 * @dev: PCIe root port or event collector.
2234 void pcie_clear_root_pme_status(struct pci_dev *dev)
2236 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2240 * pci_check_pme_status - Check if given device has generated PME.
2241 * @dev: Device to check.
2243 * Check the PME status of the device and if set, clear it and clear PME enable
2244 * (if set). Return 'true' if PME status and PME enable were both set or
2245 * 'false' otherwise.
2247 bool pci_check_pme_status(struct pci_dev *dev)
2256 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2257 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2258 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2261 /* Clear PME status. */
2262 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2263 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2264 /* Disable PME to avoid interrupt flood. */
2265 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2269 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2275 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2276 * @dev: Device to handle.
2277 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2279 * Check if @dev has generated PME and queue a resume request for it in that
2282 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2284 if (pme_poll_reset && dev->pme_poll)
2285 dev->pme_poll = false;
2287 if (pci_check_pme_status(dev)) {
2288 pci_wakeup_event(dev);
2289 pm_request_resume(&dev->dev);
2295 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2296 * @bus: Top bus of the subtree to walk.
2298 void pci_pme_wakeup_bus(struct pci_bus *bus)
2301 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2306 * pci_pme_capable - check the capability of PCI device to generate PME#
2307 * @dev: PCI device to handle.
2308 * @state: PCI state from which device will issue PME#.
2310 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2315 return !!(dev->pme_support & (1 << state));
2317 EXPORT_SYMBOL(pci_pme_capable);
2319 static void pci_pme_list_scan(struct work_struct *work)
2321 struct pci_pme_device *pme_dev, *n;
2323 mutex_lock(&pci_pme_list_mutex);
2324 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2325 if (pme_dev->dev->pme_poll) {
2326 struct pci_dev *bridge;
2328 bridge = pme_dev->dev->bus->self;
2330 * If bridge is in low power state, the
2331 * configuration space of subordinate devices
2332 * may be not accessible
2334 if (bridge && bridge->current_state != PCI_D0)
2337 * If the device is in D3cold it should not be
2340 if (pme_dev->dev->current_state == PCI_D3cold)
2343 pci_pme_wakeup(pme_dev->dev, NULL);
2345 list_del(&pme_dev->list);
2349 if (!list_empty(&pci_pme_list))
2350 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2351 msecs_to_jiffies(PME_TIMEOUT));
2352 mutex_unlock(&pci_pme_list_mutex);
2355 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2359 if (!dev->pme_support)
2362 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2363 /* Clear PME_Status by writing 1 to it and enable PME# */
2364 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2366 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2368 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2372 * pci_pme_restore - Restore PME configuration after config space restore.
2373 * @dev: PCI device to update.
2375 void pci_pme_restore(struct pci_dev *dev)
2379 if (!dev->pme_support)
2382 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2383 if (dev->wakeup_prepared) {
2384 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2385 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2387 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2388 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2390 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2394 * pci_pme_active - enable or disable PCI device's PME# function
2395 * @dev: PCI device to handle.
2396 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2398 * The caller must verify that the device is capable of generating PME# before
2399 * calling this function with @enable equal to 'true'.
2401 void pci_pme_active(struct pci_dev *dev, bool enable)
2403 __pci_pme_active(dev, enable);
2406 * PCI (as opposed to PCIe) PME requires that the device have
2407 * its PME# line hooked up correctly. Not all hardware vendors
2408 * do this, so the PME never gets delivered and the device
2409 * remains asleep. The easiest way around this is to
2410 * periodically walk the list of suspended devices and check
2411 * whether any have their PME flag set. The assumption is that
2412 * we'll wake up often enough anyway that this won't be a huge
2413 * hit, and the power savings from the devices will still be a
2416 * Although PCIe uses in-band PME message instead of PME# line
2417 * to report PME, PME does not work for some PCIe devices in
2418 * reality. For example, there are devices that set their PME
2419 * status bits, but don't really bother to send a PME message;
2420 * there are PCI Express Root Ports that don't bother to
2421 * trigger interrupts when they receive PME messages from the
2422 * devices below. So PME poll is used for PCIe devices too.
2425 if (dev->pme_poll) {
2426 struct pci_pme_device *pme_dev;
2428 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2431 pci_warn(dev, "can't enable PME#\n");
2435 mutex_lock(&pci_pme_list_mutex);
2436 list_add(&pme_dev->list, &pci_pme_list);
2437 if (list_is_singular(&pci_pme_list))
2438 queue_delayed_work(system_freezable_wq,
2440 msecs_to_jiffies(PME_TIMEOUT));
2441 mutex_unlock(&pci_pme_list_mutex);
2443 mutex_lock(&pci_pme_list_mutex);
2444 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2445 if (pme_dev->dev == dev) {
2446 list_del(&pme_dev->list);
2451 mutex_unlock(&pci_pme_list_mutex);
2455 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2457 EXPORT_SYMBOL(pci_pme_active);
2460 * __pci_enable_wake - enable PCI device as wakeup event source
2461 * @dev: PCI device affected
2462 * @state: PCI state from which device will issue wakeup events
2463 * @enable: True to enable event generation; false to disable
2465 * This enables the device as a wakeup event source, or disables it.
2466 * When such events involves platform-specific hooks, those hooks are
2467 * called automatically by this routine.
2469 * Devices with legacy power management (no standard PCI PM capabilities)
2470 * always require such platform hooks.
2473 * 0 is returned on success
2474 * -EINVAL is returned if device is not supposed to wake up the system
2475 * Error code depending on the platform is returned if both the platform and
2476 * the native mechanism fail to enable the generation of wake-up events
2478 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2483 * Bridges that are not power-manageable directly only signal
2484 * wakeup on behalf of subordinate devices which is set up
2485 * elsewhere, so skip them. However, bridges that are
2486 * power-manageable may signal wakeup for themselves (for example,
2487 * on a hotplug event) and they need to be covered here.
2489 if (!pci_power_manageable(dev))
2492 /* Don't do the same thing twice in a row for one device. */
2493 if (!!enable == !!dev->wakeup_prepared)
2497 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2498 * Anderson we should be doing PME# wake enable followed by ACPI wake
2499 * enable. To disable wake-up we call the platform first, for symmetry.
2506 * Enable PME signaling if the device can signal PME from
2507 * D3cold regardless of whether or not it can signal PME from
2508 * the current target state, because that will allow it to
2509 * signal PME when the hierarchy above it goes into D3cold and
2510 * the device itself ends up in D3cold as a result of that.
2512 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2513 pci_pme_active(dev, true);
2516 error = platform_pci_set_wakeup(dev, true);
2520 dev->wakeup_prepared = true;
2522 platform_pci_set_wakeup(dev, false);
2523 pci_pme_active(dev, false);
2524 dev->wakeup_prepared = false;
2531 * pci_enable_wake - change wakeup settings for a PCI device
2532 * @pci_dev: Target device
2533 * @state: PCI state from which device will issue wakeup events
2534 * @enable: Whether or not to enable event generation
2536 * If @enable is set, check device_may_wakeup() for the device before calling
2537 * __pci_enable_wake() for it.
2539 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2541 if (enable && !device_may_wakeup(&pci_dev->dev))
2544 return __pci_enable_wake(pci_dev, state, enable);
2546 EXPORT_SYMBOL(pci_enable_wake);
2549 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2550 * @dev: PCI device to prepare
2551 * @enable: True to enable wake-up event generation; false to disable
2553 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2554 * and this function allows them to set that up cleanly - pci_enable_wake()
2555 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2556 * ordering constraints.
2558 * This function only returns error code if the device is not allowed to wake
2559 * up the system from sleep or it is not capable of generating PME# from both
2560 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2562 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2564 return pci_pme_capable(dev, PCI_D3cold) ?
2565 pci_enable_wake(dev, PCI_D3cold, enable) :
2566 pci_enable_wake(dev, PCI_D3hot, enable);
2568 EXPORT_SYMBOL(pci_wake_from_d3);
2571 * pci_target_state - find an appropriate low power state for a given PCI dev
2573 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2575 * Use underlying platform code to find a supported low power state for @dev.
2576 * If the platform can't manage @dev, return the deepest state from which it
2577 * can generate wake events, based on any available PME info.
2579 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2581 if (platform_pci_power_manageable(dev)) {
2583 * Call the platform to find the target state for the device.
2585 pci_power_t state = platform_pci_choose_state(dev);
2588 case PCI_POWER_ERROR:
2594 if (pci_no_d1d2(dev))
2602 * If the device is in D3cold even though it's not power-manageable by
2603 * the platform, it may have been powered down by non-standard means.
2604 * Best to let it slumber.
2606 if (dev->current_state == PCI_D3cold)
2608 else if (!dev->pm_cap)
2611 if (wakeup && dev->pme_support) {
2612 pci_power_t state = PCI_D3hot;
2615 * Find the deepest state from which the device can generate
2618 while (state && !(dev->pme_support & (1 << state)))
2623 else if (dev->pme_support & 1)
2631 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2632 * into a sleep state
2633 * @dev: Device to handle.
2635 * Choose the power state appropriate for the device depending on whether
2636 * it can wake up the system and/or is power manageable by the platform
2637 * (PCI_D3hot is the default) and put the device into that state.
2639 int pci_prepare_to_sleep(struct pci_dev *dev)
2641 bool wakeup = device_may_wakeup(&dev->dev);
2642 pci_power_t target_state = pci_target_state(dev, wakeup);
2645 if (target_state == PCI_POWER_ERROR)
2649 * There are systems (for example, Intel mobile chips since Coffee
2650 * Lake) where the power drawn while suspended can be significantly
2651 * reduced by disabling PTM on PCIe root ports as this allows the
2652 * port to enter a lower-power PM state and the SoC to reach a
2653 * lower-power idle state as a whole.
2655 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2656 pci_disable_ptm(dev);
2658 pci_enable_wake(dev, target_state, wakeup);
2660 error = pci_set_power_state(dev, target_state);
2663 pci_enable_wake(dev, target_state, false);
2664 pci_restore_ptm_state(dev);
2669 EXPORT_SYMBOL(pci_prepare_to_sleep);
2672 * pci_back_from_sleep - turn PCI device on during system-wide transition
2673 * into working state
2674 * @dev: Device to handle.
2676 * Disable device's system wake-up capability and put it into D0.
2678 int pci_back_from_sleep(struct pci_dev *dev)
2680 int ret = pci_set_power_state(dev, PCI_D0);
2685 pci_enable_wake(dev, PCI_D0, false);
2688 EXPORT_SYMBOL(pci_back_from_sleep);
2691 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2692 * @dev: PCI device being suspended.
2694 * Prepare @dev to generate wake-up events at run time and put it into a low
2697 int pci_finish_runtime_suspend(struct pci_dev *dev)
2699 pci_power_t target_state;
2702 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2703 if (target_state == PCI_POWER_ERROR)
2706 dev->runtime_d3cold = target_state == PCI_D3cold;
2709 * There are systems (for example, Intel mobile chips since Coffee
2710 * Lake) where the power drawn while suspended can be significantly
2711 * reduced by disabling PTM on PCIe root ports as this allows the
2712 * port to enter a lower-power PM state and the SoC to reach a
2713 * lower-power idle state as a whole.
2715 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2716 pci_disable_ptm(dev);
2718 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2720 error = pci_set_power_state(dev, target_state);
2723 pci_enable_wake(dev, target_state, false);
2724 pci_restore_ptm_state(dev);
2725 dev->runtime_d3cold = false;
2732 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2733 * @dev: Device to check.
2735 * Return true if the device itself is capable of generating wake-up events
2736 * (through the platform or using the native PCIe PME) or if the device supports
2737 * PME and one of its upstream bridges can generate wake-up events.
2739 bool pci_dev_run_wake(struct pci_dev *dev)
2741 struct pci_bus *bus = dev->bus;
2743 if (!dev->pme_support)
2746 /* PME-capable in principle, but not from the target power state */
2747 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2750 if (device_can_wakeup(&dev->dev))
2753 while (bus->parent) {
2754 struct pci_dev *bridge = bus->self;
2756 if (device_can_wakeup(&bridge->dev))
2762 /* We have reached the root bus. */
2764 return device_can_wakeup(bus->bridge);
2768 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2771 * pci_dev_need_resume - Check if it is necessary to resume the device.
2772 * @pci_dev: Device to check.
2774 * Return 'true' if the device is not runtime-suspended or it has to be
2775 * reconfigured due to wakeup settings difference between system and runtime
2776 * suspend, or the current power state of it is not suitable for the upcoming
2777 * (system-wide) transition.
2779 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2781 struct device *dev = &pci_dev->dev;
2782 pci_power_t target_state;
2784 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2787 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2790 * If the earlier platform check has not triggered, D3cold is just power
2791 * removal on top of D3hot, so no need to resume the device in that
2794 return target_state != pci_dev->current_state &&
2795 target_state != PCI_D3cold &&
2796 pci_dev->current_state != PCI_D3hot;
2800 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2801 * @pci_dev: Device to check.
2803 * If the device is suspended and it is not configured for system wakeup,
2804 * disable PME for it to prevent it from waking up the system unnecessarily.
2806 * Note that if the device's power state is D3cold and the platform check in
2807 * pci_dev_need_resume() has not triggered, the device's configuration need not
2810 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2812 struct device *dev = &pci_dev->dev;
2814 spin_lock_irq(&dev->power.lock);
2816 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2817 pci_dev->current_state < PCI_D3cold)
2818 __pci_pme_active(pci_dev, false);
2820 spin_unlock_irq(&dev->power.lock);
2824 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2825 * @pci_dev: Device to handle.
2827 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2828 * it might have been disabled during the prepare phase of system suspend if
2829 * the device was not configured for system wakeup.
2831 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2833 struct device *dev = &pci_dev->dev;
2835 if (!pci_dev_run_wake(pci_dev))
2838 spin_lock_irq(&dev->power.lock);
2840 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2841 __pci_pme_active(pci_dev, true);
2843 spin_unlock_irq(&dev->power.lock);
2847 * pci_choose_state - Choose the power state of a PCI device.
2848 * @dev: Target PCI device.
2849 * @state: Target state for the whole system.
2851 * Returns PCI power state suitable for @dev and @state.
2853 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
2855 if (state.event == PM_EVENT_ON)
2858 return pci_target_state(dev, false);
2860 EXPORT_SYMBOL(pci_choose_state);
2862 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2864 struct device *dev = &pdev->dev;
2865 struct device *parent = dev->parent;
2868 pm_runtime_get_sync(parent);
2869 pm_runtime_get_noresume(dev);
2871 * pdev->current_state is set to PCI_D3cold during suspending,
2872 * so wait until suspending completes
2874 pm_runtime_barrier(dev);
2876 * Only need to resume devices in D3cold, because config
2877 * registers are still accessible for devices suspended but
2880 if (pdev->current_state == PCI_D3cold)
2881 pm_runtime_resume(dev);
2884 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2886 struct device *dev = &pdev->dev;
2887 struct device *parent = dev->parent;
2889 pm_runtime_put(dev);
2891 pm_runtime_put_sync(parent);
2894 static const struct dmi_system_id bridge_d3_blacklist[] = {
2898 * Gigabyte X299 root port is not marked as hotplug capable
2899 * which allows Linux to power manage it. However, this
2900 * confuses the BIOS SMI handler so don't power manage root
2901 * ports on that system.
2903 .ident = "X299 DESIGNARE EX-CF",
2905 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2906 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2914 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2915 * @bridge: Bridge to check
2917 * This function checks if it is possible to move the bridge to D3.
2918 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2920 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2922 if (!pci_is_pcie(bridge))
2925 switch (pci_pcie_type(bridge)) {
2926 case PCI_EXP_TYPE_ROOT_PORT:
2927 case PCI_EXP_TYPE_UPSTREAM:
2928 case PCI_EXP_TYPE_DOWNSTREAM:
2929 if (pci_bridge_d3_disable)
2933 * Hotplug ports handled by firmware in System Management Mode
2934 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2936 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2939 if (pci_bridge_d3_force)
2942 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2943 if (bridge->is_thunderbolt)
2946 /* Platform might know better if the bridge supports D3 */
2947 if (platform_pci_bridge_d3(bridge))
2951 * Hotplug ports handled natively by the OS were not validated
2952 * by vendors for runtime D3 at least until 2018 because there
2953 * was no OS support.
2955 if (bridge->is_hotplug_bridge)
2958 if (dmi_check_system(bridge_d3_blacklist))
2962 * It should be safe to put PCIe ports from 2015 or newer
2965 if (dmi_get_bios_year() >= 2015)
2973 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2975 bool *d3cold_ok = data;
2977 if (/* The device needs to be allowed to go D3cold ... */
2978 dev->no_d3cold || !dev->d3cold_allowed ||
2980 /* ... and if it is wakeup capable to do so from D3cold. */
2981 (device_may_wakeup(&dev->dev) &&
2982 !pci_pme_capable(dev, PCI_D3cold)) ||
2984 /* If it is a bridge it must be allowed to go to D3. */
2985 !pci_power_manageable(dev))
2993 * pci_bridge_d3_update - Update bridge D3 capabilities
2994 * @dev: PCI device which is changed
2996 * Update upstream bridge PM capabilities accordingly depending on if the
2997 * device PM configuration was changed or the device is being removed. The
2998 * change is also propagated upstream.
3000 void pci_bridge_d3_update(struct pci_dev *dev)
3002 bool remove = !device_is_registered(&dev->dev);
3003 struct pci_dev *bridge;
3004 bool d3cold_ok = true;
3006 bridge = pci_upstream_bridge(dev);
3007 if (!bridge || !pci_bridge_d3_possible(bridge))
3011 * If D3 is currently allowed for the bridge, removing one of its
3012 * children won't change that.
3014 if (remove && bridge->bridge_d3)
3018 * If D3 is currently allowed for the bridge and a child is added or
3019 * changed, disallowance of D3 can only be caused by that child, so
3020 * we only need to check that single device, not any of its siblings.
3022 * If D3 is currently not allowed for the bridge, checking the device
3023 * first may allow us to skip checking its siblings.
3026 pci_dev_check_d3cold(dev, &d3cold_ok);
3029 * If D3 is currently not allowed for the bridge, this may be caused
3030 * either by the device being changed/removed or any of its siblings,
3031 * so we need to go through all children to find out if one of them
3032 * continues to block D3.
3034 if (d3cold_ok && !bridge->bridge_d3)
3035 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3038 if (bridge->bridge_d3 != d3cold_ok) {
3039 bridge->bridge_d3 = d3cold_ok;
3040 /* Propagate change to upstream bridges */
3041 pci_bridge_d3_update(bridge);
3046 * pci_d3cold_enable - Enable D3cold for device
3047 * @dev: PCI device to handle
3049 * This function can be used in drivers to enable D3cold from the device
3050 * they handle. It also updates upstream PCI bridge PM capabilities
3053 void pci_d3cold_enable(struct pci_dev *dev)
3055 if (dev->no_d3cold) {
3056 dev->no_d3cold = false;
3057 pci_bridge_d3_update(dev);
3060 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3063 * pci_d3cold_disable - Disable D3cold for device
3064 * @dev: PCI device to handle
3066 * This function can be used in drivers to disable D3cold from the device
3067 * they handle. It also updates upstream PCI bridge PM capabilities
3070 void pci_d3cold_disable(struct pci_dev *dev)
3072 if (!dev->no_d3cold) {
3073 dev->no_d3cold = true;
3074 pci_bridge_d3_update(dev);
3077 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3080 * pci_pm_init - Initialize PM functions of given PCI device
3081 * @dev: PCI device to handle.
3083 void pci_pm_init(struct pci_dev *dev)
3089 pm_runtime_forbid(&dev->dev);
3090 pm_runtime_set_active(&dev->dev);
3091 pm_runtime_enable(&dev->dev);
3092 device_enable_async_suspend(&dev->dev);
3093 dev->wakeup_prepared = false;
3096 dev->pme_support = 0;
3098 /* find PCI PM capability in list */
3099 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3102 /* Check device's ability to generate PME# */
3103 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3105 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3106 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3107 pmc & PCI_PM_CAP_VER_MASK);
3112 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3113 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3114 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3115 dev->d3cold_allowed = true;
3117 dev->d1_support = false;
3118 dev->d2_support = false;
3119 if (!pci_no_d1d2(dev)) {
3120 if (pmc & PCI_PM_CAP_D1)
3121 dev->d1_support = true;
3122 if (pmc & PCI_PM_CAP_D2)
3123 dev->d2_support = true;
3125 if (dev->d1_support || dev->d2_support)
3126 pci_info(dev, "supports%s%s\n",
3127 dev->d1_support ? " D1" : "",
3128 dev->d2_support ? " D2" : "");
3131 pmc &= PCI_PM_CAP_PME_MASK;
3133 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3134 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3135 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3136 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3137 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3138 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3139 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3140 dev->pme_poll = true;
3142 * Make device's PM flags reflect the wake-up capability, but
3143 * let the user space enable it to wake up the system as needed.
3145 device_set_wakeup_capable(&dev->dev, true);
3146 /* Disable the PME# generation functionality */
3147 pci_pme_active(dev, false);
3150 pci_read_config_word(dev, PCI_STATUS, &status);
3151 if (status & PCI_STATUS_IMM_READY)
3155 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3157 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3161 case PCI_EA_P_VF_MEM:
3162 flags |= IORESOURCE_MEM;
3164 case PCI_EA_P_MEM_PREFETCH:
3165 case PCI_EA_P_VF_MEM_PREFETCH:
3166 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3169 flags |= IORESOURCE_IO;
3178 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3181 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3182 return &dev->resource[bei];
3183 #ifdef CONFIG_PCI_IOV
3184 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3185 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3186 return &dev->resource[PCI_IOV_RESOURCES +
3187 bei - PCI_EA_BEI_VF_BAR0];
3189 else if (bei == PCI_EA_BEI_ROM)
3190 return &dev->resource[PCI_ROM_RESOURCE];
3195 /* Read an Enhanced Allocation (EA) entry */
3196 static int pci_ea_read(struct pci_dev *dev, int offset)
3198 struct resource *res;
3199 int ent_size, ent_offset = offset;
3200 resource_size_t start, end;
3201 unsigned long flags;
3202 u32 dw0, bei, base, max_offset;
3204 bool support_64 = (sizeof(resource_size_t) >= 8);
3206 pci_read_config_dword(dev, ent_offset, &dw0);
3209 /* Entry size field indicates DWORDs after 1st */
3210 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3212 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3215 bei = (dw0 & PCI_EA_BEI) >> 4;
3216 prop = (dw0 & PCI_EA_PP) >> 8;
3219 * If the Property is in the reserved range, try the Secondary
3222 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3223 prop = (dw0 & PCI_EA_SP) >> 16;
3224 if (prop > PCI_EA_P_BRIDGE_IO)
3227 res = pci_ea_get_resource(dev, bei, prop);
3229 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3233 flags = pci_ea_flags(dev, prop);
3235 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3240 pci_read_config_dword(dev, ent_offset, &base);
3241 start = (base & PCI_EA_FIELD_MASK);
3244 /* Read MaxOffset */
3245 pci_read_config_dword(dev, ent_offset, &max_offset);
3248 /* Read Base MSBs (if 64-bit entry) */
3249 if (base & PCI_EA_IS_64) {
3252 pci_read_config_dword(dev, ent_offset, &base_upper);
3255 flags |= IORESOURCE_MEM_64;
3257 /* entry starts above 32-bit boundary, can't use */
3258 if (!support_64 && base_upper)
3262 start |= ((u64)base_upper << 32);
3265 end = start + (max_offset | 0x03);
3267 /* Read MaxOffset MSBs (if 64-bit entry) */
3268 if (max_offset & PCI_EA_IS_64) {
3269 u32 max_offset_upper;
3271 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3274 flags |= IORESOURCE_MEM_64;
3276 /* entry too big, can't use */
3277 if (!support_64 && max_offset_upper)
3281 end += ((u64)max_offset_upper << 32);
3285 pci_err(dev, "EA Entry crosses address boundary\n");
3289 if (ent_size != ent_offset - offset) {
3290 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3291 ent_size, ent_offset - offset);
3295 res->name = pci_name(dev);
3300 if (bei <= PCI_EA_BEI_BAR5)
3301 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3303 else if (bei == PCI_EA_BEI_ROM)
3304 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3306 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3307 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3308 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3310 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3314 return offset + ent_size;
3317 /* Enhanced Allocation Initialization */
3318 void pci_ea_init(struct pci_dev *dev)
3325 /* find PCI EA capability in list */
3326 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3330 /* determine the number of entries */
3331 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3333 num_ent &= PCI_EA_NUM_ENT_MASK;
3335 offset = ea + PCI_EA_FIRST_ENT;
3337 /* Skip DWORD 2 for type 1 functions */
3338 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3341 /* parse each EA entry */
3342 for (i = 0; i < num_ent; ++i)
3343 offset = pci_ea_read(dev, offset);
3346 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3347 struct pci_cap_saved_state *new_cap)
3349 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3353 * _pci_add_cap_save_buffer - allocate buffer for saving given
3354 * capability registers
3355 * @dev: the PCI device
3356 * @cap: the capability to allocate the buffer for
3357 * @extended: Standard or Extended capability ID
3358 * @size: requested size of the buffer
3360 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3361 bool extended, unsigned int size)
3364 struct pci_cap_saved_state *save_state;
3367 pos = pci_find_ext_capability(dev, cap);
3369 pos = pci_find_capability(dev, cap);
3374 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3378 save_state->cap.cap_nr = cap;
3379 save_state->cap.cap_extended = extended;
3380 save_state->cap.size = size;
3381 pci_add_saved_cap(dev, save_state);
3386 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3388 return _pci_add_cap_save_buffer(dev, cap, false, size);
3391 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3393 return _pci_add_cap_save_buffer(dev, cap, true, size);
3397 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3398 * @dev: the PCI device
3400 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3404 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3405 PCI_EXP_SAVE_REGS * sizeof(u16));
3407 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3409 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3411 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3413 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3416 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3418 pci_allocate_vc_save_buffers(dev);
3421 void pci_free_cap_save_buffers(struct pci_dev *dev)
3423 struct pci_cap_saved_state *tmp;
3424 struct hlist_node *n;
3426 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3431 * pci_configure_ari - enable or disable ARI forwarding
3432 * @dev: the PCI device
3434 * If @dev and its upstream bridge both support ARI, enable ARI in the
3435 * bridge. Otherwise, disable ARI in the bridge.
3437 void pci_configure_ari(struct pci_dev *dev)
3440 struct pci_dev *bridge;
3442 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3445 bridge = dev->bus->self;
3449 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3450 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3453 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3454 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3455 PCI_EXP_DEVCTL2_ARI);
3456 bridge->ari_enabled = 1;
3458 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3459 PCI_EXP_DEVCTL2_ARI);
3460 bridge->ari_enabled = 0;
3464 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3469 pos = pdev->acs_cap;
3474 * Except for egress control, capabilities are either required
3475 * or only required if controllable. Features missing from the
3476 * capability field can therefore be assumed as hard-wired enabled.
3478 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3479 acs_flags &= (cap | PCI_ACS_EC);
3481 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3482 return (ctrl & acs_flags) == acs_flags;
3486 * pci_acs_enabled - test ACS against required flags for a given device
3487 * @pdev: device to test
3488 * @acs_flags: required PCI ACS flags
3490 * Return true if the device supports the provided flags. Automatically
3491 * filters out flags that are not implemented on multifunction devices.
3493 * Note that this interface checks the effective ACS capabilities of the
3494 * device rather than the actual capabilities. For instance, most single
3495 * function endpoints are not required to support ACS because they have no
3496 * opportunity for peer-to-peer access. We therefore return 'true'
3497 * regardless of whether the device exposes an ACS capability. This makes
3498 * it much easier for callers of this function to ignore the actual type
3499 * or topology of the device when testing ACS support.
3501 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3505 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3510 * Conventional PCI and PCI-X devices never support ACS, either
3511 * effectively or actually. The shared bus topology implies that
3512 * any device on the bus can receive or snoop DMA.
3514 if (!pci_is_pcie(pdev))
3517 switch (pci_pcie_type(pdev)) {
3519 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3520 * but since their primary interface is PCI/X, we conservatively
3521 * handle them as we would a non-PCIe device.
3523 case PCI_EXP_TYPE_PCIE_BRIDGE:
3525 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3526 * applicable... must never implement an ACS Extended Capability...".
3527 * This seems arbitrary, but we take a conservative interpretation
3528 * of this statement.
3530 case PCI_EXP_TYPE_PCI_BRIDGE:
3531 case PCI_EXP_TYPE_RC_EC:
3534 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3535 * implement ACS in order to indicate their peer-to-peer capabilities,
3536 * regardless of whether they are single- or multi-function devices.
3538 case PCI_EXP_TYPE_DOWNSTREAM:
3539 case PCI_EXP_TYPE_ROOT_PORT:
3540 return pci_acs_flags_enabled(pdev, acs_flags);
3542 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3543 * implemented by the remaining PCIe types to indicate peer-to-peer
3544 * capabilities, but only when they are part of a multifunction
3545 * device. The footnote for section 6.12 indicates the specific
3546 * PCIe types included here.
3548 case PCI_EXP_TYPE_ENDPOINT:
3549 case PCI_EXP_TYPE_UPSTREAM:
3550 case PCI_EXP_TYPE_LEG_END:
3551 case PCI_EXP_TYPE_RC_END:
3552 if (!pdev->multifunction)
3555 return pci_acs_flags_enabled(pdev, acs_flags);
3559 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3560 * to single function devices with the exception of downstream ports.
3566 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3567 * @start: starting downstream device
3568 * @end: ending upstream device or NULL to search to the root bus
3569 * @acs_flags: required flags
3571 * Walk up a device tree from start to end testing PCI ACS support. If
3572 * any step along the way does not support the required flags, return false.
3574 bool pci_acs_path_enabled(struct pci_dev *start,
3575 struct pci_dev *end, u16 acs_flags)
3577 struct pci_dev *pdev, *parent = start;
3582 if (!pci_acs_enabled(pdev, acs_flags))
3585 if (pci_is_root_bus(pdev->bus))
3586 return (end == NULL);
3588 parent = pdev->bus->self;
3589 } while (pdev != end);
3595 * pci_acs_init - Initialize ACS if hardware supports it
3596 * @dev: the PCI device
3598 void pci_acs_init(struct pci_dev *dev)
3600 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3603 * Attempt to enable ACS regardless of capability because some Root
3604 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3605 * the standard ACS capability but still support ACS via those
3608 pci_enable_acs(dev);
3612 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3616 * Helper to find the position of the ctrl register for a BAR.
3617 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3618 * Returns -ENOENT if no ctrl register for the BAR could be found.
3620 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3622 unsigned int pos, nbars, i;
3625 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3629 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3630 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3631 PCI_REBAR_CTRL_NBAR_SHIFT;
3633 for (i = 0; i < nbars; i++, pos += 8) {
3636 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3637 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3646 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3648 * @bar: BAR to query
3650 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3651 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3653 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3658 pos = pci_rebar_find_pos(pdev, bar);
3662 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3663 cap &= PCI_REBAR_CAP_SIZES;
3665 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3666 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3667 bar == 0 && cap == 0x7000)
3672 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3675 * pci_rebar_get_current_size - get the current size of a BAR
3677 * @bar: BAR to set size to
3679 * Read the size of a BAR from the resizable BAR config.
3680 * Returns size if found or negative error code.
3682 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3687 pos = pci_rebar_find_pos(pdev, bar);
3691 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3692 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3696 * pci_rebar_set_size - set a new size for a BAR
3698 * @bar: BAR to set size to
3699 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3701 * Set the new size of a BAR as defined in the spec.
3702 * Returns zero if resizing was successful, error code otherwise.
3704 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3709 pos = pci_rebar_find_pos(pdev, bar);
3713 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3714 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3715 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3716 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3721 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3722 * @dev: the PCI device
3723 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3724 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3725 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3726 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3728 * Return 0 if all upstream bridges support AtomicOp routing, egress
3729 * blocking is disabled on all upstream ports, and the root port supports
3730 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3731 * AtomicOp completion), or negative otherwise.
3733 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3735 struct pci_bus *bus = dev->bus;
3736 struct pci_dev *bridge;
3740 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3741 * in Device Control 2 is reserved in VFs and the PF value applies
3742 * to all associated VFs.
3747 if (!pci_is_pcie(dev))
3751 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3752 * AtomicOp requesters. For now, we only support endpoints as
3753 * requesters and root ports as completers. No endpoints as
3754 * completers, and no peer-to-peer.
3757 switch (pci_pcie_type(dev)) {
3758 case PCI_EXP_TYPE_ENDPOINT:
3759 case PCI_EXP_TYPE_LEG_END:
3760 case PCI_EXP_TYPE_RC_END:
3766 while (bus->parent) {
3769 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3771 switch (pci_pcie_type(bridge)) {
3772 /* Ensure switch ports support AtomicOp routing */
3773 case PCI_EXP_TYPE_UPSTREAM:
3774 case PCI_EXP_TYPE_DOWNSTREAM:
3775 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3779 /* Ensure root port supports all the sizes we care about */
3780 case PCI_EXP_TYPE_ROOT_PORT:
3781 if ((cap & cap_mask) != cap_mask)
3786 /* Ensure upstream ports don't block AtomicOps on egress */
3787 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3788 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3790 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3797 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3798 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3801 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3804 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3805 * @dev: the PCI device
3806 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3808 * Perform INTx swizzling for a device behind one level of bridge. This is
3809 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3810 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3811 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3812 * the PCI Express Base Specification, Revision 2.1)
3814 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3818 if (pci_ari_enabled(dev->bus))
3821 slot = PCI_SLOT(dev->devfn);
3823 return (((pin - 1) + slot) % 4) + 1;
3826 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3834 while (!pci_is_root_bus(dev->bus)) {
3835 pin = pci_swizzle_interrupt_pin(dev, pin);
3836 dev = dev->bus->self;
3843 * pci_common_swizzle - swizzle INTx all the way to root bridge
3844 * @dev: the PCI device
3845 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3847 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3848 * bridges all the way up to a PCI root bus.
3850 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3854 while (!pci_is_root_bus(dev->bus)) {
3855 pin = pci_swizzle_interrupt_pin(dev, pin);
3856 dev = dev->bus->self;
3859 return PCI_SLOT(dev->devfn);
3861 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3864 * pci_release_region - Release a PCI bar
3865 * @pdev: PCI device whose resources were previously reserved by
3866 * pci_request_region()
3867 * @bar: BAR to release
3869 * Releases the PCI I/O and memory resources previously reserved by a
3870 * successful call to pci_request_region(). Call this function only
3871 * after all use of the PCI regions has ceased.
3873 void pci_release_region(struct pci_dev *pdev, int bar)
3875 struct pci_devres *dr;
3877 if (pci_resource_len(pdev, bar) == 0)
3879 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3880 release_region(pci_resource_start(pdev, bar),
3881 pci_resource_len(pdev, bar));
3882 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3883 release_mem_region(pci_resource_start(pdev, bar),
3884 pci_resource_len(pdev, bar));
3886 dr = find_pci_dr(pdev);
3888 dr->region_mask &= ~(1 << bar);
3890 EXPORT_SYMBOL(pci_release_region);
3893 * __pci_request_region - Reserved PCI I/O and memory resource
3894 * @pdev: PCI device whose resources are to be reserved
3895 * @bar: BAR to be reserved
3896 * @res_name: Name to be associated with resource.
3897 * @exclusive: whether the region access is exclusive or not
3899 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3900 * being reserved by owner @res_name. Do not access any
3901 * address inside the PCI regions unless this call returns
3904 * If @exclusive is set, then the region is marked so that userspace
3905 * is explicitly not allowed to map the resource via /dev/mem or
3906 * sysfs MMIO access.
3908 * Returns 0 on success, or %EBUSY on error. A warning
3909 * message is also printed on failure.
3911 static int __pci_request_region(struct pci_dev *pdev, int bar,
3912 const char *res_name, int exclusive)
3914 struct pci_devres *dr;
3916 if (pci_resource_len(pdev, bar) == 0)
3919 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3920 if (!request_region(pci_resource_start(pdev, bar),
3921 pci_resource_len(pdev, bar), res_name))
3923 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3924 if (!__request_mem_region(pci_resource_start(pdev, bar),
3925 pci_resource_len(pdev, bar), res_name,
3930 dr = find_pci_dr(pdev);
3932 dr->region_mask |= 1 << bar;
3937 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3938 &pdev->resource[bar]);
3943 * pci_request_region - Reserve PCI I/O and memory resource
3944 * @pdev: PCI device whose resources are to be reserved
3945 * @bar: BAR to be reserved
3946 * @res_name: Name to be associated with resource
3948 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3949 * being reserved by owner @res_name. Do not access any
3950 * address inside the PCI regions unless this call returns
3953 * Returns 0 on success, or %EBUSY on error. A warning
3954 * message is also printed on failure.
3956 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3958 return __pci_request_region(pdev, bar, res_name, 0);
3960 EXPORT_SYMBOL(pci_request_region);
3963 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3964 * @pdev: PCI device whose resources were previously reserved
3965 * @bars: Bitmask of BARs to be released
3967 * Release selected PCI I/O and memory resources previously reserved.
3968 * Call this function only after all use of the PCI regions has ceased.
3970 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3974 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3975 if (bars & (1 << i))
3976 pci_release_region(pdev, i);
3978 EXPORT_SYMBOL(pci_release_selected_regions);
3980 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3981 const char *res_name, int excl)
3985 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3986 if (bars & (1 << i))
3987 if (__pci_request_region(pdev, i, res_name, excl))
3993 if (bars & (1 << i))
3994 pci_release_region(pdev, i);
4001 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4002 * @pdev: PCI device whose resources are to be reserved
4003 * @bars: Bitmask of BARs to be requested
4004 * @res_name: Name to be associated with resource
4006 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
4007 const char *res_name)
4009 return __pci_request_selected_regions(pdev, bars, res_name, 0);
4011 EXPORT_SYMBOL(pci_request_selected_regions);
4013 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
4014 const char *res_name)
4016 return __pci_request_selected_regions(pdev, bars, res_name,
4017 IORESOURCE_EXCLUSIVE);
4019 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4022 * pci_release_regions - Release reserved PCI I/O and memory resources
4023 * @pdev: PCI device whose resources were previously reserved by
4024 * pci_request_regions()
4026 * Releases all PCI I/O and memory resources previously reserved by a
4027 * successful call to pci_request_regions(). Call this function only
4028 * after all use of the PCI regions has ceased.
4031 void pci_release_regions(struct pci_dev *pdev)
4033 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4035 EXPORT_SYMBOL(pci_release_regions);
4038 * pci_request_regions - Reserve PCI I/O and memory resources
4039 * @pdev: PCI device whose resources are to be reserved
4040 * @res_name: Name to be associated with resource.
4042 * Mark all PCI regions associated with PCI device @pdev as
4043 * being reserved by owner @res_name. Do not access any
4044 * address inside the PCI regions unless this call returns
4047 * Returns 0 on success, or %EBUSY on error. A warning
4048 * message is also printed on failure.
4050 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4052 return pci_request_selected_regions(pdev,
4053 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4055 EXPORT_SYMBOL(pci_request_regions);
4058 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4059 * @pdev: PCI device whose resources are to be reserved
4060 * @res_name: Name to be associated with resource.
4062 * Mark all PCI regions associated with PCI device @pdev as being reserved
4063 * by owner @res_name. Do not access any address inside the PCI regions
4064 * unless this call returns successfully.
4066 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4067 * and the sysfs MMIO access will not be allowed.
4069 * Returns 0 on success, or %EBUSY on error. A warning message is also
4070 * printed on failure.
4072 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4074 return pci_request_selected_regions_exclusive(pdev,
4075 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4077 EXPORT_SYMBOL(pci_request_regions_exclusive);
4080 * Record the PCI IO range (expressed as CPU physical address + size).
4081 * Return a negative value if an error has occurred, zero otherwise
4083 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4084 resource_size_t size)
4088 struct logic_pio_hwaddr *range;
4090 if (!size || addr + size < addr)
4093 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4097 range->fwnode = fwnode;
4099 range->hw_start = addr;
4100 range->flags = LOGIC_PIO_CPU_MMIO;
4102 ret = logic_pio_register_range(range);
4106 /* Ignore duplicates due to deferred probing */
4114 phys_addr_t pci_pio_to_address(unsigned long pio)
4116 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4119 if (pio >= MMIO_UPPER_LIMIT)
4122 address = logic_pio_to_hwaddr(pio);
4127 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4129 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4132 return logic_pio_trans_cpuaddr(address);
4134 if (address > IO_SPACE_LIMIT)
4135 return (unsigned long)-1;
4137 return (unsigned long) address;
4142 * pci_remap_iospace - Remap the memory mapped I/O space
4143 * @res: Resource describing the I/O space
4144 * @phys_addr: physical address of range to be mapped
4146 * Remap the memory mapped I/O space described by the @res and the CPU
4147 * physical address @phys_addr into virtual address space. Only
4148 * architectures that have memory mapped IO functions defined (and the
4149 * PCI_IOBASE value defined) should call this function.
4151 #ifndef pci_remap_iospace
4152 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4154 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4155 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4157 if (!(res->flags & IORESOURCE_IO))
4160 if (res->end > IO_SPACE_LIMIT)
4163 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4164 pgprot_device(PAGE_KERNEL));
4167 * This architecture does not have memory mapped I/O space,
4168 * so this function should never be called
4170 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4174 EXPORT_SYMBOL(pci_remap_iospace);
4178 * pci_unmap_iospace - Unmap the memory mapped I/O space
4179 * @res: resource to be unmapped
4181 * Unmap the CPU virtual address @res from virtual address space. Only
4182 * architectures that have memory mapped IO functions defined (and the
4183 * PCI_IOBASE value defined) should call this function.
4185 void pci_unmap_iospace(struct resource *res)
4187 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4188 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4190 vunmap_range(vaddr, vaddr + resource_size(res));
4193 EXPORT_SYMBOL(pci_unmap_iospace);
4195 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4197 struct resource **res = ptr;
4199 pci_unmap_iospace(*res);
4203 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4204 * @dev: Generic device to remap IO address for
4205 * @res: Resource describing the I/O space
4206 * @phys_addr: physical address of range to be mapped
4208 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4211 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4212 phys_addr_t phys_addr)
4214 const struct resource **ptr;
4217 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4221 error = pci_remap_iospace(res, phys_addr);
4226 devres_add(dev, ptr);
4231 EXPORT_SYMBOL(devm_pci_remap_iospace);
4234 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4235 * @dev: Generic device to remap IO address for
4236 * @offset: Resource address to map
4237 * @size: Size of map
4239 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4242 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4243 resource_size_t offset,
4244 resource_size_t size)
4246 void __iomem **ptr, *addr;
4248 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4252 addr = pci_remap_cfgspace(offset, size);
4255 devres_add(dev, ptr);
4261 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4264 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4265 * @dev: generic device to handle the resource for
4266 * @res: configuration space resource to be handled
4268 * Checks that a resource is a valid memory region, requests the memory
4269 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4270 * proper PCI configuration space memory attributes are guaranteed.
4272 * All operations are managed and will be undone on driver detach.
4274 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4275 * on failure. Usage example::
4277 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4278 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4280 * return PTR_ERR(base);
4282 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4283 struct resource *res)
4285 resource_size_t size;
4287 void __iomem *dest_ptr;
4291 if (!res || resource_type(res) != IORESOURCE_MEM) {
4292 dev_err(dev, "invalid resource\n");
4293 return IOMEM_ERR_PTR(-EINVAL);
4296 size = resource_size(res);
4299 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4302 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4304 return IOMEM_ERR_PTR(-ENOMEM);
4306 if (!devm_request_mem_region(dev, res->start, size, name)) {
4307 dev_err(dev, "can't request region for resource %pR\n", res);
4308 return IOMEM_ERR_PTR(-EBUSY);
4311 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4313 dev_err(dev, "ioremap failed for resource %pR\n", res);
4314 devm_release_mem_region(dev, res->start, size);
4315 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4320 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4322 static void __pci_set_master(struct pci_dev *dev, bool enable)
4326 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4328 cmd = old_cmd | PCI_COMMAND_MASTER;
4330 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4331 if (cmd != old_cmd) {
4332 pci_dbg(dev, "%s bus mastering\n",
4333 enable ? "enabling" : "disabling");
4334 pci_write_config_word(dev, PCI_COMMAND, cmd);
4336 dev->is_busmaster = enable;
4340 * pcibios_setup - process "pci=" kernel boot arguments
4341 * @str: string used to pass in "pci=" kernel boot arguments
4343 * Process kernel boot arguments. This is the default implementation.
4344 * Architecture specific implementations can override this as necessary.
4346 char * __weak __init pcibios_setup(char *str)
4352 * pcibios_set_master - enable PCI bus-mastering for device dev
4353 * @dev: the PCI device to enable
4355 * Enables PCI bus-mastering for the device. This is the default
4356 * implementation. Architecture specific implementations can override
4357 * this if necessary.
4359 void __weak pcibios_set_master(struct pci_dev *dev)
4363 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4364 if (pci_is_pcie(dev))
4367 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4369 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4370 else if (lat > pcibios_max_latency)
4371 lat = pcibios_max_latency;
4375 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4379 * pci_set_master - enables bus-mastering for device dev
4380 * @dev: the PCI device to enable
4382 * Enables bus-mastering on the device and calls pcibios_set_master()
4383 * to do the needed arch specific settings.
4385 void pci_set_master(struct pci_dev *dev)
4387 __pci_set_master(dev, true);
4388 pcibios_set_master(dev);
4390 EXPORT_SYMBOL(pci_set_master);
4393 * pci_clear_master - disables bus-mastering for device dev
4394 * @dev: the PCI device to disable
4396 void pci_clear_master(struct pci_dev *dev)
4398 __pci_set_master(dev, false);
4400 EXPORT_SYMBOL(pci_clear_master);
4403 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4404 * @dev: the PCI device for which MWI is to be enabled
4406 * Helper function for pci_set_mwi.
4407 * Originally copied from drivers/net/acenic.c.
4408 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4410 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4412 int pci_set_cacheline_size(struct pci_dev *dev)
4416 if (!pci_cache_line_size)
4419 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4420 equal to or multiple of the right value. */
4421 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4422 if (cacheline_size >= pci_cache_line_size &&
4423 (cacheline_size % pci_cache_line_size) == 0)
4426 /* Write the correct value. */
4427 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4429 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4430 if (cacheline_size == pci_cache_line_size)
4433 pci_dbg(dev, "cache line size of %d is not supported\n",
4434 pci_cache_line_size << 2);
4438 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4441 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4442 * @dev: the PCI device for which MWI is enabled
4444 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4446 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4448 int pci_set_mwi(struct pci_dev *dev)
4450 #ifdef PCI_DISABLE_MWI
4456 rc = pci_set_cacheline_size(dev);
4460 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4461 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4462 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4463 cmd |= PCI_COMMAND_INVALIDATE;
4464 pci_write_config_word(dev, PCI_COMMAND, cmd);
4469 EXPORT_SYMBOL(pci_set_mwi);
4472 * pcim_set_mwi - a device-managed pci_set_mwi()
4473 * @dev: the PCI device for which MWI is enabled
4475 * Managed pci_set_mwi().
4477 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4479 int pcim_set_mwi(struct pci_dev *dev)
4481 struct pci_devres *dr;
4483 dr = find_pci_dr(dev);
4488 return pci_set_mwi(dev);
4490 EXPORT_SYMBOL(pcim_set_mwi);
4493 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4494 * @dev: the PCI device for which MWI is enabled
4496 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4497 * Callers are not required to check the return value.
4499 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4501 int pci_try_set_mwi(struct pci_dev *dev)
4503 #ifdef PCI_DISABLE_MWI
4506 return pci_set_mwi(dev);
4509 EXPORT_SYMBOL(pci_try_set_mwi);
4512 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4513 * @dev: the PCI device to disable
4515 * Disables PCI Memory-Write-Invalidate transaction on the device
4517 void pci_clear_mwi(struct pci_dev *dev)
4519 #ifndef PCI_DISABLE_MWI
4522 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4523 if (cmd & PCI_COMMAND_INVALIDATE) {
4524 cmd &= ~PCI_COMMAND_INVALIDATE;
4525 pci_write_config_word(dev, PCI_COMMAND, cmd);
4529 EXPORT_SYMBOL(pci_clear_mwi);
4532 * pci_disable_parity - disable parity checking for device
4533 * @dev: the PCI device to operate on
4535 * Disable parity checking for device @dev
4537 void pci_disable_parity(struct pci_dev *dev)
4541 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4542 if (cmd & PCI_COMMAND_PARITY) {
4543 cmd &= ~PCI_COMMAND_PARITY;
4544 pci_write_config_word(dev, PCI_COMMAND, cmd);
4549 * pci_intx - enables/disables PCI INTx for device dev
4550 * @pdev: the PCI device to operate on
4551 * @enable: boolean: whether to enable or disable PCI INTx
4553 * Enables/disables PCI INTx for device @pdev
4555 void pci_intx(struct pci_dev *pdev, int enable)
4557 u16 pci_command, new;
4559 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4562 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4564 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4566 if (new != pci_command) {
4567 struct pci_devres *dr;
4569 pci_write_config_word(pdev, PCI_COMMAND, new);
4571 dr = find_pci_dr(pdev);
4572 if (dr && !dr->restore_intx) {
4573 dr->restore_intx = 1;
4574 dr->orig_intx = !enable;
4578 EXPORT_SYMBOL_GPL(pci_intx);
4580 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4582 struct pci_bus *bus = dev->bus;
4583 bool mask_updated = true;
4584 u32 cmd_status_dword;
4585 u16 origcmd, newcmd;
4586 unsigned long flags;
4590 * We do a single dword read to retrieve both command and status.
4591 * Document assumptions that make this possible.
4593 BUILD_BUG_ON(PCI_COMMAND % 4);
4594 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4596 raw_spin_lock_irqsave(&pci_lock, flags);
4598 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4600 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4603 * Check interrupt status register to see whether our device
4604 * triggered the interrupt (when masking) or the next IRQ is
4605 * already pending (when unmasking).
4607 if (mask != irq_pending) {
4608 mask_updated = false;
4612 origcmd = cmd_status_dword;
4613 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4615 newcmd |= PCI_COMMAND_INTX_DISABLE;
4616 if (newcmd != origcmd)
4617 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4620 raw_spin_unlock_irqrestore(&pci_lock, flags);
4622 return mask_updated;
4626 * pci_check_and_mask_intx - mask INTx on pending interrupt
4627 * @dev: the PCI device to operate on
4629 * Check if the device dev has its INTx line asserted, mask it and return
4630 * true in that case. False is returned if no interrupt was pending.
4632 bool pci_check_and_mask_intx(struct pci_dev *dev)
4634 return pci_check_and_set_intx_mask(dev, true);
4636 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4639 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4640 * @dev: the PCI device to operate on
4642 * Check if the device dev has its INTx line asserted, unmask it if not and
4643 * return true. False is returned and the mask remains active if there was
4644 * still an interrupt pending.
4646 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4648 return pci_check_and_set_intx_mask(dev, false);
4650 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4653 * pci_wait_for_pending_transaction - wait for pending transaction
4654 * @dev: the PCI device to operate on
4656 * Return 0 if transaction is pending 1 otherwise.
4658 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4660 if (!pci_is_pcie(dev))
4663 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4664 PCI_EXP_DEVSTA_TRPND);
4666 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4669 * pcie_flr - initiate a PCIe function level reset
4670 * @dev: device to reset
4672 * Initiate a function level reset unconditionally on @dev without
4673 * checking any flags and DEVCAP
4675 int pcie_flr(struct pci_dev *dev)
4677 if (!pci_wait_for_pending_transaction(dev))
4678 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4680 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4686 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4687 * 100ms, but may silently discard requests while the FLR is in
4688 * progress. Wait 100ms before trying to access the device.
4692 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4694 EXPORT_SYMBOL_GPL(pcie_flr);
4697 * pcie_reset_flr - initiate a PCIe function level reset
4698 * @dev: device to reset
4699 * @probe: if true, return 0 if device can be reset this way
4701 * Initiate a function level reset on @dev.
4703 int pcie_reset_flr(struct pci_dev *dev, bool probe)
4705 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4708 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4714 return pcie_flr(dev);
4716 EXPORT_SYMBOL_GPL(pcie_reset_flr);
4718 static int pci_af_flr(struct pci_dev *dev, bool probe)
4723 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4727 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4730 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4731 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4738 * Wait for Transaction Pending bit to clear. A word-aligned test
4739 * is used, so we use the control offset rather than status and shift
4740 * the test bit to match.
4742 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4743 PCI_AF_STATUS_TP << 8))
4744 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4746 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4752 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4753 * updated 27 July 2006; a device must complete an FLR within
4754 * 100ms, but may silently discard requests while the FLR is in
4755 * progress. Wait 100ms before trying to access the device.
4759 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4763 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4764 * @dev: Device to reset.
4765 * @probe: if true, return 0 if the device can be reset this way.
4767 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4768 * unset, it will be reinitialized internally when going from PCI_D3hot to
4769 * PCI_D0. If that's the case and the device is not in a low-power state
4770 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4772 * NOTE: This causes the caller to sleep for twice the device power transition
4773 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4774 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4775 * Moreover, only devices in D0 can be reset by this function.
4777 static int pci_pm_reset(struct pci_dev *dev, bool probe)
4781 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4784 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4785 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4791 if (dev->current_state != PCI_D0)
4794 csr &= ~PCI_PM_CTRL_STATE_MASK;
4796 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4797 pci_dev_d3_sleep(dev);
4799 csr &= ~PCI_PM_CTRL_STATE_MASK;
4801 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4802 pci_dev_d3_sleep(dev);
4804 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4808 * pcie_wait_for_link_delay - Wait until link is active or inactive
4809 * @pdev: Bridge device
4810 * @active: waiting for active or inactive?
4811 * @delay: Delay to wait after link has become active (in ms)
4813 * Use this to wait till link becomes active or inactive.
4815 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4823 * Some controllers might not implement link active reporting. In this
4824 * case, we wait for 1000 ms + any delay requested by the caller.
4826 if (!pdev->link_active_reporting) {
4827 msleep(timeout + delay);
4832 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4833 * after which we should expect an link active if the reset was
4834 * successful. If so, software must wait a minimum 100ms before sending
4835 * configuration requests to devices downstream this port.
4837 * If the link fails to activate, either the device was physically
4838 * removed or the link is permanently failed.
4843 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4844 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4855 return ret == active;
4859 * pcie_wait_for_link - Wait until link is active or inactive
4860 * @pdev: Bridge device
4861 * @active: waiting for active or inactive?
4863 * Use this to wait till link becomes active or inactive.
4865 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4867 return pcie_wait_for_link_delay(pdev, active, 100);
4871 * Find maximum D3cold delay required by all the devices on the bus. The
4872 * spec says 100 ms, but firmware can lower it and we allow drivers to
4873 * increase it as well.
4875 * Called with @pci_bus_sem locked for reading.
4877 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4879 const struct pci_dev *pdev;
4880 int min_delay = 100;
4883 list_for_each_entry(pdev, &bus->devices, bus_list) {
4884 if (pdev->d3cold_delay < min_delay)
4885 min_delay = pdev->d3cold_delay;
4886 if (pdev->d3cold_delay > max_delay)
4887 max_delay = pdev->d3cold_delay;
4890 return max(min_delay, max_delay);
4894 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4897 * Handle necessary delays before access to the devices on the secondary
4898 * side of the bridge are permitted after D3cold to D0 transition.
4900 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4901 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4904 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4906 struct pci_dev *child;
4909 if (pci_dev_is_disconnected(dev))
4912 if (!pci_is_bridge(dev) || !dev->bridge_d3)
4915 down_read(&pci_bus_sem);
4918 * We only deal with devices that are present currently on the bus.
4919 * For any hot-added devices the access delay is handled in pciehp
4920 * board_added(). In case of ACPI hotplug the firmware is expected
4921 * to configure the devices before OS is notified.
4923 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4924 up_read(&pci_bus_sem);
4928 /* Take d3cold_delay requirements into account */
4929 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4931 up_read(&pci_bus_sem);
4935 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4937 up_read(&pci_bus_sem);
4940 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4941 * accessing the device after reset (that is 1000 ms + 100 ms). In
4942 * practice this should not be needed because we don't do power
4943 * management for them (see pci_bridge_d3_possible()).
4945 if (!pci_is_pcie(dev)) {
4946 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4947 msleep(1000 + delay);
4952 * For PCIe downstream and root ports that do not support speeds
4953 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4954 * speeds (gen3) we need to wait first for the data link layer to
4957 * However, 100 ms is the minimum and the PCIe spec says the
4958 * software must allow at least 1s before it can determine that the
4959 * device that did not respond is a broken device. There is
4960 * evidence that 100 ms is not always enough, for example certain
4961 * Titan Ridge xHCI controller does not always respond to
4962 * configuration requests if we only wait for 100 ms (see
4963 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4965 * Therefore we wait for 100 ms and check for the device presence.
4966 * If it is still not present give it an additional 100 ms.
4968 if (!pcie_downstream_port(dev))
4971 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
4972 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4975 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
4977 if (!pcie_wait_for_link_delay(dev, true, delay)) {
4978 /* Did not train, no need to wait any further */
4979 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
4984 if (!pci_device_is_present(child)) {
4985 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
4990 void pci_reset_secondary_bus(struct pci_dev *dev)
4994 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4995 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4996 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4999 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5000 * this to 2ms to ensure that we meet the minimum requirement.
5004 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
5005 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5008 * Trhfa for conventional PCI is 2^25 clock cycles.
5009 * Assuming a minimum 33MHz clock this results in a 1s
5010 * delay before we can consider subordinate devices to
5011 * be re-initialized. PCIe has some ways to shorten this,
5012 * but we don't make use of them yet.
5017 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5019 pci_reset_secondary_bus(dev);
5023 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5024 * @dev: Bridge device
5026 * Use the bridge control register to assert reset on the secondary bus.
5027 * Devices on the secondary bus are left in power-on state.
5029 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5031 pcibios_reset_secondary_bus(dev);
5033 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
5035 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
5037 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5039 struct pci_dev *pdev;
5041 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5042 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5045 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5052 return pci_bridge_secondary_bus_reset(dev->bus->self);
5055 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5059 if (!hotplug || !try_module_get(hotplug->owner))
5062 if (hotplug->ops->reset_slot)
5063 rc = hotplug->ops->reset_slot(hotplug, probe);
5065 module_put(hotplug->owner);
5070 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5072 if (dev->multifunction || dev->subordinate || !dev->slot ||
5073 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5076 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5079 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5083 rc = pci_dev_reset_slot_function(dev, probe);
5086 return pci_parent_bus_reset(dev, probe);
5089 void pci_dev_lock(struct pci_dev *dev)
5091 pci_cfg_access_lock(dev);
5092 /* block PM suspend, driver probe, etc. */
5093 device_lock(&dev->dev);
5095 EXPORT_SYMBOL_GPL(pci_dev_lock);
5097 /* Return 1 on successful lock, 0 on contention */
5098 int pci_dev_trylock(struct pci_dev *dev)
5100 if (pci_cfg_access_trylock(dev)) {
5101 if (device_trylock(&dev->dev))
5103 pci_cfg_access_unlock(dev);
5108 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5110 void pci_dev_unlock(struct pci_dev *dev)
5112 device_unlock(&dev->dev);
5113 pci_cfg_access_unlock(dev);
5115 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5117 static void pci_dev_save_and_disable(struct pci_dev *dev)
5119 const struct pci_error_handlers *err_handler =
5120 dev->driver ? dev->driver->err_handler : NULL;
5123 * dev->driver->err_handler->reset_prepare() is protected against
5124 * races with ->remove() by the device lock, which must be held by
5127 if (err_handler && err_handler->reset_prepare)
5128 err_handler->reset_prepare(dev);
5131 * Wake-up device prior to save. PM registers default to D0 after
5132 * reset and a simple register restore doesn't reliably return
5133 * to a non-D0 state anyway.
5135 pci_set_power_state(dev, PCI_D0);
5137 pci_save_state(dev);
5139 * Disable the device by clearing the Command register, except for
5140 * INTx-disable which is set. This not only disables MMIO and I/O port
5141 * BARs, but also prevents the device from being Bus Master, preventing
5142 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5143 * compliant devices, INTx-disable prevents legacy interrupts.
5145 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5148 static void pci_dev_restore(struct pci_dev *dev)
5150 const struct pci_error_handlers *err_handler =
5151 dev->driver ? dev->driver->err_handler : NULL;
5153 pci_restore_state(dev);
5156 * dev->driver->err_handler->reset_done() is protected against
5157 * races with ->remove() by the device lock, which must be held by
5160 if (err_handler && err_handler->reset_done)
5161 err_handler->reset_done(dev);
5164 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5165 static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5167 { pci_dev_specific_reset, .name = "device_specific" },
5168 { pci_dev_acpi_reset, .name = "acpi" },
5169 { pcie_reset_flr, .name = "flr" },
5170 { pci_af_flr, .name = "af_flr" },
5171 { pci_pm_reset, .name = "pm" },
5172 { pci_reset_bus_function, .name = "bus" },
5175 static ssize_t reset_method_show(struct device *dev,
5176 struct device_attribute *attr, char *buf)
5178 struct pci_dev *pdev = to_pci_dev(dev);
5182 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5183 m = pdev->reset_methods[i];
5187 len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5188 pci_reset_fn_methods[m].name);
5192 len += sysfs_emit_at(buf, len, "\n");
5197 static int reset_method_lookup(const char *name)
5201 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5202 if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5206 return 0; /* not found */
5209 static ssize_t reset_method_store(struct device *dev,
5210 struct device_attribute *attr,
5211 const char *buf, size_t count)
5213 struct pci_dev *pdev = to_pci_dev(dev);
5214 char *options, *name;
5216 u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5218 if (sysfs_streq(buf, "")) {
5219 pdev->reset_methods[0] = 0;
5220 pci_warn(pdev, "All device reset methods disabled by user");
5224 if (sysfs_streq(buf, "default")) {
5225 pci_init_reset_methods(pdev);
5229 options = kstrndup(buf, count, GFP_KERNEL);
5234 while ((name = strsep(&options, " ")) != NULL) {
5235 if (sysfs_streq(name, ""))
5240 m = reset_method_lookup(name);
5242 pci_err(pdev, "Invalid reset method '%s'", name);
5246 if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5247 pci_err(pdev, "Unsupported reset method '%s'", name);
5251 if (n == PCI_NUM_RESET_METHODS - 1) {
5252 pci_err(pdev, "Too many reset methods\n");
5256 reset_methods[n++] = m;
5259 reset_methods[n] = 0;
5261 /* Warn if dev-specific supported but not highest priority */
5262 if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5263 reset_methods[0] != 1)
5264 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5265 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5270 /* Leave previous methods unchanged */
5274 static DEVICE_ATTR_RW(reset_method);
5276 static struct attribute *pci_dev_reset_method_attrs[] = {
5277 &dev_attr_reset_method.attr,
5281 static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5282 struct attribute *a, int n)
5284 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5286 if (!pci_reset_supported(pdev))
5292 const struct attribute_group pci_dev_reset_method_attr_group = {
5293 .attrs = pci_dev_reset_method_attrs,
5294 .is_visible = pci_dev_reset_method_attr_is_visible,
5298 * __pci_reset_function_locked - reset a PCI device function while holding
5299 * the @dev mutex lock.
5300 * @dev: PCI device to reset
5302 * Some devices allow an individual function to be reset without affecting
5303 * other functions in the same device. The PCI device must be responsive
5304 * to PCI config space in order to use this function.
5306 * The device function is presumed to be unused and the caller is holding
5307 * the device mutex lock when this function is called.
5309 * Resetting the device will make the contents of PCI configuration space
5310 * random, so any caller of this must be prepared to reinitialise the
5311 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5314 * Returns 0 if the device function was successfully reset or negative if the
5315 * device doesn't support resetting a single function.
5317 int __pci_reset_function_locked(struct pci_dev *dev)
5324 * A reset method returns -ENOTTY if it doesn't support this device and
5325 * we should try the next method.
5327 * If it returns 0 (success), we're finished. If it returns any other
5328 * error, we're also finished: this indicates that further reset
5329 * mechanisms might be broken on the device.
5331 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5332 m = dev->reset_methods[i];
5336 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5345 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5348 * pci_init_reset_methods - check whether device can be safely reset
5349 * and store supported reset mechanisms.
5350 * @dev: PCI device to check for reset mechanisms
5352 * Some devices allow an individual function to be reset without affecting
5353 * other functions in the same device. The PCI device must be in D0-D3hot
5356 * Stores reset mechanisms supported by device in reset_methods byte array
5357 * which is a member of struct pci_dev.
5359 void pci_init_reset_methods(struct pci_dev *dev)
5363 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5368 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5369 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5371 dev->reset_methods[i++] = m;
5372 else if (rc != -ENOTTY)
5376 dev->reset_methods[i] = 0;
5380 * pci_reset_function - quiesce and reset a PCI device function
5381 * @dev: PCI device to reset
5383 * Some devices allow an individual function to be reset without affecting
5384 * other functions in the same device. The PCI device must be responsive
5385 * to PCI config space in order to use this function.
5387 * This function does not just reset the PCI portion of a device, but
5388 * clears all the state associated with the device. This function differs
5389 * from __pci_reset_function_locked() in that it saves and restores device state
5390 * over the reset and takes the PCI device lock.
5392 * Returns 0 if the device function was successfully reset or negative if the
5393 * device doesn't support resetting a single function.
5395 int pci_reset_function(struct pci_dev *dev)
5399 if (!pci_reset_supported(dev))
5403 pci_dev_save_and_disable(dev);
5405 rc = __pci_reset_function_locked(dev);
5407 pci_dev_restore(dev);
5408 pci_dev_unlock(dev);
5412 EXPORT_SYMBOL_GPL(pci_reset_function);
5415 * pci_reset_function_locked - quiesce and reset a PCI device function
5416 * @dev: PCI device to reset
5418 * Some devices allow an individual function to be reset without affecting
5419 * other functions in the same device. The PCI device must be responsive
5420 * to PCI config space in order to use this function.
5422 * This function does not just reset the PCI portion of a device, but
5423 * clears all the state associated with the device. This function differs
5424 * from __pci_reset_function_locked() in that it saves and restores device state
5425 * over the reset. It also differs from pci_reset_function() in that it
5426 * requires the PCI device lock to be held.
5428 * Returns 0 if the device function was successfully reset or negative if the
5429 * device doesn't support resetting a single function.
5431 int pci_reset_function_locked(struct pci_dev *dev)
5435 if (!pci_reset_supported(dev))
5438 pci_dev_save_and_disable(dev);
5440 rc = __pci_reset_function_locked(dev);
5442 pci_dev_restore(dev);
5446 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5449 * pci_try_reset_function - quiesce and reset a PCI device function
5450 * @dev: PCI device to reset
5452 * Same as above, except return -EAGAIN if unable to lock device.
5454 int pci_try_reset_function(struct pci_dev *dev)
5458 if (!pci_reset_supported(dev))
5461 if (!pci_dev_trylock(dev))
5464 pci_dev_save_and_disable(dev);
5465 rc = __pci_reset_function_locked(dev);
5466 pci_dev_restore(dev);
5467 pci_dev_unlock(dev);
5471 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5473 /* Do any devices on or below this bus prevent a bus reset? */
5474 static bool pci_bus_resetable(struct pci_bus *bus)
5476 struct pci_dev *dev;
5479 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5482 list_for_each_entry(dev, &bus->devices, bus_list) {
5483 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5484 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5491 /* Lock devices from the top of the tree down */
5492 static void pci_bus_lock(struct pci_bus *bus)
5494 struct pci_dev *dev;
5496 list_for_each_entry(dev, &bus->devices, bus_list) {
5498 if (dev->subordinate)
5499 pci_bus_lock(dev->subordinate);
5503 /* Unlock devices from the bottom of the tree up */
5504 static void pci_bus_unlock(struct pci_bus *bus)
5506 struct pci_dev *dev;
5508 list_for_each_entry(dev, &bus->devices, bus_list) {
5509 if (dev->subordinate)
5510 pci_bus_unlock(dev->subordinate);
5511 pci_dev_unlock(dev);
5515 /* Return 1 on successful lock, 0 on contention */
5516 static int pci_bus_trylock(struct pci_bus *bus)
5518 struct pci_dev *dev;
5520 list_for_each_entry(dev, &bus->devices, bus_list) {
5521 if (!pci_dev_trylock(dev))
5523 if (dev->subordinate) {
5524 if (!pci_bus_trylock(dev->subordinate)) {
5525 pci_dev_unlock(dev);
5533 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5534 if (dev->subordinate)
5535 pci_bus_unlock(dev->subordinate);
5536 pci_dev_unlock(dev);
5541 /* Do any devices on or below this slot prevent a bus reset? */
5542 static bool pci_slot_resetable(struct pci_slot *slot)
5544 struct pci_dev *dev;
5546 if (slot->bus->self &&
5547 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5550 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5551 if (!dev->slot || dev->slot != slot)
5553 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5554 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5561 /* Lock devices from the top of the tree down */
5562 static void pci_slot_lock(struct pci_slot *slot)
5564 struct pci_dev *dev;
5566 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5567 if (!dev->slot || dev->slot != slot)
5570 if (dev->subordinate)
5571 pci_bus_lock(dev->subordinate);
5575 /* Unlock devices from the bottom of the tree up */
5576 static void pci_slot_unlock(struct pci_slot *slot)
5578 struct pci_dev *dev;
5580 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5581 if (!dev->slot || dev->slot != slot)
5583 if (dev->subordinate)
5584 pci_bus_unlock(dev->subordinate);
5585 pci_dev_unlock(dev);
5589 /* Return 1 on successful lock, 0 on contention */
5590 static int pci_slot_trylock(struct pci_slot *slot)
5592 struct pci_dev *dev;
5594 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5595 if (!dev->slot || dev->slot != slot)
5597 if (!pci_dev_trylock(dev))
5599 if (dev->subordinate) {
5600 if (!pci_bus_trylock(dev->subordinate)) {
5601 pci_dev_unlock(dev);
5609 list_for_each_entry_continue_reverse(dev,
5610 &slot->bus->devices, bus_list) {
5611 if (!dev->slot || dev->slot != slot)
5613 if (dev->subordinate)
5614 pci_bus_unlock(dev->subordinate);
5615 pci_dev_unlock(dev);
5621 * Save and disable devices from the top of the tree down while holding
5622 * the @dev mutex lock for the entire tree.
5624 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5626 struct pci_dev *dev;
5628 list_for_each_entry(dev, &bus->devices, bus_list) {
5629 pci_dev_save_and_disable(dev);
5630 if (dev->subordinate)
5631 pci_bus_save_and_disable_locked(dev->subordinate);
5636 * Restore devices from top of the tree down while holding @dev mutex lock
5637 * for the entire tree. Parent bridges need to be restored before we can
5638 * get to subordinate devices.
5640 static void pci_bus_restore_locked(struct pci_bus *bus)
5642 struct pci_dev *dev;
5644 list_for_each_entry(dev, &bus->devices, bus_list) {
5645 pci_dev_restore(dev);
5646 if (dev->subordinate)
5647 pci_bus_restore_locked(dev->subordinate);
5652 * Save and disable devices from the top of the tree down while holding
5653 * the @dev mutex lock for the entire tree.
5655 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5657 struct pci_dev *dev;
5659 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5660 if (!dev->slot || dev->slot != slot)
5662 pci_dev_save_and_disable(dev);
5663 if (dev->subordinate)
5664 pci_bus_save_and_disable_locked(dev->subordinate);
5669 * Restore devices from top of the tree down while holding @dev mutex lock
5670 * for the entire tree. Parent bridges need to be restored before we can
5671 * get to subordinate devices.
5673 static void pci_slot_restore_locked(struct pci_slot *slot)
5675 struct pci_dev *dev;
5677 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5678 if (!dev->slot || dev->slot != slot)
5680 pci_dev_restore(dev);
5681 if (dev->subordinate)
5682 pci_bus_restore_locked(dev->subordinate);
5686 static int pci_slot_reset(struct pci_slot *slot, bool probe)
5690 if (!slot || !pci_slot_resetable(slot))
5694 pci_slot_lock(slot);
5698 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5701 pci_slot_unlock(slot);
5707 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5708 * @slot: PCI slot to probe
5710 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5712 int pci_probe_reset_slot(struct pci_slot *slot)
5714 return pci_slot_reset(slot, PCI_RESET_PROBE);
5716 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5719 * __pci_reset_slot - Try to reset a PCI slot
5720 * @slot: PCI slot to reset
5722 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5723 * independent of other slots. For instance, some slots may support slot power
5724 * control. In the case of a 1:1 bus to slot architecture, this function may
5725 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5726 * Generally a slot reset should be attempted before a bus reset. All of the
5727 * function of the slot and any subordinate buses behind the slot are reset
5728 * through this function. PCI config space of all devices in the slot and
5729 * behind the slot is saved before and restored after reset.
5731 * Same as above except return -EAGAIN if the slot cannot be locked
5733 static int __pci_reset_slot(struct pci_slot *slot)
5737 rc = pci_slot_reset(slot, PCI_RESET_PROBE);
5741 if (pci_slot_trylock(slot)) {
5742 pci_slot_save_and_disable_locked(slot);
5744 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
5745 pci_slot_restore_locked(slot);
5746 pci_slot_unlock(slot);
5753 static int pci_bus_reset(struct pci_bus *bus, bool probe)
5757 if (!bus->self || !pci_bus_resetable(bus))
5767 ret = pci_bridge_secondary_bus_reset(bus->self);
5769 pci_bus_unlock(bus);
5775 * pci_bus_error_reset - reset the bridge's subordinate bus
5776 * @bridge: The parent device that connects to the bus to reset
5778 * This function will first try to reset the slots on this bus if the method is
5779 * available. If slot reset fails or is not available, this will fall back to a
5780 * secondary bus reset.
5782 int pci_bus_error_reset(struct pci_dev *bridge)
5784 struct pci_bus *bus = bridge->subordinate;
5785 struct pci_slot *slot;
5790 mutex_lock(&pci_slot_mutex);
5791 if (list_empty(&bus->slots))
5794 list_for_each_entry(slot, &bus->slots, list)
5795 if (pci_probe_reset_slot(slot))
5798 list_for_each_entry(slot, &bus->slots, list)
5799 if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
5802 mutex_unlock(&pci_slot_mutex);
5805 mutex_unlock(&pci_slot_mutex);
5806 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
5810 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5811 * @bus: PCI bus to probe
5813 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5815 int pci_probe_reset_bus(struct pci_bus *bus)
5817 return pci_bus_reset(bus, PCI_RESET_PROBE);
5819 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5822 * __pci_reset_bus - Try to reset a PCI bus
5823 * @bus: top level PCI bus to reset
5825 * Same as above except return -EAGAIN if the bus cannot be locked
5827 static int __pci_reset_bus(struct pci_bus *bus)
5831 rc = pci_bus_reset(bus, PCI_RESET_PROBE);
5835 if (pci_bus_trylock(bus)) {
5836 pci_bus_save_and_disable_locked(bus);
5838 rc = pci_bridge_secondary_bus_reset(bus->self);
5839 pci_bus_restore_locked(bus);
5840 pci_bus_unlock(bus);
5848 * pci_reset_bus - Try to reset a PCI bus
5849 * @pdev: top level PCI device to reset via slot/bus
5851 * Same as above except return -EAGAIN if the bus cannot be locked
5853 int pci_reset_bus(struct pci_dev *pdev)
5855 return (!pci_probe_reset_slot(pdev->slot)) ?
5856 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5858 EXPORT_SYMBOL_GPL(pci_reset_bus);
5861 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5862 * @dev: PCI device to query
5864 * Returns mmrbc: maximum designed memory read count in bytes or
5865 * appropriate error value.
5867 int pcix_get_max_mmrbc(struct pci_dev *dev)
5872 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5876 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5879 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5881 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5884 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5885 * @dev: PCI device to query
5887 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5890 int pcix_get_mmrbc(struct pci_dev *dev)
5895 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5899 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5902 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5904 EXPORT_SYMBOL(pcix_get_mmrbc);
5907 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5908 * @dev: PCI device to query
5909 * @mmrbc: maximum memory read count in bytes
5910 * valid values are 512, 1024, 2048, 4096
5912 * If possible sets maximum memory read byte count, some bridges have errata
5913 * that prevent this.
5915 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5921 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5924 v = ffs(mmrbc) - 10;
5926 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5930 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5933 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5936 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5939 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5941 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5944 cmd &= ~PCI_X_CMD_MAX_READ;
5946 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5951 EXPORT_SYMBOL(pcix_set_mmrbc);
5954 * pcie_get_readrq - get PCI Express read request size
5955 * @dev: PCI device to query
5957 * Returns maximum memory read request in bytes or appropriate error value.
5959 int pcie_get_readrq(struct pci_dev *dev)
5963 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5965 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5967 EXPORT_SYMBOL(pcie_get_readrq);
5970 * pcie_set_readrq - set PCI Express maximum memory read request
5971 * @dev: PCI device to query
5972 * @rq: maximum memory read count in bytes
5973 * valid values are 128, 256, 512, 1024, 2048, 4096
5975 * If possible sets maximum memory read request in bytes
5977 int pcie_set_readrq(struct pci_dev *dev, int rq)
5982 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5986 * If using the "performance" PCIe config, we clamp the read rq
5987 * size to the max packet size to keep the host bridge from
5988 * generating requests larger than we can cope with.
5990 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5991 int mps = pcie_get_mps(dev);
5997 v = (ffs(rq) - 8) << 12;
5999 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6000 PCI_EXP_DEVCTL_READRQ, v);
6002 return pcibios_err_to_errno(ret);
6004 EXPORT_SYMBOL(pcie_set_readrq);
6007 * pcie_get_mps - get PCI Express maximum payload size
6008 * @dev: PCI device to query
6010 * Returns maximum payload size in bytes
6012 int pcie_get_mps(struct pci_dev *dev)
6016 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6018 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6020 EXPORT_SYMBOL(pcie_get_mps);
6023 * pcie_set_mps - set PCI Express maximum payload size
6024 * @dev: PCI device to query
6025 * @mps: maximum payload size in bytes
6026 * valid values are 128, 256, 512, 1024, 2048, 4096
6028 * If possible sets maximum payload size
6030 int pcie_set_mps(struct pci_dev *dev, int mps)
6035 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
6039 if (v > dev->pcie_mpss)
6043 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6044 PCI_EXP_DEVCTL_PAYLOAD, v);
6046 return pcibios_err_to_errno(ret);
6048 EXPORT_SYMBOL(pcie_set_mps);
6051 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6052 * device and its bandwidth limitation
6053 * @dev: PCI device to query
6054 * @limiting_dev: storage for device causing the bandwidth limitation
6055 * @speed: storage for speed of limiting device
6056 * @width: storage for width of limiting device
6058 * Walk up the PCI device chain and find the point where the minimum
6059 * bandwidth is available. Return the bandwidth available there and (if
6060 * limiting_dev, speed, and width pointers are supplied) information about
6061 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6064 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6065 enum pci_bus_speed *speed,
6066 enum pcie_link_width *width)
6069 enum pci_bus_speed next_speed;
6070 enum pcie_link_width next_width;
6074 *speed = PCI_SPEED_UNKNOWN;
6076 *width = PCIE_LNK_WIDTH_UNKNOWN;
6081 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6083 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
6084 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
6085 PCI_EXP_LNKSTA_NLW_SHIFT;
6087 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6089 /* Check if current device limits the total bandwidth */
6090 if (!bw || next_bw <= bw) {
6094 *limiting_dev = dev;
6096 *speed = next_speed;
6098 *width = next_width;
6101 dev = pci_upstream_bridge(dev);
6106 EXPORT_SYMBOL(pcie_bandwidth_available);
6109 * pcie_get_speed_cap - query for the PCI device's link speed capability
6110 * @dev: PCI device to query
6112 * Query the PCI device speed capability. Return the maximum link speed
6113 * supported by the device.
6115 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6117 u32 lnkcap2, lnkcap;
6120 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6121 * implementation note there recommends using the Supported Link
6122 * Speeds Vector in Link Capabilities 2 when supported.
6124 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6125 * should use the Supported Link Speeds field in Link Capabilities,
6126 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6128 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6130 /* PCIe r3.0-compliant */
6132 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6134 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6135 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6136 return PCIE_SPEED_5_0GT;
6137 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6138 return PCIE_SPEED_2_5GT;
6140 return PCI_SPEED_UNKNOWN;
6142 EXPORT_SYMBOL(pcie_get_speed_cap);
6145 * pcie_get_width_cap - query for the PCI device's link width capability
6146 * @dev: PCI device to query
6148 * Query the PCI device width capability. Return the maximum link width
6149 * supported by the device.
6151 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6155 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6157 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
6159 return PCIE_LNK_WIDTH_UNKNOWN;
6161 EXPORT_SYMBOL(pcie_get_width_cap);
6164 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6166 * @speed: storage for link speed
6167 * @width: storage for link width
6169 * Calculate a PCI device's link bandwidth by querying for its link speed
6170 * and width, multiplying them, and applying encoding overhead. The result
6171 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6173 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6174 enum pcie_link_width *width)
6176 *speed = pcie_get_speed_cap(dev);
6177 *width = pcie_get_width_cap(dev);
6179 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6182 return *width * PCIE_SPEED2MBS_ENC(*speed);
6186 * __pcie_print_link_status - Report the PCI device's link speed and width
6187 * @dev: PCI device to query
6188 * @verbose: Print info even when enough bandwidth is available
6190 * If the available bandwidth at the device is less than the device is
6191 * capable of, report the device's maximum possible bandwidth and the
6192 * upstream link that limits its performance. If @verbose, always print
6193 * the available bandwidth, even if the device isn't constrained.
6195 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6197 enum pcie_link_width width, width_cap;
6198 enum pci_bus_speed speed, speed_cap;
6199 struct pci_dev *limiting_dev = NULL;
6200 u32 bw_avail, bw_cap;
6202 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6203 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6205 if (bw_avail >= bw_cap && verbose)
6206 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6207 bw_cap / 1000, bw_cap % 1000,
6208 pci_speed_string(speed_cap), width_cap);
6209 else if (bw_avail < bw_cap)
6210 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6211 bw_avail / 1000, bw_avail % 1000,
6212 pci_speed_string(speed), width,
6213 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6214 bw_cap / 1000, bw_cap % 1000,
6215 pci_speed_string(speed_cap), width_cap);
6219 * pcie_print_link_status - Report the PCI device's link speed and width
6220 * @dev: PCI device to query
6222 * Report the available bandwidth at the device.
6224 void pcie_print_link_status(struct pci_dev *dev)
6226 __pcie_print_link_status(dev, true);
6228 EXPORT_SYMBOL(pcie_print_link_status);
6231 * pci_select_bars - Make BAR mask from the type of resource
6232 * @dev: the PCI device for which BAR mask is made
6233 * @flags: resource type mask to be selected
6235 * This helper routine makes bar mask from the type of resource.
6237 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6240 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6241 if (pci_resource_flags(dev, i) & flags)
6245 EXPORT_SYMBOL(pci_select_bars);
6247 /* Some architectures require additional programming to enable VGA */
6248 static arch_set_vga_state_t arch_set_vga_state;
6250 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6252 arch_set_vga_state = func; /* NULL disables */
6255 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6256 unsigned int command_bits, u32 flags)
6258 if (arch_set_vga_state)
6259 return arch_set_vga_state(dev, decode, command_bits,
6265 * pci_set_vga_state - set VGA decode state on device and parents if requested
6266 * @dev: the PCI device
6267 * @decode: true = enable decoding, false = disable decoding
6268 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6269 * @flags: traverse ancestors and change bridges
6270 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6272 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6273 unsigned int command_bits, u32 flags)
6275 struct pci_bus *bus;
6276 struct pci_dev *bridge;
6280 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6282 /* ARCH specific VGA enables */
6283 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6287 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6288 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6290 cmd |= command_bits;
6292 cmd &= ~command_bits;
6293 pci_write_config_word(dev, PCI_COMMAND, cmd);
6296 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6303 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6306 cmd |= PCI_BRIDGE_CTL_VGA;
6308 cmd &= ~PCI_BRIDGE_CTL_VGA;
6309 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6318 bool pci_pr3_present(struct pci_dev *pdev)
6320 struct acpi_device *adev;
6325 adev = ACPI_COMPANION(&pdev->dev);
6329 return adev->power.flags.power_resources &&
6330 acpi_has_method(adev->handle, "_PR3");
6332 EXPORT_SYMBOL_GPL(pci_pr3_present);
6336 * pci_add_dma_alias - Add a DMA devfn alias for a device
6337 * @dev: the PCI device for which alias is added
6338 * @devfn_from: alias slot and function
6339 * @nr_devfns: number of subsequent devfns to alias
6341 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6342 * which is used to program permissible bus-devfn source addresses for DMA
6343 * requests in an IOMMU. These aliases factor into IOMMU group creation
6344 * and are useful for devices generating DMA requests beyond or different
6345 * from their logical bus-devfn. Examples include device quirks where the
6346 * device simply uses the wrong devfn, as well as non-transparent bridges
6347 * where the alias may be a proxy for devices in another domain.
6349 * IOMMU group creation is performed during device discovery or addition,
6350 * prior to any potential DMA mapping and therefore prior to driver probing
6351 * (especially for userspace assigned devices where IOMMU group definition
6352 * cannot be left as a userspace activity). DMA aliases should therefore
6353 * be configured via quirks, such as the PCI fixup header quirk.
6355 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from,
6356 unsigned int nr_devfns)
6360 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from);
6361 devfn_to = devfn_from + nr_devfns - 1;
6363 if (!dev->dma_alias_mask)
6364 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6365 if (!dev->dma_alias_mask) {
6366 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6370 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6373 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6374 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6375 else if (nr_devfns > 1)
6376 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6377 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6378 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6381 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6383 return (dev1->dma_alias_mask &&
6384 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6385 (dev2->dma_alias_mask &&
6386 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6387 pci_real_dma_dev(dev1) == dev2 ||
6388 pci_real_dma_dev(dev2) == dev1;
6391 bool pci_device_is_present(struct pci_dev *pdev)
6395 if (pci_dev_is_disconnected(pdev))
6397 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6399 EXPORT_SYMBOL_GPL(pci_device_is_present);
6401 void pci_ignore_hotplug(struct pci_dev *dev)
6403 struct pci_dev *bridge = dev->bus->self;
6405 dev->ignore_hotplug = 1;
6406 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6408 bridge->ignore_hotplug = 1;
6410 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6413 * pci_real_dma_dev - Get PCI DMA device for PCI device
6414 * @dev: the PCI device that may have a PCI DMA alias
6416 * Permits the platform to provide architecture-specific functionality to
6417 * devices needing to alias DMA to another PCI device on another PCI bus. If
6418 * the PCI device is on the same bus, it is recommended to use
6419 * pci_add_dma_alias(). This is the default implementation. Architecture
6420 * implementations can override this.
6422 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6427 resource_size_t __weak pcibios_default_alignment(void)
6433 * Arches that don't want to expose struct resource to userland as-is in
6434 * sysfs and /proc can implement their own pci_resource_to_user().
6436 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6437 const struct resource *rsrc,
6438 resource_size_t *start, resource_size_t *end)
6440 *start = rsrc->start;
6444 static char *resource_alignment_param;
6445 static DEFINE_SPINLOCK(resource_alignment_lock);
6448 * pci_specified_resource_alignment - get resource alignment specified by user.
6449 * @dev: the PCI device to get
6450 * @resize: whether or not to change resources' size when reassigning alignment
6452 * RETURNS: Resource alignment if it is specified.
6453 * Zero if it is not specified.
6455 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6458 int align_order, count;
6459 resource_size_t align = pcibios_default_alignment();
6463 spin_lock(&resource_alignment_lock);
6464 p = resource_alignment_param;
6467 if (pci_has_flag(PCI_PROBE_ONLY)) {
6469 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6475 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6478 if (align_order > 63) {
6479 pr_err("PCI: Invalid requested alignment (order %d)\n",
6481 align_order = PAGE_SHIFT;
6484 align_order = PAGE_SHIFT;
6487 ret = pci_dev_str_match(dev, p, &p);
6490 align = 1ULL << align_order;
6492 } else if (ret < 0) {
6493 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6498 if (*p != ';' && *p != ',') {
6499 /* End of param or invalid format */
6505 spin_unlock(&resource_alignment_lock);
6509 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6510 resource_size_t align, bool resize)
6512 struct resource *r = &dev->resource[bar];
6513 resource_size_t size;
6515 if (!(r->flags & IORESOURCE_MEM))
6518 if (r->flags & IORESOURCE_PCI_FIXED) {
6519 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6520 bar, r, (unsigned long long)align);
6524 size = resource_size(r);
6529 * Increase the alignment of the resource. There are two ways we
6532 * 1) Increase the size of the resource. BARs are aligned on their
6533 * size, so when we reallocate space for this resource, we'll
6534 * allocate it with the larger alignment. This also prevents
6535 * assignment of any other BARs inside the alignment region, so
6536 * if we're requesting page alignment, this means no other BARs
6537 * will share the page.
6539 * The disadvantage is that this makes the resource larger than
6540 * the hardware BAR, which may break drivers that compute things
6541 * based on the resource size, e.g., to find registers at a
6542 * fixed offset before the end of the BAR.
6544 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6545 * set r->start to the desired alignment. By itself this
6546 * doesn't prevent other BARs being put inside the alignment
6547 * region, but if we realign *every* resource of every device in
6548 * the system, none of them will share an alignment region.
6550 * When the user has requested alignment for only some devices via
6551 * the "pci=resource_alignment" argument, "resize" is true and we
6552 * use the first method. Otherwise we assume we're aligning all
6553 * devices and we use the second.
6556 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6557 bar, r, (unsigned long long)align);
6563 r->flags &= ~IORESOURCE_SIZEALIGN;
6564 r->flags |= IORESOURCE_STARTALIGN;
6566 r->end = r->start + size - 1;
6568 r->flags |= IORESOURCE_UNSET;
6572 * This function disables memory decoding and releases memory resources
6573 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6574 * It also rounds up size to specified alignment.
6575 * Later on, the kernel will assign page-aligned memory resource back
6578 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6582 resource_size_t align;
6584 bool resize = false;
6587 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6588 * 3.4.1.11. Their resources are allocated from the space
6589 * described by the VF BARx register in the PF's SR-IOV capability.
6590 * We can't influence their alignment here.
6595 /* check if specified PCI is target device to reassign */
6596 align = pci_specified_resource_alignment(dev, &resize);
6600 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6601 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6602 pci_warn(dev, "Can't reassign resources to host bridge\n");
6606 pci_read_config_word(dev, PCI_COMMAND, &command);
6607 command &= ~PCI_COMMAND_MEMORY;
6608 pci_write_config_word(dev, PCI_COMMAND, command);
6610 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6611 pci_request_resource_alignment(dev, i, align, resize);
6614 * Need to disable bridge's resource window,
6615 * to enable the kernel to reassign new resource
6618 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6619 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6620 r = &dev->resource[i];
6621 if (!(r->flags & IORESOURCE_MEM))
6623 r->flags |= IORESOURCE_UNSET;
6624 r->end = resource_size(r) - 1;
6627 pci_disable_bridge_window(dev);
6631 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6635 spin_lock(&resource_alignment_lock);
6636 if (resource_alignment_param)
6637 count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6638 spin_unlock(&resource_alignment_lock);
6643 static ssize_t resource_alignment_store(struct bus_type *bus,
6644 const char *buf, size_t count)
6646 char *param, *old, *end;
6648 if (count >= (PAGE_SIZE - 1))
6651 param = kstrndup(buf, count, GFP_KERNEL);
6655 end = strchr(param, '\n');
6659 spin_lock(&resource_alignment_lock);
6660 old = resource_alignment_param;
6661 if (strlen(param)) {
6662 resource_alignment_param = param;
6665 resource_alignment_param = NULL;
6667 spin_unlock(&resource_alignment_lock);
6674 static BUS_ATTR_RW(resource_alignment);
6676 static int __init pci_resource_alignment_sysfs_init(void)
6678 return bus_create_file(&pci_bus_type,
6679 &bus_attr_resource_alignment);
6681 late_initcall(pci_resource_alignment_sysfs_init);
6683 static void pci_no_domains(void)
6685 #ifdef CONFIG_PCI_DOMAINS
6686 pci_domains_supported = 0;
6690 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6691 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6693 static int pci_get_new_domain_nr(void)
6695 return atomic_inc_return(&__domain_nr);
6698 static int of_pci_bus_find_domain_nr(struct device *parent)
6700 static int use_dt_domains = -1;
6704 domain = of_get_pci_domain_nr(parent->of_node);
6707 * Check DT domain and use_dt_domains values.
6709 * If DT domain property is valid (domain >= 0) and
6710 * use_dt_domains != 0, the DT assignment is valid since this means
6711 * we have not previously allocated a domain number by using
6712 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6713 * 1, to indicate that we have just assigned a domain number from
6716 * If DT domain property value is not valid (ie domain < 0), and we
6717 * have not previously assigned a domain number from DT
6718 * (use_dt_domains != 1) we should assign a domain number by
6721 * pci_get_new_domain_nr()
6723 * API and update the use_dt_domains value to keep track of method we
6724 * are using to assign domain numbers (use_dt_domains = 0).
6726 * All other combinations imply we have a platform that is trying
6727 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6728 * which is a recipe for domain mishandling and it is prevented by
6729 * invalidating the domain value (domain = -1) and printing a
6730 * corresponding error.
6732 if (domain >= 0 && use_dt_domains) {
6734 } else if (domain < 0 && use_dt_domains != 1) {
6736 domain = pci_get_new_domain_nr();
6739 pr_err("Node %pOF has ", parent->of_node);
6740 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6747 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6749 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6750 acpi_pci_bus_find_domain_nr(bus);
6755 * pci_ext_cfg_avail - can we access extended PCI config space?
6757 * Returns 1 if we can access PCI extended config space (offsets
6758 * greater than 0xff). This is the default implementation. Architecture
6759 * implementations can override this.
6761 int __weak pci_ext_cfg_avail(void)
6766 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6769 EXPORT_SYMBOL(pci_fixup_cardbus);
6771 static int __init pci_setup(char *str)
6774 char *k = strchr(str, ',');
6777 if (*str && (str = pcibios_setup(str)) && *str) {
6778 if (!strcmp(str, "nomsi")) {
6780 } else if (!strncmp(str, "noats", 5)) {
6781 pr_info("PCIe: ATS is disabled\n");
6782 pcie_ats_disabled = true;
6783 } else if (!strcmp(str, "noaer")) {
6785 } else if (!strcmp(str, "earlydump")) {
6786 pci_early_dump = true;
6787 } else if (!strncmp(str, "realloc=", 8)) {
6788 pci_realloc_get_opt(str + 8);
6789 } else if (!strncmp(str, "realloc", 7)) {
6790 pci_realloc_get_opt("on");
6791 } else if (!strcmp(str, "nodomains")) {
6793 } else if (!strncmp(str, "noari", 5)) {
6794 pcie_ari_disabled = true;
6795 } else if (!strncmp(str, "cbiosize=", 9)) {
6796 pci_cardbus_io_size = memparse(str + 9, &str);
6797 } else if (!strncmp(str, "cbmemsize=", 10)) {
6798 pci_cardbus_mem_size = memparse(str + 10, &str);
6799 } else if (!strncmp(str, "resource_alignment=", 19)) {
6800 resource_alignment_param = str + 19;
6801 } else if (!strncmp(str, "ecrc=", 5)) {
6802 pcie_ecrc_get_policy(str + 5);
6803 } else if (!strncmp(str, "hpiosize=", 9)) {
6804 pci_hotplug_io_size = memparse(str + 9, &str);
6805 } else if (!strncmp(str, "hpmmiosize=", 11)) {
6806 pci_hotplug_mmio_size = memparse(str + 11, &str);
6807 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6808 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6809 } else if (!strncmp(str, "hpmemsize=", 10)) {
6810 pci_hotplug_mmio_size = memparse(str + 10, &str);
6811 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6812 } else if (!strncmp(str, "hpbussize=", 10)) {
6813 pci_hotplug_bus_size =
6814 simple_strtoul(str + 10, &str, 0);
6815 if (pci_hotplug_bus_size > 0xff)
6816 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6817 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6818 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6819 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6820 pcie_bus_config = PCIE_BUS_SAFE;
6821 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6822 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6823 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6824 pcie_bus_config = PCIE_BUS_PEER2PEER;
6825 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6826 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6827 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6828 disable_acs_redir_param = str + 18;
6830 pr_err("PCI: Unknown option `%s'\n", str);
6837 early_param("pci", pci_setup);
6840 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6841 * in pci_setup(), above, to point to data in the __initdata section which
6842 * will be freed after the init sequence is complete. We can't allocate memory
6843 * in pci_setup() because some architectures do not have any memory allocation
6844 * service available during an early_param() call. So we allocate memory and
6845 * copy the variable here before the init section is freed.
6848 static int __init pci_realloc_setup_params(void)
6850 resource_alignment_param = kstrdup(resource_alignment_param,
6852 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6856 pure_initcall(pci_realloc_setup_params);