1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI Express PCI Hot Plug Driver
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
10 * All rights reserved.
12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
15 #define dev_fmt(fmt) "pciehp: " fmt
17 #include <linux/dmi.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/jiffies.h>
21 #include <linux/kthread.h>
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
30 static const struct dmi_system_id inband_presence_disabled_dmi_table[] = {
32 * Match all Dell systems, as some Dell systems have inband
33 * presence disabled on NVMe slots (but don't support the bit to
34 * report it). Setting inband presence disabled should have no
35 * negative effect, except on broken hotplug slots that never
36 * assert presence detect--and those will still work, they will
37 * just have a bit of extra delay before being probed.
40 .ident = "Dell System",
42 DMI_MATCH(DMI_OEM_STRING, "Dell System"),
48 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
50 return ctrl->pcie->port;
53 static irqreturn_t pciehp_isr(int irq, void *dev_id);
54 static irqreturn_t pciehp_ist(int irq, void *dev_id);
55 static int pciehp_poll(void *data);
57 static inline int pciehp_request_irq(struct controller *ctrl)
59 int retval, irq = ctrl->pcie->irq;
61 if (pciehp_poll_mode) {
62 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
65 return PTR_ERR_OR_ZERO(ctrl->poll_thread);
68 /* Installs the interrupt handler */
69 retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
70 IRQF_SHARED, "pciehp", ctrl);
72 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
77 static inline void pciehp_free_irq(struct controller *ctrl)
80 kthread_stop(ctrl->poll_thread);
82 free_irq(ctrl->pcie->irq, ctrl);
85 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
87 struct pci_dev *pdev = ctrl_dev(ctrl);
91 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
92 if (slot_status == (u16) ~0) {
93 ctrl_info(ctrl, "%s: no response from device\n",
98 if (slot_status & PCI_EXP_SLTSTA_CC) {
99 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
105 } while (timeout >= 0);
106 return 0; /* timeout */
109 static void pcie_wait_cmd(struct controller *ctrl)
111 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
112 unsigned long duration = msecs_to_jiffies(msecs);
113 unsigned long cmd_timeout = ctrl->cmd_started + duration;
114 unsigned long now, timeout;
118 * If the controller does not generate notifications for command
119 * completions, we never need to wait between writes.
121 if (NO_CMD_CMPL(ctrl))
128 * Even if the command has already timed out, we want to call
129 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
132 if (time_before_eq(cmd_timeout, now))
135 timeout = cmd_timeout - now;
137 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
138 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
139 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
141 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
144 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
146 jiffies_to_msecs(jiffies - ctrl->cmd_started));
149 #define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \
150 PCI_EXP_SLTCTL_PIC | \
151 PCI_EXP_SLTCTL_AIC | \
154 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
157 struct pci_dev *pdev = ctrl_dev(ctrl);
158 u16 slot_ctrl_orig, slot_ctrl;
160 mutex_lock(&ctrl->ctrl_lock);
163 * Always wait for any previous command that might still be in progress
167 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
168 if (slot_ctrl == (u16) ~0) {
169 ctrl_info(ctrl, "%s: no response from device\n", __func__);
173 slot_ctrl_orig = slot_ctrl;
175 slot_ctrl |= (cmd & mask);
178 ctrl->slot_ctrl = slot_ctrl;
179 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
180 ctrl->cmd_started = jiffies;
183 * Controllers with the Intel CF118 and similar errata advertise
184 * Command Completed support, but they only set Command Completed
185 * if we change the "Control" bits for power, power indicator,
186 * attention indicator, or interlock. If we only change the
187 * "Enable" bits, they never set the Command Completed bit.
189 if (pdev->broken_cmd_compl &&
190 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
194 * Optionally wait for the hardware to be ready for a new command,
195 * indicating completion of the above issued command.
201 mutex_unlock(&ctrl->ctrl_lock);
205 * pcie_write_cmd - Issue controller command
206 * @ctrl: controller to which the command is issued
207 * @cmd: command value written to slot control register
208 * @mask: bitmask of slot control register to be modified
210 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
212 pcie_do_write_cmd(ctrl, cmd, mask, true);
215 /* Same as above without waiting for the hardware to latch */
216 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
218 pcie_do_write_cmd(ctrl, cmd, mask, false);
222 * pciehp_check_link_active() - Is the link active
223 * @ctrl: PCIe hotplug controller
225 * Check whether the downstream link is currently active. Note it is
226 * possible that the card is removed immediately after this so the
227 * caller may need to take it into account.
229 * If the hotplug controller itself is not available anymore returns
232 int pciehp_check_link_active(struct controller *ctrl)
234 struct pci_dev *pdev = ctrl_dev(ctrl);
238 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
239 if (ret == PCIBIOS_DEVICE_NOT_FOUND || lnk_status == (u16)~0)
242 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
243 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
248 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
252 int delay = 1000, step = 20;
256 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
267 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
268 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
269 PCI_FUNC(devfn), count, step, l);
274 static void pcie_wait_for_presence(struct pci_dev *pdev)
280 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
281 if (slot_status & PCI_EXP_SLTSTA_PDS)
285 } while (timeout > 0);
288 int pciehp_check_link_status(struct controller *ctrl)
290 struct pci_dev *pdev = ctrl_dev(ctrl);
294 if (!pcie_wait_for_link(pdev, true)) {
295 ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl));
299 if (ctrl->inband_presence_disabled)
300 pcie_wait_for_presence(pdev);
302 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
305 /* ignore link or presence changes up to this point */
307 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
308 &ctrl->pending_events);
310 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
311 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
312 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
313 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
314 ctrl_info(ctrl, "Slot(%s): Cannot train link: status %#06x\n",
315 slot_name(ctrl), lnk_status);
319 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
322 ctrl_info(ctrl, "Slot(%s): No device found\n",
330 static int __pciehp_link_set(struct controller *ctrl, bool enable)
332 struct pci_dev *pdev = ctrl_dev(ctrl);
335 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
338 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
340 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
342 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
343 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
347 static int pciehp_link_enable(struct controller *ctrl)
349 return __pciehp_link_set(ctrl, true);
352 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
355 struct controller *ctrl = to_ctrl(hotplug_slot);
356 struct pci_dev *pdev = ctrl_dev(ctrl);
359 pci_config_pm_runtime_get(pdev);
360 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
361 pci_config_pm_runtime_put(pdev);
362 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
366 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
368 struct controller *ctrl = to_ctrl(hotplug_slot);
369 struct pci_dev *pdev = ctrl_dev(ctrl);
372 pci_config_pm_runtime_get(pdev);
373 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
374 pci_config_pm_runtime_put(pdev);
375 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
376 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
378 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
379 case PCI_EXP_SLTCTL_ATTN_IND_ON:
380 *status = 1; /* On */
382 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
383 *status = 2; /* Blink */
385 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
386 *status = 0; /* Off */
396 void pciehp_get_power_status(struct controller *ctrl, u8 *status)
398 struct pci_dev *pdev = ctrl_dev(ctrl);
401 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
402 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
403 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
405 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
406 case PCI_EXP_SLTCTL_PWR_ON:
407 *status = 1; /* On */
409 case PCI_EXP_SLTCTL_PWR_OFF:
410 *status = 0; /* Off */
418 void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
420 struct pci_dev *pdev = ctrl_dev(ctrl);
423 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
424 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
428 * pciehp_card_present() - Is the card present
429 * @ctrl: PCIe hotplug controller
431 * Function checks whether the card is currently present in the slot and
432 * in that case returns true. Note it is possible that the card is
433 * removed immediately after the check so the caller may need to take
436 * It the hotplug controller itself is not available anymore returns
439 int pciehp_card_present(struct controller *ctrl)
441 struct pci_dev *pdev = ctrl_dev(ctrl);
445 ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
446 if (ret == PCIBIOS_DEVICE_NOT_FOUND || slot_status == (u16)~0)
449 return !!(slot_status & PCI_EXP_SLTSTA_PDS);
453 * pciehp_card_present_or_link_active() - whether given slot is occupied
454 * @ctrl: PCIe hotplug controller
456 * Unlike pciehp_card_present(), which determines presence solely from the
457 * Presence Detect State bit, this helper also returns true if the Link Active
458 * bit is set. This is a concession to broken hotplug ports which hardwire
459 * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
461 * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug
462 * port is not present anymore returns %-ENODEV.
464 int pciehp_card_present_or_link_active(struct controller *ctrl)
468 ret = pciehp_card_present(ctrl);
472 return pciehp_check_link_active(ctrl);
475 int pciehp_query_power_fault(struct controller *ctrl)
477 struct pci_dev *pdev = ctrl_dev(ctrl);
480 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
481 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
484 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
487 struct controller *ctrl = to_ctrl(hotplug_slot);
488 struct pci_dev *pdev = ctrl_dev(ctrl);
490 pci_config_pm_runtime_get(pdev);
491 pcie_write_cmd_nowait(ctrl, status << 6,
492 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
493 pci_config_pm_runtime_put(pdev);
498 * pciehp_set_indicators() - set attention indicator, power indicator, or both
499 * @ctrl: PCIe hotplug controller
501 * PCI_EXP_SLTCTL_PWR_IND_ON
502 * PCI_EXP_SLTCTL_PWR_IND_BLINK
503 * PCI_EXP_SLTCTL_PWR_IND_OFF
505 * PCI_EXP_SLTCTL_ATTN_IND_ON
506 * PCI_EXP_SLTCTL_ATTN_IND_BLINK
507 * PCI_EXP_SLTCTL_ATTN_IND_OFF
509 * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
512 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
514 u16 cmd = 0, mask = 0;
516 if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
517 cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
518 mask |= PCI_EXP_SLTCTL_PIC;
521 if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
522 cmd |= (attn & PCI_EXP_SLTCTL_AIC);
523 mask |= PCI_EXP_SLTCTL_AIC;
527 pcie_write_cmd_nowait(ctrl, cmd, mask);
528 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
529 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
533 int pciehp_power_on_slot(struct controller *ctrl)
535 struct pci_dev *pdev = ctrl_dev(ctrl);
539 /* Clear power-fault bit from previous power failures */
540 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
541 if (slot_status & PCI_EXP_SLTSTA_PFD)
542 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
544 ctrl->power_fault_detected = 0;
546 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
547 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
548 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
549 PCI_EXP_SLTCTL_PWR_ON);
551 retval = pciehp_link_enable(ctrl);
553 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
558 void pciehp_power_off_slot(struct controller *ctrl)
560 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
561 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
562 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
563 PCI_EXP_SLTCTL_PWR_OFF);
566 static void pciehp_ignore_dpc_link_change(struct controller *ctrl,
567 struct pci_dev *pdev, int irq)
570 * Ignore link changes which occurred while waiting for DPC recovery.
571 * Could be several if DPC triggered multiple times consecutively.
573 synchronize_hardirq(irq);
574 atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events);
575 if (pciehp_poll_mode)
576 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
577 PCI_EXP_SLTSTA_DLLSC);
578 ctrl_info(ctrl, "Slot(%s): Link Down/Up ignored (recovered by DPC)\n",
582 * If the link is unexpectedly down after successful recovery,
583 * the corresponding link change may have been ignored above.
584 * Synthesize it to ensure that it is acted on.
586 down_read(&ctrl->reset_lock);
587 if (!pciehp_check_link_active(ctrl))
588 pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
589 up_read(&ctrl->reset_lock);
592 static irqreturn_t pciehp_isr(int irq, void *dev_id)
594 struct controller *ctrl = (struct controller *)dev_id;
595 struct pci_dev *pdev = ctrl_dev(ctrl);
596 struct device *parent = pdev->dev.parent;
597 u16 status, events = 0;
600 * Interrupts only occur in D3hot or shallower and only if enabled
601 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
603 if (pdev->current_state == PCI_D3cold ||
604 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
608 * Keep the port accessible by holding a runtime PM ref on its parent.
609 * Defer resume of the parent to the IRQ thread if it's suspended.
610 * Mask the interrupt until then.
613 pm_runtime_get_noresume(parent);
614 if (!pm_runtime_active(parent)) {
615 pm_runtime_put(parent);
616 disable_irq_nosync(irq);
617 atomic_or(RERUN_ISR, &ctrl->pending_events);
618 return IRQ_WAKE_THREAD;
623 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
624 if (status == (u16) ~0) {
625 ctrl_info(ctrl, "%s: no response from device\n", __func__);
627 pm_runtime_put(parent);
632 * Slot Status contains plain status bits as well as event
633 * notification bits; right now we only want the event bits.
635 status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
636 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
637 PCI_EXP_SLTSTA_DLLSC;
640 * If we've already reported a power fault, don't report it again
641 * until we've done something to handle it.
643 if (ctrl->power_fault_detected)
644 status &= ~PCI_EXP_SLTSTA_PFD;
649 pm_runtime_put(parent);
654 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
657 * In MSI mode, all event bits must be zero before the port
658 * will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4).
659 * So re-read the Slot Status register in case a bit was set
660 * between read and write.
662 if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode)
666 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
668 pm_runtime_put(parent);
671 * Command Completed notifications are not deferred to the
672 * IRQ thread because it may be waiting for their arrival.
674 if (events & PCI_EXP_SLTSTA_CC) {
677 wake_up(&ctrl->queue);
679 if (events == PCI_EXP_SLTSTA_CC)
682 events &= ~PCI_EXP_SLTSTA_CC;
685 if (pdev->ignore_hotplug) {
686 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
690 /* Save pending events for consumption by IRQ thread. */
691 atomic_or(events, &ctrl->pending_events);
692 return IRQ_WAKE_THREAD;
695 static irqreturn_t pciehp_ist(int irq, void *dev_id)
697 struct controller *ctrl = (struct controller *)dev_id;
698 struct pci_dev *pdev = ctrl_dev(ctrl);
702 ctrl->ist_running = true;
703 pci_config_pm_runtime_get(pdev);
705 /* rerun pciehp_isr() if the port was inaccessible on interrupt */
706 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
707 ret = pciehp_isr(irq, dev_id);
709 if (ret != IRQ_WAKE_THREAD)
713 synchronize_hardirq(irq);
714 events = atomic_xchg(&ctrl->pending_events, 0);
720 /* Check Attention Button Pressed */
721 if (events & PCI_EXP_SLTSTA_ABP) {
722 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
724 pciehp_handle_button_press(ctrl);
727 /* Check Power Fault Detected */
728 if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
729 ctrl->power_fault_detected = 1;
730 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
731 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
732 PCI_EXP_SLTCTL_ATTN_IND_ON);
736 * Ignore Link Down/Up events caused by Downstream Port Containment
737 * if recovery from the error succeeded.
739 if ((events & PCI_EXP_SLTSTA_DLLSC) && pci_dpc_recovered(pdev) &&
740 ctrl->state == ON_STATE) {
741 events &= ~PCI_EXP_SLTSTA_DLLSC;
742 pciehp_ignore_dpc_link_change(ctrl, pdev, irq);
746 * Disable requests have higher priority than Presence Detect Changed
747 * or Data Link Layer State Changed events.
749 down_read(&ctrl->reset_lock);
750 if (events & DISABLE_SLOT)
751 pciehp_handle_disable_request(ctrl);
752 else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
753 pciehp_handle_presence_or_link_change(ctrl, events);
754 up_read(&ctrl->reset_lock);
758 pci_config_pm_runtime_put(pdev);
759 ctrl->ist_running = false;
760 wake_up(&ctrl->requester);
764 static int pciehp_poll(void *data)
766 struct controller *ctrl = data;
768 schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
770 while (!kthread_should_stop()) {
771 /* poll for interrupt events or user requests */
772 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
773 atomic_read(&ctrl->pending_events))
774 pciehp_ist(IRQ_NOTCONNECTED, ctrl);
776 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
777 pciehp_poll_time = 2; /* clamp to sane value */
779 schedule_timeout_idle(pciehp_poll_time * HZ);
785 static void pcie_enable_notification(struct controller *ctrl)
790 * TBD: Power fault detected software notification support.
792 * Power fault detected software notification is not enabled
793 * now, because it caused power fault detected interrupt storm
794 * on some machines. On those machines, power fault detected
795 * bit in the slot status register was set again immediately
796 * when it is cleared in the interrupt service routine, and
797 * next power fault detected interrupt was notified again.
801 * Always enable link events: thus link-up and link-down shall
802 * always be treated as hotplug and unplug respectively. Enable
803 * presence detect only if Attention Button is not present.
805 cmd = PCI_EXP_SLTCTL_DLLSCE;
806 if (ATTN_BUTTN(ctrl))
807 cmd |= PCI_EXP_SLTCTL_ABPE;
809 cmd |= PCI_EXP_SLTCTL_PDCE;
810 if (!pciehp_poll_mode)
811 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
813 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
814 PCI_EXP_SLTCTL_PFDE |
815 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
816 PCI_EXP_SLTCTL_DLLSCE);
818 pcie_write_cmd_nowait(ctrl, cmd, mask);
819 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
820 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
823 static void pcie_disable_notification(struct controller *ctrl)
827 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
828 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
829 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
830 PCI_EXP_SLTCTL_DLLSCE);
831 pcie_write_cmd(ctrl, 0, mask);
832 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
833 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
836 void pcie_clear_hotplug_events(struct controller *ctrl)
838 pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
839 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
842 void pcie_enable_interrupt(struct controller *ctrl)
846 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
847 pcie_write_cmd(ctrl, mask, mask);
850 void pcie_disable_interrupt(struct controller *ctrl)
855 * Mask hot-plug interrupt to prevent it triggering immediately
856 * when the link goes inactive (we still get PME when any of the
857 * enabled events is detected). Same goes with Link Layer State
858 * changed event which generates PME immediately when the link goes
859 * inactive so mask it as well.
861 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
862 pcie_write_cmd(ctrl, 0, mask);
866 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
867 * bus reset of the bridge, but at the same time we want to ensure that it is
868 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
869 * disable link state notification and presence detection change notification
870 * momentarily, if we see that they could interfere. Also, clear any spurious
873 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe)
875 struct controller *ctrl = to_ctrl(hotplug_slot);
876 struct pci_dev *pdev = ctrl_dev(ctrl);
877 u16 stat_mask = 0, ctrl_mask = 0;
883 down_write(&ctrl->reset_lock);
885 if (!ATTN_BUTTN(ctrl)) {
886 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
887 stat_mask |= PCI_EXP_SLTSTA_PDC;
889 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
890 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
892 pcie_write_cmd(ctrl, 0, ctrl_mask);
893 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
894 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
896 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
898 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
899 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
900 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
901 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
903 up_write(&ctrl->reset_lock);
907 int pcie_init_notification(struct controller *ctrl)
909 if (pciehp_request_irq(ctrl))
911 pcie_enable_notification(ctrl);
912 ctrl->notification_enabled = 1;
916 void pcie_shutdown_notification(struct controller *ctrl)
918 if (ctrl->notification_enabled) {
919 pcie_disable_notification(ctrl);
920 pciehp_free_irq(ctrl);
921 ctrl->notification_enabled = 0;
925 static inline void dbg_ctrl(struct controller *ctrl)
927 struct pci_dev *pdev = ctrl->pcie->port;
930 ctrl_dbg(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
931 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
932 ctrl_dbg(ctrl, "Slot Status : 0x%04x\n", reg16);
933 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
934 ctrl_dbg(ctrl, "Slot Control : 0x%04x\n", reg16);
937 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
939 struct controller *pcie_init(struct pcie_device *dev)
941 struct controller *ctrl;
942 u32 slot_cap, slot_cap2, link_cap;
944 struct pci_dev *pdev = dev->port;
945 struct pci_bus *subordinate = pdev->subordinate;
947 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
952 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
954 if (pdev->hotplug_user_indicators)
955 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
958 * We assume no Thunderbolt controllers support Command Complete events,
959 * but some controllers falsely claim they do.
961 if (pdev->is_thunderbolt)
962 slot_cap |= PCI_EXP_SLTCAP_NCCS;
964 ctrl->slot_cap = slot_cap;
965 mutex_init(&ctrl->ctrl_lock);
966 mutex_init(&ctrl->state_lock);
967 init_rwsem(&ctrl->reset_lock);
968 init_waitqueue_head(&ctrl->requester);
969 init_waitqueue_head(&ctrl->queue);
970 INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
973 down_read(&pci_bus_sem);
974 ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
975 up_read(&pci_bus_sem);
977 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2);
978 if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) {
979 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE,
980 PCI_EXP_SLTCTL_IBPD_DISABLE);
981 ctrl->inband_presence_disabled = 1;
984 if (dmi_first_match(inband_presence_disabled_dmi_table))
985 ctrl->inband_presence_disabled = 1;
987 /* Check if Data Link Layer Link Active Reporting is implemented */
988 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
990 /* Clear all remaining event bits in Slot Status register. */
991 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
992 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
993 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
994 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
996 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n",
997 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
998 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
999 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
1000 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
1001 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
1002 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
1003 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
1004 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
1005 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
1006 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
1007 FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD),
1008 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
1009 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
1012 * If empty slot's power status is on, turn power off. The IRQ isn't
1013 * requested yet, so avoid triggering a notification with this command.
1015 if (POWER_CTRL(ctrl)) {
1016 pciehp_get_power_status(ctrl, &poweron);
1017 if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
1018 pcie_disable_notification(ctrl);
1019 pciehp_power_off_slot(ctrl);
1026 void pciehp_release_ctrl(struct controller *ctrl)
1028 cancel_delayed_work_sync(&ctrl->button_work);
1032 static void quirk_cmd_compl(struct pci_dev *pdev)
1036 if (pci_is_pcie(pdev)) {
1037 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
1038 if (slot_cap & PCI_EXP_SLTCAP_HPC &&
1039 !(slot_cap & PCI_EXP_SLTCAP_NCCS))
1040 pdev->broken_cmd_compl = 1;
1043 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1044 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1045 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
1046 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1047 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
1048 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1049 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
1050 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);