1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
11 * Author: Phil Edworthy <phil.edworthy@renesas.com>
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/iopoll.h>
24 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/pci.h>
30 #include <linux/phy/phy.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/slab.h>
35 #include "pcie-rcar.h"
38 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
39 struct irq_domain *domain;
40 struct mutex map_lock;
48 * Here we keep a static copy of the remapped PCIe controller address.
49 * This is only used on aarch32 systems, all of which have one single
50 * PCIe controller, to provide quick access to the PCIe controller in
51 * the L1 link state fixup function, called from the ARM fault handler.
53 static void __iomem *pcie_base;
55 * Static copy of bus clock pointer, so we can check whether the clock
58 static struct clk *pcie_bus_clk;
61 /* Structure representing the PCIe interface */
62 struct rcar_pcie_host {
63 struct rcar_pcie pcie;
67 int (*phy_init_fn)(struct rcar_pcie_host *host);
70 static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi)
72 return container_of(msi, struct rcar_pcie_host, msi);
75 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
77 unsigned int shift = BITS_PER_BYTE * (where & 3);
78 u32 val = rcar_pci_read_reg(pcie, where & ~3);
83 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
84 static int rcar_pcie_config_access(struct rcar_pcie_host *host,
85 unsigned char access_type, struct pci_bus *bus,
86 unsigned int devfn, int where, u32 *data)
88 struct rcar_pcie *pcie = &host->pcie;
89 unsigned int dev, func, reg, index;
91 dev = PCI_SLOT(devfn);
92 func = PCI_FUNC(devfn);
97 * While each channel has its own memory-mapped extended config
98 * space, it's generally only accessible when in endpoint mode.
99 * When in root complex mode, the controller is unable to target
100 * itself with either type 0 or type 1 accesses, and indeed, any
101 * controller initiated target transfer to its own config space
102 * result in a completer abort.
104 * Each channel effectively only supports a single device, but as
105 * the same channel <-> device access works for any PCI_SLOT()
106 * value, we cheat a bit here and bind the controller's config
107 * space to devfn 0 in order to enable self-enumeration. In this
108 * case the regular ECAR/ECDR path is sidelined and the mangled
109 * config access itself is initiated as an internal bus transaction.
111 if (pci_is_root_bus(bus)) {
113 return PCIBIOS_DEVICE_NOT_FOUND;
115 if (access_type == RCAR_PCI_ACCESS_READ)
116 *data = rcar_pci_read_reg(pcie, PCICONF(index));
118 rcar_pci_write_reg(pcie, *data, PCICONF(index));
120 return PCIBIOS_SUCCESSFUL;
124 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
126 /* Set the PIO address */
127 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
128 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
130 /* Enable the configuration access */
131 if (pci_is_root_bus(bus->parent))
132 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
134 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
136 /* Check for errors */
137 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
138 return PCIBIOS_DEVICE_NOT_FOUND;
140 /* Check for master and target aborts */
141 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
142 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
143 return PCIBIOS_DEVICE_NOT_FOUND;
145 if (access_type == RCAR_PCI_ACCESS_READ)
146 *data = rcar_pci_read_reg(pcie, PCIECDR);
148 rcar_pci_write_reg(pcie, *data, PCIECDR);
150 /* Disable the configuration access */
151 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
153 return PCIBIOS_SUCCESSFUL;
156 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
157 int where, int size, u32 *val)
159 struct rcar_pcie_host *host = bus->sysdata;
162 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
163 bus, devfn, where, val);
164 if (ret != PCIBIOS_SUCCESSFUL) {
170 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff;
172 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff;
174 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
175 bus->number, devfn, where, size, *val);
180 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
181 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
182 int where, int size, u32 val)
184 struct rcar_pcie_host *host = bus->sysdata;
189 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
190 bus, devfn, where, &data);
191 if (ret != PCIBIOS_SUCCESSFUL)
194 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
195 bus->number, devfn, where, size, val);
198 shift = BITS_PER_BYTE * (where & 3);
199 data &= ~(0xff << shift);
200 data |= ((val & 0xff) << shift);
201 } else if (size == 2) {
202 shift = BITS_PER_BYTE * (where & 2);
203 data &= ~(0xffff << shift);
204 data |= ((val & 0xffff) << shift);
208 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE,
209 bus, devfn, where, &data);
214 static struct pci_ops rcar_pcie_ops = {
215 .read = rcar_pcie_read_conf,
216 .write = rcar_pcie_write_conf,
219 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
221 struct device *dev = pcie->dev;
222 unsigned int timeout = 1000;
225 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
228 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
229 dev_err(dev, "Speed change already in progress\n");
233 macsr = rcar_pci_read_reg(pcie, MACSR);
234 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
237 /* Set target link speed to 5.0 GT/s */
238 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
239 PCI_EXP_LNKSTA_CLS_5_0GB);
241 /* Set speed change reason as intentional factor */
242 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
244 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
245 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
246 rcar_pci_write_reg(pcie, macsr, MACSR);
248 /* Start link speed change */
249 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
252 macsr = rcar_pci_read_reg(pcie, MACSR);
253 if (macsr & SPCHGFIN) {
254 /* Clear the interrupt bits */
255 rcar_pci_write_reg(pcie, macsr, MACSR);
257 if (macsr & SPCHGFAIL)
258 dev_err(dev, "Speed change failed\n");
266 dev_err(dev, "Speed change timed out\n");
269 dev_info(dev, "Current link speed is %s GT/s\n",
270 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
273 static void rcar_pcie_hw_enable(struct rcar_pcie_host *host)
275 struct rcar_pcie *pcie = &host->pcie;
276 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
277 struct resource_entry *win;
281 /* Try setting 5 GT/s link speed */
282 rcar_pcie_force_speedup(pcie);
284 /* Setup PCI resources */
285 resource_list_for_each_entry(win, &bridge->windows) {
286 struct resource *res = win->res;
291 switch (resource_type(res)) {
294 rcar_pcie_set_outbound(pcie, i, win);
301 static int rcar_pcie_enable(struct rcar_pcie_host *host)
303 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
305 rcar_pcie_hw_enable(host);
307 pci_add_flags(PCI_REASSIGN_ALL_BUS);
309 bridge->sysdata = host;
310 bridge->ops = &rcar_pcie_ops;
312 return pci_host_probe(bridge);
315 static int phy_wait_for_ack(struct rcar_pcie *pcie)
317 struct device *dev = pcie->dev;
318 unsigned int timeout = 100;
321 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
327 dev_err(dev, "Access to PCIe phy timed out\n");
332 static void phy_write_reg(struct rcar_pcie *pcie,
333 unsigned int rate, u32 addr,
334 unsigned int lane, u32 data)
338 phyaddr = WRITE_CMD |
339 ((rate & 1) << RATE_POS) |
340 ((lane & 0xf) << LANE_POS) |
341 ((addr & 0xff) << ADR_POS);
344 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
345 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
347 /* Ignore errors as they will be dealt with if the data link is down */
348 phy_wait_for_ack(pcie);
351 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
352 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
354 /* Ignore errors as they will be dealt with if the data link is down */
355 phy_wait_for_ack(pcie);
358 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
362 /* Begin initialization */
363 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
366 rcar_pci_write_reg(pcie, 1, PCIEMSR);
368 err = rcar_pcie_wait_for_phyrdy(pcie);
373 * Initial header for port config space is type 1, set the device
374 * class to match. Hardware takes care of propagating the IDSETR
375 * settings, so there is no need to bother with a quirk.
377 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
380 * Setup Secondary Bus Number & Subordinate Bus Number, even though
381 * they aren't used, to avoid bridge being detected as broken.
383 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
384 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
386 /* Initialize default capabilities. */
387 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
388 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
389 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
390 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
391 PCI_HEADER_TYPE_BRIDGE);
393 /* Enable data link layer active state reporting */
394 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
395 PCI_EXP_LNKCAP_DLLLARC);
397 /* Write out the physical slot number = 0 */
398 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
400 /* Set the completion timer timeout to the maximum 50ms. */
401 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
403 /* Terminate list of capabilities (Next Capability Offset=0) */
404 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
407 if (IS_ENABLED(CONFIG_PCI_MSI))
408 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
410 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
412 /* Finish initialization - establish a PCI Express link */
413 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
415 /* This will timeout if we don't have a link. */
416 err = rcar_pcie_wait_for_dl(pcie);
420 /* Enable INTx interrupts */
421 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
428 static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host)
430 struct rcar_pcie *pcie = &host->pcie;
432 /* Initialize the phy */
433 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
434 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
435 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
436 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
437 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
438 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
439 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
440 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
441 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
442 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
443 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
444 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
446 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
447 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
448 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
453 static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host)
455 struct rcar_pcie *pcie = &host->pcie;
458 * These settings come from the R-Car Series, 2nd Generation User's
459 * Manual, section 50.3.1 (2) Initialization of the physical layer.
461 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
462 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
463 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
464 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
466 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
467 /* The following value is for DC connection, no termination resistor */
468 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
469 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
470 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
475 static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host)
479 err = phy_init(host->phy);
483 err = phy_power_on(host->phy);
490 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
492 struct rcar_pcie_host *host = data;
493 struct rcar_pcie *pcie = &host->pcie;
494 struct rcar_msi *msi = &host->msi;
495 struct device *dev = pcie->dev;
498 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
500 /* MSI & INTx share an interrupt - we only handle MSI here */
505 unsigned int index = find_first_bit(®, 32);
508 ret = generic_handle_domain_irq(msi->domain->parent, index);
510 /* Unknown MSI, just clear it */
511 dev_dbg(dev, "unexpected MSI\n");
512 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR);
515 /* see if there's any more pending in this vector */
516 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
522 static void rcar_msi_top_irq_ack(struct irq_data *d)
524 irq_chip_ack_parent(d);
527 static void rcar_msi_top_irq_mask(struct irq_data *d)
530 irq_chip_mask_parent(d);
533 static void rcar_msi_top_irq_unmask(struct irq_data *d)
535 pci_msi_unmask_irq(d);
536 irq_chip_unmask_parent(d);
539 static struct irq_chip rcar_msi_top_chip = {
541 .irq_ack = rcar_msi_top_irq_ack,
542 .irq_mask = rcar_msi_top_irq_mask,
543 .irq_unmask = rcar_msi_top_irq_unmask,
546 static void rcar_msi_irq_ack(struct irq_data *d)
548 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
549 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
551 /* clear the interrupt */
552 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR);
555 static void rcar_msi_irq_mask(struct irq_data *d)
557 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
558 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
562 spin_lock_irqsave(&msi->mask_lock, flags);
563 value = rcar_pci_read_reg(pcie, PCIEMSIIER);
564 value &= ~BIT(d->hwirq);
565 rcar_pci_write_reg(pcie, value, PCIEMSIIER);
566 spin_unlock_irqrestore(&msi->mask_lock, flags);
569 static void rcar_msi_irq_unmask(struct irq_data *d)
571 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
572 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
576 spin_lock_irqsave(&msi->mask_lock, flags);
577 value = rcar_pci_read_reg(pcie, PCIEMSIIER);
578 value |= BIT(d->hwirq);
579 rcar_pci_write_reg(pcie, value, PCIEMSIIER);
580 spin_unlock_irqrestore(&msi->mask_lock, flags);
583 static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
588 static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
590 struct rcar_msi *msi = irq_data_get_irq_chip_data(data);
591 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
593 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
594 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
595 msg->data = data->hwirq;
598 static struct irq_chip rcar_msi_bottom_chip = {
600 .irq_ack = rcar_msi_irq_ack,
601 .irq_mask = rcar_msi_irq_mask,
602 .irq_unmask = rcar_msi_irq_unmask,
603 .irq_set_affinity = rcar_msi_set_affinity,
604 .irq_compose_msi_msg = rcar_compose_msi_msg,
607 static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
608 unsigned int nr_irqs, void *args)
610 struct rcar_msi *msi = domain->host_data;
614 mutex_lock(&msi->map_lock);
616 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs));
618 mutex_unlock(&msi->map_lock);
623 for (i = 0; i < nr_irqs; i++)
624 irq_domain_set_info(domain, virq + i, hwirq + i,
625 &rcar_msi_bottom_chip, domain->host_data,
626 handle_edge_irq, NULL, NULL);
631 static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq,
632 unsigned int nr_irqs)
634 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
635 struct rcar_msi *msi = domain->host_data;
637 mutex_lock(&msi->map_lock);
639 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs));
641 mutex_unlock(&msi->map_lock);
644 static const struct irq_domain_ops rcar_msi_domain_ops = {
645 .alloc = rcar_msi_domain_alloc,
646 .free = rcar_msi_domain_free,
649 static struct msi_domain_info rcar_msi_info = {
650 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
651 MSI_FLAG_MULTI_PCI_MSI),
652 .chip = &rcar_msi_top_chip,
655 static int rcar_allocate_domains(struct rcar_msi *msi)
657 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
658 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);
659 struct irq_domain *parent;
661 parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR,
662 &rcar_msi_domain_ops, msi);
664 dev_err(pcie->dev, "failed to create IRQ domain\n");
667 irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
669 msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent);
671 dev_err(pcie->dev, "failed to create MSI domain\n");
672 irq_domain_remove(parent);
679 static void rcar_free_domains(struct rcar_msi *msi)
681 struct irq_domain *parent = msi->domain->parent;
683 irq_domain_remove(msi->domain);
684 irq_domain_remove(parent);
687 static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
689 struct rcar_pcie *pcie = &host->pcie;
690 struct device *dev = pcie->dev;
691 struct rcar_msi *msi = &host->msi;
695 mutex_init(&msi->map_lock);
696 spin_lock_init(&msi->mask_lock);
698 err = of_address_to_resource(dev->of_node, 0, &res);
702 err = rcar_allocate_domains(msi);
706 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
707 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
708 IRQF_SHARED | IRQF_NO_THREAD,
709 rcar_msi_bottom_chip.name, host);
711 dev_err(dev, "failed to request IRQ: %d\n", err);
715 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
716 IRQF_SHARED | IRQF_NO_THREAD,
717 rcar_msi_bottom_chip.name, host);
719 dev_err(dev, "failed to request IRQ: %d\n", err);
723 /* disable all MSIs */
724 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
727 * Setup MSI data target using RC base address address, which
728 * is guaranteed to be in the low 32bit range on any RCar HW.
730 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
731 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
736 rcar_free_domains(msi);
740 static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host)
742 struct rcar_pcie *pcie = &host->pcie;
744 /* Disable all MSI interrupts */
745 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
747 /* Disable address decoding of the MSI interrupt, MSIFE */
748 rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
750 rcar_free_domains(&host->msi);
753 static int rcar_pcie_get_resources(struct rcar_pcie_host *host)
755 struct rcar_pcie *pcie = &host->pcie;
756 struct device *dev = pcie->dev;
760 host->phy = devm_phy_optional_get(dev, "pcie");
761 if (IS_ERR(host->phy))
762 return PTR_ERR(host->phy);
764 err = of_address_to_resource(dev->of_node, 0, &res);
768 pcie->base = devm_ioremap_resource(dev, &res);
769 if (IS_ERR(pcie->base))
770 return PTR_ERR(pcie->base);
772 host->bus_clk = devm_clk_get(dev, "pcie_bus");
773 if (IS_ERR(host->bus_clk)) {
774 dev_err(dev, "cannot get pcie bus clock\n");
775 return PTR_ERR(host->bus_clk);
778 i = irq_of_parse_and_map(dev->of_node, 0);
780 dev_err(dev, "cannot get platform resources for msi interrupt\n");
786 i = irq_of_parse_and_map(dev->of_node, 1);
788 dev_err(dev, "cannot get platform resources for msi interrupt\n");
795 /* Cache static copy for L1 link state fixup hook on aarch32 */
796 pcie_base = pcie->base;
797 pcie_bus_clk = host->bus_clk;
803 irq_dispose_mapping(host->msi.irq1);
808 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
809 struct resource_entry *entry,
812 u64 restype = entry->res->flags;
813 u64 cpu_addr = entry->res->start;
814 u64 cpu_end = entry->res->end;
815 u64 pci_addr = entry->res->start - entry->offset;
816 u32 flags = LAM_64BIT | LAR_ENABLE;
818 u64 size = resource_size(entry->res);
821 if (restype & IORESOURCE_PREFETCH)
822 flags |= LAM_PREFETCH;
824 while (cpu_addr < cpu_end) {
825 if (idx >= MAX_NR_INBOUND_MAPS - 1) {
826 dev_err(pcie->dev, "Failed to map inbound regions!\n");
830 * If the size of the range is larger than the alignment of
831 * the start address, we have to use multiple entries to
832 * perform the mapping.
835 unsigned long nr_zeros = __ffs64(cpu_addr);
836 u64 alignment = 1ULL << nr_zeros;
838 size = min(size, alignment);
840 /* Hardware supports max 4GiB inbound region */
841 size = min(size, 1ULL << 32);
843 mask = roundup_pow_of_two(size) - 1;
846 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr,
847 lower_32_bits(mask) | flags, idx, true);
858 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host)
860 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
861 struct resource_entry *entry;
862 int index = 0, err = 0;
864 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
865 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index);
873 static const struct of_device_id rcar_pcie_of_match[] = {
874 { .compatible = "renesas,pcie-r8a7779",
875 .data = rcar_pcie_phy_init_h1 },
876 { .compatible = "renesas,pcie-r8a7790",
877 .data = rcar_pcie_phy_init_gen2 },
878 { .compatible = "renesas,pcie-r8a7791",
879 .data = rcar_pcie_phy_init_gen2 },
880 { .compatible = "renesas,pcie-rcar-gen2",
881 .data = rcar_pcie_phy_init_gen2 },
882 { .compatible = "renesas,pcie-r8a7795",
883 .data = rcar_pcie_phy_init_gen3 },
884 { .compatible = "renesas,pcie-rcar-gen3",
885 .data = rcar_pcie_phy_init_gen3 },
889 static int rcar_pcie_probe(struct platform_device *pdev)
891 struct device *dev = &pdev->dev;
892 struct rcar_pcie_host *host;
893 struct rcar_pcie *pcie;
896 struct pci_host_bridge *bridge;
898 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
902 host = pci_host_bridge_priv(bridge);
905 platform_set_drvdata(pdev, host);
907 pm_runtime_enable(pcie->dev);
908 err = pm_runtime_get_sync(pcie->dev);
910 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
914 err = rcar_pcie_get_resources(host);
916 dev_err(dev, "failed to request resources: %d\n", err);
920 err = clk_prepare_enable(host->bus_clk);
922 dev_err(dev, "failed to enable bus clock: %d\n", err);
923 goto err_unmap_msi_irqs;
926 err = rcar_pcie_parse_map_dma_ranges(host);
928 goto err_clk_disable;
930 host->phy_init_fn = of_device_get_match_data(dev);
931 err = host->phy_init_fn(host);
933 dev_err(dev, "failed to init PCIe PHY\n");
934 goto err_clk_disable;
937 /* Failure to get a link might just be that no cards are inserted */
938 if (rcar_pcie_hw_init(pcie)) {
939 dev_info(dev, "PCIe link down\n");
941 goto err_phy_shutdown;
944 data = rcar_pci_read_reg(pcie, MACSR);
945 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
947 if (IS_ENABLED(CONFIG_PCI_MSI)) {
948 err = rcar_pcie_enable_msi(host);
951 "failed to enable MSI support: %d\n",
953 goto err_phy_shutdown;
957 err = rcar_pcie_enable(host);
959 goto err_msi_teardown;
964 if (IS_ENABLED(CONFIG_PCI_MSI))
965 rcar_pcie_teardown_msi(host);
969 phy_power_off(host->phy);
974 clk_disable_unprepare(host->bus_clk);
977 irq_dispose_mapping(host->msi.irq2);
978 irq_dispose_mapping(host->msi.irq1);
982 pm_runtime_disable(dev);
987 static int __maybe_unused rcar_pcie_resume(struct device *dev)
989 struct rcar_pcie_host *host = dev_get_drvdata(dev);
990 struct rcar_pcie *pcie = &host->pcie;
994 err = rcar_pcie_parse_map_dma_ranges(host);
998 /* Failure to get a link might just be that no cards are inserted */
999 err = host->phy_init_fn(host);
1001 dev_info(dev, "PCIe link down\n");
1005 data = rcar_pci_read_reg(pcie, MACSR);
1006 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1009 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1010 struct resource res;
1013 of_address_to_resource(dev->of_node, 0, &res);
1014 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
1015 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
1017 bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR);
1018 rcar_pci_write_reg(pcie, val, PCIEMSIIER);
1021 rcar_pcie_hw_enable(host);
1026 static int rcar_pcie_resume_noirq(struct device *dev)
1028 struct rcar_pcie_host *host = dev_get_drvdata(dev);
1029 struct rcar_pcie *pcie = &host->pcie;
1031 if (rcar_pci_read_reg(pcie, PMSR) &&
1032 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
1035 /* Re-establish the PCIe link */
1036 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
1037 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
1038 return rcar_pcie_wait_for_dl(pcie);
1041 static const struct dev_pm_ops rcar_pcie_pm_ops = {
1042 SET_SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume)
1043 .resume_noirq = rcar_pcie_resume_noirq,
1046 static struct platform_driver rcar_pcie_driver = {
1048 .name = "rcar-pcie",
1049 .of_match_table = rcar_pcie_of_match,
1050 .pm = &rcar_pcie_pm_ops,
1051 .suppress_bind_attrs = true,
1053 .probe = rcar_pcie_probe,
1057 static DEFINE_SPINLOCK(pmsr_lock);
1058 static int rcar_pcie_aarch32_abort_handler(unsigned long addr,
1059 unsigned int fsr, struct pt_regs *regs)
1061 unsigned long flags;
1065 spin_lock_irqsave(&pmsr_lock, flags);
1067 if (!pcie_base || !__clk_is_enabled(pcie_bus_clk)) {
1072 pmsr = readl(pcie_base + PMSR);
1075 * Test if the PCIe controller received PM_ENTER_L1 DLLP and
1076 * the PCIe controller is not in L1 link state. If true, apply
1077 * fix, which will put the controller into L1 link state, from
1078 * which it can return to L0s/L0 on its own.
1080 if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) {
1081 writel(L1IATN, pcie_base + PMCTLR);
1082 ret = readl_poll_timeout_atomic(pcie_base + PMSR, val,
1083 val & L1FAEG, 10, 1000);
1084 WARN(ret, "Timeout waiting for L1 link state, ret=%d\n", ret);
1085 writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
1089 spin_unlock_irqrestore(&pmsr_lock, flags);
1093 static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = {
1094 { .compatible = "renesas,pcie-r8a7779" },
1095 { .compatible = "renesas,pcie-r8a7790" },
1096 { .compatible = "renesas,pcie-r8a7791" },
1097 { .compatible = "renesas,pcie-rcar-gen2" },
1101 static int __init rcar_pcie_init(void)
1103 if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) {
1104 #ifdef CONFIG_ARM_LPAE
1105 hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
1106 "asynchronous external abort");
1108 hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
1109 "imprecise external abort");
1113 return platform_driver_register(&rcar_pcie_driver);
1115 device_initcall(rcar_pcie_init);
1117 builtin_platform_driver(rcar_pcie_driver);