1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint driver for Renesas R-Car SoCs
4 * Copyright (c) 2020 Renesas Electronics Europe GmbH
6 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
10 #include <linux/delay.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13 #include <linux/of_pci.h>
14 #include <linux/of_platform.h>
15 #include <linux/pci.h>
16 #include <linux/pci-epc.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
20 #include "pcie-rcar.h"
22 #define RCAR_EPC_MAX_FUNCTIONS 1
24 /* Structure representing the PCIe interface */
25 struct rcar_pcie_endpoint {
26 struct rcar_pcie pcie;
27 phys_addr_t *ob_mapped_addr;
28 struct pci_epc_mem_window *ob_window;
30 unsigned int bar_to_atu[MAX_NR_INBOUND_MAPS];
31 unsigned long *ib_window_map;
36 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie)
40 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
42 /* Set endpoint mode */
43 rcar_pci_write_reg(pcie, 0, PCIEMSR);
45 /* Initialize default capabilities. */
46 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
47 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
48 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ENDPOINT << 4);
49 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
50 PCI_HEADER_TYPE_NORMAL);
52 /* Write out the physical slot number = 0 */
53 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
55 val = rcar_pci_read_reg(pcie, EXPCAP(1));
56 /* device supports fixed 128 bytes MPSS */
57 val &= ~GENMASK(2, 0);
58 rcar_pci_write_reg(pcie, val, EXPCAP(1));
60 val = rcar_pci_read_reg(pcie, EXPCAP(2));
61 /* read requests size 128 bytes */
62 val &= ~GENMASK(14, 12);
63 /* payload size 128 bytes */
64 val &= ~GENMASK(7, 5);
65 rcar_pci_write_reg(pcie, val, EXPCAP(2));
67 /* Set target link speed to 5.0 GT/s */
68 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
69 PCI_EXP_LNKSTA_CLS_5_0GB);
71 /* Set the completion timer timeout to the maximum 50ms. */
72 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
74 /* Terminate list of capabilities (Next Capability Offset=0) */
75 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
77 /* flush modifications */
81 static int rcar_pcie_ep_get_window(struct rcar_pcie_endpoint *ep,
86 for (i = 0; i < ep->num_ob_windows; i++)
87 if (ep->ob_window[i].phys_base == addr)
93 static int rcar_pcie_parse_outbound_ranges(struct rcar_pcie_endpoint *ep,
94 struct platform_device *pdev)
96 struct rcar_pcie *pcie = &ep->pcie;
97 char outbound_name[10];
101 ep->num_ob_windows = 0;
102 for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
103 sprintf(outbound_name, "memory%u", i);
104 res = platform_get_resource_byname(pdev,
108 dev_err(pcie->dev, "missing outbound window %u\n", i);
111 if (!devm_request_mem_region(&pdev->dev, res->start,
114 dev_err(pcie->dev, "Cannot request memory region %s.\n",
119 ep->ob_window[i].phys_base = res->start;
120 ep->ob_window[i].size = resource_size(res);
121 /* controller doesn't support multiple allocation
122 * from same window, so set page_size to window size
124 ep->ob_window[i].page_size = resource_size(res);
126 ep->num_ob_windows = i;
131 static int rcar_pcie_ep_get_pdata(struct rcar_pcie_endpoint *ep,
132 struct platform_device *pdev)
134 struct rcar_pcie *pcie = &ep->pcie;
135 struct pci_epc_mem_window *window;
136 struct device *dev = pcie->dev;
140 err = of_address_to_resource(dev->of_node, 0, &res);
143 pcie->base = devm_ioremap_resource(dev, &res);
144 if (IS_ERR(pcie->base))
145 return PTR_ERR(pcie->base);
147 ep->ob_window = devm_kcalloc(dev, RCAR_PCI_MAX_RESOURCES,
148 sizeof(*window), GFP_KERNEL);
152 rcar_pcie_parse_outbound_ranges(ep, pdev);
154 err = of_property_read_u8(dev->of_node, "max-functions",
156 if (err < 0 || ep->max_functions > RCAR_EPC_MAX_FUNCTIONS)
157 ep->max_functions = RCAR_EPC_MAX_FUNCTIONS;
162 static int rcar_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
163 struct pci_epf_header *hdr)
165 struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
166 struct rcar_pcie *pcie = &ep->pcie;
172 val = rcar_pci_read_reg(pcie, IDSETR0);
173 val |= hdr->deviceid << 16;
174 rcar_pci_write_reg(pcie, val, IDSETR0);
177 val |= hdr->progif_code << 8;
178 val |= hdr->subclass_code << 16;
179 val |= hdr->baseclass_code << 24;
180 rcar_pci_write_reg(pcie, val, IDSETR1);
183 val = hdr->subsys_vendor_id;
185 val = rcar_pci_read_reg(pcie, SUBIDSETR);
186 val |= hdr->subsys_id << 16;
187 rcar_pci_write_reg(pcie, val, SUBIDSETR);
189 if (hdr->interrupt_pin > PCI_INTERRUPT_INTA)
191 val = rcar_pci_read_reg(pcie, PCICONF(15));
192 val |= (hdr->interrupt_pin << 8);
193 rcar_pci_write_reg(pcie, val, PCICONF(15));
198 static int rcar_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
199 struct pci_epf_bar *epf_bar)
201 int flags = epf_bar->flags | LAR_ENABLE | LAM_64BIT;
202 struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
203 u64 size = 1ULL << fls64(epf_bar->size - 1);
204 dma_addr_t cpu_addr = epf_bar->phys_addr;
205 enum pci_barno bar = epf_bar->barno;
206 struct rcar_pcie *pcie = &ep->pcie;
211 idx = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
212 if (idx >= ep->num_ib_windows) {
213 dev_err(pcie->dev, "no free inbound window\n");
217 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
220 ep->bar_to_atu[bar] = idx;
221 /* use 64-bit BARs */
222 set_bit(idx, ep->ib_window_map);
223 set_bit(idx + 1, ep->ib_window_map);
226 unsigned long nr_zeros = __ffs64(cpu_addr);
227 u64 alignment = 1ULL << nr_zeros;
229 size = min(size, alignment);
232 size = min(size, 1ULL << 32);
234 mask = roundup_pow_of_two(size) - 1;
237 rcar_pcie_set_inbound(pcie, cpu_addr,
238 0x0, mask | flags, idx, false);
240 err = rcar_pcie_wait_for_phyrdy(pcie);
242 dev_err(pcie->dev, "phy not ready\n");
249 static void rcar_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn,
250 struct pci_epf_bar *epf_bar)
252 struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
253 enum pci_barno bar = epf_bar->barno;
254 u32 atu_index = ep->bar_to_atu[bar];
256 rcar_pcie_set_inbound(&ep->pcie, 0x0, 0x0, 0x0, bar, false);
258 clear_bit(atu_index, ep->ib_window_map);
259 clear_bit(atu_index + 1, ep->ib_window_map);
262 static int rcar_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn,
265 struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
266 struct rcar_pcie *pcie = &ep->pcie;
269 flags = rcar_pci_read_reg(pcie, MSICAP(fn));
270 flags |= interrupts << MSICAP0_MMESCAP_OFFSET;
271 rcar_pci_write_reg(pcie, flags, MSICAP(fn));
276 static int rcar_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
278 struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
279 struct rcar_pcie *pcie = &ep->pcie;
282 flags = rcar_pci_read_reg(pcie, MSICAP(fn));
283 if (!(flags & MSICAP0_MSIE))
286 return ((flags & MSICAP0_MMESE_MASK) >> MSICAP0_MMESE_OFFSET);
289 static int rcar_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,
290 phys_addr_t addr, u64 pci_addr, size_t size)
292 struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
293 struct rcar_pcie *pcie = &ep->pcie;
294 struct resource_entry win;
299 /* check if we have a link. */
300 err = rcar_pcie_wait_for_dl(pcie);
302 dev_err(pcie->dev, "link not up\n");
306 window = rcar_pcie_ep_get_window(ep, addr);
308 dev_err(pcie->dev, "failed to get corresponding window\n");
312 memset(&win, 0x0, sizeof(win));
313 memset(&res, 0x0, sizeof(res));
314 res.start = pci_addr;
315 res.end = pci_addr + size - 1;
316 res.flags = IORESOURCE_MEM;
319 rcar_pcie_set_outbound(pcie, window, &win);
321 ep->ob_mapped_addr[window] = addr;
326 static void rcar_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn,
329 struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
330 struct resource_entry win;
334 for (idx = 0; idx < ep->num_ob_windows; idx++)
335 if (ep->ob_mapped_addr[idx] == addr)
338 if (idx >= ep->num_ob_windows)
341 memset(&win, 0x0, sizeof(win));
342 memset(&res, 0x0, sizeof(res));
344 rcar_pcie_set_outbound(&ep->pcie, idx, &win);
346 ep->ob_mapped_addr[idx] = 0;
349 static int rcar_pcie_ep_assert_intx(struct rcar_pcie_endpoint *ep,
352 struct rcar_pcie *pcie = &ep->pcie;
355 val = rcar_pci_read_reg(pcie, PCIEMSITXR);
356 if ((val & PCI_MSI_FLAGS_ENABLE)) {
357 dev_err(pcie->dev, "MSI is enabled, cannot assert INTx\n");
361 val = rcar_pci_read_reg(pcie, PCICONF(1));
362 if ((val & INTDIS)) {
363 dev_err(pcie->dev, "INTx message transmission is disabled\n");
367 val = rcar_pci_read_reg(pcie, PCIEINTXR);
368 if ((val & ASTINTX)) {
369 dev_err(pcie->dev, "INTx is already asserted\n");
374 rcar_pci_write_reg(pcie, val, PCIEINTXR);
375 usleep_range(1000, 1001);
376 val = rcar_pci_read_reg(pcie, PCIEINTXR);
378 rcar_pci_write_reg(pcie, val, PCIEINTXR);
383 static int rcar_pcie_ep_assert_msi(struct rcar_pcie *pcie,
384 u8 fn, u8 interrupt_num)
389 /* Check MSI enable bit */
390 val = rcar_pci_read_reg(pcie, MSICAP(fn));
391 if (!(val & MSICAP0_MSIE))
394 /* Get MSI numbers from MME */
395 msi_count = ((val & MSICAP0_MMESE_MASK) >> MSICAP0_MMESE_OFFSET);
396 msi_count = 1 << msi_count;
398 if (!interrupt_num || interrupt_num > msi_count)
401 val = rcar_pci_read_reg(pcie, PCIEMSITXR);
402 rcar_pci_write_reg(pcie, val | (interrupt_num - 1), PCIEMSITXR);
407 static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
408 enum pci_epc_irq_type type,
411 struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
414 case PCI_EPC_IRQ_LEGACY:
415 return rcar_pcie_ep_assert_intx(ep, fn, 0);
417 case PCI_EPC_IRQ_MSI:
418 return rcar_pcie_ep_assert_msi(&ep->pcie, fn, interrupt_num);
425 static int rcar_pcie_ep_start(struct pci_epc *epc)
427 struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
429 rcar_pci_write_reg(&ep->pcie, MACCTLR_INIT_VAL, MACCTLR);
430 rcar_pci_write_reg(&ep->pcie, CFINIT, PCIETCTLR);
435 static void rcar_pcie_ep_stop(struct pci_epc *epc)
437 struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
439 rcar_pci_write_reg(&ep->pcie, 0, PCIETCTLR);
442 static const struct pci_epc_features rcar_pcie_epc_features = {
443 .linkup_notifier = false,
445 .msix_capable = false,
446 /* use 64-bit BARs so mark BAR[1,3,5] as reserved */
447 .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
448 .bar_fixed_64bit = 1 << BAR_0 | 1 << BAR_2 | 1 << BAR_4,
449 .bar_fixed_size[0] = 128,
450 .bar_fixed_size[2] = 256,
451 .bar_fixed_size[4] = 256,
454 static const struct pci_epc_features*
455 rcar_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
457 return &rcar_pcie_epc_features;
460 static const struct pci_epc_ops rcar_pcie_epc_ops = {
461 .write_header = rcar_pcie_ep_write_header,
462 .set_bar = rcar_pcie_ep_set_bar,
463 .clear_bar = rcar_pcie_ep_clear_bar,
464 .set_msi = rcar_pcie_ep_set_msi,
465 .get_msi = rcar_pcie_ep_get_msi,
466 .map_addr = rcar_pcie_ep_map_addr,
467 .unmap_addr = rcar_pcie_ep_unmap_addr,
468 .raise_irq = rcar_pcie_ep_raise_irq,
469 .start = rcar_pcie_ep_start,
470 .stop = rcar_pcie_ep_stop,
471 .get_features = rcar_pcie_ep_get_features,
474 static const struct of_device_id rcar_pcie_ep_of_match[] = {
475 { .compatible = "renesas,r8a774c0-pcie-ep", },
476 { .compatible = "renesas,rcar-gen3-pcie-ep" },
480 static int rcar_pcie_ep_probe(struct platform_device *pdev)
482 struct device *dev = &pdev->dev;
483 struct rcar_pcie_endpoint *ep;
484 struct rcar_pcie *pcie;
488 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
495 pm_runtime_enable(dev);
496 err = pm_runtime_resume_and_get(dev);
498 dev_err(dev, "pm_runtime_resume_and_get failed\n");
502 err = rcar_pcie_ep_get_pdata(ep, pdev);
504 dev_err(dev, "failed to request resources: %d\n", err);
508 ep->num_ib_windows = MAX_NR_INBOUND_MAPS;
510 devm_kcalloc(dev, BITS_TO_LONGS(ep->num_ib_windows),
511 sizeof(long), GFP_KERNEL);
512 if (!ep->ib_window_map) {
514 dev_err(dev, "failed to allocate memory for inbound map\n");
518 ep->ob_mapped_addr = devm_kcalloc(dev, ep->num_ob_windows,
519 sizeof(*ep->ob_mapped_addr),
521 if (!ep->ob_mapped_addr) {
523 dev_err(dev, "failed to allocate memory for outbound memory pointers\n");
527 epc = devm_pci_epc_create(dev, &rcar_pcie_epc_ops);
529 dev_err(dev, "failed to create epc device\n");
534 epc->max_functions = ep->max_functions;
535 epc_set_drvdata(epc, ep);
537 rcar_pcie_ep_hw_init(pcie);
539 err = pci_epc_multi_mem_init(epc, ep->ob_window, ep->num_ob_windows);
541 dev_err(dev, "failed to initialize the epc memory space\n");
551 pm_runtime_disable(dev);
556 static struct platform_driver rcar_pcie_ep_driver = {
558 .name = "rcar-pcie-ep",
559 .of_match_table = rcar_pcie_ep_of_match,
560 .suppress_bind_attrs = true,
562 .probe = rcar_pcie_ep_probe,
564 builtin_platform_driver(rcar_pcie_ep_driver);