1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/msi.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/of_platform.h>
22 #include <linux/pci.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/reset.h>
30 /* PCIe shared registers */
31 #define PCIE_SYS_CFG 0x00
32 #define PCIE_INT_ENABLE 0x0c
33 #define PCIE_CFG_ADDR 0x20
34 #define PCIE_CFG_DATA 0x24
36 /* PCIe per port registers */
37 #define PCIE_BAR0_SETUP 0x10
38 #define PCIE_CLASS 0x34
39 #define PCIE_LINK_STATUS 0x50
41 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
42 #define PCIE_PORT_PERST(x) BIT(1 + (x))
43 #define PCIE_PORT_LINKUP BIT(0)
44 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
46 #define PCIE_BAR_ENABLE BIT(0)
47 #define PCIE_REVISION_ID BIT(0)
48 #define PCIE_CLASS_CODE (0x60400 << 8)
49 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
50 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
51 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
52 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
53 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
54 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
55 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
56 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
58 /* MediaTek specific configuration registers */
59 #define PCIE_FTS_NUM 0x70c
60 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
61 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
63 #define PCIE_FC_CREDIT 0x73c
64 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
65 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
67 /* PCIe V2 share registers */
68 #define PCIE_SYS_CFG_V2 0x0
69 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
70 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
72 /* PCIe V2 per-port registers */
73 #define PCIE_MSI_VECTOR 0x0c0
75 #define PCIE_CONF_VEND_ID 0x100
76 #define PCIE_CONF_DEVICE_ID 0x102
77 #define PCIE_CONF_CLASS_ID 0x106
79 #define PCIE_INT_MASK 0x420
80 #define INTX_MASK GENMASK(19, 16)
82 #define PCIE_INT_STATUS 0x424
83 #define MSI_STATUS BIT(23)
84 #define PCIE_IMSI_STATUS 0x42c
85 #define PCIE_IMSI_ADDR 0x430
86 #define MSI_MASK BIT(23)
87 #define MTK_MSI_IRQS_NUM 32
89 #define PCIE_AHB_TRANS_BASE0_L 0x438
90 #define PCIE_AHB_TRANS_BASE0_H 0x43c
91 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
92 #define PCIE_AXI_WINDOW0 0x448
93 #define WIN_ENABLE BIT(7)
95 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
96 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
97 * start from 0x40000000).
99 #define PCIE2AHB_SIZE 0x21
101 /* PCIe V2 configuration transaction header */
102 #define PCIE_CFG_HEADER0 0x460
103 #define PCIE_CFG_HEADER1 0x464
104 #define PCIE_CFG_HEADER2 0x468
105 #define PCIE_CFG_WDATA 0x470
106 #define PCIE_APP_TLP_REQ 0x488
107 #define PCIE_CFG_RDATA 0x48c
108 #define APP_CFG_REQ BIT(0)
109 #define APP_CPL_STATUS GENMASK(7, 5)
111 #define CFG_WRRD_TYPE_0 4
115 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
116 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
117 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
118 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
119 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
120 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
121 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
122 #define CFG_HEADER_DW0(type, fmt) \
123 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
124 #define CFG_HEADER_DW1(where, size) \
125 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
126 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
127 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
128 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
130 #define PCIE_RST_CTRL 0x510
131 #define PCIE_PHY_RSTB BIT(0)
132 #define PCIE_PIPE_SRSTB BIT(1)
133 #define PCIE_MAC_SRSTB BIT(2)
134 #define PCIE_CRSTB BIT(3)
135 #define PCIE_PERSTB BIT(8)
136 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
137 #define PCIE_LINK_STATUS_V2 0x804
138 #define PCIE_PORT_LINKUP_V2 BIT(10)
140 struct mtk_pcie_port;
143 * struct mtk_pcie_soc - differentiate between host generations
144 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
145 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
146 * @no_msi: Bridge has no MSI support, and relies on an external block
147 * @device_id: device ID which this host need to be fixed
148 * @ops: pointer to configuration access functions
149 * @startup: pointer to controller setting functions
150 * @setup_irq: pointer to initialize IRQ functions
152 struct mtk_pcie_soc {
153 bool need_fix_class_id;
154 bool need_fix_device_id;
156 unsigned int device_id;
158 int (*startup)(struct mtk_pcie_port *port);
159 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
163 * struct mtk_pcie_port - PCIe port information
164 * @base: IO mapped register base
166 * @pcie: pointer to PCIe host info
167 * @reset: pointer to port reset control
168 * @sys_ck: pointer to transaction/data link layer clock
169 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
170 * and RC initiated MMIO access
171 * @axi_ck: pointer to application layer MMIO channel operating clock
172 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
173 * when pcie_mac_ck/pcie_pipe_ck is turned off
174 * @obff_ck: pointer to OBFF functional block operating clock
175 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
176 * @phy: pointer to PHY control block
179 * @irq_domain: legacy INTx IRQ domain
180 * @inner_domain: inner IRQ domain
181 * @msi_domain: MSI IRQ domain
182 * @lock: protect the msi_irq_in_use bitmap
183 * @msi_irq_in_use: bit map for assigned MSI IRQ
185 struct mtk_pcie_port {
187 struct list_head list;
188 struct mtk_pcie *pcie;
189 struct reset_control *reset;
199 struct irq_domain *irq_domain;
200 struct irq_domain *inner_domain;
201 struct irq_domain *msi_domain;
203 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
207 * struct mtk_pcie - PCIe host information
208 * @dev: pointer to PCIe device
209 * @base: IO mapped register base
210 * @free_ck: free-run reference clock
211 * @mem: non-prefetchable memory resource
212 * @ports: pointer to PCIe port information
213 * @soc: pointer to SoC-dependent operations
220 struct list_head ports;
221 const struct mtk_pcie_soc *soc;
224 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
226 struct device *dev = pcie->dev;
228 clk_disable_unprepare(pcie->free_ck);
230 pm_runtime_put_sync(dev);
231 pm_runtime_disable(dev);
234 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
236 struct mtk_pcie *pcie = port->pcie;
237 struct device *dev = pcie->dev;
239 devm_iounmap(dev, port->base);
240 list_del(&port->list);
241 devm_kfree(dev, port);
244 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
246 struct mtk_pcie_port *port, *tmp;
248 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
249 phy_power_off(port->phy);
251 clk_disable_unprepare(port->pipe_ck);
252 clk_disable_unprepare(port->obff_ck);
253 clk_disable_unprepare(port->axi_ck);
254 clk_disable_unprepare(port->aux_ck);
255 clk_disable_unprepare(port->ahb_ck);
256 clk_disable_unprepare(port->sys_ck);
257 mtk_pcie_port_free(port);
260 mtk_pcie_subsys_powerdown(pcie);
263 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
268 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
269 !(val & APP_CFG_REQ), 10,
270 100 * USEC_PER_MSEC);
272 return PCIBIOS_SET_FAILED;
274 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
275 return PCIBIOS_SET_FAILED;
277 return PCIBIOS_SUCCESSFUL;
280 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
281 int where, int size, u32 *val)
285 /* Write PCIe configuration transaction header for Cfgrd */
286 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
287 port->base + PCIE_CFG_HEADER0);
288 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
289 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
290 port->base + PCIE_CFG_HEADER2);
292 /* Trigger h/w to transmit Cfgrd TLP */
293 tmp = readl(port->base + PCIE_APP_TLP_REQ);
295 writel(tmp, port->base + PCIE_APP_TLP_REQ);
297 /* Check completion status */
298 if (mtk_pcie_check_cfg_cpld(port))
299 return PCIBIOS_SET_FAILED;
301 /* Read cpld payload of Cfgrd */
302 *val = readl(port->base + PCIE_CFG_RDATA);
305 *val = (*val >> (8 * (where & 3))) & 0xff;
307 *val = (*val >> (8 * (where & 3))) & 0xffff;
309 return PCIBIOS_SUCCESSFUL;
312 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
313 int where, int size, u32 val)
315 /* Write PCIe configuration transaction header for Cfgwr */
316 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
317 port->base + PCIE_CFG_HEADER0);
318 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
319 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
320 port->base + PCIE_CFG_HEADER2);
322 /* Write Cfgwr data */
323 val = val << 8 * (where & 3);
324 writel(val, port->base + PCIE_CFG_WDATA);
326 /* Trigger h/w to transmit Cfgwr TLP */
327 val = readl(port->base + PCIE_APP_TLP_REQ);
329 writel(val, port->base + PCIE_APP_TLP_REQ);
331 /* Check completion status */
332 return mtk_pcie_check_cfg_cpld(port);
335 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
338 struct mtk_pcie *pcie = bus->sysdata;
339 struct mtk_pcie_port *port;
340 struct pci_dev *dev = NULL;
343 * Walk the bus hierarchy to get the devfn value
344 * of the port in the root bus.
346 while (bus && bus->number) {
352 list_for_each_entry(port, &pcie->ports, list)
353 if (port->slot == PCI_SLOT(devfn))
359 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
360 int where, int size, u32 *val)
362 struct mtk_pcie_port *port;
363 u32 bn = bus->number;
366 port = mtk_pcie_find_port(bus, devfn);
369 return PCIBIOS_DEVICE_NOT_FOUND;
372 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
379 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
380 int where, int size, u32 val)
382 struct mtk_pcie_port *port;
383 u32 bn = bus->number;
385 port = mtk_pcie_find_port(bus, devfn);
387 return PCIBIOS_DEVICE_NOT_FOUND;
389 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
392 static struct pci_ops mtk_pcie_ops_v2 = {
393 .read = mtk_pcie_config_read,
394 .write = mtk_pcie_config_write,
397 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
399 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
402 /* MT2712/MT7622 only support 32-bit MSI addresses */
403 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
405 msg->address_lo = lower_32_bits(addr);
407 msg->data = data->hwirq;
409 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
410 (int)data->hwirq, msg->address_hi, msg->address_lo);
413 static int mtk_msi_set_affinity(struct irq_data *irq_data,
414 const struct cpumask *mask, bool force)
419 static void mtk_msi_ack_irq(struct irq_data *data)
421 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
422 u32 hwirq = data->hwirq;
424 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
427 static struct irq_chip mtk_msi_bottom_irq_chip = {
429 .irq_compose_msi_msg = mtk_compose_msi_msg,
430 .irq_set_affinity = mtk_msi_set_affinity,
431 .irq_ack = mtk_msi_ack_irq,
434 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
435 unsigned int nr_irqs, void *args)
437 struct mtk_pcie_port *port = domain->host_data;
440 WARN_ON(nr_irqs != 1);
441 mutex_lock(&port->lock);
443 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
444 if (bit >= MTK_MSI_IRQS_NUM) {
445 mutex_unlock(&port->lock);
449 __set_bit(bit, port->msi_irq_in_use);
451 mutex_unlock(&port->lock);
453 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
454 domain->host_data, handle_edge_irq,
460 static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
461 unsigned int virq, unsigned int nr_irqs)
463 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
464 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
466 mutex_lock(&port->lock);
468 if (!test_bit(d->hwirq, port->msi_irq_in_use))
469 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
472 __clear_bit(d->hwirq, port->msi_irq_in_use);
474 mutex_unlock(&port->lock);
476 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
479 static const struct irq_domain_ops msi_domain_ops = {
480 .alloc = mtk_pcie_irq_domain_alloc,
481 .free = mtk_pcie_irq_domain_free,
484 static struct irq_chip mtk_msi_irq_chip = {
485 .name = "MTK PCIe MSI",
486 .irq_ack = irq_chip_ack_parent,
487 .irq_mask = pci_msi_mask_irq,
488 .irq_unmask = pci_msi_unmask_irq,
491 static struct msi_domain_info mtk_msi_domain_info = {
492 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
494 .chip = &mtk_msi_irq_chip,
497 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
499 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
501 mutex_init(&port->lock);
503 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
504 &msi_domain_ops, port);
505 if (!port->inner_domain) {
506 dev_err(port->pcie->dev, "failed to create IRQ domain\n");
510 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
512 if (!port->msi_domain) {
513 dev_err(port->pcie->dev, "failed to create MSI domain\n");
514 irq_domain_remove(port->inner_domain);
521 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
524 phys_addr_t msg_addr;
526 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
527 val = lower_32_bits(msg_addr);
528 writel(val, port->base + PCIE_IMSI_ADDR);
530 val = readl(port->base + PCIE_INT_MASK);
532 writel(val, port->base + PCIE_INT_MASK);
535 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
537 struct mtk_pcie_port *port, *tmp;
539 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
540 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
542 if (port->irq_domain)
543 irq_domain_remove(port->irq_domain);
545 if (IS_ENABLED(CONFIG_PCI_MSI)) {
546 if (port->msi_domain)
547 irq_domain_remove(port->msi_domain);
548 if (port->inner_domain)
549 irq_domain_remove(port->inner_domain);
552 irq_dispose_mapping(port->irq);
556 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
557 irq_hw_number_t hwirq)
559 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
560 irq_set_chip_data(irq, domain->host_data);
565 static const struct irq_domain_ops intx_domain_ops = {
566 .map = mtk_pcie_intx_map,
569 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
570 struct device_node *node)
572 struct device *dev = port->pcie->dev;
573 struct device_node *pcie_intc_node;
577 pcie_intc_node = of_get_next_child(node, NULL);
578 if (!pcie_intc_node) {
579 dev_err(dev, "no PCIe Intc node found\n");
583 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
584 &intx_domain_ops, port);
585 of_node_put(pcie_intc_node);
586 if (!port->irq_domain) {
587 dev_err(dev, "failed to get INTx IRQ domain\n");
591 if (IS_ENABLED(CONFIG_PCI_MSI)) {
592 ret = mtk_pcie_allocate_msi_domains(port);
600 static void mtk_pcie_intr_handler(struct irq_desc *desc)
602 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
603 struct irq_chip *irqchip = irq_desc_get_chip(desc);
604 unsigned long status;
605 u32 bit = INTX_SHIFT;
607 chained_irq_enter(irqchip, desc);
609 status = readl(port->base + PCIE_INT_STATUS);
610 if (status & INTX_MASK) {
611 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
613 writel(1 << bit, port->base + PCIE_INT_STATUS);
614 generic_handle_domain_irq(port->irq_domain,
619 if (IS_ENABLED(CONFIG_PCI_MSI)) {
620 if (status & MSI_STATUS){
621 unsigned long imsi_status;
623 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
624 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
625 generic_handle_domain_irq(port->inner_domain, bit);
627 /* Clear MSI interrupt status */
628 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
632 chained_irq_exit(irqchip, desc);
635 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
636 struct device_node *node)
638 struct mtk_pcie *pcie = port->pcie;
639 struct device *dev = pcie->dev;
640 struct platform_device *pdev = to_platform_device(dev);
643 err = mtk_pcie_init_irq_domain(port, node);
645 dev_err(dev, "failed to init PCIe IRQ domain\n");
649 port->irq = platform_get_irq(pdev, port->slot);
653 irq_set_chained_handler_and_data(port->irq,
654 mtk_pcie_intr_handler, port);
659 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
661 struct mtk_pcie *pcie = port->pcie;
662 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
663 struct resource *mem = NULL;
664 struct resource_entry *entry;
665 const struct mtk_pcie_soc *soc = port->pcie->soc;
669 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
675 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
677 val = readl(pcie->base + PCIE_SYS_CFG_V2);
678 val |= PCIE_CSR_LTSSM_EN(port->slot) |
679 PCIE_CSR_ASPM_L1_EN(port->slot);
680 writel(val, pcie->base + PCIE_SYS_CFG_V2);
683 /* Assert all reset signals */
684 writel(0, port->base + PCIE_RST_CTRL);
687 * Enable PCIe link down reset, if link status changed from link up to
688 * link down, this will reset MAC control registers and configuration
691 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
693 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
694 val = readl(port->base + PCIE_RST_CTRL);
695 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
696 PCIE_MAC_SRSTB | PCIE_CRSTB;
697 writel(val, port->base + PCIE_RST_CTRL);
699 /* Set up vendor ID and class code */
700 if (soc->need_fix_class_id) {
701 val = PCI_VENDOR_ID_MEDIATEK;
702 writew(val, port->base + PCIE_CONF_VEND_ID);
704 val = PCI_CLASS_BRIDGE_PCI;
705 writew(val, port->base + PCIE_CONF_CLASS_ID);
708 if (soc->need_fix_device_id)
709 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
711 /* 100ms timeout value should be enough for Gen1/2 training */
712 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
713 !!(val & PCIE_PORT_LINKUP_V2), 20,
714 100 * USEC_PER_MSEC);
719 val = readl(port->base + PCIE_INT_MASK);
721 writel(val, port->base + PCIE_INT_MASK);
723 if (IS_ENABLED(CONFIG_PCI_MSI))
724 mtk_pcie_enable_msi(port);
726 /* Set AHB to PCIe translation windows */
727 val = lower_32_bits(mem->start) |
728 AHB2PCIE_SIZE(fls(resource_size(mem)));
729 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
731 val = upper_32_bits(mem->start);
732 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
734 /* Set PCIe to AXI translation memory space.*/
735 val = PCIE2AHB_SIZE | WIN_ENABLE;
736 writel(val, port->base + PCIE_AXI_WINDOW0);
741 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
742 unsigned int devfn, int where)
744 struct mtk_pcie *pcie = bus->sysdata;
746 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
747 bus->number), pcie->base + PCIE_CFG_ADDR);
749 return pcie->base + PCIE_CFG_DATA + (where & 3);
752 static struct pci_ops mtk_pcie_ops = {
753 .map_bus = mtk_pcie_map_bus,
754 .read = pci_generic_config_read,
755 .write = pci_generic_config_write,
758 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
760 struct mtk_pcie *pcie = port->pcie;
761 u32 func = PCI_FUNC(port->slot);
762 u32 slot = PCI_SLOT(port->slot << 3);
766 /* assert port PERST_N */
767 val = readl(pcie->base + PCIE_SYS_CFG);
768 val |= PCIE_PORT_PERST(port->slot);
769 writel(val, pcie->base + PCIE_SYS_CFG);
771 /* de-assert port PERST_N */
772 val = readl(pcie->base + PCIE_SYS_CFG);
773 val &= ~PCIE_PORT_PERST(port->slot);
774 writel(val, pcie->base + PCIE_SYS_CFG);
776 /* 100ms timeout value should be enough for Gen1/2 training */
777 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
778 !!(val & PCIE_PORT_LINKUP), 20,
779 100 * USEC_PER_MSEC);
783 /* enable interrupt */
784 val = readl(pcie->base + PCIE_INT_ENABLE);
785 val |= PCIE_PORT_INT_EN(port->slot);
786 writel(val, pcie->base + PCIE_INT_ENABLE);
788 /* map to all DDR region. We need to set it before cfg operation. */
789 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
790 port->base + PCIE_BAR0_SETUP);
792 /* configure class code and revision ID */
793 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
795 /* configure FC credit */
796 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
797 pcie->base + PCIE_CFG_ADDR);
798 val = readl(pcie->base + PCIE_CFG_DATA);
799 val &= ~PCIE_FC_CREDIT_MASK;
800 val |= PCIE_FC_CREDIT_VAL(0x806c);
801 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
802 pcie->base + PCIE_CFG_ADDR);
803 writel(val, pcie->base + PCIE_CFG_DATA);
805 /* configure RC FTS number to 250 when it leaves L0s */
806 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
807 pcie->base + PCIE_CFG_ADDR);
808 val = readl(pcie->base + PCIE_CFG_DATA);
809 val &= ~PCIE_FTS_NUM_MASK;
810 val |= PCIE_FTS_NUM_L0(0x50);
811 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
812 pcie->base + PCIE_CFG_ADDR);
813 writel(val, pcie->base + PCIE_CFG_DATA);
818 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
820 struct mtk_pcie *pcie = port->pcie;
821 struct device *dev = pcie->dev;
824 err = clk_prepare_enable(port->sys_ck);
826 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
830 err = clk_prepare_enable(port->ahb_ck);
832 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
836 err = clk_prepare_enable(port->aux_ck);
838 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
842 err = clk_prepare_enable(port->axi_ck);
844 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
848 err = clk_prepare_enable(port->obff_ck);
850 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
854 err = clk_prepare_enable(port->pipe_ck);
856 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
860 reset_control_assert(port->reset);
861 reset_control_deassert(port->reset);
863 err = phy_init(port->phy);
865 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
869 err = phy_power_on(port->phy);
871 dev_err(dev, "failed to power on port%d phy\n", port->slot);
875 if (!pcie->soc->startup(port))
878 dev_info(dev, "Port%d link down\n", port->slot);
880 phy_power_off(port->phy);
884 clk_disable_unprepare(port->pipe_ck);
886 clk_disable_unprepare(port->obff_ck);
888 clk_disable_unprepare(port->axi_ck);
890 clk_disable_unprepare(port->aux_ck);
892 clk_disable_unprepare(port->ahb_ck);
894 clk_disable_unprepare(port->sys_ck);
896 mtk_pcie_port_free(port);
899 static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
900 struct device_node *node,
903 struct mtk_pcie_port *port;
904 struct device *dev = pcie->dev;
905 struct platform_device *pdev = to_platform_device(dev);
909 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
913 snprintf(name, sizeof(name), "port%d", slot);
914 port->base = devm_platform_ioremap_resource_byname(pdev, name);
915 if (IS_ERR(port->base)) {
916 dev_err(dev, "failed to map port%d base\n", slot);
917 return PTR_ERR(port->base);
920 snprintf(name, sizeof(name), "sys_ck%d", slot);
921 port->sys_ck = devm_clk_get(dev, name);
922 if (IS_ERR(port->sys_ck)) {
923 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
924 return PTR_ERR(port->sys_ck);
927 /* sys_ck might be divided into the following parts in some chips */
928 snprintf(name, sizeof(name), "ahb_ck%d", slot);
929 port->ahb_ck = devm_clk_get_optional(dev, name);
930 if (IS_ERR(port->ahb_ck))
931 return PTR_ERR(port->ahb_ck);
933 snprintf(name, sizeof(name), "axi_ck%d", slot);
934 port->axi_ck = devm_clk_get_optional(dev, name);
935 if (IS_ERR(port->axi_ck))
936 return PTR_ERR(port->axi_ck);
938 snprintf(name, sizeof(name), "aux_ck%d", slot);
939 port->aux_ck = devm_clk_get_optional(dev, name);
940 if (IS_ERR(port->aux_ck))
941 return PTR_ERR(port->aux_ck);
943 snprintf(name, sizeof(name), "obff_ck%d", slot);
944 port->obff_ck = devm_clk_get_optional(dev, name);
945 if (IS_ERR(port->obff_ck))
946 return PTR_ERR(port->obff_ck);
948 snprintf(name, sizeof(name), "pipe_ck%d", slot);
949 port->pipe_ck = devm_clk_get_optional(dev, name);
950 if (IS_ERR(port->pipe_ck))
951 return PTR_ERR(port->pipe_ck);
953 snprintf(name, sizeof(name), "pcie-rst%d", slot);
954 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
955 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
956 return PTR_ERR(port->reset);
958 /* some platforms may use default PHY setting */
959 snprintf(name, sizeof(name), "pcie-phy%d", slot);
960 port->phy = devm_phy_optional_get(dev, name);
961 if (IS_ERR(port->phy))
962 return PTR_ERR(port->phy);
967 if (pcie->soc->setup_irq) {
968 err = pcie->soc->setup_irq(port, node);
973 INIT_LIST_HEAD(&port->list);
974 list_add_tail(&port->list, &pcie->ports);
979 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
981 struct device *dev = pcie->dev;
982 struct platform_device *pdev = to_platform_device(dev);
983 struct resource *regs;
986 /* get shared registers, which are optional */
987 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
989 pcie->base = devm_ioremap_resource(dev, regs);
990 if (IS_ERR(pcie->base))
991 return PTR_ERR(pcie->base);
994 pcie->free_ck = devm_clk_get(dev, "free_ck");
995 if (IS_ERR(pcie->free_ck)) {
996 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
997 return -EPROBE_DEFER;
999 pcie->free_ck = NULL;
1002 pm_runtime_enable(dev);
1003 pm_runtime_get_sync(dev);
1005 /* enable top level clock */
1006 err = clk_prepare_enable(pcie->free_ck);
1008 dev_err(dev, "failed to enable free_ck\n");
1015 pm_runtime_put_sync(dev);
1016 pm_runtime_disable(dev);
1021 static int mtk_pcie_setup(struct mtk_pcie *pcie)
1023 struct device *dev = pcie->dev;
1024 struct device_node *node = dev->of_node, *child;
1025 struct mtk_pcie_port *port, *tmp;
1028 for_each_available_child_of_node(node, child) {
1031 err = of_pci_get_devfn(child);
1033 dev_err(dev, "failed to parse devfn: %d\n", err);
1034 goto error_put_node;
1037 slot = PCI_SLOT(err);
1039 err = mtk_pcie_parse_port(pcie, child, slot);
1041 goto error_put_node;
1044 err = mtk_pcie_subsys_powerup(pcie);
1048 /* enable each port, and then check link status */
1049 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1050 mtk_pcie_enable_port(port);
1052 /* power down PCIe subsys if slots are all empty (link down) */
1053 if (list_empty(&pcie->ports))
1054 mtk_pcie_subsys_powerdown(pcie);
1062 static int mtk_pcie_probe(struct platform_device *pdev)
1064 struct device *dev = &pdev->dev;
1065 struct mtk_pcie *pcie;
1066 struct pci_host_bridge *host;
1069 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1073 pcie = pci_host_bridge_priv(host);
1076 pcie->soc = of_device_get_match_data(dev);
1077 platform_set_drvdata(pdev, pcie);
1078 INIT_LIST_HEAD(&pcie->ports);
1080 err = mtk_pcie_setup(pcie);
1084 host->ops = pcie->soc->ops;
1085 host->sysdata = pcie;
1086 host->msi_domain = pcie->soc->no_msi;
1088 err = pci_host_probe(host);
1095 if (!list_empty(&pcie->ports))
1096 mtk_pcie_put_resources(pcie);
1102 static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1104 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1105 struct list_head *windows = &host->windows;
1107 pci_free_resource_list(windows);
1110 static int mtk_pcie_remove(struct platform_device *pdev)
1112 struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1113 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1115 pci_stop_root_bus(host->bus);
1116 pci_remove_root_bus(host->bus);
1117 mtk_pcie_free_resources(pcie);
1119 mtk_pcie_irq_teardown(pcie);
1121 mtk_pcie_put_resources(pcie);
1126 static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
1128 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1129 struct mtk_pcie_port *port;
1131 if (list_empty(&pcie->ports))
1134 list_for_each_entry(port, &pcie->ports, list) {
1135 clk_disable_unprepare(port->pipe_ck);
1136 clk_disable_unprepare(port->obff_ck);
1137 clk_disable_unprepare(port->axi_ck);
1138 clk_disable_unprepare(port->aux_ck);
1139 clk_disable_unprepare(port->ahb_ck);
1140 clk_disable_unprepare(port->sys_ck);
1141 phy_power_off(port->phy);
1142 phy_exit(port->phy);
1145 clk_disable_unprepare(pcie->free_ck);
1150 static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
1152 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1153 struct mtk_pcie_port *port, *tmp;
1155 if (list_empty(&pcie->ports))
1158 clk_prepare_enable(pcie->free_ck);
1160 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1161 mtk_pcie_enable_port(port);
1163 /* In case of EP was removed while system suspend. */
1164 if (list_empty(&pcie->ports))
1165 clk_disable_unprepare(pcie->free_ck);
1170 static const struct dev_pm_ops mtk_pcie_pm_ops = {
1171 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1172 mtk_pcie_resume_noirq)
1175 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1177 .ops = &mtk_pcie_ops,
1178 .startup = mtk_pcie_startup_port,
1181 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1182 .ops = &mtk_pcie_ops_v2,
1183 .startup = mtk_pcie_startup_port_v2,
1184 .setup_irq = mtk_pcie_setup_irq,
1187 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1188 .need_fix_class_id = true,
1189 .ops = &mtk_pcie_ops_v2,
1190 .startup = mtk_pcie_startup_port_v2,
1191 .setup_irq = mtk_pcie_setup_irq,
1194 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1195 .need_fix_class_id = true,
1196 .need_fix_device_id = true,
1197 .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1198 .ops = &mtk_pcie_ops_v2,
1199 .startup = mtk_pcie_startup_port_v2,
1200 .setup_irq = mtk_pcie_setup_irq,
1203 static const struct of_device_id mtk_pcie_ids[] = {
1204 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1205 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1206 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1207 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1208 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1211 MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
1213 static struct platform_driver mtk_pcie_driver = {
1214 .probe = mtk_pcie_probe,
1215 .remove = mtk_pcie_remove,
1218 .of_match_table = mtk_pcie_ids,
1219 .suppress_bind_attrs = true,
1220 .pm = &mtk_pcie_pm_ops,
1223 module_platform_driver(mtk_pcie_driver);
1224 MODULE_LICENSE("GPL v2");