1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra194 SoC
5 * Copyright (C) 2019 NVIDIA Corporation.
7 * Author: Vidya Sagar <vidyas@nvidia.com>
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_pci.h>
24 #include <linux/pci.h>
25 #include <linux/phy/phy.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/random.h>
30 #include <linux/reset.h>
31 #include <linux/resource.h>
32 #include <linux/types.h>
33 #include "pcie-designware.h"
34 #include <soc/tegra/bpmp.h>
35 #include <soc/tegra/bpmp-abi.h>
36 #include "../../pci.h"
38 #define APPL_PINMUX 0x0
39 #define APPL_PINMUX_PEX_RST BIT(0)
40 #define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2)
41 #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3)
42 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4)
43 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5)
46 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6)
47 #define APPL_CTRL_LTSSM_EN BIT(7)
48 #define APPL_CTRL_HW_HOT_RST_EN BIT(20)
49 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
50 #define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22
51 #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1
53 #define APPL_INTR_EN_L0_0 0x8
54 #define APPL_INTR_EN_L0_0_LINK_STATE_INT_EN BIT(0)
55 #define APPL_INTR_EN_L0_0_MSI_RCV_INT_EN BIT(4)
56 #define APPL_INTR_EN_L0_0_INT_INT_EN BIT(8)
57 #define APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN BIT(15)
58 #define APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN BIT(19)
59 #define APPL_INTR_EN_L0_0_SYS_INTR_EN BIT(30)
60 #define APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN BIT(31)
62 #define APPL_INTR_STATUS_L0 0xC
63 #define APPL_INTR_STATUS_L0_LINK_STATE_INT BIT(0)
64 #define APPL_INTR_STATUS_L0_INT_INT BIT(8)
65 #define APPL_INTR_STATUS_L0_PCI_CMD_EN_INT BIT(15)
66 #define APPL_INTR_STATUS_L0_PEX_RST_INT BIT(16)
67 #define APPL_INTR_STATUS_L0_CDM_REG_CHK_INT BIT(18)
69 #define APPL_INTR_EN_L1_0_0 0x1C
70 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1)
71 #define APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN BIT(3)
72 #define APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN BIT(30)
74 #define APPL_INTR_STATUS_L1_0_0 0x20
75 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1)
76 #define APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED BIT(3)
77 #define APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE BIT(30)
79 #define APPL_INTR_STATUS_L1_1 0x2C
80 #define APPL_INTR_STATUS_L1_2 0x30
81 #define APPL_INTR_STATUS_L1_3 0x34
82 #define APPL_INTR_STATUS_L1_6 0x3C
83 #define APPL_INTR_STATUS_L1_7 0x40
84 #define APPL_INTR_STATUS_L1_15_CFG_BME_CHGED BIT(1)
86 #define APPL_INTR_EN_L1_8_0 0x44
87 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2)
88 #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3)
89 #define APPL_INTR_EN_L1_8_INTX_EN BIT(11)
90 #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15)
92 #define APPL_INTR_STATUS_L1_8_0 0x4C
93 #define APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK GENMASK(11, 6)
94 #define APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS BIT(2)
95 #define APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS BIT(3)
97 #define APPL_INTR_STATUS_L1_9 0x54
98 #define APPL_INTR_STATUS_L1_10 0x58
99 #define APPL_INTR_STATUS_L1_11 0x64
100 #define APPL_INTR_STATUS_L1_13 0x74
101 #define APPL_INTR_STATUS_L1_14 0x78
102 #define APPL_INTR_STATUS_L1_15 0x7C
103 #define APPL_INTR_STATUS_L1_17 0x88
105 #define APPL_INTR_EN_L1_18 0x90
106 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMPLT BIT(2)
107 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
108 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0)
110 #define APPL_INTR_STATUS_L1_18 0x94
111 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT BIT(2)
112 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
113 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0)
115 #define APPL_MSI_CTRL_1 0xAC
117 #define APPL_MSI_CTRL_2 0xB0
119 #define APPL_LEGACY_INTX 0xB8
121 #define APPL_LTR_MSG_1 0xC4
122 #define LTR_MSG_REQ BIT(15)
123 #define LTR_MST_NO_SNOOP_SHIFT 16
125 #define APPL_LTR_MSG_2 0xC8
126 #define APPL_LTR_MSG_2_LTR_MSG_REQ_STATE BIT(3)
128 #define APPL_LINK_STATUS 0xCC
129 #define APPL_LINK_STATUS_RDLH_LINK_UP BIT(0)
131 #define APPL_DEBUG 0xD0
132 #define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21)
133 #define APPL_DEBUG_PM_LINKST_IN_L0 0x11
134 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3)
135 #define APPL_DEBUG_LTSSM_STATE_SHIFT 3
136 #define LTSSM_STATE_PRE_DETECT 5
138 #define APPL_RADM_STATUS 0xE4
139 #define APPL_PM_XMT_TURNOFF_STATE BIT(0)
141 #define APPL_DM_TYPE 0x100
142 #define APPL_DM_TYPE_MASK GENMASK(3, 0)
143 #define APPL_DM_TYPE_RP 0x4
144 #define APPL_DM_TYPE_EP 0x0
146 #define APPL_CFG_BASE_ADDR 0x104
147 #define APPL_CFG_BASE_ADDR_MASK GENMASK(31, 12)
149 #define APPL_CFG_IATU_DMA_BASE_ADDR 0x108
150 #define APPL_CFG_IATU_DMA_BASE_ADDR_MASK GENMASK(31, 18)
152 #define APPL_CFG_MISC 0x110
153 #define APPL_CFG_MISC_SLV_EP_MODE BIT(14)
154 #define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10)
155 #define APPL_CFG_MISC_ARCACHE_SHIFT 10
156 #define APPL_CFG_MISC_ARCACHE_VAL 3
158 #define APPL_CFG_SLCG_OVERRIDE 0x114
159 #define APPL_CFG_SLCG_OVERRIDE_SLCG_EN_MASTER BIT(0)
161 #define APPL_CAR_RESET_OVRD 0x12C
162 #define APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N BIT(0)
164 #define IO_BASE_IO_DECODE BIT(0)
165 #define IO_BASE_IO_DECODE_BIT8 BIT(8)
167 #define CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE BIT(0)
168 #define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16)
170 #define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x718
171 #define CFG_TIMER_CTRL_ACK_NAK_SHIFT (19)
173 #define EVENT_COUNTER_ALL_CLEAR 0x3
174 #define EVENT_COUNTER_ENABLE_ALL 0x7
175 #define EVENT_COUNTER_ENABLE_SHIFT 2
176 #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)
177 #define EVENT_COUNTER_EVENT_SEL_SHIFT 16
178 #define EVENT_COUNTER_EVENT_Tx_L0S 0x2
179 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3
180 #define EVENT_COUNTER_EVENT_L1 0x5
181 #define EVENT_COUNTER_EVENT_L1_1 0x7
182 #define EVENT_COUNTER_EVENT_L1_2 0x8
183 #define EVENT_COUNTER_GROUP_SEL_SHIFT 24
184 #define EVENT_COUNTER_GROUP_5 0x5
189 #define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828
191 #define GEN3_EQ_CONTROL_OFF 0x8a8
192 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT 8
193 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
194 #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
196 #define GEN3_RELATED_OFF 0x890
197 #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
198 #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
199 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
200 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
202 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
203 #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
204 #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
205 #define AMBA_ERROR_RESPONSE_CRS_OKAY 0
206 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1
207 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2
209 #define MSIX_ADDR_MATCH_LOW_OFF 0x940
210 #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0)
211 #define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2)
213 #define MSIX_ADDR_MATCH_HIGH_OFF 0x944
214 #define MSIX_ADDR_MATCH_HIGH_OFF_MASK GENMASK(31, 0)
216 #define PORT_LOGIC_MSIX_DOORBELL 0x948
218 #define CAP_SPCIE_CAP_OFF 0x154
219 #define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0)
220 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8)
221 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8
223 #define PME_ACK_TIMEOUT 10000
225 #define LTSSM_TIMEOUT 50000 /* 50ms */
227 #define GEN3_GEN4_EQ_PRESET_INIT 5
229 #define GEN1_CORE_CLK_FREQ 62500000
230 #define GEN2_CORE_CLK_FREQ 125000000
231 #define GEN3_CORE_CLK_FREQ 250000000
232 #define GEN4_CORE_CLK_FREQ 500000000
234 #define LTR_MSG_TIMEOUT (100 * 1000)
236 #define PERST_DEBOUNCE_TIME (5 * 1000)
238 #define EP_STATE_DISABLED 0
239 #define EP_STATE_ENABLED 1
241 static const unsigned int pcie_gen_freq[] = {
248 static const u32 event_cntr_ctrl_offset[] = {
257 static const u32 event_cntr_data_offset[] = {
266 struct tegra_pcie_dw {
268 struct resource *appl_res;
269 struct resource *dbi_res;
270 struct resource *atu_dma_res;
271 void __iomem *appl_base;
272 struct clk *core_clk;
273 struct reset_control *core_apb_rst;
274 struct reset_control *core_rst;
276 struct tegra_bpmp *bpmp;
278 enum dw_pcie_device_mode mode;
280 bool supports_clkreq;
281 bool enable_cdm_check;
283 bool update_fc_fixup;
288 u32 cfg_link_cap_l1sub;
292 u32 aspm_l0s_enter_lat;
294 struct regulator *pex_ctl_supply;
295 struct regulator *slot_ctl_3v3;
296 struct regulator *slot_ctl_12v;
298 unsigned int phy_count;
301 struct dentry *debugfs;
303 /* Endpoint mode specific */
304 struct gpio_desc *pex_rst_gpiod;
305 struct gpio_desc *pex_refclk_sel_gpiod;
306 unsigned int pex_rst_irq;
310 struct tegra_pcie_dw_of_data {
311 enum dw_pcie_device_mode mode;
314 static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
316 return container_of(pci, struct tegra_pcie_dw, pci);
319 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
322 writel_relaxed(value, pcie->appl_base + reg);
325 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg)
327 return readl_relaxed(pcie->appl_base + reg);
330 struct tegra_pcie_soc {
331 enum dw_pcie_device_mode mode;
334 static void apply_bad_link_workaround(struct pcie_port *pp)
336 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
337 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
338 u32 current_link_width;
342 * NOTE:- Since this scenario is uncommon and link as such is not
343 * stable anyway, not waiting to confirm if link is really
344 * transitioning to Gen-2 speed
346 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
347 if (val & PCI_EXP_LNKSTA_LBMS) {
348 current_link_width = (val & PCI_EXP_LNKSTA_NLW) >>
349 PCI_EXP_LNKSTA_NLW_SHIFT;
350 if (pcie->init_link_width > current_link_width) {
351 dev_warn(pci->dev, "PCIe link is bad, width reduced\n");
352 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
354 val &= ~PCI_EXP_LNKCTL2_TLS;
355 val |= PCI_EXP_LNKCTL2_TLS_2_5GT;
356 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
357 PCI_EXP_LNKCTL2, val);
359 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
361 val |= PCI_EXP_LNKCTL_RL;
362 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
363 PCI_EXP_LNKCTL, val);
368 static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
370 struct tegra_pcie_dw *pcie = arg;
371 struct dw_pcie *pci = &pcie->pci;
372 struct pcie_port *pp = &pci->pp;
376 val = appl_readl(pcie, APPL_INTR_STATUS_L0);
377 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
378 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
379 if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {
380 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
382 /* SBR & Surprise Link Down WAR */
383 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
384 val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
385 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
387 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
388 val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
389 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
391 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
392 val |= PORT_LOGIC_SPEED_CHANGE;
393 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
397 if (val & APPL_INTR_STATUS_L0_INT_INT) {
398 val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
399 if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {
401 APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS,
402 APPL_INTR_STATUS_L1_8_0);
403 apply_bad_link_workaround(pp);
405 if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {
407 APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS,
408 APPL_INTR_STATUS_L1_8_0);
410 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
412 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w &
417 val = appl_readl(pcie, APPL_INTR_STATUS_L0);
418 if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) {
419 val = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
420 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
421 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {
422 dev_info(pci->dev, "CDM check complete\n");
423 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
425 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {
426 dev_err(pci->dev, "CDM comparison mismatch\n");
427 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
429 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {
430 dev_err(pci->dev, "CDM Logic error\n");
431 tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
433 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp);
434 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
435 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp);
441 static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie)
445 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
446 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
447 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
448 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
449 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
450 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
451 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
452 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
453 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
454 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
455 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
456 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
457 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
458 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
459 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
460 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2);
462 val = appl_readl(pcie, APPL_CTRL);
463 val |= APPL_CTRL_LTSSM_EN;
464 appl_writel(pcie, val, APPL_CTRL);
467 static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
469 struct tegra_pcie_dw *pcie = arg;
470 struct dw_pcie *pci = &pcie->pci;
473 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
475 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
477 /* If EP doesn't advertise L1SS, just return */
478 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
479 if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2)))
482 /* Check if BME is set to '1' */
483 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
484 if (val & PCI_COMMAND_MASTER) {
487 /* 110us for both snoop and no-snoop */
488 val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ;
489 val |= (val << LTR_MST_NO_SNOOP_SHIFT);
490 appl_writel(pcie, val, APPL_LTR_MSG_1);
492 /* Send LTR upstream */
493 val = appl_readl(pcie, APPL_LTR_MSG_2);
494 val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;
495 appl_writel(pcie, val, APPL_LTR_MSG_2);
497 timeout = ktime_add_us(ktime_get(), LTR_MSG_TIMEOUT);
499 val = appl_readl(pcie, APPL_LTR_MSG_2);
500 if (!(val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE))
502 if (ktime_after(ktime_get(), timeout))
504 usleep_range(1000, 1100);
506 if (val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE)
507 dev_err(pcie->dev, "Failed to send LTR message\n");
513 static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
515 struct tegra_pcie_dw *pcie = arg;
516 struct dw_pcie_ep *ep = &pcie->pci.ep;
520 val = appl_readl(pcie, APPL_INTR_STATUS_L0);
521 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
522 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
523 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
525 if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)
526 pex_ep_event_hot_rst_done(pcie);
528 if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {
529 tmp = appl_readl(pcie, APPL_LINK_STATUS);
530 if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) {
531 dev_dbg(pcie->dev, "Link is up with Host\n");
532 dw_pcie_ep_linkup(ep);
539 if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
540 val = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
541 appl_writel(pcie, val, APPL_INTR_STATUS_L1_15);
543 if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)
544 return IRQ_WAKE_THREAD;
550 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
552 appl_writel(pcie, val, APPL_INTR_STATUS_L0);
558 static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where,
562 * This is an endpoint mode specific register happen to appear even
563 * when controller is operating in root port mode and system hangs
564 * when it is accessed with link being in ASPM-L1 state.
565 * So skip accessing it altogether
567 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) {
569 return PCIBIOS_SUCCESSFUL;
572 return pci_generic_config_read(bus, devfn, where, size, val);
575 static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where,
579 * This is an endpoint mode specific register happen to appear even
580 * when controller is operating in root port mode and system hangs
581 * when it is accessed with link being in ASPM-L1 state.
582 * So skip accessing it altogether
584 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL)
585 return PCIBIOS_SUCCESSFUL;
587 return pci_generic_config_write(bus, devfn, where, size, val);
590 static struct pci_ops tegra_pci_ops = {
591 .map_bus = dw_pcie_own_conf_map_bus,
592 .read = tegra_pcie_dw_rd_own_conf,
593 .write = tegra_pcie_dw_wr_own_conf,
596 #if defined(CONFIG_PCIEASPM)
597 static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
601 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
602 val &= ~PCI_L1SS_CAP_ASPM_L1_1;
603 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
606 static void disable_aspm_l12(struct tegra_pcie_dw *pcie)
610 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
611 val &= ~PCI_L1SS_CAP_ASPM_L1_2;
612 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
615 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
619 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]);
620 val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
621 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
622 val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
623 val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
624 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
625 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]);
630 static int aspm_state_cnt(struct seq_file *s, void *data)
632 struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)
633 dev_get_drvdata(s->private);
636 seq_printf(s, "Tx L0s entry count : %u\n",
637 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S));
639 seq_printf(s, "Rx L0s entry count : %u\n",
640 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S));
642 seq_printf(s, "Link L1 entry count : %u\n",
643 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1));
645 seq_printf(s, "Link L1.1 entry count : %u\n",
646 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1));
648 seq_printf(s, "Link L1.2 entry count : %u\n",
649 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2));
651 /* Clear all counters */
652 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid],
653 EVENT_COUNTER_ALL_CLEAR);
655 /* Re-enable counting */
656 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
657 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
658 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
663 static void init_host_aspm(struct tegra_pcie_dw *pcie)
665 struct dw_pcie *pci = &pcie->pci;
668 val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
669 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP;
671 /* Enable ASPM counters */
672 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
673 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
674 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val);
676 /* Program T_cmrt and T_pwr_on values */
677 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
678 val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE);
679 val |= (pcie->aspm_cmrt << 8);
680 val |= (pcie->aspm_pwr_on_t << 19);
681 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
683 /* Program L0s and L1 entrance latencies */
684 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
685 val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
686 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
687 val |= PORT_AFR_ENTER_ASPM;
688 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
691 static void init_debugfs(struct tegra_pcie_dw *pcie)
693 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs,
697 static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; }
698 static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; }
699 static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; }
700 static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; }
703 static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
705 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
706 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
710 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
711 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
712 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
714 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
715 val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN;
716 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
718 if (pcie->enable_cdm_check) {
719 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
720 val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN;
721 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
723 val = appl_readl(pcie, APPL_INTR_EN_L1_18);
724 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR;
725 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR;
726 appl_writel(pcie, val, APPL_INTR_EN_L1_18);
729 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
731 pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >>
732 PCI_EXP_LNKSTA_NLW_SHIFT;
734 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
736 val_w |= PCI_EXP_LNKCTL_LBMIE;
737 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL,
741 static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
743 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
744 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
747 /* Enable legacy interrupt generation */
748 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
749 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
750 val |= APPL_INTR_EN_L0_0_INT_INT_EN;
751 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
753 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
754 val |= APPL_INTR_EN_L1_8_INTX_EN;
755 val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
756 val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
757 if (IS_ENABLED(CONFIG_PCIEAER))
758 val |= APPL_INTR_EN_L1_8_AER_INT_EN;
759 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
762 static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
764 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
765 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
768 dw_pcie_msi_init(pp);
770 /* Enable MSI interrupt generation */
771 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
772 val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN;
773 val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN;
774 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
777 static void tegra_pcie_enable_interrupts(struct pcie_port *pp)
779 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
780 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
782 /* Clear interrupt statuses before enabling interrupts */
783 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
784 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
785 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
786 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
787 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
788 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
789 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
790 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
791 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
792 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
793 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
794 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
795 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
796 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
797 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
799 tegra_pcie_enable_system_interrupts(pp);
800 tegra_pcie_enable_legacy_interrupts(pp);
801 if (IS_ENABLED(CONFIG_PCI_MSI))
802 tegra_pcie_enable_msi_interrupts(pp);
805 static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
807 struct dw_pcie *pci = &pcie->pci;
810 /* Program init preset */
811 for (i = 0; i < pcie->num_lanes; i++) {
812 val = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2));
813 val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK;
814 val |= GEN3_GEN4_EQ_PRESET_INIT;
815 val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK;
816 val |= (GEN3_GEN4_EQ_PRESET_INIT <<
817 CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT);
818 dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val);
820 offset = dw_pcie_find_ext_capability(pci,
821 PCI_EXT_CAP_ID_PL_16GT) +
823 val = dw_pcie_readb_dbi(pci, offset + i);
824 val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK;
825 val |= GEN3_GEN4_EQ_PRESET_INIT;
826 val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK;
827 val |= (GEN3_GEN4_EQ_PRESET_INIT <<
828 PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT);
829 dw_pcie_writeb_dbi(pci, offset + i, val);
832 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
833 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
834 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
836 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
837 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
838 val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
839 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
840 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
842 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
843 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
844 val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
845 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
847 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
848 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
849 val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
850 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
851 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
853 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
854 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
855 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
858 static void tegra_pcie_prepare_host(struct pcie_port *pp)
860 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
861 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
864 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
865 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
866 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
868 val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE);
869 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE;
870 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE;
871 dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val);
873 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
875 /* Enable as 0xFFFF0001 response for CRS */
876 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
877 val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT);
878 val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 <<
879 AMBA_ERROR_RESPONSE_CRS_SHIFT);
880 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
882 /* Configure Max lane width from DT */
883 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
884 val &= ~PCI_EXP_LNKCAP_MLW;
885 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
886 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
888 config_gen3_gen4_eq_presets(pcie);
890 init_host_aspm(pcie);
892 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
893 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
894 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
896 if (pcie->update_fc_fixup) {
897 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
898 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
899 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
902 dw_pcie_setup_rc(pp);
904 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
907 val = appl_readl(pcie, APPL_PINMUX);
908 val &= ~APPL_PINMUX_PEX_RST;
909 appl_writel(pcie, val, APPL_PINMUX);
911 usleep_range(100, 200);
914 val = appl_readl(pcie, APPL_CTRL);
915 val |= APPL_CTRL_LTSSM_EN;
916 appl_writel(pcie, val, APPL_CTRL);
919 val = appl_readl(pcie, APPL_PINMUX);
920 val |= APPL_PINMUX_PEX_RST;
921 appl_writel(pcie, val, APPL_PINMUX);
926 static int tegra_pcie_dw_host_init(struct pcie_port *pp)
928 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
929 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
930 u32 val, tmp, offset, speed;
932 pp->bridge->ops = &tegra_pci_ops;
934 tegra_pcie_prepare_host(pp);
936 if (dw_pcie_wait_for_link(pci)) {
938 * There are some endpoints which can't get the link up if
939 * root port has Data Link Feature (DLF) enabled.
940 * Refer Spec rev 4.0 ver 1.0 sec 3.4.2 & 7.7.4 for more info
941 * on Scaled Flow Control and DLF.
942 * So, need to confirm that is indeed the case here and attempt
943 * link up once again with DLF disabled.
945 val = appl_readl(pcie, APPL_DEBUG);
946 val &= APPL_DEBUG_LTSSM_STATE_MASK;
947 val >>= APPL_DEBUG_LTSSM_STATE_SHIFT;
948 tmp = appl_readl(pcie, APPL_LINK_STATUS);
949 tmp &= APPL_LINK_STATUS_RDLH_LINK_UP;
950 if (!(val == 0x11 && !tmp)) {
951 /* Link is down for all good reasons */
955 dev_info(pci->dev, "Link is down in DLL");
956 dev_info(pci->dev, "Trying again with DLFE disabled\n");
958 val = appl_readl(pcie, APPL_CTRL);
959 val &= ~APPL_CTRL_LTSSM_EN;
960 appl_writel(pcie, val, APPL_CTRL);
962 reset_control_assert(pcie->core_rst);
963 reset_control_deassert(pcie->core_rst);
965 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF);
966 val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP);
967 val &= ~PCI_DLF_EXCHANGE_ENABLE;
968 dw_pcie_writel_dbi(pci, offset, val);
970 tegra_pcie_prepare_host(pp);
972 if (dw_pcie_wait_for_link(pci))
976 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
978 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
980 tegra_pcie_enable_interrupts(pp);
985 static int tegra_pcie_dw_link_up(struct dw_pcie *pci)
987 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
988 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
990 return !!(val & PCI_EXP_LNKSTA_DLLLA);
993 static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
995 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
997 enable_irq(pcie->pex_rst_irq);
1002 static void tegra_pcie_dw_stop_link(struct dw_pcie *pci)
1004 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1006 disable_irq(pcie->pex_rst_irq);
1009 static const struct dw_pcie_ops tegra_dw_pcie_ops = {
1010 .link_up = tegra_pcie_dw_link_up,
1011 .start_link = tegra_pcie_dw_start_link,
1012 .stop_link = tegra_pcie_dw_stop_link,
1015 static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
1016 .host_init = tegra_pcie_dw_host_init,
1019 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
1021 unsigned int phy_count = pcie->phy_count;
1023 while (phy_count--) {
1024 phy_power_off(pcie->phys[phy_count]);
1025 phy_exit(pcie->phys[phy_count]);
1029 static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
1034 for (i = 0; i < pcie->phy_count; i++) {
1035 ret = phy_init(pcie->phys[i]);
1039 ret = phy_power_on(pcie->phys[i]);
1048 phy_power_off(pcie->phys[i]);
1050 phy_exit(pcie->phys[i]);
1056 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
1058 struct device_node *np = pcie->dev->of_node;
1061 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
1063 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
1067 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us",
1068 &pcie->aspm_pwr_on_t);
1070 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
1073 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us",
1074 &pcie->aspm_l0s_enter_lat);
1077 "Failed to read ASPM L0s Entrance latency: %d\n", ret);
1079 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
1081 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
1085 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
1087 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
1091 ret = of_property_count_strings(np, "phy-names");
1093 dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
1097 pcie->phy_count = ret;
1099 if (of_property_read_bool(np, "nvidia,update-fc-fixup"))
1100 pcie->update_fc_fixup = true;
1102 pcie->supports_clkreq =
1103 of_property_read_bool(pcie->dev->of_node, "supports-clkreq");
1105 pcie->enable_cdm_check =
1106 of_property_read_bool(np, "snps,enable-cdm-check");
1108 if (pcie->mode == DW_PCIE_RC_TYPE)
1111 /* Endpoint mode specific DT entries */
1112 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN);
1113 if (IS_ERR(pcie->pex_rst_gpiod)) {
1114 int err = PTR_ERR(pcie->pex_rst_gpiod);
1115 const char *level = KERN_ERR;
1117 if (err == -EPROBE_DEFER)
1120 dev_printk(level, pcie->dev,
1121 dev_fmt("Failed to get PERST GPIO: %d\n"),
1126 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev,
1127 "nvidia,refclk-select",
1129 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) {
1130 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod);
1131 const char *level = KERN_ERR;
1133 if (err == -EPROBE_DEFER)
1136 dev_printk(level, pcie->dev,
1137 dev_fmt("Failed to get REFCLK select GPIOs: %d\n"),
1139 pcie->pex_refclk_sel_gpiod = NULL;
1145 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
1148 struct mrq_uphy_response resp;
1149 struct tegra_bpmp_message msg;
1150 struct mrq_uphy_request req;
1152 /* Controller-5 doesn't need to have its state set by BPMP-FW */
1156 memset(&req, 0, sizeof(req));
1157 memset(&resp, 0, sizeof(resp));
1159 req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
1160 req.controller_state.pcie_controller = pcie->cid;
1161 req.controller_state.enable = enable;
1163 memset(&msg, 0, sizeof(msg));
1166 msg.tx.size = sizeof(req);
1167 msg.rx.data = &resp;
1168 msg.rx.size = sizeof(resp);
1170 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1173 static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
1176 struct mrq_uphy_response resp;
1177 struct tegra_bpmp_message msg;
1178 struct mrq_uphy_request req;
1180 memset(&req, 0, sizeof(req));
1181 memset(&resp, 0, sizeof(resp));
1184 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT;
1185 req.ep_ctrlr_pll_init.ep_controller = pcie->cid;
1187 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF;
1188 req.ep_ctrlr_pll_off.ep_controller = pcie->cid;
1191 memset(&msg, 0, sizeof(msg));
1194 msg.tx.size = sizeof(req);
1195 msg.rx.data = &resp;
1196 msg.rx.size = sizeof(resp);
1198 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1201 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
1203 struct pcie_port *pp = &pcie->pci.pp;
1204 struct pci_bus *child, *root_bus = NULL;
1205 struct pci_dev *pdev;
1208 * link doesn't go into L2 state with some of the endpoints with Tegra
1209 * if they are not in D0 state. So, need to make sure that immediate
1210 * downstream devices are in D0 state before sending PME_TurnOff to put
1211 * link into L2 state.
1212 * This is as per PCI Express Base r4.0 v1.0 September 27-2017,
1213 * 5.2 Link State Power Management (Page #428).
1216 list_for_each_entry(child, &pp->bridge->bus->children, node) {
1217 /* Bring downstream devices to D0 if they are not already in */
1218 if (child->parent == pp->bridge->bus) {
1225 dev_err(pcie->dev, "Failed to find downstream devices\n");
1229 list_for_each_entry(pdev, &root_bus->devices, bus_list) {
1230 if (PCI_SLOT(pdev->devfn) == 0) {
1231 if (pci_set_power_state(pdev, PCI_D0))
1233 "Failed to transition %s to D0 state\n",
1234 dev_name(&pdev->dev));
1239 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
1241 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
1242 if (IS_ERR(pcie->slot_ctl_3v3)) {
1243 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV)
1244 return PTR_ERR(pcie->slot_ctl_3v3);
1246 pcie->slot_ctl_3v3 = NULL;
1249 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v");
1250 if (IS_ERR(pcie->slot_ctl_12v)) {
1251 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV)
1252 return PTR_ERR(pcie->slot_ctl_12v);
1254 pcie->slot_ctl_12v = NULL;
1260 static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
1264 if (pcie->slot_ctl_3v3) {
1265 ret = regulator_enable(pcie->slot_ctl_3v3);
1268 "Failed to enable 3.3V slot supply: %d\n", ret);
1273 if (pcie->slot_ctl_12v) {
1274 ret = regulator_enable(pcie->slot_ctl_12v);
1277 "Failed to enable 12V slot supply: %d\n", ret);
1278 goto fail_12v_enable;
1283 * According to PCI Express Card Electromechanical Specification
1284 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive)
1285 * should be a minimum of 100ms.
1287 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v)
1293 if (pcie->slot_ctl_3v3)
1294 regulator_disable(pcie->slot_ctl_3v3);
1298 static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie)
1300 if (pcie->slot_ctl_12v)
1301 regulator_disable(pcie->slot_ctl_12v);
1302 if (pcie->slot_ctl_3v3)
1303 regulator_disable(pcie->slot_ctl_3v3);
1306 static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
1312 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
1315 "Failed to enable controller %u: %d\n", pcie->cid, ret);
1319 ret = tegra_pcie_enable_slot_regulators(pcie);
1321 goto fail_slot_reg_en;
1323 ret = regulator_enable(pcie->pex_ctl_supply);
1325 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
1329 ret = clk_prepare_enable(pcie->core_clk);
1331 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
1335 ret = reset_control_deassert(pcie->core_apb_rst);
1337 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
1339 goto fail_core_apb_rst;
1342 if (en_hw_hot_rst) {
1343 /* Enable HW_HOT_RST mode */
1344 val = appl_readl(pcie, APPL_CTRL);
1345 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
1346 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
1347 val |= APPL_CTRL_HW_HOT_RST_EN;
1348 appl_writel(pcie, val, APPL_CTRL);
1351 ret = tegra_pcie_enable_phy(pcie);
1353 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
1357 /* Update CFG base address */
1358 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1359 APPL_CFG_BASE_ADDR);
1361 /* Configure this core for RP mode operation */
1362 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE);
1364 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1366 val = appl_readl(pcie, APPL_CTRL);
1367 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
1369 val = appl_readl(pcie, APPL_CFG_MISC);
1370 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
1371 appl_writel(pcie, val, APPL_CFG_MISC);
1373 if (!pcie->supports_clkreq) {
1374 val = appl_readl(pcie, APPL_PINMUX);
1375 val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
1376 val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
1377 appl_writel(pcie, val, APPL_PINMUX);
1380 /* Update iATU_DMA base address */
1382 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
1383 APPL_CFG_IATU_DMA_BASE_ADDR);
1385 reset_control_deassert(pcie->core_rst);
1387 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
1390 /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */
1391 if (!pcie->supports_clkreq) {
1392 disable_aspm_l11(pcie);
1393 disable_aspm_l12(pcie);
1399 reset_control_assert(pcie->core_apb_rst);
1401 clk_disable_unprepare(pcie->core_clk);
1403 regulator_disable(pcie->pex_ctl_supply);
1405 tegra_pcie_disable_slot_regulators(pcie);
1407 tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1412 static int __deinit_controller(struct tegra_pcie_dw *pcie)
1416 ret = reset_control_assert(pcie->core_rst);
1418 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n",
1423 tegra_pcie_disable_phy(pcie);
1425 ret = reset_control_assert(pcie->core_apb_rst);
1427 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
1431 clk_disable_unprepare(pcie->core_clk);
1433 ret = regulator_disable(pcie->pex_ctl_supply);
1435 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
1439 tegra_pcie_disable_slot_regulators(pcie);
1441 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1443 dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
1451 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
1453 struct dw_pcie *pci = &pcie->pci;
1454 struct pcie_port *pp = &pci->pp;
1457 ret = tegra_pcie_config_controller(pcie, false);
1461 pp->ops = &tegra_pcie_dw_host_ops;
1463 ret = dw_pcie_host_init(pp);
1465 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
1466 goto fail_host_init;
1472 return __deinit_controller(pcie);
1475 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)
1479 if (!tegra_pcie_dw_link_up(&pcie->pci))
1482 val = appl_readl(pcie, APPL_RADM_STATUS);
1483 val |= APPL_PM_XMT_TURNOFF_STATE;
1484 appl_writel(pcie, val, APPL_RADM_STATUS);
1486 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
1487 val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,
1488 1, PME_ACK_TIMEOUT);
1491 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
1496 if (!tegra_pcie_dw_link_up(&pcie->pci)) {
1497 dev_dbg(pcie->dev, "PCIe link is not up...!\n");
1501 if (tegra_pcie_try_link_l2(pcie)) {
1502 dev_info(pcie->dev, "Link didn't transition to L2 state\n");
1504 * TX lane clock freq will reset to Gen1 only if link is in L2
1506 * So apply pex_rst to end point to force RP to go into detect
1509 data = appl_readl(pcie, APPL_PINMUX);
1510 data &= ~APPL_PINMUX_PEX_RST;
1511 appl_writel(pcie, data, APPL_PINMUX);
1513 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
1516 APPL_DEBUG_LTSSM_STATE_MASK) >>
1517 APPL_DEBUG_LTSSM_STATE_SHIFT) ==
1518 LTSSM_STATE_PRE_DETECT,
1521 dev_info(pcie->dev, "Link didn't go to detect state\n");
1523 /* Disable LTSSM after link is in detect state */
1524 data = appl_readl(pcie, APPL_CTRL);
1525 data &= ~APPL_CTRL_LTSSM_EN;
1526 appl_writel(pcie, data, APPL_CTRL);
1530 * DBI registers may not be accessible after this as PLL-E would be
1531 * down depending on how CLKREQ is pulled by end point
1533 data = appl_readl(pcie, APPL_PINMUX);
1534 data |= (APPL_PINMUX_CLKREQ_OVERRIDE_EN | APPL_PINMUX_CLKREQ_OVERRIDE);
1535 /* Cut REFCLK to slot */
1536 data |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
1537 data &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
1538 appl_writel(pcie, data, APPL_PINMUX);
1541 static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
1543 tegra_pcie_downstream_dev_to_D0(pcie);
1544 dw_pcie_host_deinit(&pcie->pci.pp);
1545 tegra_pcie_dw_pme_turnoff(pcie);
1547 return __deinit_controller(pcie);
1550 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
1552 struct pcie_port *pp = &pcie->pci.pp;
1553 struct device *dev = pcie->dev;
1557 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1558 pp->msi_irq = of_irq_get_byname(dev->of_node, "msi");
1560 dev_err(dev, "Failed to get MSI interrupt\n");
1565 pm_runtime_enable(dev);
1567 ret = pm_runtime_get_sync(dev);
1569 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
1571 goto fail_pm_get_sync;
1574 ret = pinctrl_pm_select_default_state(dev);
1576 dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
1577 goto fail_pm_get_sync;
1580 tegra_pcie_init_controller(pcie);
1582 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
1583 if (!pcie->link_state) {
1585 goto fail_host_init;
1588 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
1591 goto fail_host_init;
1594 pcie->debugfs = debugfs_create_dir(name, NULL);
1600 tegra_pcie_deinit_controller(pcie);
1602 pm_runtime_put_sync(dev);
1603 pm_runtime_disable(dev);
1607 static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
1612 if (pcie->ep_state == EP_STATE_DISABLED)
1616 val = appl_readl(pcie, APPL_CTRL);
1617 val &= ~APPL_CTRL_LTSSM_EN;
1618 appl_writel(pcie, val, APPL_CTRL);
1620 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
1621 ((val & APPL_DEBUG_LTSSM_STATE_MASK) >>
1622 APPL_DEBUG_LTSSM_STATE_SHIFT) ==
1623 LTSSM_STATE_PRE_DETECT,
1626 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
1628 reset_control_assert(pcie->core_rst);
1630 tegra_pcie_disable_phy(pcie);
1632 reset_control_assert(pcie->core_apb_rst);
1634 clk_disable_unprepare(pcie->core_clk);
1636 pm_runtime_put_sync(pcie->dev);
1638 ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
1640 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret);
1642 pcie->ep_state = EP_STATE_DISABLED;
1643 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n");
1646 static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
1648 struct dw_pcie *pci = &pcie->pci;
1649 struct dw_pcie_ep *ep = &pci->ep;
1650 struct device *dev = pcie->dev;
1654 if (pcie->ep_state == EP_STATE_ENABLED)
1657 ret = pm_runtime_get_sync(dev);
1659 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
1664 ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
1666 dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret);
1670 ret = clk_prepare_enable(pcie->core_clk);
1672 dev_err(dev, "Failed to enable core clock: %d\n", ret);
1673 goto fail_core_clk_enable;
1676 ret = reset_control_deassert(pcie->core_apb_rst);
1678 dev_err(dev, "Failed to deassert core APB reset: %d\n", ret);
1679 goto fail_core_apb_rst;
1682 ret = tegra_pcie_enable_phy(pcie);
1684 dev_err(dev, "Failed to enable PHY: %d\n", ret);
1688 /* Clear any stale interrupt statuses */
1689 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
1690 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
1691 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
1692 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
1693 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
1694 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
1695 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
1696 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
1697 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
1698 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
1699 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
1700 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
1701 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
1702 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
1703 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
1705 /* configure this core for EP mode operation */
1706 val = appl_readl(pcie, APPL_DM_TYPE);
1707 val &= ~APPL_DM_TYPE_MASK;
1708 val |= APPL_DM_TYPE_EP;
1709 appl_writel(pcie, val, APPL_DM_TYPE);
1711 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1713 val = appl_readl(pcie, APPL_CTRL);
1714 val |= APPL_CTRL_SYS_PRE_DET_STATE;
1715 val |= APPL_CTRL_HW_HOT_RST_EN;
1716 appl_writel(pcie, val, APPL_CTRL);
1718 val = appl_readl(pcie, APPL_CFG_MISC);
1719 val |= APPL_CFG_MISC_SLV_EP_MODE;
1720 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
1721 appl_writel(pcie, val, APPL_CFG_MISC);
1723 val = appl_readl(pcie, APPL_PINMUX);
1724 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
1725 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
1726 appl_writel(pcie, val, APPL_PINMUX);
1728 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1729 APPL_CFG_BASE_ADDR);
1731 appl_writel(pcie, pcie->atu_dma_res->start &
1732 APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
1733 APPL_CFG_IATU_DMA_BASE_ADDR);
1735 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
1736 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
1737 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
1738 val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN;
1739 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
1741 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
1742 val |= APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN;
1743 val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
1744 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
1746 reset_control_deassert(pcie->core_rst);
1748 if (pcie->update_fc_fixup) {
1749 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
1750 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
1751 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
1754 config_gen3_gen4_eq_presets(pcie);
1756 init_host_aspm(pcie);
1758 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */
1759 if (!pcie->supports_clkreq) {
1760 disable_aspm_l11(pcie);
1761 disable_aspm_l12(pcie);
1764 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
1765 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
1766 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
1768 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
1770 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
1772 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
1773 val |= MSIX_ADDR_MATCH_LOW_OFF_EN;
1774 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val);
1775 val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
1776 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
1778 ret = dw_pcie_ep_init_complete(ep);
1780 dev_err(dev, "Failed to complete initialization: %d\n", ret);
1781 goto fail_init_complete;
1784 dw_pcie_ep_init_notify(ep);
1787 val = appl_readl(pcie, APPL_CTRL);
1788 val |= APPL_CTRL_LTSSM_EN;
1789 appl_writel(pcie, val, APPL_CTRL);
1791 pcie->ep_state = EP_STATE_ENABLED;
1792 dev_dbg(dev, "Initialization of endpoint is completed\n");
1797 reset_control_assert(pcie->core_rst);
1798 tegra_pcie_disable_phy(pcie);
1800 reset_control_assert(pcie->core_apb_rst);
1802 clk_disable_unprepare(pcie->core_clk);
1803 fail_core_clk_enable:
1804 tegra_pcie_bpmp_set_pll_state(pcie, false);
1806 pm_runtime_put_sync(dev);
1809 static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
1811 struct tegra_pcie_dw *pcie = arg;
1813 if (gpiod_get_value(pcie->pex_rst_gpiod))
1814 pex_ep_event_pex_rst_assert(pcie);
1816 pex_ep_event_pex_rst_deassert(pcie);
1821 static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq)
1823 /* Tegra194 supports only INTA */
1827 appl_writel(pcie, 1, APPL_LEGACY_INTX);
1828 usleep_range(1000, 2000);
1829 appl_writel(pcie, 0, APPL_LEGACY_INTX);
1833 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
1835 if (unlikely(irq > 31))
1838 appl_writel(pcie, (1 << irq), APPL_MSI_CTRL_1);
1843 static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
1845 struct dw_pcie_ep *ep = &pcie->pci.ep;
1847 writel(irq, ep->msi_mem);
1852 static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
1853 enum pci_epc_irq_type type,
1856 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1857 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1860 case PCI_EPC_IRQ_LEGACY:
1861 return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
1863 case PCI_EPC_IRQ_MSI:
1864 return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
1866 case PCI_EPC_IRQ_MSIX:
1867 return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
1870 dev_err(pci->dev, "Unknown IRQ type\n");
1877 static const struct pci_epc_features tegra_pcie_epc_features = {
1878 .linkup_notifier = true,
1879 .core_init_notifier = true,
1880 .msi_capable = false,
1881 .msix_capable = false,
1882 .reserved_bar = 1 << BAR_2 | 1 << BAR_3 | 1 << BAR_4 | 1 << BAR_5,
1883 .bar_fixed_64bit = 1 << BAR_0,
1884 .bar_fixed_size[0] = SZ_1M,
1887 static const struct pci_epc_features*
1888 tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)
1890 return &tegra_pcie_epc_features;
1893 static struct dw_pcie_ep_ops pcie_ep_ops = {
1894 .raise_irq = tegra_pcie_ep_raise_irq,
1895 .get_features = tegra_pcie_ep_get_features,
1898 static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
1899 struct platform_device *pdev)
1901 struct dw_pcie *pci = &pcie->pci;
1902 struct device *dev = pcie->dev;
1903 struct dw_pcie_ep *ep;
1908 ep->ops = &pcie_ep_ops;
1910 ep->page_size = SZ_64K;
1912 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME);
1914 dev_err(dev, "Failed to set PERST GPIO debounce time: %d\n",
1919 ret = gpiod_to_irq(pcie->pex_rst_gpiod);
1921 dev_err(dev, "Failed to get IRQ for PERST GPIO: %d\n", ret);
1924 pcie->pex_rst_irq = (unsigned int)ret;
1926 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_pex_rst_irq",
1929 dev_err(dev, "Failed to create PERST IRQ string\n");
1933 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN);
1935 pcie->ep_state = EP_STATE_DISABLED;
1937 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL,
1938 tegra_pcie_ep_pex_rst_irq,
1939 IRQF_TRIGGER_RISING |
1940 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1941 name, (void *)pcie);
1943 dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret);
1947 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_ep_work",
1950 dev_err(dev, "Failed to create PCIe EP work thread string\n");
1954 pm_runtime_enable(dev);
1956 ret = dw_pcie_ep_init(ep);
1958 dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %d\n",
1966 static int tegra_pcie_dw_probe(struct platform_device *pdev)
1968 const struct tegra_pcie_dw_of_data *data;
1969 struct device *dev = &pdev->dev;
1970 struct resource *atu_dma_res;
1971 struct tegra_pcie_dw *pcie;
1972 struct pcie_port *pp;
1973 struct dw_pcie *pci;
1979 data = of_device_get_match_data(dev);
1981 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1986 pci->dev = &pdev->dev;
1987 pci->ops = &tegra_dw_pcie_ops;
1988 pci->n_fts[0] = N_FTS_VAL;
1989 pci->n_fts[1] = FTS_VAL;
1992 pp->num_vectors = MAX_MSI_IRQS;
1993 pcie->dev = &pdev->dev;
1994 pcie->mode = (enum dw_pcie_device_mode)data->mode;
1996 ret = tegra_pcie_dw_parse_dt(pcie);
1998 const char *level = KERN_ERR;
2000 if (ret == -EPROBE_DEFER)
2003 dev_printk(level, dev,
2004 dev_fmt("Failed to parse device tree: %d\n"),
2009 ret = tegra_pcie_get_slot_regulators(pcie);
2011 const char *level = KERN_ERR;
2013 if (ret == -EPROBE_DEFER)
2016 dev_printk(level, dev,
2017 dev_fmt("Failed to get slot regulators: %d\n"),
2022 if (pcie->pex_refclk_sel_gpiod)
2023 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1);
2025 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
2026 if (IS_ERR(pcie->pex_ctl_supply)) {
2027 ret = PTR_ERR(pcie->pex_ctl_supply);
2028 if (ret != -EPROBE_DEFER)
2029 dev_err(dev, "Failed to get regulator: %ld\n",
2030 PTR_ERR(pcie->pex_ctl_supply));
2034 pcie->core_clk = devm_clk_get(dev, "core");
2035 if (IS_ERR(pcie->core_clk)) {
2036 dev_err(dev, "Failed to get core clock: %ld\n",
2037 PTR_ERR(pcie->core_clk));
2038 return PTR_ERR(pcie->core_clk);
2041 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2043 if (!pcie->appl_res) {
2044 dev_err(dev, "Failed to find \"appl\" region\n");
2048 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
2049 if (IS_ERR(pcie->appl_base))
2050 return PTR_ERR(pcie->appl_base);
2052 pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
2053 if (IS_ERR(pcie->core_apb_rst)) {
2054 dev_err(dev, "Failed to get APB reset: %ld\n",
2055 PTR_ERR(pcie->core_apb_rst));
2056 return PTR_ERR(pcie->core_apb_rst);
2059 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
2063 for (i = 0; i < pcie->phy_count; i++) {
2064 name = kasprintf(GFP_KERNEL, "p2u-%u", i);
2066 dev_err(dev, "Failed to create P2U string\n");
2069 phys[i] = devm_phy_get(dev, name);
2071 if (IS_ERR(phys[i])) {
2072 ret = PTR_ERR(phys[i]);
2073 if (ret != -EPROBE_DEFER)
2074 dev_err(dev, "Failed to get PHY: %d\n", ret);
2081 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2084 dev_err(dev, "Failed to find \"atu_dma\" region\n");
2087 pcie->atu_dma_res = atu_dma_res;
2089 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
2090 if (IS_ERR(pci->atu_base))
2091 return PTR_ERR(pci->atu_base);
2093 pcie->core_rst = devm_reset_control_get(dev, "core");
2094 if (IS_ERR(pcie->core_rst)) {
2095 dev_err(dev, "Failed to get core reset: %ld\n",
2096 PTR_ERR(pcie->core_rst));
2097 return PTR_ERR(pcie->core_rst);
2100 pp->irq = platform_get_irq_byname(pdev, "intr");
2104 pcie->bpmp = tegra_bpmp_get(dev);
2105 if (IS_ERR(pcie->bpmp))
2106 return PTR_ERR(pcie->bpmp);
2108 platform_set_drvdata(pdev, pcie);
2110 switch (pcie->mode) {
2111 case DW_PCIE_RC_TYPE:
2112 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler,
2113 IRQF_SHARED, "tegra-pcie-intr", pcie);
2115 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
2120 ret = tegra_pcie_config_rp(pcie);
2121 if (ret && ret != -ENOMEDIUM)
2127 case DW_PCIE_EP_TYPE:
2128 ret = devm_request_threaded_irq(dev, pp->irq,
2129 tegra_pcie_ep_hard_irq,
2130 tegra_pcie_ep_irq_thread,
2131 IRQF_SHARED | IRQF_ONESHOT,
2132 "tegra-pcie-ep-intr", pcie);
2134 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
2139 ret = tegra_pcie_config_ep(pcie, pdev);
2145 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode);
2149 tegra_bpmp_put(pcie->bpmp);
2153 static int tegra_pcie_dw_remove(struct platform_device *pdev)
2155 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
2157 if (!pcie->link_state)
2160 debugfs_remove_recursive(pcie->debugfs);
2161 tegra_pcie_deinit_controller(pcie);
2162 pm_runtime_put_sync(pcie->dev);
2163 pm_runtime_disable(pcie->dev);
2164 tegra_bpmp_put(pcie->bpmp);
2165 if (pcie->pex_refclk_sel_gpiod)
2166 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0);
2171 static int tegra_pcie_dw_suspend_late(struct device *dev)
2173 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2176 if (!pcie->link_state)
2179 /* Enable HW_HOT_RST mode */
2180 val = appl_readl(pcie, APPL_CTRL);
2181 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
2182 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
2183 val |= APPL_CTRL_HW_HOT_RST_EN;
2184 appl_writel(pcie, val, APPL_CTRL);
2189 static int tegra_pcie_dw_suspend_noirq(struct device *dev)
2191 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2193 if (!pcie->link_state)
2196 /* Save MSI interrupt vector */
2197 pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
2198 PORT_LOGIC_MSI_CTRL_INT_0_EN);
2199 tegra_pcie_downstream_dev_to_D0(pcie);
2200 tegra_pcie_dw_pme_turnoff(pcie);
2202 return __deinit_controller(pcie);
2205 static int tegra_pcie_dw_resume_noirq(struct device *dev)
2207 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2210 if (!pcie->link_state)
2213 ret = tegra_pcie_config_controller(pcie, true);
2217 ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
2219 dev_err(dev, "Failed to init host: %d\n", ret);
2220 goto fail_host_init;
2223 /* Restore MSI interrupt vector */
2224 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
2225 pcie->msi_ctrl_int);
2230 return __deinit_controller(pcie);
2233 static int tegra_pcie_dw_resume_early(struct device *dev)
2235 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2238 if (!pcie->link_state)
2241 /* Disable HW_HOT_RST mode */
2242 val = appl_readl(pcie, APPL_CTRL);
2243 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
2244 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
2245 val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST <<
2246 APPL_CTRL_HW_HOT_RST_MODE_SHIFT;
2247 val &= ~APPL_CTRL_HW_HOT_RST_EN;
2248 appl_writel(pcie, val, APPL_CTRL);
2253 static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
2255 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
2257 if (!pcie->link_state)
2260 debugfs_remove_recursive(pcie->debugfs);
2261 tegra_pcie_downstream_dev_to_D0(pcie);
2263 disable_irq(pcie->pci.pp.irq);
2264 if (IS_ENABLED(CONFIG_PCI_MSI))
2265 disable_irq(pcie->pci.pp.msi_irq);
2267 tegra_pcie_dw_pme_turnoff(pcie);
2268 __deinit_controller(pcie);
2271 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = {
2272 .mode = DW_PCIE_RC_TYPE,
2275 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_ep_of_data = {
2276 .mode = DW_PCIE_EP_TYPE,
2279 static const struct of_device_id tegra_pcie_dw_of_match[] = {
2281 .compatible = "nvidia,tegra194-pcie",
2282 .data = &tegra_pcie_dw_rc_of_data,
2285 .compatible = "nvidia,tegra194-pcie-ep",
2286 .data = &tegra_pcie_dw_ep_of_data,
2291 static const struct dev_pm_ops tegra_pcie_dw_pm_ops = {
2292 .suspend_late = tegra_pcie_dw_suspend_late,
2293 .suspend_noirq = tegra_pcie_dw_suspend_noirq,
2294 .resume_noirq = tegra_pcie_dw_resume_noirq,
2295 .resume_early = tegra_pcie_dw_resume_early,
2298 static struct platform_driver tegra_pcie_dw_driver = {
2299 .probe = tegra_pcie_dw_probe,
2300 .remove = tegra_pcie_dw_remove,
2301 .shutdown = tegra_pcie_dw_shutdown,
2303 .name = "tegra194-pcie",
2304 .pm = &tegra_pcie_dw_pm_ops,
2305 .of_match_table = tegra_pcie_dw_of_match,
2308 module_platform_driver(tegra_pcie_dw_driver);
2310 MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match);
2312 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
2313 MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
2314 MODULE_LICENSE("GPL v2");