1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/pci.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/platform_device.h>
24 #include <linux/phy/phy.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/reset.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
30 #include "../../pci.h"
31 #include "pcie-designware.h"
33 #define PCIE20_PARF_SYS_CTRL 0x00
34 #define MST_WAKEUP_EN BIT(13)
35 #define SLV_WAKEUP_EN BIT(12)
36 #define MSTR_ACLK_CGC_DIS BIT(10)
37 #define SLV_ACLK_CGC_DIS BIT(9)
38 #define CORE_CLK_CGC_DIS BIT(6)
39 #define AUX_PWR_DET BIT(4)
40 #define L23_CLK_RMV_DIS BIT(2)
41 #define L1_CLK_RMV_DIS BIT(1)
43 #define PCIE20_PARF_PHY_CTRL 0x40
44 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
45 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
47 #define PCIE20_PARF_PHY_REFCLK 0x4C
48 #define PHY_REFCLK_SSP_EN BIT(16)
49 #define PHY_REFCLK_USE_PAD BIT(12)
51 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
52 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
53 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
54 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
55 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
56 #define PCIE20_PARF_LTSSM 0x1B0
57 #define PCIE20_PARF_SID_OFFSET 0x234
58 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
59 #define PCIE20_PARF_DEVICE_TYPE 0x1000
61 #define PCIE20_ELBI_SYS_CTRL 0x04
62 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
64 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
65 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
66 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
67 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
68 #define CFG_BRIDGE_SB_INIT BIT(0)
70 #define PCIE_CAP_LINK1_VAL 0x2FD7F
72 #define PCIE20_PARF_Q2A_FLUSH 0x1AC
74 #define PCIE20_MISC_CONTROL_1_REG 0x8BC
75 #define DBI_RO_WR_EN 1
77 #define PERST_DELAY_US 1000
79 #define PCIE20_PARF_PCS_DEEMPH 0x34
80 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
81 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
82 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
84 #define PCIE20_PARF_PCS_SWING 0x38
85 #define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
86 #define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
88 #define PCIE20_PARF_CONFIG_BITS 0x50
89 #define PHY_RX0_EQ(x) ((x) << 24)
91 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
92 #define SLV_ADDR_SPACE_SZ 0x10000000
94 #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
96 #define DEVICE_TYPE_RC 0x4
98 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
99 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
100 struct qcom_pcie_resources_2_1_0 {
101 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
102 struct reset_control *pci_reset;
103 struct reset_control *axi_reset;
104 struct reset_control *ahb_reset;
105 struct reset_control *por_reset;
106 struct reset_control *phy_reset;
107 struct reset_control *ext_reset;
108 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
111 struct qcom_pcie_resources_1_0_0 {
114 struct clk *master_bus;
115 struct clk *slave_bus;
116 struct reset_control *core;
117 struct regulator *vdda;
120 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
121 struct qcom_pcie_resources_2_3_2 {
123 struct clk *master_clk;
124 struct clk *slave_clk;
126 struct clk *pipe_clk;
127 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
130 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
131 struct qcom_pcie_resources_2_4_0 {
132 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
134 struct reset_control *axi_m_reset;
135 struct reset_control *axi_s_reset;
136 struct reset_control *pipe_reset;
137 struct reset_control *axi_m_vmid_reset;
138 struct reset_control *axi_s_xpu_reset;
139 struct reset_control *parf_reset;
140 struct reset_control *phy_reset;
141 struct reset_control *axi_m_sticky_reset;
142 struct reset_control *pipe_sticky_reset;
143 struct reset_control *pwr_reset;
144 struct reset_control *ahb_reset;
145 struct reset_control *phy_ahb_reset;
148 struct qcom_pcie_resources_2_3_3 {
150 struct clk *axi_m_clk;
151 struct clk *axi_s_clk;
154 struct reset_control *rst[7];
157 struct qcom_pcie_resources_2_7_0 {
158 struct clk_bulk_data clks[6];
159 struct regulator_bulk_data supplies[2];
160 struct reset_control *pci_reset;
161 struct clk *pipe_clk;
164 union qcom_pcie_resources {
165 struct qcom_pcie_resources_1_0_0 v1_0_0;
166 struct qcom_pcie_resources_2_1_0 v2_1_0;
167 struct qcom_pcie_resources_2_3_2 v2_3_2;
168 struct qcom_pcie_resources_2_3_3 v2_3_3;
169 struct qcom_pcie_resources_2_4_0 v2_4_0;
170 struct qcom_pcie_resources_2_7_0 v2_7_0;
175 struct qcom_pcie_ops {
176 int (*get_resources)(struct qcom_pcie *pcie);
177 int (*init)(struct qcom_pcie *pcie);
178 int (*post_init)(struct qcom_pcie *pcie);
179 void (*deinit)(struct qcom_pcie *pcie);
180 void (*post_deinit)(struct qcom_pcie *pcie);
181 void (*ltssm_enable)(struct qcom_pcie *pcie);
186 void __iomem *parf; /* DT parf */
187 void __iomem *elbi; /* DT elbi */
188 union qcom_pcie_resources res;
190 struct gpio_desc *reset;
191 const struct qcom_pcie_ops *ops;
194 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
196 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
198 gpiod_set_value_cansleep(pcie->reset, 1);
199 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
202 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
204 /* Ensure that PERST has been asserted for at least 100 ms */
206 gpiod_set_value_cansleep(pcie->reset, 0);
207 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
210 static int qcom_pcie_start_link(struct dw_pcie *pci)
212 struct qcom_pcie *pcie = to_qcom_pcie(pci);
214 /* Enable Link Training state machine */
215 if (pcie->ops->ltssm_enable)
216 pcie->ops->ltssm_enable(pcie);
221 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
225 /* enable link training */
226 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
227 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
228 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
231 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
233 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
234 struct dw_pcie *pci = pcie->pci;
235 struct device *dev = pci->dev;
238 res->supplies[0].supply = "vdda";
239 res->supplies[1].supply = "vdda_phy";
240 res->supplies[2].supply = "vdda_refclk";
241 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
246 res->clks[0].id = "iface";
247 res->clks[1].id = "core";
248 res->clks[2].id = "phy";
249 res->clks[3].id = "aux";
250 res->clks[4].id = "ref";
252 /* iface, core, phy are required */
253 ret = devm_clk_bulk_get(dev, 3, res->clks);
257 /* aux, ref are optional */
258 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
262 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
263 if (IS_ERR(res->pci_reset))
264 return PTR_ERR(res->pci_reset);
266 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
267 if (IS_ERR(res->axi_reset))
268 return PTR_ERR(res->axi_reset);
270 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
271 if (IS_ERR(res->ahb_reset))
272 return PTR_ERR(res->ahb_reset);
274 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
275 if (IS_ERR(res->por_reset))
276 return PTR_ERR(res->por_reset);
278 res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
279 if (IS_ERR(res->ext_reset))
280 return PTR_ERR(res->ext_reset);
282 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
283 return PTR_ERR_OR_ZERO(res->phy_reset);
286 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
288 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
290 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
291 reset_control_assert(res->pci_reset);
292 reset_control_assert(res->axi_reset);
293 reset_control_assert(res->ahb_reset);
294 reset_control_assert(res->por_reset);
295 reset_control_assert(res->ext_reset);
296 reset_control_assert(res->phy_reset);
298 writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
300 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
303 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
305 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
306 struct dw_pcie *pci = pcie->pci;
307 struct device *dev = pci->dev;
308 struct device_node *node = dev->of_node;
312 /* reset the PCIe interface as uboot can leave it undefined state */
313 reset_control_assert(res->pci_reset);
314 reset_control_assert(res->axi_reset);
315 reset_control_assert(res->ahb_reset);
316 reset_control_assert(res->por_reset);
317 reset_control_assert(res->ext_reset);
318 reset_control_assert(res->phy_reset);
320 writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
322 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
324 dev_err(dev, "cannot enable regulators\n");
328 ret = reset_control_deassert(res->ahb_reset);
330 dev_err(dev, "cannot deassert ahb reset\n");
331 goto err_deassert_ahb;
334 ret = reset_control_deassert(res->ext_reset);
336 dev_err(dev, "cannot deassert ext reset\n");
337 goto err_deassert_ext;
340 ret = reset_control_deassert(res->phy_reset);
342 dev_err(dev, "cannot deassert phy reset\n");
343 goto err_deassert_phy;
346 ret = reset_control_deassert(res->pci_reset);
348 dev_err(dev, "cannot deassert pci reset\n");
349 goto err_deassert_pci;
352 ret = reset_control_deassert(res->por_reset);
354 dev_err(dev, "cannot deassert por reset\n");
355 goto err_deassert_por;
358 ret = reset_control_deassert(res->axi_reset);
360 dev_err(dev, "cannot deassert axi reset\n");
361 goto err_deassert_axi;
364 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
368 /* enable PCIe clocks and resets */
369 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
371 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
373 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
374 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
375 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
376 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
377 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
378 pcie->parf + PCIE20_PARF_PCS_DEEMPH);
379 writel(PCS_SWING_TX_SWING_FULL(120) |
380 PCS_SWING_TX_SWING_LOW(120),
381 pcie->parf + PCIE20_PARF_PCS_SWING);
382 writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
385 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
386 /* set TX termination offset */
387 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
388 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
389 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
390 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
393 /* enable external reference clock */
394 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
395 val &= ~PHY_REFCLK_USE_PAD;
396 val |= PHY_REFCLK_SSP_EN;
397 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
399 /* wait for clock acquisition */
400 usleep_range(1000, 1500);
402 /* Set the Max TLP size to 2K, instead of using default of 4K */
403 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
404 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
405 writel(CFG_BRIDGE_SB_INIT,
406 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
411 reset_control_assert(res->axi_reset);
413 reset_control_assert(res->por_reset);
415 reset_control_assert(res->pci_reset);
417 reset_control_assert(res->phy_reset);
419 reset_control_assert(res->ext_reset);
421 reset_control_assert(res->ahb_reset);
423 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
428 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
430 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
431 struct dw_pcie *pci = pcie->pci;
432 struct device *dev = pci->dev;
434 res->vdda = devm_regulator_get(dev, "vdda");
435 if (IS_ERR(res->vdda))
436 return PTR_ERR(res->vdda);
438 res->iface = devm_clk_get(dev, "iface");
439 if (IS_ERR(res->iface))
440 return PTR_ERR(res->iface);
442 res->aux = devm_clk_get(dev, "aux");
443 if (IS_ERR(res->aux))
444 return PTR_ERR(res->aux);
446 res->master_bus = devm_clk_get(dev, "master_bus");
447 if (IS_ERR(res->master_bus))
448 return PTR_ERR(res->master_bus);
450 res->slave_bus = devm_clk_get(dev, "slave_bus");
451 if (IS_ERR(res->slave_bus))
452 return PTR_ERR(res->slave_bus);
454 res->core = devm_reset_control_get_exclusive(dev, "core");
455 return PTR_ERR_OR_ZERO(res->core);
458 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
460 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
462 reset_control_assert(res->core);
463 clk_disable_unprepare(res->slave_bus);
464 clk_disable_unprepare(res->master_bus);
465 clk_disable_unprepare(res->iface);
466 clk_disable_unprepare(res->aux);
467 regulator_disable(res->vdda);
470 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
472 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
473 struct dw_pcie *pci = pcie->pci;
474 struct device *dev = pci->dev;
477 ret = reset_control_deassert(res->core);
479 dev_err(dev, "cannot deassert core reset\n");
483 ret = clk_prepare_enable(res->aux);
485 dev_err(dev, "cannot prepare/enable aux clock\n");
489 ret = clk_prepare_enable(res->iface);
491 dev_err(dev, "cannot prepare/enable iface clock\n");
495 ret = clk_prepare_enable(res->master_bus);
497 dev_err(dev, "cannot prepare/enable master_bus clock\n");
501 ret = clk_prepare_enable(res->slave_bus);
503 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
507 ret = regulator_enable(res->vdda);
509 dev_err(dev, "cannot enable vdda regulator\n");
513 /* change DBI base address */
514 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
516 if (IS_ENABLED(CONFIG_PCI_MSI)) {
517 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
520 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
525 clk_disable_unprepare(res->slave_bus);
527 clk_disable_unprepare(res->master_bus);
529 clk_disable_unprepare(res->iface);
531 clk_disable_unprepare(res->aux);
533 reset_control_assert(res->core);
538 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
542 /* enable link training */
543 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
545 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
548 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
550 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
551 struct dw_pcie *pci = pcie->pci;
552 struct device *dev = pci->dev;
555 res->supplies[0].supply = "vdda";
556 res->supplies[1].supply = "vddpe-3v3";
557 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
562 res->aux_clk = devm_clk_get(dev, "aux");
563 if (IS_ERR(res->aux_clk))
564 return PTR_ERR(res->aux_clk);
566 res->cfg_clk = devm_clk_get(dev, "cfg");
567 if (IS_ERR(res->cfg_clk))
568 return PTR_ERR(res->cfg_clk);
570 res->master_clk = devm_clk_get(dev, "bus_master");
571 if (IS_ERR(res->master_clk))
572 return PTR_ERR(res->master_clk);
574 res->slave_clk = devm_clk_get(dev, "bus_slave");
575 if (IS_ERR(res->slave_clk))
576 return PTR_ERR(res->slave_clk);
578 res->pipe_clk = devm_clk_get(dev, "pipe");
579 return PTR_ERR_OR_ZERO(res->pipe_clk);
582 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
584 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
586 clk_disable_unprepare(res->slave_clk);
587 clk_disable_unprepare(res->master_clk);
588 clk_disable_unprepare(res->cfg_clk);
589 clk_disable_unprepare(res->aux_clk);
591 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
594 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
596 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
598 clk_disable_unprepare(res->pipe_clk);
601 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
603 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
604 struct dw_pcie *pci = pcie->pci;
605 struct device *dev = pci->dev;
609 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
611 dev_err(dev, "cannot enable regulators\n");
615 ret = clk_prepare_enable(res->aux_clk);
617 dev_err(dev, "cannot prepare/enable aux clock\n");
621 ret = clk_prepare_enable(res->cfg_clk);
623 dev_err(dev, "cannot prepare/enable cfg clock\n");
627 ret = clk_prepare_enable(res->master_clk);
629 dev_err(dev, "cannot prepare/enable master clock\n");
633 ret = clk_prepare_enable(res->slave_clk);
635 dev_err(dev, "cannot prepare/enable slave clock\n");
639 /* enable PCIe clocks and resets */
640 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
642 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
644 /* change DBI base address */
645 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
647 /* MAC PHY_POWERDOWN MUX DISABLE */
648 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
650 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
652 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
654 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
656 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
658 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
663 clk_disable_unprepare(res->master_clk);
665 clk_disable_unprepare(res->cfg_clk);
667 clk_disable_unprepare(res->aux_clk);
670 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
675 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
677 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
678 struct dw_pcie *pci = pcie->pci;
679 struct device *dev = pci->dev;
682 ret = clk_prepare_enable(res->pipe_clk);
684 dev_err(dev, "cannot prepare/enable pipe clock\n");
691 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
693 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
694 struct dw_pcie *pci = pcie->pci;
695 struct device *dev = pci->dev;
696 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
699 res->clks[0].id = "aux";
700 res->clks[1].id = "master_bus";
701 res->clks[2].id = "slave_bus";
702 res->clks[3].id = "iface";
704 /* qcom,pcie-ipq4019 is defined without "iface" */
705 res->num_clks = is_ipq ? 3 : 4;
707 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
711 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
712 if (IS_ERR(res->axi_m_reset))
713 return PTR_ERR(res->axi_m_reset);
715 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
716 if (IS_ERR(res->axi_s_reset))
717 return PTR_ERR(res->axi_s_reset);
721 * These resources relates to the PHY or are secure clocks, but
722 * are controlled here for IPQ4019
724 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
725 if (IS_ERR(res->pipe_reset))
726 return PTR_ERR(res->pipe_reset);
728 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
730 if (IS_ERR(res->axi_m_vmid_reset))
731 return PTR_ERR(res->axi_m_vmid_reset);
733 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
735 if (IS_ERR(res->axi_s_xpu_reset))
736 return PTR_ERR(res->axi_s_xpu_reset);
738 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
739 if (IS_ERR(res->parf_reset))
740 return PTR_ERR(res->parf_reset);
742 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
743 if (IS_ERR(res->phy_reset))
744 return PTR_ERR(res->phy_reset);
747 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
749 if (IS_ERR(res->axi_m_sticky_reset))
750 return PTR_ERR(res->axi_m_sticky_reset);
752 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
754 if (IS_ERR(res->pipe_sticky_reset))
755 return PTR_ERR(res->pipe_sticky_reset);
757 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
758 if (IS_ERR(res->pwr_reset))
759 return PTR_ERR(res->pwr_reset);
761 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
762 if (IS_ERR(res->ahb_reset))
763 return PTR_ERR(res->ahb_reset);
766 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
767 if (IS_ERR(res->phy_ahb_reset))
768 return PTR_ERR(res->phy_ahb_reset);
774 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
776 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
778 reset_control_assert(res->axi_m_reset);
779 reset_control_assert(res->axi_s_reset);
780 reset_control_assert(res->pipe_reset);
781 reset_control_assert(res->pipe_sticky_reset);
782 reset_control_assert(res->phy_reset);
783 reset_control_assert(res->phy_ahb_reset);
784 reset_control_assert(res->axi_m_sticky_reset);
785 reset_control_assert(res->pwr_reset);
786 reset_control_assert(res->ahb_reset);
787 clk_bulk_disable_unprepare(res->num_clks, res->clks);
790 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
792 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
793 struct dw_pcie *pci = pcie->pci;
794 struct device *dev = pci->dev;
798 ret = reset_control_assert(res->axi_m_reset);
800 dev_err(dev, "cannot assert axi master reset\n");
804 ret = reset_control_assert(res->axi_s_reset);
806 dev_err(dev, "cannot assert axi slave reset\n");
810 usleep_range(10000, 12000);
812 ret = reset_control_assert(res->pipe_reset);
814 dev_err(dev, "cannot assert pipe reset\n");
818 ret = reset_control_assert(res->pipe_sticky_reset);
820 dev_err(dev, "cannot assert pipe sticky reset\n");
824 ret = reset_control_assert(res->phy_reset);
826 dev_err(dev, "cannot assert phy reset\n");
830 ret = reset_control_assert(res->phy_ahb_reset);
832 dev_err(dev, "cannot assert phy ahb reset\n");
836 usleep_range(10000, 12000);
838 ret = reset_control_assert(res->axi_m_sticky_reset);
840 dev_err(dev, "cannot assert axi master sticky reset\n");
844 ret = reset_control_assert(res->pwr_reset);
846 dev_err(dev, "cannot assert power reset\n");
850 ret = reset_control_assert(res->ahb_reset);
852 dev_err(dev, "cannot assert ahb reset\n");
856 usleep_range(10000, 12000);
858 ret = reset_control_deassert(res->phy_ahb_reset);
860 dev_err(dev, "cannot deassert phy ahb reset\n");
864 ret = reset_control_deassert(res->phy_reset);
866 dev_err(dev, "cannot deassert phy reset\n");
870 ret = reset_control_deassert(res->pipe_reset);
872 dev_err(dev, "cannot deassert pipe reset\n");
876 ret = reset_control_deassert(res->pipe_sticky_reset);
878 dev_err(dev, "cannot deassert pipe sticky reset\n");
879 goto err_rst_pipe_sticky;
882 usleep_range(10000, 12000);
884 ret = reset_control_deassert(res->axi_m_reset);
886 dev_err(dev, "cannot deassert axi master reset\n");
890 ret = reset_control_deassert(res->axi_m_sticky_reset);
892 dev_err(dev, "cannot deassert axi master sticky reset\n");
893 goto err_rst_axi_m_sticky;
896 ret = reset_control_deassert(res->axi_s_reset);
898 dev_err(dev, "cannot deassert axi slave reset\n");
902 ret = reset_control_deassert(res->pwr_reset);
904 dev_err(dev, "cannot deassert power reset\n");
908 ret = reset_control_deassert(res->ahb_reset);
910 dev_err(dev, "cannot deassert ahb reset\n");
914 usleep_range(10000, 12000);
916 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
920 /* enable PCIe clocks and resets */
921 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
923 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
925 /* change DBI base address */
926 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
928 /* MAC PHY_POWERDOWN MUX DISABLE */
929 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
931 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
933 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
935 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
937 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
939 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
944 reset_control_assert(res->ahb_reset);
946 reset_control_assert(res->pwr_reset);
948 reset_control_assert(res->axi_s_reset);
950 reset_control_assert(res->axi_m_sticky_reset);
951 err_rst_axi_m_sticky:
952 reset_control_assert(res->axi_m_reset);
954 reset_control_assert(res->pipe_sticky_reset);
956 reset_control_assert(res->pipe_reset);
958 reset_control_assert(res->phy_reset);
960 reset_control_assert(res->phy_ahb_reset);
964 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
966 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
967 struct dw_pcie *pci = pcie->pci;
968 struct device *dev = pci->dev;
970 const char *rst_names[] = { "axi_m", "axi_s", "pipe",
971 "axi_m_sticky", "sticky",
974 res->iface = devm_clk_get(dev, "iface");
975 if (IS_ERR(res->iface))
976 return PTR_ERR(res->iface);
978 res->axi_m_clk = devm_clk_get(dev, "axi_m");
979 if (IS_ERR(res->axi_m_clk))
980 return PTR_ERR(res->axi_m_clk);
982 res->axi_s_clk = devm_clk_get(dev, "axi_s");
983 if (IS_ERR(res->axi_s_clk))
984 return PTR_ERR(res->axi_s_clk);
986 res->ahb_clk = devm_clk_get(dev, "ahb");
987 if (IS_ERR(res->ahb_clk))
988 return PTR_ERR(res->ahb_clk);
990 res->aux_clk = devm_clk_get(dev, "aux");
991 if (IS_ERR(res->aux_clk))
992 return PTR_ERR(res->aux_clk);
994 for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
995 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
996 if (IS_ERR(res->rst[i]))
997 return PTR_ERR(res->rst[i]);
1003 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
1005 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1007 clk_disable_unprepare(res->iface);
1008 clk_disable_unprepare(res->axi_m_clk);
1009 clk_disable_unprepare(res->axi_s_clk);
1010 clk_disable_unprepare(res->ahb_clk);
1011 clk_disable_unprepare(res->aux_clk);
1014 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
1016 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1017 struct dw_pcie *pci = pcie->pci;
1018 struct device *dev = pci->dev;
1019 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1023 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1024 ret = reset_control_assert(res->rst[i]);
1026 dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
1031 usleep_range(2000, 2500);
1033 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1034 ret = reset_control_deassert(res->rst[i]);
1036 dev_err(dev, "reset #%d deassert failed (%d)\n", i,
1043 * Don't have a way to see if the reset has completed.
1044 * Wait for some time.
1046 usleep_range(2000, 2500);
1048 ret = clk_prepare_enable(res->iface);
1050 dev_err(dev, "cannot prepare/enable core clock\n");
1054 ret = clk_prepare_enable(res->axi_m_clk);
1056 dev_err(dev, "cannot prepare/enable core clock\n");
1060 ret = clk_prepare_enable(res->axi_s_clk);
1062 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1066 ret = clk_prepare_enable(res->ahb_clk);
1068 dev_err(dev, "cannot prepare/enable ahb clock\n");
1072 ret = clk_prepare_enable(res->aux_clk);
1074 dev_err(dev, "cannot prepare/enable aux clock\n");
1078 writel(SLV_ADDR_SPACE_SZ,
1079 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1081 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1083 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1085 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1087 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1088 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1089 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1090 pcie->parf + PCIE20_PARF_SYS_CTRL);
1091 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1093 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
1094 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1095 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1097 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1098 val &= ~PCI_EXP_LNKCAP_ASPMS;
1099 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1101 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1107 clk_disable_unprepare(res->ahb_clk);
1109 clk_disable_unprepare(res->axi_s_clk);
1111 clk_disable_unprepare(res->axi_m_clk);
1113 clk_disable_unprepare(res->iface);
1116 * Not checking for failure, will anyway return
1117 * the original failure in 'ret'.
1119 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1120 reset_control_assert(res->rst[i]);
1125 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
1127 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1128 struct dw_pcie *pci = pcie->pci;
1129 struct device *dev = pci->dev;
1132 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
1133 if (IS_ERR(res->pci_reset))
1134 return PTR_ERR(res->pci_reset);
1136 res->supplies[0].supply = "vdda";
1137 res->supplies[1].supply = "vddpe-3v3";
1138 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
1143 res->clks[0].id = "aux";
1144 res->clks[1].id = "cfg";
1145 res->clks[2].id = "bus_master";
1146 res->clks[3].id = "bus_slave";
1147 res->clks[4].id = "slave_q2a";
1148 res->clks[5].id = "tbu";
1150 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
1154 res->pipe_clk = devm_clk_get(dev, "pipe");
1155 return PTR_ERR_OR_ZERO(res->pipe_clk);
1158 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
1160 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1161 struct dw_pcie *pci = pcie->pci;
1162 struct device *dev = pci->dev;
1166 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
1168 dev_err(dev, "cannot enable regulators\n");
1172 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
1174 goto err_disable_regulators;
1176 ret = reset_control_assert(res->pci_reset);
1178 dev_err(dev, "cannot deassert pci reset\n");
1179 goto err_disable_clocks;
1182 usleep_range(1000, 1500);
1184 ret = reset_control_deassert(res->pci_reset);
1186 dev_err(dev, "cannot deassert pci reset\n");
1187 goto err_disable_clocks;
1190 ret = clk_prepare_enable(res->pipe_clk);
1192 dev_err(dev, "cannot prepare/enable pipe clock\n");
1193 goto err_disable_clocks;
1196 /* configure PCIe to RC mode */
1197 writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
1199 /* enable PCIe clocks and resets */
1200 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1202 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1204 /* change DBI base address */
1205 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1207 /* MAC PHY_POWERDOWN MUX DISABLE */
1208 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
1210 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
1212 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1214 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1216 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1217 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1219 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1224 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
1225 err_disable_regulators:
1226 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1231 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1233 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1235 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
1236 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1239 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
1241 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1243 return clk_prepare_enable(res->pipe_clk);
1246 static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
1248 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1250 clk_disable_unprepare(res->pipe_clk);
1253 static int qcom_pcie_link_up(struct dw_pcie *pci)
1255 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1256 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1258 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1261 static int qcom_pcie_host_init(struct pcie_port *pp)
1263 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1264 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1267 qcom_ep_reset_assert(pcie);
1269 ret = pcie->ops->init(pcie);
1273 ret = phy_power_on(pcie->phy);
1277 if (pcie->ops->post_init) {
1278 ret = pcie->ops->post_init(pcie);
1280 goto err_disable_phy;
1283 qcom_ep_reset_deassert(pcie);
1288 phy_power_off(pcie->phy);
1290 pcie->ops->deinit(pcie);
1295 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1296 .host_init = qcom_pcie_host_init,
1299 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1300 static const struct qcom_pcie_ops ops_2_1_0 = {
1301 .get_resources = qcom_pcie_get_resources_2_1_0,
1302 .init = qcom_pcie_init_2_1_0,
1303 .deinit = qcom_pcie_deinit_2_1_0,
1304 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1307 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1308 static const struct qcom_pcie_ops ops_1_0_0 = {
1309 .get_resources = qcom_pcie_get_resources_1_0_0,
1310 .init = qcom_pcie_init_1_0_0,
1311 .deinit = qcom_pcie_deinit_1_0_0,
1312 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1315 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1316 static const struct qcom_pcie_ops ops_2_3_2 = {
1317 .get_resources = qcom_pcie_get_resources_2_3_2,
1318 .init = qcom_pcie_init_2_3_2,
1319 .post_init = qcom_pcie_post_init_2_3_2,
1320 .deinit = qcom_pcie_deinit_2_3_2,
1321 .post_deinit = qcom_pcie_post_deinit_2_3_2,
1322 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1325 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1326 static const struct qcom_pcie_ops ops_2_4_0 = {
1327 .get_resources = qcom_pcie_get_resources_2_4_0,
1328 .init = qcom_pcie_init_2_4_0,
1329 .deinit = qcom_pcie_deinit_2_4_0,
1330 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1333 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1334 static const struct qcom_pcie_ops ops_2_3_3 = {
1335 .get_resources = qcom_pcie_get_resources_2_3_3,
1336 .init = qcom_pcie_init_2_3_3,
1337 .deinit = qcom_pcie_deinit_2_3_3,
1338 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1341 /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
1342 static const struct qcom_pcie_ops ops_2_7_0 = {
1343 .get_resources = qcom_pcie_get_resources_2_7_0,
1344 .init = qcom_pcie_init_2_7_0,
1345 .deinit = qcom_pcie_deinit_2_7_0,
1346 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1347 .post_init = qcom_pcie_post_init_2_7_0,
1348 .post_deinit = qcom_pcie_post_deinit_2_7_0,
1351 static const struct dw_pcie_ops dw_pcie_ops = {
1352 .link_up = qcom_pcie_link_up,
1353 .start_link = qcom_pcie_start_link,
1356 static int qcom_pcie_probe(struct platform_device *pdev)
1358 struct device *dev = &pdev->dev;
1359 struct pcie_port *pp;
1360 struct dw_pcie *pci;
1361 struct qcom_pcie *pcie;
1364 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1368 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1372 pm_runtime_enable(dev);
1373 ret = pm_runtime_get_sync(dev);
1375 goto err_pm_runtime_put;
1378 pci->ops = &dw_pcie_ops;
1383 pcie->ops = of_device_get_match_data(dev);
1385 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1386 if (IS_ERR(pcie->reset)) {
1387 ret = PTR_ERR(pcie->reset);
1388 goto err_pm_runtime_put;
1391 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1392 if (IS_ERR(pcie->parf)) {
1393 ret = PTR_ERR(pcie->parf);
1394 goto err_pm_runtime_put;
1397 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1398 if (IS_ERR(pcie->elbi)) {
1399 ret = PTR_ERR(pcie->elbi);
1400 goto err_pm_runtime_put;
1403 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1404 if (IS_ERR(pcie->phy)) {
1405 ret = PTR_ERR(pcie->phy);
1406 goto err_pm_runtime_put;
1409 ret = pcie->ops->get_resources(pcie);
1411 goto err_pm_runtime_put;
1413 pp->ops = &qcom_pcie_dw_ops;
1415 ret = phy_init(pcie->phy);
1417 pm_runtime_disable(&pdev->dev);
1418 goto err_pm_runtime_put;
1421 platform_set_drvdata(pdev, pcie);
1423 ret = dw_pcie_host_init(pp);
1425 dev_err(dev, "cannot initialize host\n");
1426 pm_runtime_disable(&pdev->dev);
1427 goto err_pm_runtime_put;
1433 pm_runtime_put(dev);
1434 pm_runtime_disable(dev);
1439 static const struct of_device_id qcom_pcie_match[] = {
1440 { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
1441 { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
1442 { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
1443 { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
1444 { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
1445 { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
1446 { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
1447 { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
1448 { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
1452 static void qcom_fixup_class(struct pci_dev *dev)
1454 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
1456 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1457 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1458 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1459 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1460 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1461 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1462 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1464 static struct platform_driver qcom_pcie_driver = {
1465 .probe = qcom_pcie_probe,
1467 .name = "qcom-pcie",
1468 .suppress_bind_attrs = true,
1469 .of_match_table = qcom_pcie_match,
1472 builtin_platform_driver(qcom_pcie_driver);