1 // SPDX-License-Identifier: GPL-2.0
3 * Synopsys DesignWare PCIe host controller driver
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
8 * Author: Jingoo Han <jg1.han@samsung.com>
11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/msi.h>
14 #include <linux/of_address.h>
15 #include <linux/of_pci.h>
16 #include <linux/pci_regs.h>
17 #include <linux/platform_device.h>
19 #include "../../pci.h"
20 #include "pcie-designware.h"
22 static struct pci_ops dw_pcie_ops;
23 static struct pci_ops dw_child_pcie_ops;
25 static void dw_msi_ack_irq(struct irq_data *d)
27 irq_chip_ack_parent(d);
30 static void dw_msi_mask_irq(struct irq_data *d)
33 irq_chip_mask_parent(d);
36 static void dw_msi_unmask_irq(struct irq_data *d)
38 pci_msi_unmask_irq(d);
39 irq_chip_unmask_parent(d);
42 static struct irq_chip dw_pcie_msi_irq_chip = {
44 .irq_ack = dw_msi_ack_irq,
45 .irq_mask = dw_msi_mask_irq,
46 .irq_unmask = dw_msi_unmask_irq,
49 static struct msi_domain_info dw_pcie_msi_domain_info = {
50 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
51 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
52 .chip = &dw_pcie_msi_irq_chip,
56 irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
60 u32 status, num_ctrls;
61 irqreturn_t ret = IRQ_NONE;
62 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
64 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
66 for (i = 0; i < num_ctrls; i++) {
67 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
68 (i * MSI_REG_CTRL_BLOCK_SIZE));
75 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
76 pos)) != MAX_MSI_IRQS_PER_CTRL) {
77 generic_handle_domain_irq(pp->irq_domain,
78 (i * MAX_MSI_IRQS_PER_CTRL) +
87 /* Chained MSI interrupt service routine */
88 static void dw_chained_msi_isr(struct irq_desc *desc)
90 struct irq_chip *chip = irq_desc_get_chip(desc);
91 struct dw_pcie_rp *pp;
93 chained_irq_enter(chip, desc);
95 pp = irq_desc_get_handler_data(desc);
96 dw_handle_msi_irq(pp);
98 chained_irq_exit(chip, desc);
101 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
103 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
104 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
107 msi_target = (u64)pp->msi_data;
109 msg->address_lo = lower_32_bits(msi_target);
110 msg->address_hi = upper_32_bits(msi_target);
112 msg->data = d->hwirq;
114 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
115 (int)d->hwirq, msg->address_hi, msg->address_lo);
118 static int dw_pci_msi_set_affinity(struct irq_data *d,
119 const struct cpumask *mask, bool force)
124 static void dw_pci_bottom_mask(struct irq_data *d)
126 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
127 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
128 unsigned int res, bit, ctrl;
131 raw_spin_lock_irqsave(&pp->lock, flags);
133 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
134 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
135 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
137 pp->irq_mask[ctrl] |= BIT(bit);
138 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
140 raw_spin_unlock_irqrestore(&pp->lock, flags);
143 static void dw_pci_bottom_unmask(struct irq_data *d)
145 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
146 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
147 unsigned int res, bit, ctrl;
150 raw_spin_lock_irqsave(&pp->lock, flags);
152 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
153 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
154 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
156 pp->irq_mask[ctrl] &= ~BIT(bit);
157 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
159 raw_spin_unlock_irqrestore(&pp->lock, flags);
162 static void dw_pci_bottom_ack(struct irq_data *d)
164 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
165 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
166 unsigned int res, bit, ctrl;
168 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
169 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
170 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
172 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
175 static struct irq_chip dw_pci_msi_bottom_irq_chip = {
177 .irq_ack = dw_pci_bottom_ack,
178 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
179 .irq_set_affinity = dw_pci_msi_set_affinity,
180 .irq_mask = dw_pci_bottom_mask,
181 .irq_unmask = dw_pci_bottom_unmask,
184 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
185 unsigned int virq, unsigned int nr_irqs,
188 struct dw_pcie_rp *pp = domain->host_data;
193 raw_spin_lock_irqsave(&pp->lock, flags);
195 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
196 order_base_2(nr_irqs));
198 raw_spin_unlock_irqrestore(&pp->lock, flags);
203 for (i = 0; i < nr_irqs; i++)
204 irq_domain_set_info(domain, virq + i, bit + i,
212 static void dw_pcie_irq_domain_free(struct irq_domain *domain,
213 unsigned int virq, unsigned int nr_irqs)
215 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
216 struct dw_pcie_rp *pp = domain->host_data;
219 raw_spin_lock_irqsave(&pp->lock, flags);
221 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
222 order_base_2(nr_irqs));
224 raw_spin_unlock_irqrestore(&pp->lock, flags);
227 static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
228 .alloc = dw_pcie_irq_domain_alloc,
229 .free = dw_pcie_irq_domain_free,
232 int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
234 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
235 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
237 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
238 &dw_pcie_msi_domain_ops, pp);
239 if (!pp->irq_domain) {
240 dev_err(pci->dev, "Failed to create IRQ domain\n");
244 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
246 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
247 &dw_pcie_msi_domain_info,
249 if (!pp->msi_domain) {
250 dev_err(pci->dev, "Failed to create MSI domain\n");
251 irq_domain_remove(pp->irq_domain);
258 static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
262 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
263 if (pp->msi_irq[ctrl] > 0)
264 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
268 irq_domain_remove(pp->msi_domain);
269 irq_domain_remove(pp->irq_domain);
272 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
273 struct device *dev = pci->dev;
275 dma_unmap_page(dev, pp->msi_data, PAGE_SIZE, DMA_FROM_DEVICE);
277 __free_page(pp->msi_page);
281 static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
283 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
284 u64 msi_target = (u64)pp->msi_data;
286 if (!pci_msi_enabled() || !pp->has_msi_ctrl)
289 /* Program the msi_data */
290 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
291 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
294 static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
296 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
297 struct device *dev = pci->dev;
298 struct platform_device *pdev = to_platform_device(dev);
299 u32 ctrl, max_vectors;
302 /* Parse any "msiX" IRQs described in the devicetree */
303 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
304 char msi_name[] = "msiX";
306 msi_name[3] = '0' + ctrl;
307 irq = platform_get_irq_byname_optional(pdev, msi_name);
311 return dev_err_probe(dev, irq,
312 "Failed to parse MSI IRQ '%s'\n",
315 pp->msi_irq[ctrl] = irq;
318 /* If no "msiX" IRQs, caller should fallback to "msi" IRQ */
322 max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL;
323 if (pp->num_vectors > max_vectors) {
324 dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n",
326 pp->num_vectors = max_vectors;
328 if (!pp->num_vectors)
329 pp->num_vectors = max_vectors;
334 static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
336 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
337 struct device *dev = pci->dev;
338 struct platform_device *pdev = to_platform_device(dev);
342 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
343 pp->irq_mask[ctrl] = ~0;
345 if (!pp->msi_irq[0]) {
346 ret = dw_pcie_parse_split_msi_irq(pp);
347 if (ret < 0 && ret != -ENXIO)
351 if (!pp->num_vectors)
352 pp->num_vectors = MSI_DEF_NUM_VECTORS;
353 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
355 if (!pp->msi_irq[0]) {
356 pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi");
357 if (pp->msi_irq[0] < 0) {
358 pp->msi_irq[0] = platform_get_irq(pdev, 0);
359 if (pp->msi_irq[0] < 0)
360 return pp->msi_irq[0];
364 dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors);
366 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
368 ret = dw_pcie_allocate_domains(pp);
372 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
373 if (pp->msi_irq[ctrl] > 0)
374 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
375 dw_chained_msi_isr, pp);
378 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
380 dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
382 pp->msi_page = alloc_page(GFP_DMA32);
383 pp->msi_data = dma_map_page(dev, pp->msi_page, 0,
384 PAGE_SIZE, DMA_FROM_DEVICE);
385 ret = dma_mapping_error(dev, pp->msi_data);
387 dev_err(pci->dev, "Failed to map MSI data\n");
388 __free_page(pp->msi_page);
391 dw_pcie_free_msi(pp);
399 int dw_pcie_host_init(struct dw_pcie_rp *pp)
401 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
402 struct device *dev = pci->dev;
403 struct device_node *np = dev->of_node;
404 struct platform_device *pdev = to_platform_device(dev);
405 struct resource_entry *win;
406 struct pci_host_bridge *bridge;
407 struct resource *res;
410 raw_spin_lock_init(&pp->lock);
412 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
414 pp->cfg0_size = resource_size(res);
415 pp->cfg0_base = res->start;
417 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
418 if (IS_ERR(pp->va_cfg0_base))
419 return PTR_ERR(pp->va_cfg0_base);
421 dev_err(dev, "Missing *config* reg space\n");
425 if (!pci->dbi_base) {
426 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
427 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
428 if (IS_ERR(pci->dbi_base))
429 return PTR_ERR(pci->dbi_base);
432 bridge = devm_pci_alloc_host_bridge(dev, 0);
438 /* Get the I/O range from DT */
439 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
441 pp->io_size = resource_size(win->res);
442 pp->io_bus_addr = win->res->start - win->offset;
443 pp->io_base = pci_pio_to_address(win->res->start);
446 if (pci->link_gen < 1)
447 pci->link_gen = of_pci_get_max_link_speed(np);
449 /* Set default bus ops */
450 bridge->ops = &dw_pcie_ops;
451 bridge->child_ops = &dw_child_pcie_ops;
453 if (pp->ops->host_init) {
454 ret = pp->ops->host_init(pp);
459 if (pci_msi_enabled()) {
460 pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
461 of_property_read_bool(np, "msi-parent") ||
462 of_property_read_bool(np, "msi-map"));
465 * For the has_msi_ctrl case the default assignment is handled
466 * in the dw_pcie_msi_host_init().
468 if (!pp->has_msi_ctrl && !pp->num_vectors) {
469 pp->num_vectors = MSI_DEF_NUM_VECTORS;
470 } else if (pp->num_vectors > MAX_MSI_IRQS) {
471 dev_err(dev, "Invalid number of vectors\n");
473 goto err_deinit_host;
476 if (pp->ops->msi_host_init) {
477 ret = pp->ops->msi_host_init(pp);
479 goto err_deinit_host;
480 } else if (pp->has_msi_ctrl) {
481 ret = dw_pcie_msi_host_init(pp);
483 goto err_deinit_host;
487 dw_pcie_version_detect(pci);
489 dw_pcie_iatu_detect(pci);
491 ret = dw_pcie_setup_rc(pp);
495 if (!dw_pcie_link_up(pci)) {
496 ret = dw_pcie_start_link(pci);
501 /* Ignore errors, the link may come up later */
502 dw_pcie_wait_for_link(pci);
504 bridge->sysdata = pp;
506 ret = pci_host_probe(bridge);
513 dw_pcie_stop_link(pci);
516 if (pp->has_msi_ctrl)
517 dw_pcie_free_msi(pp);
520 if (pp->ops->host_deinit)
521 pp->ops->host_deinit(pp);
525 EXPORT_SYMBOL_GPL(dw_pcie_host_init);
527 void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
529 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
531 pci_stop_root_bus(pp->bridge->bus);
532 pci_remove_root_bus(pp->bridge->bus);
534 dw_pcie_stop_link(pci);
536 if (pp->has_msi_ctrl)
537 dw_pcie_free_msi(pp);
539 if (pp->ops->host_deinit)
540 pp->ops->host_deinit(pp);
542 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
544 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
545 unsigned int devfn, int where)
547 struct dw_pcie_rp *pp = bus->sysdata;
548 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
553 * Checking whether the link is up here is a last line of defense
554 * against platforms that forward errors on the system bus as
555 * SError upon PCI configuration transactions issued when the link
556 * is down. This check is racy by definition and does not stop
557 * the system from triggering an SError if the link goes down
558 * after this check is performed.
560 if (!dw_pcie_link_up(pci))
563 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
564 PCIE_ATU_FUNC(PCI_FUNC(devfn));
566 if (pci_is_root_bus(bus->parent))
567 type = PCIE_ATU_TYPE_CFG0;
569 type = PCIE_ATU_TYPE_CFG1;
571 ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
576 return pp->va_cfg0_base + where;
579 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
580 int where, int size, u32 *val)
582 struct dw_pcie_rp *pp = bus->sysdata;
583 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
586 ret = pci_generic_config_read(bus, devfn, where, size, val);
587 if (ret != PCIBIOS_SUCCESSFUL)
590 if (pp->cfg0_io_shared) {
591 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
592 pp->io_base, pp->io_bus_addr,
595 return PCIBIOS_SET_FAILED;
598 return PCIBIOS_SUCCESSFUL;
601 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
602 int where, int size, u32 val)
604 struct dw_pcie_rp *pp = bus->sysdata;
605 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
608 ret = pci_generic_config_write(bus, devfn, where, size, val);
609 if (ret != PCIBIOS_SUCCESSFUL)
612 if (pp->cfg0_io_shared) {
613 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
614 pp->io_base, pp->io_bus_addr,
617 return PCIBIOS_SET_FAILED;
620 return PCIBIOS_SUCCESSFUL;
623 static struct pci_ops dw_child_pcie_ops = {
624 .map_bus = dw_pcie_other_conf_map_bus,
625 .read = dw_pcie_rd_other_conf,
626 .write = dw_pcie_wr_other_conf,
629 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
631 struct dw_pcie_rp *pp = bus->sysdata;
632 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
634 if (PCI_SLOT(devfn) > 0)
637 return pci->dbi_base + where;
639 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
641 static struct pci_ops dw_pcie_ops = {
642 .map_bus = dw_pcie_own_conf_map_bus,
643 .read = pci_generic_config_read,
644 .write = pci_generic_config_write,
647 static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
649 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
650 struct resource_entry *entry;
653 /* Note the very first outbound ATU is used for CFG IOs */
654 if (!pci->num_ob_windows) {
655 dev_err(pci->dev, "No outbound iATU found\n");
660 * Ensure all outbound windows are disabled before proceeding with
661 * the MEM/IO ranges setups.
663 for (i = 0; i < pci->num_ob_windows; i++)
664 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i);
667 resource_list_for_each_entry(entry, &pp->bridge->windows) {
668 if (resource_type(entry->res) != IORESOURCE_MEM)
671 if (pci->num_ob_windows <= ++i)
674 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
676 entry->res->start - entry->offset,
677 resource_size(entry->res));
679 dev_err(pci->dev, "Failed to set MEM range %pr\n",
686 if (pci->num_ob_windows > ++i) {
687 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
692 dev_err(pci->dev, "Failed to set IO range %pr\n",
697 pp->cfg0_io_shared = true;
701 if (pci->num_ob_windows <= i)
702 dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n",
703 pci->num_ob_windows);
708 int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
710 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
711 u32 val, ctrl, num_ctrls;
715 * Enable DBI read-only registers for writing/updating configuration.
716 * Write permission gets disabled towards the end of this function.
718 dw_pcie_dbi_ro_wr_en(pci);
722 if (pp->has_msi_ctrl) {
723 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
725 /* Initialize IRQ Status array */
726 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
727 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
728 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
730 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
731 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
736 dw_pcie_msi_init(pp);
739 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
740 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
742 /* Setup interrupt pins */
743 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
746 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
748 /* Setup bus numbers */
749 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
752 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
754 /* Setup command register */
755 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
757 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
758 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
759 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
762 * If the platform provides its own child bus config accesses, it means
763 * the platform uses its own address translation component rather than
764 * ATU, so we should not program the ATU here.
766 if (pp->bridge->child_ops == &dw_child_pcie_ops) {
767 ret = dw_pcie_iatu_setup(pp);
772 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
774 /* Program correct class for RC */
775 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
777 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
778 val |= PORT_LOGIC_SPEED_CHANGE;
779 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
781 dw_pcie_dbi_ro_wr_dis(pci);
785 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);