1 // SPDX-License-Identifier: GPL-2.0
3 * Synopsys DesignWare PCIe host controller driver
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
8 * Author: Jingoo Han <jg1.han@samsung.com>
11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/msi.h>
14 #include <linux/of_address.h>
15 #include <linux/of_pci.h>
16 #include <linux/pci_regs.h>
17 #include <linux/platform_device.h>
19 #include "../../pci.h"
20 #include "pcie-designware.h"
22 static struct pci_ops dw_pcie_ops;
23 static struct pci_ops dw_child_pcie_ops;
25 static void dw_msi_ack_irq(struct irq_data *d)
27 irq_chip_ack_parent(d);
30 static void dw_msi_mask_irq(struct irq_data *d)
33 irq_chip_mask_parent(d);
36 static void dw_msi_unmask_irq(struct irq_data *d)
38 pci_msi_unmask_irq(d);
39 irq_chip_unmask_parent(d);
42 static struct irq_chip dw_pcie_msi_irq_chip = {
44 .irq_ack = dw_msi_ack_irq,
45 .irq_mask = dw_msi_mask_irq,
46 .irq_unmask = dw_msi_unmask_irq,
49 static struct msi_domain_info dw_pcie_msi_domain_info = {
50 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
51 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
52 .chip = &dw_pcie_msi_irq_chip,
56 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
60 u32 status, num_ctrls;
61 irqreturn_t ret = IRQ_NONE;
62 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
64 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
66 for (i = 0; i < num_ctrls; i++) {
67 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
68 (i * MSI_REG_CTRL_BLOCK_SIZE));
75 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
76 pos)) != MAX_MSI_IRQS_PER_CTRL) {
77 irq = irq_find_mapping(pp->irq_domain,
78 (i * MAX_MSI_IRQS_PER_CTRL) +
80 generic_handle_irq(irq);
88 /* Chained MSI interrupt service routine */
89 static void dw_chained_msi_isr(struct irq_desc *desc)
91 struct irq_chip *chip = irq_desc_get_chip(desc);
94 chained_irq_enter(chip, desc);
96 pp = irq_desc_get_handler_data(desc);
97 dw_handle_msi_irq(pp);
99 chained_irq_exit(chip, desc);
102 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
104 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
105 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
108 msi_target = (u64)pp->msi_data;
110 msg->address_lo = lower_32_bits(msi_target);
111 msg->address_hi = upper_32_bits(msi_target);
113 msg->data = d->hwirq;
115 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
116 (int)d->hwirq, msg->address_hi, msg->address_lo);
119 static int dw_pci_msi_set_affinity(struct irq_data *d,
120 const struct cpumask *mask, bool force)
125 static void dw_pci_bottom_mask(struct irq_data *d)
127 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
128 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
129 unsigned int res, bit, ctrl;
132 raw_spin_lock_irqsave(&pp->lock, flags);
134 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
135 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
136 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
138 pp->irq_mask[ctrl] |= BIT(bit);
139 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
141 raw_spin_unlock_irqrestore(&pp->lock, flags);
144 static void dw_pci_bottom_unmask(struct irq_data *d)
146 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
147 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
148 unsigned int res, bit, ctrl;
151 raw_spin_lock_irqsave(&pp->lock, flags);
153 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
154 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
155 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
157 pp->irq_mask[ctrl] &= ~BIT(bit);
158 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
160 raw_spin_unlock_irqrestore(&pp->lock, flags);
163 static void dw_pci_bottom_ack(struct irq_data *d)
165 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
166 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
167 unsigned int res, bit, ctrl;
169 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
170 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
171 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
173 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
176 static struct irq_chip dw_pci_msi_bottom_irq_chip = {
178 .irq_ack = dw_pci_bottom_ack,
179 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
180 .irq_set_affinity = dw_pci_msi_set_affinity,
181 .irq_mask = dw_pci_bottom_mask,
182 .irq_unmask = dw_pci_bottom_unmask,
185 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
186 unsigned int virq, unsigned int nr_irqs,
189 struct pcie_port *pp = domain->host_data;
194 raw_spin_lock_irqsave(&pp->lock, flags);
196 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
197 order_base_2(nr_irqs));
199 raw_spin_unlock_irqrestore(&pp->lock, flags);
204 for (i = 0; i < nr_irqs; i++)
205 irq_domain_set_info(domain, virq + i, bit + i,
213 static void dw_pcie_irq_domain_free(struct irq_domain *domain,
214 unsigned int virq, unsigned int nr_irqs)
216 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
217 struct pcie_port *pp = domain->host_data;
220 raw_spin_lock_irqsave(&pp->lock, flags);
222 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
223 order_base_2(nr_irqs));
225 raw_spin_unlock_irqrestore(&pp->lock, flags);
228 static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
229 .alloc = dw_pcie_irq_domain_alloc,
230 .free = dw_pcie_irq_domain_free,
233 int dw_pcie_allocate_domains(struct pcie_port *pp)
235 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
236 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
238 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
239 &dw_pcie_msi_domain_ops, pp);
240 if (!pp->irq_domain) {
241 dev_err(pci->dev, "Failed to create IRQ domain\n");
245 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
247 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
248 &dw_pcie_msi_domain_info,
250 if (!pp->msi_domain) {
251 dev_err(pci->dev, "Failed to create MSI domain\n");
252 irq_domain_remove(pp->irq_domain);
259 void dw_pcie_free_msi(struct pcie_port *pp)
262 irq_set_chained_handler(pp->msi_irq, NULL);
263 irq_set_handler_data(pp->msi_irq, NULL);
266 irq_domain_remove(pp->msi_domain);
267 irq_domain_remove(pp->irq_domain);
270 __free_page(pp->msi_page);
273 void dw_pcie_msi_init(struct pcie_port *pp)
275 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
276 struct device *dev = pci->dev;
279 pp->msi_page = alloc_page(GFP_KERNEL);
280 pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE,
282 if (dma_mapping_error(dev, pp->msi_data)) {
283 dev_err(dev, "Failed to map MSI data\n");
284 __free_page(pp->msi_page);
288 msi_target = (u64)pp->msi_data;
290 /* Program the msi_data */
291 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
292 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
294 EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
296 int dw_pcie_host_init(struct pcie_port *pp)
298 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
299 struct device *dev = pci->dev;
300 struct device_node *np = dev->of_node;
301 struct platform_device *pdev = to_platform_device(dev);
302 struct resource_entry *win;
303 struct pci_host_bridge *bridge;
304 struct resource *cfg_res;
307 raw_spin_lock_init(&pci->pp.lock);
309 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
311 pp->cfg0_size = resource_size(cfg_res) >> 1;
312 pp->cfg1_size = resource_size(cfg_res) >> 1;
313 pp->cfg0_base = cfg_res->start;
314 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
315 } else if (!pp->va_cfg0_base) {
316 dev_err(dev, "Missing *config* reg space\n");
319 bridge = devm_pci_alloc_host_bridge(dev, 0);
325 /* Get the I/O and memory ranges from DT */
326 resource_list_for_each_entry(win, &bridge->windows) {
327 switch (resource_type(win->res)) {
330 pp->io->name = "I/O";
331 pp->io_size = resource_size(pp->io);
332 pp->io_bus_addr = pp->io->start - win->offset;
333 pp->io_base = pci_pio_to_address(pp->io->start);
337 pp->mem->name = "MEM";
338 pp->mem_size = resource_size(pp->mem);
339 pp->mem_bus_addr = pp->mem->start - win->offset;
343 pp->cfg0_size = resource_size(pp->cfg) >> 1;
344 pp->cfg1_size = resource_size(pp->cfg) >> 1;
345 pp->cfg0_base = pp->cfg->start;
346 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
354 if (!pci->dbi_base) {
355 pci->dbi_base = devm_pci_remap_cfgspace(dev,
357 resource_size(pp->cfg));
358 if (!pci->dbi_base) {
359 dev_err(dev, "Error with ioremap\n");
364 pp->mem_base = pp->mem->start;
366 if (!pp->va_cfg0_base) {
367 pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
368 pp->cfg0_base, pp->cfg0_size);
369 if (!pp->va_cfg0_base) {
370 dev_err(dev, "Error with ioremap in function\n");
375 if (!pp->va_cfg1_base) {
376 pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
379 if (!pp->va_cfg1_base) {
380 dev_err(dev, "Error with ioremap\n");
385 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
387 pci->num_viewport = 2;
389 if (pci_msi_enabled()) {
391 * If a specific SoC driver needs to change the
392 * default number of vectors, it needs to implement
393 * the set_num_vectors callback.
395 if (!pp->ops->set_num_vectors) {
396 pp->num_vectors = MSI_DEF_NUM_VECTORS;
398 pp->ops->set_num_vectors(pp);
400 if (pp->num_vectors > MAX_MSI_IRQS ||
401 pp->num_vectors == 0) {
403 "Invalid number of vectors\n");
408 if (!pp->ops->msi_host_init) {
409 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
411 ret = dw_pcie_allocate_domains(pp);
416 irq_set_chained_handler_and_data(pp->msi_irq,
420 ret = pp->ops->msi_host_init(pp);
426 /* Set default bus ops */
427 bridge->ops = &dw_pcie_ops;
428 bridge->child_ops = &dw_child_pcie_ops;
430 if (pp->ops->host_init) {
431 ret = pp->ops->host_init(pp);
436 bridge->sysdata = pp;
438 ret = pci_host_probe(bridge);
443 if (pci_msi_enabled() && !pp->ops->msi_host_init)
444 dw_pcie_free_msi(pp);
447 EXPORT_SYMBOL_GPL(dw_pcie_host_init);
449 void dw_pcie_host_deinit(struct pcie_port *pp)
451 pci_stop_root_bus(pp->bridge->bus);
452 pci_remove_root_bus(pp->bridge->bus);
453 if (pci_msi_enabled() && !pp->ops->msi_host_init)
454 dw_pcie_free_msi(pp);
456 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
458 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
459 unsigned int devfn, int where)
462 u32 busdev, cfg_size;
464 void __iomem *va_cfg_base;
465 struct pcie_port *pp = bus->sysdata;
466 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
468 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
469 PCIE_ATU_FUNC(PCI_FUNC(devfn));
471 if (pci_is_root_bus(bus->parent)) {
472 type = PCIE_ATU_TYPE_CFG0;
473 cpu_addr = pp->cfg0_base;
474 cfg_size = pp->cfg0_size;
475 va_cfg_base = pp->va_cfg0_base;
477 type = PCIE_ATU_TYPE_CFG1;
478 cpu_addr = pp->cfg1_base;
479 cfg_size = pp->cfg1_size;
480 va_cfg_base = pp->va_cfg1_base;
483 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
487 return va_cfg_base + where;
490 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
491 int where, int size, u32 *val)
494 struct pcie_port *pp = bus->sysdata;
495 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
497 ret = pci_generic_config_read(bus, devfn, where, size, val);
499 if (!ret && pci->num_viewport <= 2)
500 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
501 PCIE_ATU_TYPE_IO, pp->io_base,
502 pp->io_bus_addr, pp->io_size);
507 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
508 int where, int size, u32 val)
511 struct pcie_port *pp = bus->sysdata;
512 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
514 ret = pci_generic_config_write(bus, devfn, where, size, val);
516 if (!ret && pci->num_viewport <= 2)
517 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
518 PCIE_ATU_TYPE_IO, pp->io_base,
519 pp->io_bus_addr, pp->io_size);
524 static struct pci_ops dw_child_pcie_ops = {
525 .map_bus = dw_pcie_other_conf_map_bus,
526 .read = dw_pcie_rd_other_conf,
527 .write = dw_pcie_wr_other_conf,
530 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
532 struct pcie_port *pp = bus->sysdata;
533 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
535 if (PCI_SLOT(devfn) > 0)
538 return pci->dbi_base + where;
540 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
542 static struct pci_ops dw_pcie_ops = {
543 .map_bus = dw_pcie_own_conf_map_bus,
544 .read = pci_generic_config_read,
545 .write = pci_generic_config_write,
548 void dw_pcie_setup_rc(struct pcie_port *pp)
550 u32 val, ctrl, num_ctrls;
551 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
554 * Enable DBI read-only registers for writing/updating configuration.
555 * Write permission gets disabled towards the end of this function.
557 dw_pcie_dbi_ro_wr_en(pci);
561 if (!pp->ops->msi_host_init) {
562 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
564 /* Initialize IRQ Status array */
565 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
566 pp->irq_mask[ctrl] = ~0;
567 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
568 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
570 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
571 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
577 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
578 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
580 /* Setup interrupt pins */
581 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
584 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
586 /* Setup bus numbers */
587 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
590 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
592 /* Setup command register */
593 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
595 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
596 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
597 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
600 * If the platform provides its own child bus config accesses, it means
601 * the platform uses its own address translation component rather than
602 * ATU, so we should not program the ATU here.
604 if (pp->bridge->child_ops == &dw_child_pcie_ops) {
605 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
606 PCIE_ATU_TYPE_MEM, pp->mem_base,
607 pp->mem_bus_addr, pp->mem_size);
608 if (pci->num_viewport > 2)
609 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
610 PCIE_ATU_TYPE_IO, pp->io_base,
611 pp->io_bus_addr, pp->io_size);
614 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
616 /* Program correct class for RC */
617 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
619 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
620 val |= PORT_LOGIC_SPEED_CHANGE;
621 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
623 dw_pcie_dbi_ro_wr_dis(pci);
625 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);