1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Amlogic MESON SoCs
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Yue Wang <yue.wang@amlogic.com>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/of_device.h>
13 #include <linux/of_gpio.h>
14 #include <linux/pci.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17 #include <linux/resource.h>
18 #include <linux/types.h>
19 #include <linux/phy/phy.h>
21 #include "pcie-designware.h"
23 #define to_meson_pcie(x) dev_get_drvdata((x)->dev)
25 #define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
26 #define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
28 /* PCIe specific config registers */
30 #define APP_LTSSM_ENABLE BIT(7)
32 #define PCIE_CFG_STATUS12 0x30
33 #define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
34 #define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
35 #define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
37 #define PCIE_CFG_STATUS17 0x44
38 #define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
40 #define WAIT_LINKUP_TIMEOUT 4000
41 #define PORT_CLK_RATE 100000000UL
42 #define MAX_PAYLOAD_SIZE 256
43 #define MAX_READ_REQ_SIZE 256
44 #define PCIE_RESET_DELAY 500
45 #define PCIE_SHARED_RESET 1
46 #define PCIE_NORMAL_RESET 0
55 struct meson_pcie_clk_res {
58 struct clk *general_clk;
61 struct meson_pcie_rc_reset {
62 struct reset_control *port;
63 struct reset_control *apb;
68 void __iomem *cfg_base;
69 struct meson_pcie_clk_res clk_res;
70 struct meson_pcie_rc_reset mrst;
71 struct gpio_desc *reset_gpio;
75 static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
79 struct device *dev = mp->pci.dev;
80 struct reset_control *reset;
82 if (reset_type == PCIE_SHARED_RESET)
83 reset = devm_reset_control_get_shared(dev, id);
85 reset = devm_reset_control_get(dev, id);
90 static int meson_pcie_get_resets(struct meson_pcie *mp)
92 struct meson_pcie_rc_reset *mrst = &mp->mrst;
94 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
95 if (IS_ERR(mrst->port))
96 return PTR_ERR(mrst->port);
97 reset_control_deassert(mrst->port);
99 mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
100 if (IS_ERR(mrst->apb))
101 return PTR_ERR(mrst->apb);
102 reset_control_deassert(mrst->apb);
107 static int meson_pcie_get_mems(struct platform_device *pdev,
108 struct meson_pcie *mp)
110 struct dw_pcie *pci = &mp->pci;
112 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
113 if (IS_ERR(pci->dbi_base))
114 return PTR_ERR(pci->dbi_base);
116 mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
117 if (IS_ERR(mp->cfg_base))
118 return PTR_ERR(mp->cfg_base);
123 static int meson_pcie_power_on(struct meson_pcie *mp)
127 ret = phy_init(mp->phy);
131 ret = phy_power_on(mp->phy);
140 static void meson_pcie_power_off(struct meson_pcie *mp)
142 phy_power_off(mp->phy);
146 static int meson_pcie_reset(struct meson_pcie *mp)
148 struct meson_pcie_rc_reset *mrst = &mp->mrst;
151 ret = phy_reset(mp->phy);
155 reset_control_assert(mrst->port);
156 reset_control_assert(mrst->apb);
157 udelay(PCIE_RESET_DELAY);
158 reset_control_deassert(mrst->port);
159 reset_control_deassert(mrst->apb);
160 udelay(PCIE_RESET_DELAY);
165 static inline struct clk *meson_pcie_probe_clock(struct device *dev,
166 const char *id, u64 rate)
171 clk = devm_clk_get(dev, id);
176 ret = clk_set_rate(clk, rate);
178 dev_err(dev, "set clk rate failed, ret = %d\n", ret);
183 ret = clk_prepare_enable(clk);
185 dev_err(dev, "couldn't enable clk\n");
189 devm_add_action_or_reset(dev,
190 (void (*) (void *))clk_disable_unprepare,
196 static int meson_pcie_probe_clocks(struct meson_pcie *mp)
198 struct device *dev = mp->pci.dev;
199 struct meson_pcie_clk_res *res = &mp->clk_res;
201 res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
202 if (IS_ERR(res->port_clk))
203 return PTR_ERR(res->port_clk);
205 res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
206 if (IS_ERR(res->general_clk))
207 return PTR_ERR(res->general_clk);
209 res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
210 if (IS_ERR(res->clk))
211 return PTR_ERR(res->clk);
216 static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
218 return readl(mp->cfg_base + reg);
221 static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
223 writel(val, mp->cfg_base + reg);
226 static void meson_pcie_assert_reset(struct meson_pcie *mp)
228 gpiod_set_value_cansleep(mp->reset_gpio, 1);
230 gpiod_set_value_cansleep(mp->reset_gpio, 0);
233 static void meson_pcie_init_dw(struct meson_pcie *mp)
237 val = meson_cfg_readl(mp, PCIE_CFG0);
238 val |= APP_LTSSM_ENABLE;
239 meson_cfg_writel(mp, val, PCIE_CFG0);
242 static int meson_size_to_payload(struct meson_pcie *mp, int size)
244 struct device *dev = mp->pci.dev;
247 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
248 * So if input size is not 2^order alignment or less than 2^7 or bigger
249 * than 2^12, just set to default size 2^(1+7).
251 if (!is_power_of_2(size) || size < 128 || size > 4096) {
252 dev_warn(dev, "payload size %d, set to default 256\n", size);
256 return fls(size) - 8;
259 static void meson_set_max_payload(struct meson_pcie *mp, int size)
261 struct dw_pcie *pci = &mp->pci;
263 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
264 int max_payload_size = meson_size_to_payload(mp, size);
266 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
267 val &= ~PCI_EXP_DEVCTL_PAYLOAD;
268 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
270 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
271 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
272 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
275 static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
277 struct dw_pcie *pci = &mp->pci;
279 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
280 int max_rd_req_size = meson_size_to_payload(mp, size);
282 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
283 val &= ~PCI_EXP_DEVCTL_READRQ;
284 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
286 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
287 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
288 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
291 static int meson_pcie_establish_link(struct meson_pcie *mp)
293 struct dw_pcie *pci = &mp->pci;
294 struct pcie_port *pp = &pci->pp;
296 meson_pcie_init_dw(mp);
297 meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
298 meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
300 dw_pcie_setup_rc(pp);
302 meson_pcie_assert_reset(mp);
304 return dw_pcie_wait_for_link(pci);
307 static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
308 int where, int size, u32 *val)
312 ret = pci_generic_config_read(bus, devfn, where, size, val);
313 if (ret != PCIBIOS_SUCCESSFUL)
317 * There is a bug in the MESON AXG PCIe controller whereby software
318 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
319 * the return value in the config accessors.
321 if (where == PCI_CLASS_REVISION && size == 4)
322 *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
323 else if (where == PCI_CLASS_DEVICE && size == 2)
324 *val = PCI_CLASS_BRIDGE_PCI;
325 else if (where == PCI_CLASS_DEVICE && size == 1)
326 *val = PCI_CLASS_BRIDGE_PCI & 0xff;
327 else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
328 *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
330 return PCIBIOS_SUCCESSFUL;
333 static struct pci_ops meson_pci_ops = {
334 .map_bus = dw_pcie_own_conf_map_bus,
335 .read = meson_pcie_rd_own_conf,
336 .write = pci_generic_config_write,
339 static int meson_pcie_link_up(struct dw_pcie *pci)
341 struct meson_pcie *mp = to_meson_pcie(pci);
342 struct device *dev = pci->dev;
345 u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
348 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
349 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
350 smlh_up = IS_SMLH_LINK_UP(state12);
351 rdlh_up = IS_RDLH_LINK_UP(state12);
352 ltssm_up = IS_LTSSM_UP(state12);
354 if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
358 dev_dbg(dev, "smlh_link_up is on\n");
360 dev_dbg(dev, "rdlh_link_up is on\n");
362 dev_dbg(dev, "ltssm_up is on\n");
364 dev_dbg(dev, "speed_okay\n");
366 if (smlh_up && rdlh_up && ltssm_up && speed_okay)
372 } while (cnt < WAIT_LINKUP_TIMEOUT);
374 dev_err(dev, "error: wait linkup timeout\n");
378 static int meson_pcie_host_init(struct pcie_port *pp)
380 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
381 struct meson_pcie *mp = to_meson_pcie(pci);
384 pp->bridge->ops = &meson_pci_ops;
386 ret = meson_pcie_establish_link(mp);
390 dw_pcie_msi_init(pp);
395 static const struct dw_pcie_host_ops meson_pcie_host_ops = {
396 .host_init = meson_pcie_host_init,
399 static int meson_add_pcie_port(struct meson_pcie *mp,
400 struct platform_device *pdev)
402 struct dw_pcie *pci = &mp->pci;
403 struct pcie_port *pp = &pci->pp;
404 struct device *dev = &pdev->dev;
407 if (IS_ENABLED(CONFIG_PCI_MSI)) {
408 pp->msi_irq = platform_get_irq(pdev, 0);
413 pp->ops = &meson_pcie_host_ops;
415 ret = dw_pcie_host_init(pp);
417 dev_err(dev, "failed to initialize host\n");
424 static const struct dw_pcie_ops dw_pcie_ops = {
425 .link_up = meson_pcie_link_up,
428 static int meson_pcie_probe(struct platform_device *pdev)
430 struct device *dev = &pdev->dev;
432 struct meson_pcie *mp;
435 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
441 pci->ops = &dw_pcie_ops;
444 mp->phy = devm_phy_get(dev, "pcie");
445 if (IS_ERR(mp->phy)) {
446 dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
447 return PTR_ERR(mp->phy);
450 mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
451 if (IS_ERR(mp->reset_gpio)) {
452 dev_err(dev, "get reset gpio failed\n");
453 return PTR_ERR(mp->reset_gpio);
456 ret = meson_pcie_get_resets(mp);
458 dev_err(dev, "get reset resource failed, %d\n", ret);
462 ret = meson_pcie_get_mems(pdev, mp);
464 dev_err(dev, "get memory resource failed, %d\n", ret);
468 ret = meson_pcie_power_on(mp);
470 dev_err(dev, "phy power on failed, %d\n", ret);
474 ret = meson_pcie_reset(mp);
476 dev_err(dev, "reset failed, %d\n", ret);
480 ret = meson_pcie_probe_clocks(mp);
482 dev_err(dev, "init clock resources failed, %d\n", ret);
486 platform_set_drvdata(pdev, mp);
488 ret = meson_add_pcie_port(mp, pdev);
490 dev_err(dev, "Add PCIe port failed, %d\n", ret);
497 meson_pcie_power_off(mp);
501 static const struct of_device_id meson_pcie_of_match[] = {
503 .compatible = "amlogic,axg-pcie",
506 .compatible = "amlogic,g12a-pcie",
511 static struct platform_driver meson_pcie_driver = {
512 .probe = meson_pcie_probe,
514 .name = "meson-pcie",
515 .of_match_table = meson_pcie_of_match,
519 builtin_platform_driver(meson_pcie_driver);