2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/async.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/t10-pi.h>
30 #include <linux/types.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/sed-opal.h>
33 #include <linux/pci-p2pdma.h>
37 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
38 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
40 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
43 * These can be higher, but we need to ensure that any command doesn't
44 * require an sg allocation that needs more than a page of data.
46 #define NVME_MAX_KB_SZ 4096
47 #define NVME_MAX_SEGS 127
49 static int use_threaded_interrupts;
50 module_param(use_threaded_interrupts, int, 0);
52 static bool use_cmb_sqes = true;
53 module_param(use_cmb_sqes, bool, 0444);
54 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
56 static unsigned int max_host_mem_size_mb = 128;
57 module_param(max_host_mem_size_mb, uint, 0444);
58 MODULE_PARM_DESC(max_host_mem_size_mb,
59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
61 static unsigned int sgl_threshold = SZ_32K;
62 module_param(sgl_threshold, uint, 0644);
63 MODULE_PARM_DESC(sgl_threshold,
64 "Use SGLs when average request segment size is larger or equal to "
65 "this size. Use 0 to disable SGLs.");
67 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68 static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
73 static int io_queue_depth = 1024;
74 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
75 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
77 static int queue_count_set(const char *val, const struct kernel_param *kp);
78 static const struct kernel_param_ops queue_count_ops = {
79 .set = queue_count_set,
83 static int write_queues;
84 module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
85 MODULE_PARM_DESC(write_queues,
86 "Number of queues to use for writes. If not set, reads and writes "
87 "will share a queue set.");
89 static int poll_queues = 0;
90 module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
91 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
96 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
99 * Represents an NVM Express device. Each nvme_dev is a PCI function.
102 struct nvme_queue *queues;
103 struct blk_mq_tag_set tagset;
104 struct blk_mq_tag_set admin_tagset;
107 struct dma_pool *prp_page_pool;
108 struct dma_pool *prp_small_pool;
109 unsigned online_queues;
111 unsigned io_queues[HCTX_MAX_TYPES];
112 unsigned int num_vecs;
116 unsigned long bar_mapped_size;
117 struct work_struct remove_work;
118 struct mutex shutdown_lock;
124 struct nvme_ctrl ctrl;
126 mempool_t *iod_mempool;
128 /* shadow doorbell buffer support: */
130 dma_addr_t dbbuf_dbs_dma_addr;
132 dma_addr_t dbbuf_eis_dma_addr;
134 /* host memory buffer support: */
136 u32 nr_host_mem_descs;
137 dma_addr_t host_mem_descs_dma;
138 struct nvme_host_mem_buf_desc *host_mem_descs;
139 void **host_mem_desc_bufs;
142 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
146 ret = kstrtoint(val, 10, &n);
147 if (ret != 0 || n < 2)
150 return param_set_int(val, kp);
153 static int queue_count_set(const char *val, const struct kernel_param *kp)
157 ret = kstrtoint(val, 10, &n);
158 if (n > num_possible_cpus())
159 n = num_possible_cpus();
161 return param_set_int(val, kp);
164 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
166 return qid * 2 * stride;
169 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
171 return (qid * 2 + 1) * stride;
174 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
176 return container_of(ctrl, struct nvme_dev, ctrl);
180 * An NVM Express queue. Each device has at least two (one for admin
181 * commands and one for I/O commands).
184 struct device *q_dmadev;
185 struct nvme_dev *dev;
187 struct nvme_command *sq_cmds;
188 /* only used for poll queues: */
189 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
190 volatile struct nvme_completion *cqes;
191 struct blk_mq_tags **tags;
192 dma_addr_t sq_dma_addr;
193 dma_addr_t cq_dma_addr;
204 #define NVMEQ_ENABLED 0
205 #define NVMEQ_SQ_CMB 1
206 #define NVMEQ_DELETE_ERROR 2
211 struct completion delete_done;
215 * The nvme_iod describes the data in an I/O, including the list of PRP
216 * entries. You can't see it in this data structure because C doesn't let
217 * me express that. Use nvme_init_iod to ensure there's enough space
218 * allocated to store the PRP list.
221 struct nvme_request req;
222 struct nvme_queue *nvmeq;
225 int npages; /* In the PRP list. 0 means small pool in use */
226 int nents; /* Used in scatterlist */
227 int length; /* Of data, in bytes */
228 dma_addr_t first_dma;
229 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
230 struct scatterlist *sg;
231 struct scatterlist inline_sg[0];
235 * Check we didin't inadvertently grow the command struct
237 static inline void _nvme_check_size(void)
239 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
240 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
241 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
242 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
243 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
244 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
245 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
246 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
247 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
248 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
249 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
250 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
251 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
254 static unsigned int max_io_queues(void)
256 return num_possible_cpus() + write_queues + poll_queues;
259 static unsigned int max_queue_count(void)
261 /* IO queues + admin queue */
262 return 1 + max_io_queues();
265 static inline unsigned int nvme_dbbuf_size(u32 stride)
267 return (max_queue_count() * 8 * stride);
270 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
272 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
277 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
278 &dev->dbbuf_dbs_dma_addr,
282 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
283 &dev->dbbuf_eis_dma_addr,
285 if (!dev->dbbuf_eis) {
286 dma_free_coherent(dev->dev, mem_size,
287 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
288 dev->dbbuf_dbs = NULL;
295 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
297 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
299 if (dev->dbbuf_dbs) {
300 dma_free_coherent(dev->dev, mem_size,
301 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
302 dev->dbbuf_dbs = NULL;
304 if (dev->dbbuf_eis) {
305 dma_free_coherent(dev->dev, mem_size,
306 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
307 dev->dbbuf_eis = NULL;
311 static void nvme_dbbuf_init(struct nvme_dev *dev,
312 struct nvme_queue *nvmeq, int qid)
314 if (!dev->dbbuf_dbs || !qid)
317 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
318 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
319 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
320 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
323 static void nvme_dbbuf_set(struct nvme_dev *dev)
325 struct nvme_command c;
330 memset(&c, 0, sizeof(c));
331 c.dbbuf.opcode = nvme_admin_dbbuf;
332 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
333 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
335 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
336 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
337 /* Free memory and continue on */
338 nvme_dbbuf_dma_free(dev);
342 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
344 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
347 /* Update dbbuf and return true if an MMIO is required */
348 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
349 volatile u32 *dbbuf_ei)
355 * Ensure that the queue is written before updating
356 * the doorbell in memory
360 old_value = *dbbuf_db;
364 * Ensure that the doorbell is updated before reading the event
365 * index from memory. The controller needs to provide similar
366 * ordering to ensure the envent index is updated before reading
371 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
379 * Max size of iod being embedded in the request payload
381 #define NVME_INT_PAGES 2
382 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
385 * Will slightly overestimate the number of pages needed. This is OK
386 * as it only leads to a small amount of wasted memory for the lifetime of
389 static int nvme_npages(unsigned size, struct nvme_dev *dev)
391 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
392 dev->ctrl.page_size);
393 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
397 * Calculates the number of pages needed for the SGL segments. For example a 4k
398 * page can accommodate 256 SGL descriptors.
400 static int nvme_pci_npages_sgl(unsigned int num_seg)
402 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
405 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
406 unsigned int size, unsigned int nseg, bool use_sgl)
411 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
413 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
415 return alloc_size + sizeof(struct scatterlist) * nseg;
418 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
420 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
421 NVME_INT_BYTES(dev), NVME_INT_PAGES,
424 return sizeof(struct nvme_iod) + alloc_size;
427 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
428 unsigned int hctx_idx)
430 struct nvme_dev *dev = data;
431 struct nvme_queue *nvmeq = &dev->queues[0];
433 WARN_ON(hctx_idx != 0);
434 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
435 WARN_ON(nvmeq->tags);
437 hctx->driver_data = nvmeq;
438 nvmeq->tags = &dev->admin_tagset.tags[0];
442 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
444 struct nvme_queue *nvmeq = hctx->driver_data;
449 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
450 unsigned int hctx_idx)
452 struct nvme_dev *dev = data;
453 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
456 nvmeq->tags = &dev->tagset.tags[hctx_idx];
458 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
459 hctx->driver_data = nvmeq;
463 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
464 unsigned int hctx_idx, unsigned int numa_node)
466 struct nvme_dev *dev = set->driver_data;
467 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
468 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
469 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
474 nvme_req(req)->ctrl = &dev->ctrl;
478 static int queue_irq_offset(struct nvme_dev *dev)
480 /* if we have more than 1 vec, admin queue offsets us by 1 */
481 if (dev->num_vecs > 1)
487 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
489 struct nvme_dev *dev = set->driver_data;
492 offset = queue_irq_offset(dev);
493 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
494 struct blk_mq_queue_map *map = &set->map[i];
496 map->nr_queues = dev->io_queues[i];
497 if (!map->nr_queues) {
498 BUG_ON(i == HCTX_TYPE_DEFAULT);
500 /* shared set, resuse read set parameters */
501 map->nr_queues = dev->io_queues[HCTX_TYPE_DEFAULT];
503 offset = queue_irq_offset(dev);
507 * The poll queue(s) doesn't have an IRQ (and hence IRQ
508 * affinity), so use the regular blk-mq cpu mapping
510 map->queue_offset = qoff;
511 if (i != HCTX_TYPE_POLL)
512 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
514 blk_mq_map_queues(map);
515 qoff += map->nr_queues;
516 offset += map->nr_queues;
523 * Write sq tail if we are asked to, or if the next command would wrap.
525 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
528 u16 next_tail = nvmeq->sq_tail + 1;
530 if (next_tail == nvmeq->q_depth)
532 if (next_tail != nvmeq->last_sq_tail)
536 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
537 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
538 writel(nvmeq->sq_tail, nvmeq->q_db);
539 nvmeq->last_sq_tail = nvmeq->sq_tail;
543 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
544 * @nvmeq: The queue to use
545 * @cmd: The command to send
546 * @write_sq: whether to write to the SQ doorbell
548 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
551 spin_lock(&nvmeq->sq_lock);
552 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
553 if (++nvmeq->sq_tail == nvmeq->q_depth)
555 nvme_write_sq_db(nvmeq, write_sq);
556 spin_unlock(&nvmeq->sq_lock);
559 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
561 struct nvme_queue *nvmeq = hctx->driver_data;
563 spin_lock(&nvmeq->sq_lock);
564 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
565 nvme_write_sq_db(nvmeq, true);
566 spin_unlock(&nvmeq->sq_lock);
569 static void **nvme_pci_iod_list(struct request *req)
571 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
572 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
575 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
577 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
578 int nseg = blk_rq_nr_phys_segments(req);
579 unsigned int avg_seg_size;
584 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
586 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
588 if (!iod->nvmeq->qid)
590 if (!sgl_threshold || avg_seg_size < sgl_threshold)
595 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
597 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
598 int nseg = blk_rq_nr_phys_segments(rq);
599 unsigned int size = blk_rq_payload_bytes(rq);
601 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
603 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
604 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
606 return BLK_STS_RESOURCE;
608 iod->sg = iod->inline_sg;
619 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
621 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
622 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
623 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
627 if (iod->npages == 0)
628 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
631 for (i = 0; i < iod->npages; i++) {
632 void *addr = nvme_pci_iod_list(req)[i];
635 struct nvme_sgl_desc *sg_list = addr;
638 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
640 __le64 *prp_list = addr;
642 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
645 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
646 dma_addr = next_dma_addr;
649 if (iod->sg != iod->inline_sg)
650 mempool_free(iod->sg, dev->iod_mempool);
653 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
656 struct scatterlist *sg;
658 for_each_sg(sgl, sg, nents, i) {
659 dma_addr_t phys = sg_phys(sg);
660 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
661 "dma_address:%pad dma_length:%d\n",
662 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
667 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
668 struct request *req, struct nvme_rw_command *cmnd)
670 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
671 struct dma_pool *pool;
672 int length = blk_rq_payload_bytes(req);
673 struct scatterlist *sg = iod->sg;
674 int dma_len = sg_dma_len(sg);
675 u64 dma_addr = sg_dma_address(sg);
676 u32 page_size = dev->ctrl.page_size;
677 int offset = dma_addr & (page_size - 1);
679 void **list = nvme_pci_iod_list(req);
683 length -= (page_size - offset);
689 dma_len -= (page_size - offset);
691 dma_addr += (page_size - offset);
694 dma_addr = sg_dma_address(sg);
695 dma_len = sg_dma_len(sg);
698 if (length <= page_size) {
699 iod->first_dma = dma_addr;
703 nprps = DIV_ROUND_UP(length, page_size);
704 if (nprps <= (256 / 8)) {
705 pool = dev->prp_small_pool;
708 pool = dev->prp_page_pool;
712 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
714 iod->first_dma = dma_addr;
716 return BLK_STS_RESOURCE;
719 iod->first_dma = prp_dma;
722 if (i == page_size >> 3) {
723 __le64 *old_prp_list = prp_list;
724 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
726 return BLK_STS_RESOURCE;
727 list[iod->npages++] = prp_list;
728 prp_list[0] = old_prp_list[i - 1];
729 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
732 prp_list[i++] = cpu_to_le64(dma_addr);
733 dma_len -= page_size;
734 dma_addr += page_size;
740 if (unlikely(dma_len < 0))
743 dma_addr = sg_dma_address(sg);
744 dma_len = sg_dma_len(sg);
748 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
749 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
754 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
755 "Invalid SGL for payload:%d nents:%d\n",
756 blk_rq_payload_bytes(req), iod->nents);
757 return BLK_STS_IOERR;
760 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
761 struct scatterlist *sg)
763 sge->addr = cpu_to_le64(sg_dma_address(sg));
764 sge->length = cpu_to_le32(sg_dma_len(sg));
765 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
768 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
769 dma_addr_t dma_addr, int entries)
771 sge->addr = cpu_to_le64(dma_addr);
772 if (entries < SGES_PER_PAGE) {
773 sge->length = cpu_to_le32(entries * sizeof(*sge));
774 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
776 sge->length = cpu_to_le32(PAGE_SIZE);
777 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
781 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
782 struct request *req, struct nvme_rw_command *cmd, int entries)
784 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
785 struct dma_pool *pool;
786 struct nvme_sgl_desc *sg_list;
787 struct scatterlist *sg = iod->sg;
791 /* setting the transfer type as SGL */
792 cmd->flags = NVME_CMD_SGL_METABUF;
795 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
799 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
800 pool = dev->prp_small_pool;
803 pool = dev->prp_page_pool;
807 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
810 return BLK_STS_RESOURCE;
813 nvme_pci_iod_list(req)[0] = sg_list;
814 iod->first_dma = sgl_dma;
816 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
819 if (i == SGES_PER_PAGE) {
820 struct nvme_sgl_desc *old_sg_desc = sg_list;
821 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
823 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
825 return BLK_STS_RESOURCE;
828 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
829 sg_list[i++] = *link;
830 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
833 nvme_pci_sgl_set_data(&sg_list[i++], sg);
835 } while (--entries > 0);
840 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
841 struct nvme_command *cmnd)
843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
844 struct request_queue *q = req->q;
845 enum dma_data_direction dma_dir = rq_data_dir(req) ?
846 DMA_TO_DEVICE : DMA_FROM_DEVICE;
847 blk_status_t ret = BLK_STS_IOERR;
850 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
851 iod->nents = blk_rq_map_sg(q, req, iod->sg);
855 ret = BLK_STS_RESOURCE;
857 if (is_pci_p2pdma_page(sg_page(iod->sg)))
858 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
861 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
862 dma_dir, DMA_ATTR_NO_WARN);
867 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
869 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
871 if (ret != BLK_STS_OK)
875 if (blk_integrity_rq(req)) {
876 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
879 sg_init_table(&iod->meta_sg, 1);
880 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
883 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
886 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
892 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
897 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
899 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
900 enum dma_data_direction dma_dir = rq_data_dir(req) ?
901 DMA_TO_DEVICE : DMA_FROM_DEVICE;
904 /* P2PDMA requests do not need to be unmapped */
905 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
906 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
908 if (blk_integrity_rq(req))
909 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
912 nvme_cleanup_cmd(req);
913 nvme_free_iod(dev, req);
917 * NOTE: ns is NULL when called on the admin queue.
919 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
920 const struct blk_mq_queue_data *bd)
922 struct nvme_ns *ns = hctx->queue->queuedata;
923 struct nvme_queue *nvmeq = hctx->driver_data;
924 struct nvme_dev *dev = nvmeq->dev;
925 struct request *req = bd->rq;
926 struct nvme_command cmnd;
930 * We should not need to do this, but we're still using this to
931 * ensure we can drain requests on a dying queue.
933 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
934 return BLK_STS_IOERR;
936 ret = nvme_setup_cmd(ns, req, &cmnd);
940 ret = nvme_init_iod(req, dev);
944 if (blk_rq_nr_phys_segments(req)) {
945 ret = nvme_map_data(dev, req, &cmnd);
947 goto out_cleanup_iod;
950 blk_mq_start_request(req);
951 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
954 nvme_free_iod(dev, req);
956 nvme_cleanup_cmd(req);
960 static void nvme_pci_complete_rq(struct request *req)
962 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
964 nvme_unmap_data(iod->nvmeq->dev, req);
965 nvme_complete_rq(req);
968 /* We read the CQE phase first to check if the rest of the entry is valid */
969 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
971 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
975 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
977 u16 head = nvmeq->cq_head;
979 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
981 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
984 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
986 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
989 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
990 dev_warn(nvmeq->dev->ctrl.device,
991 "invalid id %d completed on queue %d\n",
992 cqe->command_id, le16_to_cpu(cqe->sq_id));
997 * AEN requests are special as they don't time out and can
998 * survive any kind of queue freeze and often don't respond to
999 * aborts. We don't even bother to allocate a struct request
1000 * for them but rather special case them here.
1002 if (unlikely(nvmeq->qid == 0 &&
1003 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
1004 nvme_complete_async_event(&nvmeq->dev->ctrl,
1005 cqe->status, &cqe->result);
1009 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
1010 nvme_end_request(req, cqe->status, cqe->result);
1013 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
1015 while (start != end) {
1016 nvme_handle_cqe(nvmeq, start);
1017 if (++start == nvmeq->q_depth)
1022 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1024 if (++nvmeq->cq_head == nvmeq->q_depth) {
1026 nvmeq->cq_phase = !nvmeq->cq_phase;
1030 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1031 u16 *end, unsigned int tag)
1035 *start = nvmeq->cq_head;
1036 while (nvme_cqe_pending(nvmeq)) {
1037 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1039 nvme_update_cq_head(nvmeq);
1041 *end = nvmeq->cq_head;
1044 nvme_ring_cq_doorbell(nvmeq);
1048 static irqreturn_t nvme_irq(int irq, void *data)
1050 struct nvme_queue *nvmeq = data;
1051 irqreturn_t ret = IRQ_NONE;
1055 * The rmb/wmb pair ensures we see all updates from a previous run of
1056 * the irq handler, even if that was on another CPU.
1059 if (nvmeq->cq_head != nvmeq->last_cq_head)
1061 nvme_process_cq(nvmeq, &start, &end, -1);
1062 nvmeq->last_cq_head = nvmeq->cq_head;
1066 nvme_complete_cqes(nvmeq, start, end);
1073 static irqreturn_t nvme_irq_check(int irq, void *data)
1075 struct nvme_queue *nvmeq = data;
1076 if (nvme_cqe_pending(nvmeq))
1077 return IRQ_WAKE_THREAD;
1082 * Poll for completions any queue, including those not dedicated to polling.
1083 * Can be called from any context.
1085 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
1087 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1092 * For a poll queue we need to protect against the polling thread
1093 * using the CQ lock. For normal interrupt driven threads we have
1094 * to disable the interrupt to avoid racing with it.
1096 if (nvmeq->cq_vector == -1)
1097 spin_lock(&nvmeq->cq_poll_lock);
1099 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1100 found = nvme_process_cq(nvmeq, &start, &end, tag);
1101 if (nvmeq->cq_vector == -1)
1102 spin_unlock(&nvmeq->cq_poll_lock);
1104 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1106 nvme_complete_cqes(nvmeq, start, end);
1110 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1112 struct nvme_queue *nvmeq = hctx->driver_data;
1116 if (!nvme_cqe_pending(nvmeq))
1119 spin_lock(&nvmeq->cq_poll_lock);
1120 found = nvme_process_cq(nvmeq, &start, &end, -1);
1121 spin_unlock(&nvmeq->cq_poll_lock);
1123 nvme_complete_cqes(nvmeq, start, end);
1127 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1129 struct nvme_dev *dev = to_nvme_dev(ctrl);
1130 struct nvme_queue *nvmeq = &dev->queues[0];
1131 struct nvme_command c;
1133 memset(&c, 0, sizeof(c));
1134 c.common.opcode = nvme_admin_async_event;
1135 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1136 nvme_submit_cmd(nvmeq, &c, true);
1139 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1141 struct nvme_command c;
1143 memset(&c, 0, sizeof(c));
1144 c.delete_queue.opcode = opcode;
1145 c.delete_queue.qid = cpu_to_le16(id);
1147 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1150 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1151 struct nvme_queue *nvmeq, s16 vector)
1153 struct nvme_command c;
1154 int flags = NVME_QUEUE_PHYS_CONTIG;
1157 flags |= NVME_CQ_IRQ_ENABLED;
1160 * Note: we (ab)use the fact that the prp fields survive if no data
1161 * is attached to the request.
1163 memset(&c, 0, sizeof(c));
1164 c.create_cq.opcode = nvme_admin_create_cq;
1165 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1166 c.create_cq.cqid = cpu_to_le16(qid);
1167 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1168 c.create_cq.cq_flags = cpu_to_le16(flags);
1170 c.create_cq.irq_vector = cpu_to_le16(vector);
1172 c.create_cq.irq_vector = 0;
1174 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1177 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1178 struct nvme_queue *nvmeq)
1180 struct nvme_ctrl *ctrl = &dev->ctrl;
1181 struct nvme_command c;
1182 int flags = NVME_QUEUE_PHYS_CONTIG;
1185 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1186 * set. Since URGENT priority is zeroes, it makes all queues
1189 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1190 flags |= NVME_SQ_PRIO_MEDIUM;
1193 * Note: we (ab)use the fact that the prp fields survive if no data
1194 * is attached to the request.
1196 memset(&c, 0, sizeof(c));
1197 c.create_sq.opcode = nvme_admin_create_sq;
1198 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1199 c.create_sq.sqid = cpu_to_le16(qid);
1200 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1201 c.create_sq.sq_flags = cpu_to_le16(flags);
1202 c.create_sq.cqid = cpu_to_le16(qid);
1204 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1207 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1209 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1212 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1214 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1217 static void abort_endio(struct request *req, blk_status_t error)
1219 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1220 struct nvme_queue *nvmeq = iod->nvmeq;
1222 dev_warn(nvmeq->dev->ctrl.device,
1223 "Abort status: 0x%x", nvme_req(req)->status);
1224 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1225 blk_mq_free_request(req);
1228 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1231 /* If true, indicates loss of adapter communication, possibly by a
1232 * NVMe Subsystem reset.
1234 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1236 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1237 switch (dev->ctrl.state) {
1238 case NVME_CTRL_RESETTING:
1239 case NVME_CTRL_CONNECTING:
1245 /* We shouldn't reset unless the controller is on fatal error state
1246 * _or_ if we lost the communication with it.
1248 if (!(csts & NVME_CSTS_CFS) && !nssro)
1254 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1256 /* Read a config register to help see what died. */
1260 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1262 if (result == PCIBIOS_SUCCESSFUL)
1263 dev_warn(dev->ctrl.device,
1264 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1267 dev_warn(dev->ctrl.device,
1268 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1272 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1274 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1275 struct nvme_queue *nvmeq = iod->nvmeq;
1276 struct nvme_dev *dev = nvmeq->dev;
1277 struct request *abort_req;
1278 struct nvme_command cmd;
1279 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1281 /* If PCI error recovery process is happening, we cannot reset or
1282 * the recovery mechanism will surely fail.
1285 if (pci_channel_offline(to_pci_dev(dev->dev)))
1286 return BLK_EH_RESET_TIMER;
1289 * Reset immediately if the controller is failed
1291 if (nvme_should_reset(dev, csts)) {
1292 nvme_warn_reset(dev, csts);
1293 nvme_dev_disable(dev, false);
1294 nvme_reset_ctrl(&dev->ctrl);
1299 * Did we miss an interrupt?
1301 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
1302 dev_warn(dev->ctrl.device,
1303 "I/O %d QID %d timeout, completion polled\n",
1304 req->tag, nvmeq->qid);
1309 * Shutdown immediately if controller times out while starting. The
1310 * reset work will see the pci device disabled when it gets the forced
1311 * cancellation error. All outstanding requests are completed on
1312 * shutdown, so we return BLK_EH_DONE.
1314 switch (dev->ctrl.state) {
1315 case NVME_CTRL_CONNECTING:
1316 case NVME_CTRL_RESETTING:
1317 dev_warn_ratelimited(dev->ctrl.device,
1318 "I/O %d QID %d timeout, disable controller\n",
1319 req->tag, nvmeq->qid);
1320 nvme_dev_disable(dev, false);
1321 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1328 * Shutdown the controller immediately and schedule a reset if the
1329 * command was already aborted once before and still hasn't been
1330 * returned to the driver, or if this is the admin queue.
1332 if (!nvmeq->qid || iod->aborted) {
1333 dev_warn(dev->ctrl.device,
1334 "I/O %d QID %d timeout, reset controller\n",
1335 req->tag, nvmeq->qid);
1336 nvme_dev_disable(dev, false);
1337 nvme_reset_ctrl(&dev->ctrl);
1339 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1343 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1344 atomic_inc(&dev->ctrl.abort_limit);
1345 return BLK_EH_RESET_TIMER;
1349 memset(&cmd, 0, sizeof(cmd));
1350 cmd.abort.opcode = nvme_admin_abort_cmd;
1351 cmd.abort.cid = req->tag;
1352 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1354 dev_warn(nvmeq->dev->ctrl.device,
1355 "I/O %d QID %d timeout, aborting\n",
1356 req->tag, nvmeq->qid);
1358 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1359 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1360 if (IS_ERR(abort_req)) {
1361 atomic_inc(&dev->ctrl.abort_limit);
1362 return BLK_EH_RESET_TIMER;
1365 abort_req->timeout = ADMIN_TIMEOUT;
1366 abort_req->end_io_data = NULL;
1367 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1370 * The aborted req will be completed on receiving the abort req.
1371 * We enable the timer again. If hit twice, it'll cause a device reset,
1372 * as the device then is in a faulty state.
1374 return BLK_EH_RESET_TIMER;
1377 static void nvme_free_queue(struct nvme_queue *nvmeq)
1379 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1380 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1381 if (!nvmeq->sq_cmds)
1384 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1385 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1386 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1388 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1389 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1393 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1397 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1398 dev->ctrl.queue_count--;
1399 nvme_free_queue(&dev->queues[i]);
1404 * nvme_suspend_queue - put queue into suspended state
1405 * @nvmeq: queue to suspend
1407 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1409 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1412 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1415 nvmeq->dev->online_queues--;
1416 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1417 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1418 if (nvmeq->cq_vector == -1)
1420 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1421 nvmeq->cq_vector = -1;
1425 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1427 struct nvme_queue *nvmeq = &dev->queues[0];
1430 nvme_shutdown_ctrl(&dev->ctrl);
1432 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1434 nvme_poll_irqdisable(nvmeq, -1);
1437 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1440 int q_depth = dev->q_depth;
1441 unsigned q_size_aligned = roundup(q_depth * entry_size,
1442 dev->ctrl.page_size);
1444 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1445 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1446 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1447 q_depth = div_u64(mem_per_q, entry_size);
1450 * Ensure the reduced q_depth is above some threshold where it
1451 * would be better to map queues in system memory with the
1461 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1464 struct pci_dev *pdev = to_pci_dev(dev->dev);
1466 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1467 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1468 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1470 if (nvmeq->sq_dma_addr) {
1471 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1476 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1477 &nvmeq->sq_dma_addr, GFP_KERNEL);
1478 if (!nvmeq->sq_cmds)
1483 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1485 struct nvme_queue *nvmeq = &dev->queues[qid];
1487 if (dev->ctrl.queue_count > qid)
1490 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1491 &nvmeq->cq_dma_addr, GFP_KERNEL);
1495 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1498 nvmeq->q_dmadev = dev->dev;
1500 spin_lock_init(&nvmeq->sq_lock);
1501 spin_lock_init(&nvmeq->cq_poll_lock);
1503 nvmeq->cq_phase = 1;
1504 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1505 nvmeq->q_depth = depth;
1507 nvmeq->cq_vector = -1;
1508 dev->ctrl.queue_count++;
1513 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1514 nvmeq->cq_dma_addr);
1519 static int queue_request_irq(struct nvme_queue *nvmeq)
1521 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1522 int nr = nvmeq->dev->ctrl.instance;
1524 if (use_threaded_interrupts) {
1525 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1526 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1528 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1529 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1533 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1535 struct nvme_dev *dev = nvmeq->dev;
1538 nvmeq->last_sq_tail = 0;
1540 nvmeq->cq_phase = 1;
1541 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1542 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1543 nvme_dbbuf_init(dev, nvmeq, qid);
1544 dev->online_queues++;
1545 wmb(); /* ensure the first interrupt sees the initialization */
1548 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1550 struct nvme_dev *dev = nvmeq->dev;
1554 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1557 * A queue's vector matches the queue identifier unless the controller
1558 * has only one vector available.
1561 vector = dev->num_vecs == 1 ? 0 : qid;
1565 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1569 result = adapter_alloc_sq(dev, qid, nvmeq);
1575 nvmeq->cq_vector = vector;
1576 nvme_init_queue(nvmeq, qid);
1579 result = queue_request_irq(nvmeq);
1584 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1588 nvmeq->cq_vector = -1;
1589 dev->online_queues--;
1590 adapter_delete_sq(dev, qid);
1592 adapter_delete_cq(dev, qid);
1596 static const struct blk_mq_ops nvme_mq_admin_ops = {
1597 .queue_rq = nvme_queue_rq,
1598 .complete = nvme_pci_complete_rq,
1599 .init_hctx = nvme_admin_init_hctx,
1600 .exit_hctx = nvme_admin_exit_hctx,
1601 .init_request = nvme_init_request,
1602 .timeout = nvme_timeout,
1605 static const struct blk_mq_ops nvme_mq_ops = {
1606 .queue_rq = nvme_queue_rq,
1607 .complete = nvme_pci_complete_rq,
1608 .commit_rqs = nvme_commit_rqs,
1609 .init_hctx = nvme_init_hctx,
1610 .init_request = nvme_init_request,
1611 .map_queues = nvme_pci_map_queues,
1612 .timeout = nvme_timeout,
1616 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1618 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1620 * If the controller was reset during removal, it's possible
1621 * user requests may be waiting on a stopped queue. Start the
1622 * queue to flush these to completion.
1624 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1625 blk_cleanup_queue(dev->ctrl.admin_q);
1626 blk_mq_free_tag_set(&dev->admin_tagset);
1630 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1632 if (!dev->ctrl.admin_q) {
1633 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1634 dev->admin_tagset.nr_hw_queues = 1;
1636 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1637 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1638 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1639 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1640 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1641 dev->admin_tagset.driver_data = dev;
1643 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1645 dev->ctrl.admin_tagset = &dev->admin_tagset;
1647 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1648 if (IS_ERR(dev->ctrl.admin_q)) {
1649 blk_mq_free_tag_set(&dev->admin_tagset);
1652 if (!blk_get_queue(dev->ctrl.admin_q)) {
1653 nvme_dev_remove_admin(dev);
1654 dev->ctrl.admin_q = NULL;
1658 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1663 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1665 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1668 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1670 struct pci_dev *pdev = to_pci_dev(dev->dev);
1672 if (size <= dev->bar_mapped_size)
1674 if (size > pci_resource_len(pdev, 0))
1678 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1680 dev->bar_mapped_size = 0;
1683 dev->bar_mapped_size = size;
1684 dev->dbs = dev->bar + NVME_REG_DBS;
1689 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1693 struct nvme_queue *nvmeq;
1695 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1699 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1700 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1702 if (dev->subsystem &&
1703 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1704 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1706 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1710 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1714 nvmeq = &dev->queues[0];
1715 aqa = nvmeq->q_depth - 1;
1718 writel(aqa, dev->bar + NVME_REG_AQA);
1719 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1720 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1722 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1726 nvmeq->cq_vector = 0;
1727 nvme_init_queue(nvmeq, 0);
1728 result = queue_request_irq(nvmeq);
1730 nvmeq->cq_vector = -1;
1734 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1738 static int nvme_create_io_queues(struct nvme_dev *dev)
1740 unsigned i, max, rw_queues;
1743 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1744 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1750 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1751 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1752 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1753 dev->io_queues[HCTX_TYPE_READ];
1758 for (i = dev->online_queues; i <= max; i++) {
1759 bool polled = i > rw_queues;
1761 ret = nvme_create_queue(&dev->queues[i], i, polled);
1767 * Ignore failing Create SQ/CQ commands, we can continue with less
1768 * than the desired amount of queues, and even a controller without
1769 * I/O queues can still be used to issue admin commands. This might
1770 * be useful to upgrade a buggy firmware for example.
1772 return ret >= 0 ? 0 : ret;
1775 static ssize_t nvme_cmb_show(struct device *dev,
1776 struct device_attribute *attr,
1779 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1781 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1782 ndev->cmbloc, ndev->cmbsz);
1784 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1786 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1788 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1790 return 1ULL << (12 + 4 * szu);
1793 static u32 nvme_cmb_size(struct nvme_dev *dev)
1795 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1798 static void nvme_map_cmb(struct nvme_dev *dev)
1801 resource_size_t bar_size;
1802 struct pci_dev *pdev = to_pci_dev(dev->dev);
1808 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1811 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1813 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1814 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1815 bar = NVME_CMB_BIR(dev->cmbloc);
1816 bar_size = pci_resource_len(pdev, bar);
1818 if (offset > bar_size)
1822 * Controllers may support a CMB size larger than their BAR,
1823 * for example, due to being behind a bridge. Reduce the CMB to
1824 * the reported size of the BAR
1826 if (size > bar_size - offset)
1827 size = bar_size - offset;
1829 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1830 dev_warn(dev->ctrl.device,
1831 "failed to register the CMB\n");
1835 dev->cmb_size = size;
1836 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1838 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1839 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1840 pci_p2pmem_publish(pdev, true);
1842 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1843 &dev_attr_cmb.attr, NULL))
1844 dev_warn(dev->ctrl.device,
1845 "failed to add sysfs attribute for CMB\n");
1848 static inline void nvme_release_cmb(struct nvme_dev *dev)
1850 if (dev->cmb_size) {
1851 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1852 &dev_attr_cmb.attr, NULL);
1857 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1859 u64 dma_addr = dev->host_mem_descs_dma;
1860 struct nvme_command c;
1863 memset(&c, 0, sizeof(c));
1864 c.features.opcode = nvme_admin_set_features;
1865 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1866 c.features.dword11 = cpu_to_le32(bits);
1867 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1868 ilog2(dev->ctrl.page_size));
1869 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1870 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1871 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1873 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1875 dev_warn(dev->ctrl.device,
1876 "failed to set host mem (err %d, flags %#x).\n",
1882 static void nvme_free_host_mem(struct nvme_dev *dev)
1886 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1887 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1888 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1890 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1891 le64_to_cpu(desc->addr));
1894 kfree(dev->host_mem_desc_bufs);
1895 dev->host_mem_desc_bufs = NULL;
1896 dma_free_coherent(dev->dev,
1897 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1898 dev->host_mem_descs, dev->host_mem_descs_dma);
1899 dev->host_mem_descs = NULL;
1900 dev->nr_host_mem_descs = 0;
1903 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1906 struct nvme_host_mem_buf_desc *descs;
1907 u32 max_entries, len;
1908 dma_addr_t descs_dma;
1913 tmp = (preferred + chunk_size - 1);
1914 do_div(tmp, chunk_size);
1917 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1918 max_entries = dev->ctrl.hmmaxd;
1920 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1921 &descs_dma, GFP_KERNEL);
1925 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1927 goto out_free_descs;
1929 for (size = 0; size < preferred && i < max_entries; size += len) {
1930 dma_addr_t dma_addr;
1932 len = min_t(u64, chunk_size, preferred - size);
1933 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1934 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1938 descs[i].addr = cpu_to_le64(dma_addr);
1939 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1946 dev->nr_host_mem_descs = i;
1947 dev->host_mem_size = size;
1948 dev->host_mem_descs = descs;
1949 dev->host_mem_descs_dma = descs_dma;
1950 dev->host_mem_desc_bufs = bufs;
1955 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1957 dma_free_coherent(dev->dev, size, bufs[i],
1958 le64_to_cpu(descs[i].addr));
1963 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1966 dev->host_mem_descs = NULL;
1970 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1974 /* start big and work our way down */
1975 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1976 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1978 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1979 if (!min || dev->host_mem_size >= min)
1981 nvme_free_host_mem(dev);
1988 static int nvme_setup_host_mem(struct nvme_dev *dev)
1990 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1991 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1992 u64 min = (u64)dev->ctrl.hmmin * 4096;
1993 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1996 preferred = min(preferred, max);
1998 dev_warn(dev->ctrl.device,
1999 "min host memory (%lld MiB) above limit (%d MiB).\n",
2000 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2001 nvme_free_host_mem(dev);
2006 * If we already have a buffer allocated check if we can reuse it.
2008 if (dev->host_mem_descs) {
2009 if (dev->host_mem_size >= min)
2010 enable_bits |= NVME_HOST_MEM_RETURN;
2012 nvme_free_host_mem(dev);
2015 if (!dev->host_mem_descs) {
2016 if (nvme_alloc_host_mem(dev, min, preferred)) {
2017 dev_warn(dev->ctrl.device,
2018 "failed to allocate host memory buffer.\n");
2019 return 0; /* controller must work without HMB */
2022 dev_info(dev->ctrl.device,
2023 "allocated %lld MiB host memory buffer.\n",
2024 dev->host_mem_size >> ilog2(SZ_1M));
2027 ret = nvme_set_host_mem(dev, enable_bits);
2029 nvme_free_host_mem(dev);
2033 static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int irq_queues)
2035 unsigned int this_w_queues = write_queues;
2038 * Setup read/write queue split
2040 if (irq_queues == 1) {
2041 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2042 dev->io_queues[HCTX_TYPE_READ] = 0;
2047 * If 'write_queues' is set, ensure it leaves room for at least
2050 if (this_w_queues >= irq_queues)
2051 this_w_queues = irq_queues - 1;
2054 * If 'write_queues' is set to zero, reads and writes will share
2057 if (!this_w_queues) {
2058 dev->io_queues[HCTX_TYPE_DEFAULT] = irq_queues;
2059 dev->io_queues[HCTX_TYPE_READ] = 0;
2061 dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues;
2062 dev->io_queues[HCTX_TYPE_READ] = irq_queues - this_w_queues;
2066 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2068 struct pci_dev *pdev = to_pci_dev(dev->dev);
2070 struct irq_affinity affd = {
2072 .nr_sets = ARRAY_SIZE(irq_sets),
2076 unsigned int irq_queues, this_p_queues;
2079 * Poll queues don't need interrupts, but we need at least one IO
2080 * queue left over for non-polled IO.
2082 this_p_queues = poll_queues;
2083 if (this_p_queues >= nr_io_queues) {
2084 this_p_queues = nr_io_queues - 1;
2087 irq_queues = nr_io_queues - this_p_queues;
2089 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2092 * For irq sets, we have to ask for minvec == maxvec. This passes
2093 * any reduction back to us, so we can adjust our queue counts and
2097 nvme_calc_io_queues(dev, irq_queues);
2098 irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT];
2099 irq_sets[1] = dev->io_queues[HCTX_TYPE_READ];
2104 * If we got a failure and we're down to asking for just
2105 * 1 + 1 queues, just ask for a single vector. We'll share
2106 * that between the single IO queue and the admin queue.
2108 if (result >= 0 && irq_queues > 1)
2109 irq_queues = irq_sets[0] + irq_sets[1] + 1;
2111 result = pci_alloc_irq_vectors_affinity(pdev, irq_queues,
2113 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2116 * Need to reduce our vec counts. If we get ENOSPC, the
2117 * platform should support mulitple vecs, we just need
2118 * to decrease our ask. If we get EINVAL, the platform
2119 * likely does not. Back down to ask for just one vector.
2121 if (result == -ENOSPC) {
2126 } else if (result == -EINVAL) {
2129 } else if (result <= 0)
2137 static int nvme_setup_io_queues(struct nvme_dev *dev)
2139 struct nvme_queue *adminq = &dev->queues[0];
2140 struct pci_dev *pdev = to_pci_dev(dev->dev);
2141 int result, nr_io_queues;
2144 nr_io_queues = max_io_queues();
2145 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2149 if (nr_io_queues == 0)
2152 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2154 if (dev->cmb_use_sqes) {
2155 result = nvme_cmb_qdepth(dev, nr_io_queues,
2156 sizeof(struct nvme_command));
2158 dev->q_depth = result;
2160 dev->cmb_use_sqes = false;
2164 size = db_bar_size(dev, nr_io_queues);
2165 result = nvme_remap_bar(dev, size);
2168 if (!--nr_io_queues)
2171 adminq->q_db = dev->dbs;
2173 /* Deregister the admin queue's interrupt */
2174 pci_free_irq(pdev, 0, adminq);
2177 * If we enable msix early due to not intx, disable it again before
2178 * setting up the full range we need.
2180 pci_free_irq_vectors(pdev);
2182 result = nvme_setup_irqs(dev, nr_io_queues);
2186 dev->num_vecs = result;
2187 result = max(result - 1, 1);
2188 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2190 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2191 dev->io_queues[HCTX_TYPE_DEFAULT],
2192 dev->io_queues[HCTX_TYPE_READ],
2193 dev->io_queues[HCTX_TYPE_POLL]);
2196 * Should investigate if there's a performance win from allocating
2197 * more queues than interrupt vectors; it might allow the submission
2198 * path to scale better, even if the receive path is limited by the
2199 * number of interrupts.
2202 result = queue_request_irq(adminq);
2204 adminq->cq_vector = -1;
2207 set_bit(NVMEQ_ENABLED, &adminq->flags);
2208 return nvme_create_io_queues(dev);
2211 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2213 struct nvme_queue *nvmeq = req->end_io_data;
2215 blk_mq_free_request(req);
2216 complete(&nvmeq->delete_done);
2219 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2221 struct nvme_queue *nvmeq = req->end_io_data;
2224 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2226 nvme_del_queue_end(req, error);
2229 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2231 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2232 struct request *req;
2233 struct nvme_command cmd;
2235 memset(&cmd, 0, sizeof(cmd));
2236 cmd.delete_queue.opcode = opcode;
2237 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2239 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2241 return PTR_ERR(req);
2243 req->timeout = ADMIN_TIMEOUT;
2244 req->end_io_data = nvmeq;
2246 init_completion(&nvmeq->delete_done);
2247 blk_execute_rq_nowait(q, NULL, req, false,
2248 opcode == nvme_admin_delete_cq ?
2249 nvme_del_cq_end : nvme_del_queue_end);
2253 static bool nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2255 int nr_queues = dev->online_queues - 1, sent = 0;
2256 unsigned long timeout;
2259 timeout = ADMIN_TIMEOUT;
2260 while (nr_queues > 0) {
2261 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2267 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2269 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2274 /* handle any remaining CQEs */
2275 if (opcode == nvme_admin_delete_cq &&
2276 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2277 nvme_poll_irqdisable(nvmeq, -1);
2287 * return error value only when tagset allocation failed
2289 static int nvme_dev_add(struct nvme_dev *dev)
2293 if (!dev->ctrl.tagset) {
2294 dev->tagset.ops = &nvme_mq_ops;
2295 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2296 dev->tagset.nr_maps = HCTX_MAX_TYPES;
2297 dev->tagset.timeout = NVME_IO_TIMEOUT;
2298 dev->tagset.numa_node = dev_to_node(dev->dev);
2299 dev->tagset.queue_depth =
2300 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2301 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2302 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2303 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2304 nvme_pci_cmd_size(dev, true));
2306 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2307 dev->tagset.driver_data = dev;
2309 ret = blk_mq_alloc_tag_set(&dev->tagset);
2311 dev_warn(dev->ctrl.device,
2312 "IO queues tagset allocation failed %d\n", ret);
2315 dev->ctrl.tagset = &dev->tagset;
2317 nvme_dbbuf_set(dev);
2319 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2321 /* Free previously allocated queues that are no longer usable */
2322 nvme_free_queues(dev, dev->online_queues);
2328 static int nvme_pci_enable(struct nvme_dev *dev)
2330 int result = -ENOMEM;
2331 struct pci_dev *pdev = to_pci_dev(dev->dev);
2333 if (pci_enable_device_mem(pdev))
2336 pci_set_master(pdev);
2338 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2339 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2342 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2348 * Some devices and/or platforms don't advertise or work with INTx
2349 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2350 * adjust this later.
2352 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2356 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2358 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2360 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2361 dev->dbs = dev->bar + 4096;
2364 * Temporary fix for the Apple controller found in the MacBook8,1 and
2365 * some MacBook7,1 to avoid controller resets and data loss.
2367 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2369 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2370 "set queue depth=%u to work around controller resets\n",
2372 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2373 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2374 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2376 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2377 "set queue depth=%u\n", dev->q_depth);
2382 pci_enable_pcie_error_reporting(pdev);
2383 pci_save_state(pdev);
2387 pci_disable_device(pdev);
2391 static void nvme_dev_unmap(struct nvme_dev *dev)
2395 pci_release_mem_regions(to_pci_dev(dev->dev));
2398 static void nvme_pci_disable(struct nvme_dev *dev)
2400 struct pci_dev *pdev = to_pci_dev(dev->dev);
2402 pci_free_irq_vectors(pdev);
2404 if (pci_is_enabled(pdev)) {
2405 pci_disable_pcie_error_reporting(pdev);
2406 pci_disable_device(pdev);
2410 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2414 struct pci_dev *pdev = to_pci_dev(dev->dev);
2416 mutex_lock(&dev->shutdown_lock);
2417 if (pci_is_enabled(pdev)) {
2418 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2420 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2421 dev->ctrl.state == NVME_CTRL_RESETTING)
2422 nvme_start_freeze(&dev->ctrl);
2423 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2424 pdev->error_state != pci_channel_io_normal);
2428 * Give the controller a chance to complete all entered requests if
2429 * doing a safe shutdown.
2433 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2436 nvme_stop_queues(&dev->ctrl);
2438 if (!dead && dev->ctrl.queue_count > 0) {
2439 if (nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2440 nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2441 nvme_disable_admin_queue(dev, shutdown);
2443 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2444 nvme_suspend_queue(&dev->queues[i]);
2446 nvme_pci_disable(dev);
2448 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2449 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2452 * The driver will not be starting up queues again if shutting down so
2453 * must flush all entered requests to their failed completion to avoid
2454 * deadlocking blk-mq hot-cpu notifier.
2457 nvme_start_queues(&dev->ctrl);
2458 mutex_unlock(&dev->shutdown_lock);
2461 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2463 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2464 PAGE_SIZE, PAGE_SIZE, 0);
2465 if (!dev->prp_page_pool)
2468 /* Optimisation for I/Os between 4k and 128k */
2469 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2471 if (!dev->prp_small_pool) {
2472 dma_pool_destroy(dev->prp_page_pool);
2478 static void nvme_release_prp_pools(struct nvme_dev *dev)
2480 dma_pool_destroy(dev->prp_page_pool);
2481 dma_pool_destroy(dev->prp_small_pool);
2484 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2486 struct nvme_dev *dev = to_nvme_dev(ctrl);
2488 nvme_dbbuf_dma_free(dev);
2489 put_device(dev->dev);
2490 if (dev->tagset.tags)
2491 blk_mq_free_tag_set(&dev->tagset);
2492 if (dev->ctrl.admin_q)
2493 blk_put_queue(dev->ctrl.admin_q);
2495 free_opal_dev(dev->ctrl.opal_dev);
2496 mempool_destroy(dev->iod_mempool);
2500 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2502 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2504 nvme_get_ctrl(&dev->ctrl);
2505 nvme_dev_disable(dev, false);
2506 nvme_kill_queues(&dev->ctrl);
2507 if (!queue_work(nvme_wq, &dev->remove_work))
2508 nvme_put_ctrl(&dev->ctrl);
2511 static void nvme_reset_work(struct work_struct *work)
2513 struct nvme_dev *dev =
2514 container_of(work, struct nvme_dev, ctrl.reset_work);
2515 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2516 int result = -ENODEV;
2517 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2519 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2523 * If we're called to reset a live controller first shut it down before
2526 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2527 nvme_dev_disable(dev, false);
2530 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2531 * initializing procedure here.
2533 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2534 dev_warn(dev->ctrl.device,
2535 "failed to mark controller CONNECTING\n");
2539 result = nvme_pci_enable(dev);
2543 result = nvme_pci_configure_admin_queue(dev);
2547 result = nvme_alloc_admin_tags(dev);
2552 * Limit the max command size to prevent iod->sg allocations going
2553 * over a single page.
2555 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2556 dev->ctrl.max_segments = NVME_MAX_SEGS;
2558 result = nvme_init_identify(&dev->ctrl);
2562 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2563 if (!dev->ctrl.opal_dev)
2564 dev->ctrl.opal_dev =
2565 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2566 else if (was_suspend)
2567 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2569 free_opal_dev(dev->ctrl.opal_dev);
2570 dev->ctrl.opal_dev = NULL;
2573 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2574 result = nvme_dbbuf_dma_alloc(dev);
2577 "unable to allocate dma for dbbuf\n");
2580 if (dev->ctrl.hmpre) {
2581 result = nvme_setup_host_mem(dev);
2586 result = nvme_setup_io_queues(dev);
2591 * Keep the controller around but remove all namespaces if we don't have
2592 * any working I/O queue.
2594 if (dev->online_queues < 2) {
2595 dev_warn(dev->ctrl.device, "IO queues not created\n");
2596 nvme_kill_queues(&dev->ctrl);
2597 nvme_remove_namespaces(&dev->ctrl);
2598 new_state = NVME_CTRL_ADMIN_ONLY;
2600 nvme_start_queues(&dev->ctrl);
2601 nvme_wait_freeze(&dev->ctrl);
2602 /* hit this only when allocate tagset fails */
2603 if (nvme_dev_add(dev))
2604 new_state = NVME_CTRL_ADMIN_ONLY;
2605 nvme_unfreeze(&dev->ctrl);
2609 * If only admin queue live, keep it to do further investigation or
2612 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2613 dev_warn(dev->ctrl.device,
2614 "failed to mark controller state %d\n", new_state);
2618 nvme_start_ctrl(&dev->ctrl);
2622 nvme_remove_dead_ctrl(dev, result);
2625 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2627 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2628 struct pci_dev *pdev = to_pci_dev(dev->dev);
2630 if (pci_get_drvdata(pdev))
2631 device_release_driver(&pdev->dev);
2632 nvme_put_ctrl(&dev->ctrl);
2635 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2637 *val = readl(to_nvme_dev(ctrl)->bar + off);
2641 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2643 writel(val, to_nvme_dev(ctrl)->bar + off);
2647 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2649 *val = readq(to_nvme_dev(ctrl)->bar + off);
2653 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2655 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2657 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2660 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2662 .module = THIS_MODULE,
2663 .flags = NVME_F_METADATA_SUPPORTED |
2665 .reg_read32 = nvme_pci_reg_read32,
2666 .reg_write32 = nvme_pci_reg_write32,
2667 .reg_read64 = nvme_pci_reg_read64,
2668 .free_ctrl = nvme_pci_free_ctrl,
2669 .submit_async_event = nvme_pci_submit_async_event,
2670 .get_address = nvme_pci_get_address,
2673 static int nvme_dev_map(struct nvme_dev *dev)
2675 struct pci_dev *pdev = to_pci_dev(dev->dev);
2677 if (pci_request_mem_regions(pdev, "nvme"))
2680 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2685 pci_release_mem_regions(pdev);
2689 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2691 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2693 * Several Samsung devices seem to drop off the PCIe bus
2694 * randomly when APST is on and uses the deepest sleep state.
2695 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2696 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2697 * 950 PRO 256GB", but it seems to be restricted to two Dell
2700 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2701 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2702 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2703 return NVME_QUIRK_NO_DEEPEST_PS;
2704 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2706 * Samsung SSD 960 EVO drops off the PCIe bus after system
2707 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2708 * within few minutes after bootup on a Coffee Lake board -
2711 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2712 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2713 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2714 return NVME_QUIRK_NO_APST;
2720 static void nvme_async_probe(void *data, async_cookie_t cookie)
2722 struct nvme_dev *dev = data;
2724 nvme_reset_ctrl_sync(&dev->ctrl);
2725 flush_work(&dev->ctrl.scan_work);
2726 nvme_put_ctrl(&dev->ctrl);
2729 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2731 int node, result = -ENOMEM;
2732 struct nvme_dev *dev;
2733 unsigned long quirks = id->driver_data;
2736 node = dev_to_node(&pdev->dev);
2737 if (node == NUMA_NO_NODE)
2738 set_dev_node(&pdev->dev, first_memory_node);
2740 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2744 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2749 dev->dev = get_device(&pdev->dev);
2750 pci_set_drvdata(pdev, dev);
2752 result = nvme_dev_map(dev);
2756 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2757 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2758 mutex_init(&dev->shutdown_lock);
2760 result = nvme_setup_prp_pools(dev);
2764 quirks |= check_vendor_combination_bug(pdev);
2767 * Double check that our mempool alloc size will cover the biggest
2768 * command we support.
2770 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2771 NVME_MAX_SEGS, true);
2772 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2774 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2776 (void *) alloc_size,
2778 if (!dev->iod_mempool) {
2783 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2786 goto release_mempool;
2788 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2790 nvme_get_ctrl(&dev->ctrl);
2791 async_schedule(nvme_async_probe, dev);
2796 mempool_destroy(dev->iod_mempool);
2798 nvme_release_prp_pools(dev);
2800 nvme_dev_unmap(dev);
2802 put_device(dev->dev);
2809 static void nvme_reset_prepare(struct pci_dev *pdev)
2811 struct nvme_dev *dev = pci_get_drvdata(pdev);
2812 nvme_dev_disable(dev, false);
2815 static void nvme_reset_done(struct pci_dev *pdev)
2817 struct nvme_dev *dev = pci_get_drvdata(pdev);
2818 nvme_reset_ctrl_sync(&dev->ctrl);
2821 static void nvme_shutdown(struct pci_dev *pdev)
2823 struct nvme_dev *dev = pci_get_drvdata(pdev);
2824 nvme_dev_disable(dev, true);
2828 * The driver's remove may be called on a device in a partially initialized
2829 * state. This function must not have any dependencies on the device state in
2832 static void nvme_remove(struct pci_dev *pdev)
2834 struct nvme_dev *dev = pci_get_drvdata(pdev);
2836 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2837 pci_set_drvdata(pdev, NULL);
2839 if (!pci_device_is_present(pdev)) {
2840 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2841 nvme_dev_disable(dev, true);
2842 nvme_dev_remove_admin(dev);
2845 flush_work(&dev->ctrl.reset_work);
2846 nvme_stop_ctrl(&dev->ctrl);
2847 nvme_remove_namespaces(&dev->ctrl);
2848 nvme_dev_disable(dev, true);
2849 nvme_release_cmb(dev);
2850 nvme_free_host_mem(dev);
2851 nvme_dev_remove_admin(dev);
2852 nvme_free_queues(dev, 0);
2853 nvme_uninit_ctrl(&dev->ctrl);
2854 nvme_release_prp_pools(dev);
2855 nvme_dev_unmap(dev);
2856 nvme_put_ctrl(&dev->ctrl);
2859 #ifdef CONFIG_PM_SLEEP
2860 static int nvme_suspend(struct device *dev)
2862 struct pci_dev *pdev = to_pci_dev(dev);
2863 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2865 nvme_dev_disable(ndev, true);
2869 static int nvme_resume(struct device *dev)
2871 struct pci_dev *pdev = to_pci_dev(dev);
2872 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2874 nvme_reset_ctrl(&ndev->ctrl);
2879 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2881 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2882 pci_channel_state_t state)
2884 struct nvme_dev *dev = pci_get_drvdata(pdev);
2887 * A frozen channel requires a reset. When detected, this method will
2888 * shutdown the controller to quiesce. The controller will be restarted
2889 * after the slot reset through driver's slot_reset callback.
2892 case pci_channel_io_normal:
2893 return PCI_ERS_RESULT_CAN_RECOVER;
2894 case pci_channel_io_frozen:
2895 dev_warn(dev->ctrl.device,
2896 "frozen state error detected, reset controller\n");
2897 nvme_dev_disable(dev, false);
2898 return PCI_ERS_RESULT_NEED_RESET;
2899 case pci_channel_io_perm_failure:
2900 dev_warn(dev->ctrl.device,
2901 "failure state error detected, request disconnect\n");
2902 return PCI_ERS_RESULT_DISCONNECT;
2904 return PCI_ERS_RESULT_NEED_RESET;
2907 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2909 struct nvme_dev *dev = pci_get_drvdata(pdev);
2911 dev_info(dev->ctrl.device, "restart after slot reset\n");
2912 pci_restore_state(pdev);
2913 nvme_reset_ctrl(&dev->ctrl);
2914 return PCI_ERS_RESULT_RECOVERED;
2917 static void nvme_error_resume(struct pci_dev *pdev)
2919 struct nvme_dev *dev = pci_get_drvdata(pdev);
2921 flush_work(&dev->ctrl.reset_work);
2924 static const struct pci_error_handlers nvme_err_handler = {
2925 .error_detected = nvme_error_detected,
2926 .slot_reset = nvme_slot_reset,
2927 .resume = nvme_error_resume,
2928 .reset_prepare = nvme_reset_prepare,
2929 .reset_done = nvme_reset_done,
2932 static const struct pci_device_id nvme_id_table[] = {
2933 { PCI_VDEVICE(INTEL, 0x0953),
2934 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2935 NVME_QUIRK_DEALLOCATE_ZEROES, },
2936 { PCI_VDEVICE(INTEL, 0x0a53),
2937 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2938 NVME_QUIRK_DEALLOCATE_ZEROES, },
2939 { PCI_VDEVICE(INTEL, 0x0a54),
2940 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2941 NVME_QUIRK_DEALLOCATE_ZEROES, },
2942 { PCI_VDEVICE(INTEL, 0x0a55),
2943 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2944 NVME_QUIRK_DEALLOCATE_ZEROES, },
2945 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2946 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2947 NVME_QUIRK_MEDIUM_PRIO_SQ },
2948 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2949 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2950 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2951 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2952 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2953 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2954 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2955 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2956 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2957 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2958 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2959 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2960 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2961 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2962 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2963 .driver_data = NVME_QUIRK_LIGHTNVM, },
2964 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2965 .driver_data = NVME_QUIRK_LIGHTNVM, },
2966 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2967 .driver_data = NVME_QUIRK_LIGHTNVM, },
2968 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2969 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2970 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2973 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2975 static struct pci_driver nvme_driver = {
2977 .id_table = nvme_id_table,
2978 .probe = nvme_probe,
2979 .remove = nvme_remove,
2980 .shutdown = nvme_shutdown,
2982 .pm = &nvme_dev_pm_ops,
2984 .sriov_configure = pci_sriov_configure_simple,
2985 .err_handler = &nvme_err_handler,
2988 static int __init nvme_init(void)
2990 return pci_register_driver(&nvme_driver);
2993 static void __exit nvme_exit(void)
2995 pci_unregister_driver(&nvme_driver);
2996 flush_workqueue(nvme_wq);
3000 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3001 MODULE_LICENSE("GPL");
3002 MODULE_VERSION("1.0");
3003 module_init(nvme_init);
3004 module_exit(nvme_exit);